Simulations gradually slows over time and finally fails with "time step too small"

John Mayega

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Jan 18, 2024, 6:46:38 AMJan 18

to xyce-users

I am running a simulation of a class A/B amplifier and trying various inputs to exercise the circuit. However, I have noticed an odd behaviour. For short simulations of a couple of transitions they finish very quickly with no issues. However, for longer simulations 100s of transitions the simulations is initially fast while activity is taking place in the circuit, and then gradually slows down by a factor of 10 and more. The slowdown increases until eventually it fails with a "time step too small" error. In the simulation the inputs to the circuit sometimes repeat so the simulator should be operating in the same condition as during the initial fast period. However the simulator remains very slow. It is almost like there is an error accumulating.

This behavior has been seen with method = default, gear, backward-euler. with the linear and non-linear solver etc...

The latest sim had the following settings:

.option TIMEINT method = trap maxord=1

* Continuation Options
.options nonlin continuation=9
.options loca
+ stepper=natural
+ predictor=constant
+ stepcontrol=adaptive
+ initialvalue=0.0
+ minvalue=0.0
+ maxvalue=1.0e12
+ initialstepsize=1.0e-6
+ minstepsize=1.0e-6
+ maxstepsize=1.0e6
+ aggressiveness=0.1
+ maxsteps=200
+ maxnliters=200
+ voltagescalefactor=1.0

.PREPROCESS REPLACEGROUND TRUE
.PREPROCESS REMOVEUNUSED C,D,M
.PREPROCESS ADDRESISTORS NODCPATH 1G

.tran 100n 200u

==================================================

The transient sim progress

==================================================

***** Device Count Summary ...
B level 1 (Expression Based Voltage or Current Source) 40
C level 1 (Capacitor) 217
D level 1,2 (Diode) 10
I level 1 (Independent Current Source) 1
M level 14 (BSIM4) 405
R level 1 (Resistor) 207
V level 1 (Independent Voltage Source) 15
----------------------------------------------------------
Total Devices 895
***** Setting up matrix structure...
***** Number of Unknowns = 442
***** Initializing...

***** Beginning DC Operating Point Calculation...

***** Beginning Transient Calculation...

***** Percent complete: 1.00501 %
***** Current system time: Thu Jan 18 13:54:41 2024
***** Estimated time to completion: 9 min., 28 sec.

***** Percent complete: 2.00608 %
***** Current system time: Thu Jan 18 13:54:50 2024
***** Estimated time to completion: 11 min., 46 sec.

***** Percent complete: 3.04726 %
***** Current system time: Thu Jan 18 13:54:56 2024
***** Estimated time to completion: 10 min., 58 sec.

***** Percent complete: 4.05005 %
***** Current system time: Thu Jan 18 13:55:01 2024
***** Estimated time to completion: 10 min., 13 sec.

***** Percent complete: 5.05005 %
***** Current system time: Thu Jan 18 13:55:12 2024
***** Estimated time to completion: 11 min., 16 sec.

***** Percent complete: 6.08288 %
***** Current system time: Thu Jan 18 13:55:19 2024
***** Estimated time to completion: 11 min., 6 sec.

***** Percent complete: 7.08965 %
***** Current system time: Thu Jan 18 13:55:28 2024
***** Estimated time to completion: 11 min., 29 sec.

***** Percent complete: 8.08967 %
***** Current system time: Thu Jan 18 13:57:03 2024
***** Estimated time to completion: 27 min., 54 sec.

***** Percent complete: 9.10673 %
***** Current system time: Thu Jan 18 13:58:50 2024
***** Estimated time to completion: 42 min., 23 sec.

***** Percent complete: 10.122 %
***** Current system time: Thu Jan 18 14:00:49 2024
***** Estimated time to completion: 55 min., 18 sec.

***** Percent complete: 11.122 %
***** Current system time: Thu Jan 18 14:05:19 2024
***** Estimated time to completion: 1 hrs., 25 min., 43 sec.

***** Percent complete: 12.1222 %
***** Current system time: Thu Jan 18 14:09:06 2024
***** Estimated time to completion: 1 hrs., 45 min., 9 sec.

***** Percent complete: 13.1255 %
***** Current system time: Thu Jan 18 14:13:23 2024
***** Estimated time to completion: 2 hrs., 4 min., 22 sec.

==================================================

The simulation

==================================================

John Mayega

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Jan 18, 2024, 8:10:41 AMJan 18

to xyce-users

Here is the Xyce output summary when the simulation is ran for 18us.

=======================================================================

***** Percent complete: 89.2968 %
***** Current system time: Thu Jan 18 16:02:05 2024
***** Estimated time to completion: 17 sec.

***** Percent complete: 90.6161 %
***** Current system time: Thu Jan 18 16:02:15 2024
***** Estimated time to completion: 16 sec.

***** Percent complete: 92.1156 %
***** Current system time: Thu Jan 18 16:02:15 2024
***** Estimated time to completion: 13 sec.

***** Percent complete: 93.7822 %
***** Current system time: Thu Jan 18 16:02:15 2024
***** Estimated time to completion: 10 sec.

***** Percent complete: 95.0006 %
***** Current system time: Thu Jan 18 16:02:15 2024
***** Estimated time to completion: 8 sec.

***** Percent complete: 96.0008 %
***** Current system time: Thu Jan 18 16:02:23 2024
***** Estimated time to completion: 6 sec.

***** Percent complete: 97.001 %
***** Current system time: Thu Jan 18 16:03:03 2024
***** Estimated time to completion: 6 sec.

***** Percent complete: 98.0012 %
***** Current system time: Thu Jan 18 16:03:27 2024
***** Estimated time to completion: 4 sec.

***** Percent complete: 99.005 %
***** Current system time: Thu Jan 18 16:03:40 2024
***** Estimated time to completion: 2 sec.

====================================================

***** Problem read in and set up time: 3.17353 seconds
***** DCOP time: 0.0158868 seconds. Breakdown follows:
Number Successful Steps Taken: 1
Number Failed Steps Attempted: 0
Number Jacobians Evaluated: 8
Number Linear Solves: 8
Number Failed Linear Solves: 0
Number Residual Evaluations: 9
Number Nonlinear Convergence Failures: 0
Total Residual Load Time: 0.0108151 seconds
Total Jacobian Load Time: 0.00109887 seconds
Total Linear Solution Time: 0.00135803 seconds

***** Transient Stepping time: 242.079 seconds. Breakdown follows:
Number Successful Steps Taken: 18627
Number Failed Steps Attempted: 3461
Number Jacobians Evaluated: 142415
Number Linear Solves: 142415
Number Failed Linear Solves: 0
Number Residual Evaluations: 164504
Number Nonlinear Convergence Failures: 3173
Total Residual Load Time: 195.237 seconds
Total Jacobian Load Time: 18.3543 seconds
Total Linear Solution Time: 20.3549 seconds

***** Solution Summary *****
Number Successful Steps Taken: 18628
Number Failed Steps Attempted: 3461
Number Jacobians Evaluated: 142423
Number Linear Solves: 142423
Number Failed Linear Solves: 0
Number Residual Evaluations: 164513
Number Nonlinear Convergence Failures: 3173
Total Residual Load Time: 195.248 seconds
Total Jacobian Load Time: 18.3554 seconds
Total Linear Solution Time: 20.3563 seconds

***** Total Simulation Solvers Run Time: 242.096 seconds
***** Total Elapsed Run Time: 245.269 seconds
*****
***** End of Xyce(TM) Simulation
*****

Timing summary of 1 processor
Stats Count CPU Time Wall Time
---------------------------------------- ------ --------------------- ---------------------
Xyce 1 4:04.291 (100.0%) 4:05.269 (100.0%)
Analysis 1 4:01.145 (98.71%) 4:02.095 (98.71%)
Transient 1 4:01.145 (98.71%) 4:02.095 (98.71%)
Nonlinear Solve 22089 3:58.758 (97.74%) 3:59.695 (97.73%)
Residual 164513 3:14.729 (79.71%) 3:15.567 (79.74%)
Jacobian 142423 18.476 ( 7.56%) 18.553 ( 7.56%)
Linear Solve 142423 20.423 ( 8.36%) 20.528 ( 8.37%)
Successful DCOP Steps 1 0.000 ( 0.00%) 0.001 (<0.01%)
Successful Step 18627 1.746 ( 0.71%) 1.759 ( 0.72%)
Failed Steps 3461 0.013 (<0.01%) 0.013 (<0.01%)
Nonlinear Failure 3173 0.001 (<0.01%) 0.001 (<0.01%)
Netlist Import 1 3.137 ( 1.28%) 3.164 ( 1.29%)
Parse Context 1 1.767 ( 0.72%) 1.776 ( 0.72%)
Distribute Devices 1 1.344 ( 0.55%) 1.358 ( 0.55%)
Verify Devices 1 0.000 (<0.01%) 0.000 (<0.01%)
Instantiate 1 0.024 (<0.01%) 0.026 ( 0.01%)
Late Initialization 1 0.007 (<0.01%) 0.007 (<0.01%)
Global Indices 1 0.003 (<0.01%) 0.003 (<0.01%)
Setup Matrix Structure 1 0.002 (<0.01%) 0.002 (<0.01%)

Mehmet Cirit

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Jan 18, 2024, 2:18:13 PMJan 18

to John Mayega, xyce-users

I have seen similar issues also, stable circuits, nothing changing, simulator  taking very small time steps. I think whenever you start reducing the time step, it also impacts the stability of the matrix, and it needs to be reordered. Also if truncation error based time step is used, it is possible that the error estimate may not be correct. If you reduce time step by half, it should be twice as close to the previous solution.  After reordering, the simulator should start with the last good large time step.

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XYCE

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Jan 18, 2024, 2:21:33 PMJan 18

to John Mayega, xyce-users

Hi John,

Thanks for your interest in Xyce.

When a simulation fails with “Time step too small” error in Xyce, you can look at the “Transient failure history” in Xyce output to help identify the problem. You can identify if the error is caused by LTE or nonlinear solver failure. The column EstErrOverTol is related to LTE and it should be less than 1. The 3 columns for nonlinear solver show the nonlinear solver status. If the time step too small error is due to nonlinear solver failure, the column node name/index tells you which node in the circuit has the largest abs value in the residual |F| vector which is one way that led nonlinear solver to fail. You can then look at the node in the circuit to see if there is any issue in this case. The large nonlinear solver update dx is another common way for nonlinear solver to fail. Also, device convergence failure and a few other things cause nonlinear solve to fail. Both LTE and nonlinear solver failures force Xyce to cut time steps. This can affect performance and you will get time step too small error if Xyce keep cutting time steps.

From the timing statistics, it looks like each cycle takes a lot of time steps. And most of the failed steps are due to nonlinear linear solver failures 3173 out of 3461. The device evaluation takes 87% of the time which seems high. From the device count summary, there are 40 behavior sources. What expressions do you use in these sources? Are they continuous? Discontinuity in the device models can lead to nonlinear solve failures. You can also use a profiler to see which part of the device evaluation takes majority of the time for your circuit, as one of the users suggested.

BTW, does Xyce have difficulty solving DC op using default Spice strategy? Why continuation=9 is used which is rarely used pseudo transient method and is not the same pseudo transient as what is implemented in other SPICE-like simulators.

Thanks,

Ting

From: xyce-...@googlegroups.com <xyce-...@googlegroups.com> On Behalf Of John Mayega
Sent: Thursday, January 18, 2024 6:11 AM
To: xyce-users <xyce-...@googlegroups.com>
Subject: [EXTERNAL] [xyce-users] Re: Simulations gradually slows over time and finally fails with "time step too small"

Some people who received this message don't often get email from jo...@metrio.co. Learn why this is important

John Mayega

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Jan 19, 2024, 6:06:34 AMJan 19

to XYCE, xyce-users

Thank you for the feedback. It appears based on your feedback that when the simulation runs until it fails that it is a non-linear solver issue. However, before it fails the simulation slows down under similar stimulus conditions. I believe, the node which fails does not have anything special characteristics (shown below). Yes, the simulator does have difficulty solving the dc operating point with the standard settings. The only settings which seem to work are continuation=9 and/or using the "uic" option in the .tran statement.

Node of concern:

These are the sources:
v3 VSS GND dc 0 ac 0
Vpulse3 vcom_ctrl VSS pulse(5 0 772.25u 0.1n 0.1n 770.25u 1544u 0 )
v2 sphase VSS dc 'sphase*vdd5' ac 0
VV2 enable VSS pwl(0 0 2u 0 2.001n 'vdd5' )
Vvmain AVDD_5v0 VSS pwl(0 0 0.1u 0 1.1u 'vdd5' )
Vvmain1 net3 VSS pwl(0 0 1.1u 0 2u 'vdd18' )
Vpulse1 clk_conv_ph2 VSS pulse(0 5 751n 0.5n 0.5n 1.351u 1.5u 0 )
Vpulse2 clk_azconv_ph2 VSS pulse(0 5 1100n 0.5n 0.5n 1.0u 1.5u 0 )
Vpulse4 clk_conv_ph2_d VSS pulse(0 5 752.5n 0.5n 0.5n 1.351u 1.5u 0 )
Vpulse5 clk_azconv_ph2_d VSS pulse(0 5 1101.5n 0.5n 0.5n 1.0u 1.5u 0 )
Ipulse net2 VSS pulse(0 10u 1u 100n 1n 1 2 0 )
Vvmain2 in_p VSS pwl(0 0 2u 0 5.2800u 2 6.7800u 2 6.7810u 2.4 8.2810u 2.4 8.2820u 2.2 9.7820u 2.2
+ 9.7830u 2.8 11.2830u 2.8 11.2840u 2.6 12.7840u 2.6 12.7850u 3.2 14.2850u 3.2 14.2860u 3 15.7860u 3 15.7870u
+ 3.6 17.2870u 3.6 17.2880u 3.4 18.7880u 3.4 18.7890u 3.8 20.2890u 3.8 20.2900u 3.6 21.7900u 3.6 21.7910u
+ 4 23.2910u 4 23.2920u 2 24.7920u 2 24.7930u 2.2 26.2930u 2.2 26.2940u 2.4 27.7940u 2.4 27.7950u 2.6
+ 29.2950u 2.6 29.2960u 2.8 30.7960u 2.8 30.7970u 3 32.2970u 3 32.2980u 3.2 33.7980u 3.2 33.7990u 3.4 35.2990u
+ 3.4 35.3000u 3.6 36.8000u 3.6 36.8010u 3.8 38.3010u 3.8 38.3020u 4 39.8020u 4 39.8030u 3.8 41.3030u 3.8
+ 41.3040u 3.6 42.8040u 3.6 42.8050u 3.4 44.3050u 3.4 44.3060u 3.2 45.8060u 3.2 45.8070u 3 47.3070u 3 47.3080u
+ 2.8 48.8080u 2.8 48.8090u 2.6 50.3090u 2.6 50.3100u 2.4 51.8100u 2.4 51.8110u 2.2 53.3110u 2.2 53.3120u
+ 2 54.8120u 2 54.8130u 2 56.3130u 2 56.3140u 1.6 57.8140u 1.6 57.8150u 1.8 59.3150u 1.8 59.3160u 1.2
+ 60.8160u 1.2 60.8170u 1.4 62.3170u 1.4 62.3180u 0.8 63.8180u 0.8 63.8190u 1 65.3190u 1 65.3200u 0.4 66.8200u
+ 0.4 66.8210u 0.6 68.3210u 0.6 68.3220u 0.2 69.8220u 0.2 69.8230u 0.4 71.3230u 0.4 71.3240u 0 72.8240u 0
+ 72.8250u 2 74.3250u 2 74.3260u 1.8 75.8260u 1.8 75.8270u 1.6 77.3270u 1.6 77.3280u 1.4 78.8280u 1.4 78.8290u
+ 1.2 80.3290u 1.2 80.3300u 1 81.8300u 1 81.8310u 0.8 83.3310u 0.8 83.3320u 0.6 84.8320u 0.6 84.8330u 0.4
+ 86.3330u 0.4 86.3340u 0.2 87.8340u 0.2 87.8350u 0 89.3350u 0 89.3360u 0.2 90.8360u 0.2 90.8370u 0.4 92.3370u
+ 0.4 92.3380u 0.6 93.8380u 0.6 93.8390u 0.8 95.3390u 0.8 95.3400u 1 96.8400u 1 96.8410u 1.2 98.3410u 1.2
+ 98.3420u 1.4 99.8420u 1.4 99.8430u 1.6 101.3430u 1.6 101.3440u 1.8 102.8440u 1.8 102.8450u 2 104.3450u 2
+ 104.3460u 2.4 105.8460u 2.4 105.8470u 2.401953125 107.3470u 2.401953125 107.3480u 2.40390625 108.8480u
+ 2.40390625 108.8490u 2.405859375 110.3490u 2.405859375 110.3500u 2.40390625 111.8500u 2.40390625 111.8510u
+ 2.401953125 113.3510u 2.401953125 113.3520u 2.4 114.8520u 2.4 114.8530u 2.8 116.3530u 2.8 116.3540u 2.801953125
+ 117.8540u 2.801953125 117.8550u 2.80390625 119.3550u 2.80390625 119.3560u 2.805859375 120.8560u 2.805859375
+ 120.8570u 2.80390625 122.3570u 2.80390625 122.3580u 2.801953125 123.8580u 2.801953125 123.8590u 2.8 125.3590u
+ 2.8 125.3600u 3.2 126.8600u 3.2 126.8610u 3.201953125 128.3610u 3.201953125 128.3620u 3.20390625
+ 129.8620u 3.20390625 129.8630u 3.205859375 131.3630u 3.205859375 131.3640u 3.20390625 132.8640u 3.20390625
+ 132.8650u 3.201953125 134.3650u 3.201953125 134.3660u 3.2 135.8660u 3.2 135.8670u 3.6 137.3670u 3.6 137.3680u
+ 3.601953125 138.8680u 3.601953125 138.8690u 3.60390625 140.3690u 3.60390625 140.3700u 3.605859375 141.8700u
+ 3.605859375 141.8710u 3.60390625 143.3710u 3.60390625 143.3720u 3.601953125 144.8720u 3.601953125 144.8730u 3.6
+ 146.3730u 3.6 146.3740u 2 147.8740u 2 147.8750u 1.6 149.3750u 1.6 149.3760u 1.598046875 150.8760u 1.598046875
+ 150.8770u 1.59609375 152.3770u 1.59609375 152.3780u 1.594140625 153.8780u 1.594140625 153.8790u 1.59609375
+ 155.3790u 1.59609375 155.3800u 1.598046875 156.8800u 1.598046875 156.8810u 1.6 158.3810u 1.6 158.3820u 1.2
+ 159.8820u 1.2 159.8830u 1.198046875 161.3830u 1.198046875 161.3840u 1.19609375 162.8840u 1.19609375 162.8850u
+ 1.194140625 164.3850u 1.194140625 164.3860u 1.19609375 165.8860u 1.19609375 165.8870u 1.198046875 167.3870u
+ 1.198046875 167.3880u 1.2 168.8880u 1.2 168.8890u 0.8 170.3890u 0.8 170.3900u 0.798046875 171.8900u 0.798046875
+ 171.8910u 0.79609375 173.3910u 0.79609375 173.3920u 0.794140625 174.8920u 0.794140625 174.8930u 0.79609375
+ 176.3930u 0.79609375 176.3940u 0.798046875 177.8940u 0.798046875 177.8950u 0.8 179.3950u 0.8 179.3960u 0.4
+ 180.8960u 0.4 180.8970u 0.398046875 182.3970u 0.398046875 182.3980u 0.39609375 183.8980u 0.39609375 183.8990u
+ 0.394140625 185.3990u 0.394140625 185.4000u 0.39609375 186.9000u 0.39609375 186.9010u 0.398046875 188.4010u
+ 0.398046875 188.4020u 0.4 189.9020u 0.4 189.9030u 2 191.4030u 2 )
Vvmain3 vin_ref VSS pwl(0 0 0.1u 0 1.1u 2 )
Vpulse7 net4 net3 pulse

Here is the failure summary:

----------------------------------------------------------------------

*** Transient failure history:
Time Time Step EstErr Non-Linear Solver node node
(sec) Step Status OverTol Status Iters ||F|| index name
2.461e-05 1.436e-11 pass 2.787e-01 P:normal 5 1.419e-03 153 XHVDRIVER.OUT_FB
2.461e-05 1.436e-11 pass 8.580e-02 P:normal 5 2.465e-03 153 XHVDRIVER.OUT_FB
2.461e-05 2.872e-11 pass 5.291e-01 P:normal 7 5.645e-03 150 XHVDRIVER.XMN_1.D1
2.461e-05 2.585e-11 fail 5.291e-01 P:near 6 9.158e-03 150 XHVDRIVER.XMN_1.D1
2.461e-05 3.231e-12 pass 2.034e-02 P:normal 4 6.688e-03 153 XHVDRIVER.OUT_FB
2.461e-05 6.462e-12 pass 5.651e-02 P:normal 3 7.798e-03 153 XHVDRIVER.OUT_FB
2.461e-05 1.292e-11 fail 5.651e-02 P:near 7 1.049e-02 153 XHVDRIVER.OUT_FB
2.461e-05 1.615e-12 pass 1.089e-03 P:normal 3 8.069e-03 153 XHVDRIVER.OUT_FB
2.461e-05 3.231e-12 pass 8.523e-03 P:normal 3 8.565e-03 153 XHVDRIVER.OUT_FB
2.461e-05 6.462e-12 pass 7.311e-02 P:normal 3 9.760e-03 153 XHVDRIVER.OUT_FB
2.461e-05 1.292e-11 fail 7.311e-02 P:near 7 1.256e-02 153 XHVDRIVER.OUT_FB
2.461e-05 1.615e-12 fail 7.311e-02 P:near 5 1.005e-02 153 XHVDRIVER.OUT_FB
2.461e-05 2.019e-13 pass 6.942e-06 P:normal 1 9.795e-03 153 XHVDRIVER.OUT_FB
2.461e-05 4.039e-13 pass 2.592e-04 P:normal 1 9.860e-03 153 XHVDRIVER.OUT_FB
2.461e-05 8.077e-13 pass 4.915e-04 P:normal 1 9.972e-03 153 XHVDRIVER.OUT_FB
2.461e-05 1.615e-12 fail 4.915e-04 P:near 5 1.018e-02 153 XHVDRIVER.OUT_FB
2.461e-05 2.019e-13 pass 1.336e-05 P:normal 1 9.998e-03 153 XHVDRIVER.OUT_FB
2.461e-05 4.039e-13 fail 1.336e-05 P:near 5 1.007e-02 153 XHVDRIVER.OUT_FB
2.461e-05 5.048e-14 fail 1.336e-05 P:near 5 1.001e-02 153 XHVDRIVER.OUT_FB
2.461e-05 6.311e-15 fail 1.336e-05 P:near 5 1.001e-02 153 XHVDRIVER.OUT_FB
2.461e-05 7.888e-16 fail 1.336e-05 P:near 5 1.001e-02 153 XHVDRIVER.OUT_FB
2.461e-05 9.860e-17 fail 1.336e-05 P:near 5 1.001e-02 153 XHVDRIVER.OUT_FB
2.461e-05 1.233e-17 pass 6.249e-10 P:normal 1 1.000e-02 153 XHVDRIVER.OUT_FB
2.461e-05 2.465e-17 fail 6.249e-10 P:near 5 1.001e-02 153 XHVDRIVER.OUT_FB
2.461e-05 3.081e-18 fail 6.249e-10 P:near 5 1.000e-02 153 XHVDRIVER.OUT_FB
Time step too small near step number: 17989 Exiting transient loop.

***** Solution Summary *****
Number Successful Steps Taken: 17990
Number Failed Steps Attempted: 2418
Number Jacobians Evaluated: 159860
Number Linear Solves: 159860

Number Failed Linear Solves: 0

Number Residual Evaluations: 338045
Number Nonlinear Convergence Failures: 2065
Total Residual Load Time: 580.872 seconds
Total Jacobian Load Time: 31.162 seconds
Total Linear Solution Time: 29.636 seconds

***** Total Simulation Solvers Run Time: 662.581 seconds
***** Total Elapsed Run Time: 667.358 seconds

*****
***** End of Xyce(TM) Simulation

Thank You,

-John

XYCE

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Jan 19, 2024, 2:59:30 PMJan 19

to John Mayega, XYCE, xyce-users

Hi John,

Thanks for the update.

Yes. Xyce cuts time steps due to nonlinear solver failure according to the history. It seems that the node 153/out_fb has the largest residual in residual vector (KCL is not satisfied in this node based on tolerance). Xyce does not take the maximum iterations (20) in this case. Instead, it only takes a few iteration and determines that it fails the nonlinear solver. It is a near convergence case and by default Xyce treats it as failure. The residual is close to RHS tolerance (1e-2 for transient analysis), but not reach the tolerance.

If you adjust RHStol using .options nonlin-tran or use .options timeint NLNEARCONV=1 (so Xyce treats near convergence as success instead of failure), you may be able to go further. But we do not normally recommend these. The default RHS tolerance of 1e-2 for transient is already pretty loose (KCL equation tolerance) and near convergence is not real convergence. One could still get convergence problem later in the simulation depending on the circuits.

Before the simulation is close to time step too small, the simulation takes small time step (1e-12 – 1e-11) due to nonlinear solver failure. Are the resistors and capacitors that are connected to node 153 expression based ones? Are these expressions continuous? Or do you set enough parasitic related parameters in the transistor model that is connected to this node?

By behavior sources, we do not mean independent sources. We mean the nonlinear behavior sources listed as B level 1 (Expression Based Voltage or Current Source) in the device count summary. Check the expressions used in these sources to see if they are continuous and smooth.

The device evaluation in this new simulation takes even more time, >90% of the run time. It is hard to know which devices led to this without the circuit or/and running a profiler on this circuit. It may or may not be a Xyce code issue.

Thanks,

Ting

From: John Mayega <jo...@metrio.co>
Sent: Friday, January 19, 2024 4:06 AM
To: XYCE <XY...@sandia.gov>
Cc: xyce-users <xyce-...@googlegroups.com>
Subject: Re: [EXTERNAL] [xyce-users] Re: Simulations gradually slows over time and finally fails with "time step too small"

You don't often get email from jo...@metrio.co. Learn why this is important

Thank you for the feedback. It appears based on your feedback that when the simulation runs until it fails that it is a non-linear solver issue. However, before it fails the simulation slows down under similar stimulus conditions. I believe, the node which fails does not have anything special characteristics (shown below). Yes, the simulator does have difficulty solving the dc operating point with the standard settings. The only settings which seem to work are continuation=9 and/or using the "uic" option in the .tran statement.

Node of concern:

Marcel Hendrix

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Jan 28, 2024, 5:25:24 AMJan 28

to xyce-users

Depending on AVSS and out_p, there could be a loop of capacitors and voltage sources. Maybe a

small resistor in series with that capacitor helps.

-marcel

John Mayega

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Jan 29, 2024, 3:59:56 AMJan 29

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Hello Ting,

Thank you for your feedback regarding the convergence issues. Yes, they was several behavioral sources in the Global Foundries 20V HV NMOS model. They were present to model self heating. I removed those portions of the model and the simulation improved somewhat, in terms of how far it would run. I then changed the capacitors and resistors from The GF capacitors to ideal capacitors and it also helped. However, the simulation still fails to run for the full desired simulation length. I can share more details of the design privately.

Thank You,

-John

John Mayega

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Jan 30, 2024, 5:45:40 AMJan 30

to Marcel Hendrix, xyce-users

Hello, Thank You for the feedback. Adding a 100 Ohm resistor in series with the capacitors stops the behavior where the simulation first slows down then eventually fails. However, the simulation fails at a similar point.

Settings --------------------------------

.options NONLIN-TRAN DELTAXTOL = 0.1
.options NONLIN-TRAN RHSTOL = 1e-3
.options TIMEINT NLNEARCONV = 1

Settings --------------------------------

*** Transient failure history:
Time Time Step EstErr Non-Linear Solver node node
(sec) Step Status OverTol Status Iters ||F|| index name

2.011e-05 3.647e-16 pass 1.719e-05 P:normal 8 4.724e-04 122 XHVDRIVER.GFBSH
2.011e-05 7.294e-16 fail 1.719e-05 F:max s 20 8.807e-04 122 XHVDRIVER.GFBSH
2.011e-05 9.118e-17 pass 6.367e-06 P:normal 2 3.765e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 1.824e-16 pass 1.579e-05 P:normal 7 4.944e-04 122 XHVDRIVER.GFBSH
2.011e-05 3.647e-16 pass 3.404e-05 P:normal 12 8.676e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 7.294e-16 fail 3.404e-05 F:max s 20 1.345e-03 122 XHVDRIVER.GFBSH
2.011e-05 9.118e-17 pass 2.103e-05 P:normal 10 7.570e-04 122 XHVDRIVER.GFBSH
2.011e-05 1.824e-16 fail 2.103e-05 F:max s 20 1.208e-03 122 XHVDRIVER.GFBSH
2.011e-05 2.279e-17 pass 4.103e-06 P:normal 2 6.102e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 4.559e-17 pass 2.924e-06 P:normal 9 6.183e-04 122 XHVDRIVER.GFBSH
2.011e-05 9.118e-17 fail 2.924e-06 F:max s 20 1.113e-03 122 XHVDRIVER.GFBSH
2.011e-05 1.140e-17 pass 8.600e-06 P:normal 2 4.937e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 2.279e-17 pass 2.170e-05 P:normal 8 5.640e-04 122 XHVDRIVER.GFBSH
2.011e-05 4.559e-17 fail 2.170e-05 F:max s 20 1.024e-03 122 XHVDRIVER.GFBSH
2.011e-05 5.699e-18 pass 7.478e-06 P:normal 2 4.501e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 1.140e-17 pass 1.841e-05 P:normal 8 5.143e-04 122 XHVDRIVER.GFBSH
2.011e-05 2.279e-17 fail 1.841e-05 F:max s 20 9.467e-04 122 XHVDRIVER.GFBSH
2.011e-05 2.849e-18 pass 6.876e-06 P:normal 2 4.101e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 5.699e-18 pass 1.726e-05 P:normal 9 4.308e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 1.140e-17 fail 1.726e-05 F:max s 20 8.984e-04 122 XHVDRIVER.GFBSH
2.011e-05 1.425e-18 pass 9.056e-06 P:normal 12 2.978e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 2.849e-18 pass 4.694e-05 P:normal 11 7.846e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 5.699e-18 fail 4.694e-05 F:max s 20 1.236e-03 122 XHVDRIVER.GFBSH
2.011e-05 7.123e-19 pass 1.346e-05 P:normal 12 5.490e-04 101 XHVDRIVER.XMN_1.D1
2.011e-05 1.425e-18 fail 1.346e-05 F:max s 20 1.257e-03 122 XHVDRIVER.GFBSH
Time step too small near step number: 10641 Exiting transient loop.

***** Solution Summary *****
Number Successful Steps Taken: 10642
Number Failed Steps Attempted: 711
Number Jacobians Evaluated: 56717
Number Linear Solves: 56717

Number Failed Linear Solves: 0

Number Residual Evaluations: 68071
Number Nonlinear Convergence Failures: 63
Total Residual Load Time: 28.548 seconds
Total Jacobian Load Time: 2.981 seconds
Total Linear Solution Time: 3.654 seconds

***** Total Simulation Solvers Run Time: 37.289 seconds
***** Total Elapsed Run Time: 39.705 seconds

*****
***** End of Xyce(TM) Simulation
*****

Timing summary of 1 processor
Stats Count CPU Time Wall Time
---------------------------------------- ----- --------------------- ---------------------

Xyce 1 39.386 (100.0%) 39.706 (100.0%)
Analysis 1 37.014 (93.98%) 37.289 (93.91%)
Transient 1 37.014 (93.98%) 37.289 (93.91%)
Nonlinear Solve 11353 36.338 (92.26%) 36.605 (92.19%)
Residual 68071 28.400 (72.11%) 28.631 (72.11%)
Jacobian 56717 3.007 ( 7.63%) 3.032 ( 7.64%)
Linear Solve 56717 3.670 ( 9.32%) 3.699 ( 9.32%)
Successful DCOP Steps 1 0.000 (<0.01%) 0.000 (<0.01%)
Successful Step 10641 0.495 ( 1.26%) 0.501 ( 1.26%)
Failed Steps 711 0.001 (<0.01%) 0.001 (<0.01%)
Nonlinear Failure 63 0.000 (<0.01%) 0.000 (<0.01%)
Netlist Import 1 2.366 ( 6.01%) 2.404 ( 6.05%)
Parse Context 1 1.462 ( 3.71%) 1.485 ( 3.74%)
Distribute Devices 1 0.886 ( 2.25%) 0.894 ( 2.25%)

Verify Devices 1 0.000 (<0.01%) 0.000 (<0.01%)

Instantiate 1 0.015 ( 0.04%) 0.016 ( 0.04%)
Late Initialization 1 0.003 (<0.01%) 0.005 ( 0.01%)
Global Indices 1 0.002 (<0.01%) 0.002 (<0.01%)
Setup Matrix Structure 1 0.000 ( 0.00%) 0.001 (<0.01%)

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Marcel Hendrix

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Jan 30, 2024, 6:05:31 AMJan 30

to xyce-users

It now fails for different nodes (adding a resistor changes the netlist)?

You may want to check the schematic for similar V-C loops (and maybe I-L cutsets).

-marcel

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