Matrix reordering options

[Mehmet Cirit (Ceridli)]

I have a latch with a lot of very small interconnect resistors. I have shorted these resistors and their impact on d-q delay very small, while slowing simulation by 2X, and causing dc convergence issues in some cases.  However, the setup times between the two versions of the latch is much much bigger.  I was attributing this difference to bugs in .step implementation. However, it may not be.  Are there any matrix ordering options as well

as reordering options in Xyce?  I use -linsolv KLU option from the command line. I use

linsol tr_partition=0

nonlin continuation"=mos

timeint method=trap

timeint newlte=1

timeint reltol=5e-5

timeint abstol=1e-9

device gmin=1e-9

Another problem has to do with leakage current and power.  We expect such currents to

reach dc levels over a long time interval. In both cases, it does not happen. They are orders of magnitude bigger than what they should be.

A third problem is run time.  Thus may be related to the previous issue, even when the circuit is stable, it may be proceeding with small time steps. 

[Keiter, Eric R]

 

Hi Mehmet,

 

Sorry I have been slow to reply to this.

 

By the way, I have fixed the issue in Xyce with .STEP and PWL sources.  That change went into the Xyce source code (in our internal repository) earlier this week.  So, it will be on the public github repo the next time we synchronize it.

 

Regarding your question below, it is hard to say exactly what would help without a copy of the circuit netlist.  Is that something you could share with us?

 

For your options below, here are a few comments.  

 

• The “tr_partition” option is only applicable when using iterative solvers.  You are using KLU (a direct solver) so I’m pretty sure that option won’t have an effect.
• The continuation=mos isn’t usually recommended.  This is a MOSFET-specific continuation method that we implemented about 20 years ago.  It was effective for some MOSFET circuits at the time, but in my experience it doesn’t actually work as well as our default continuation methods (Xyce by default does what most SPICE simulators do; it will initially attempt to solve the DCOP using straight Newton method, and if that fails, it attempts GMIN stepping and then if that fails it attempts source stepping.  Between those three things usually one of them will be more robust than the MOS continuation.    So, I wouldn’t set this unless you found that it was the only way to get your circuit to converge.
• The time integration tolerances that you are setting are pretty tight, so that could be part of why you are seeing tiny time steps.

 

 

For the leakage and power question, if Xyce is getting the wrong answer there, then my first guess is that a parameter value is being set incorrectly.  If that is the case, it is probably a Xyce issue, but I can’t track that down without a netlist to work from.

 

As for run time, we certainly want Xyce to run quickly.  I would hope if we can fix the accuracy problem this will also fix the runtime.  But we won’t know until we fix it.

 

Thanks!

Eric

--
You received this message because you are subscribed to the Google Groups "xyce-users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to xyce-users+...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/xyce-users/d84c9263-beed-44d3-80b3-dd52deedbec7n%40googlegroups.com.