XSCHEM: schematic editor for large VLSI designs. Xyce benchmark simulation

[Stefan Schippers]

A comparative simulation between NGSPICE and Xyce (Serial build on Debian Linux) has been done on a non trivial Power Amplifier design drawn with XSCHEM.
Some small changes were needed to port the original for-Ngspice design to Xyce; For example Xyce does not accept expressions for .tran Tstep and Tmax.

Since Xyce has adaptive time step calculation some tuning has been done on the .tran parameters to force the 2 simulators generating the same size output result raw file. Results were extremely good, both simulators giving the exact same results. However Xyce performed the simulation in half time:

schippes@mazinga:~/.xschem/simulations$ time ngspice -b -r poweramp.raw -o poweramp.out  poweramp.spice >log
real    0m18.738s
user    0m18.345s
sys    0m0.113s
schippes@mazinga:~/.xschem/simulations$ time Xyce -r poweramp_xyce.raw poweramp_xyce.spice > log
real    0m9.429s
user    0m8.904s
sys    0m0.380s

XSCHEM is a schematic editor for digital / analog / mixed-mode  VLSI / ASIC designs and supports SPICE, Verilog and VHDL netlist generations.

For info see XSCHEM slides submitted to F-si.org for the 2020 conference.

Stefan.

[Marcel Hendrix]

On Thursday, January 23, 2020 at 12:17:53 AM UTC+1, Stefan Schippers wrote:

[..] 

However Xyce performed the simulation in half time: 

Wow. It would be nice to have the netlist of that poweramp. The result contradicts my experience by

several factors. 

-marcel