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For anyone that is interested, I'm writing a proposal document for how
to do mixed-type resolution in SystemVerilog-AMS. This is being driven
(partially) by people wanting to do SystemC-AMS along with SystemVerilog.
Done properly it creates a bridge point for getting in and out of an
analog simulator and opens up the opportunity to use Xyce with
SystemC-AMS which would make it an entirely open-source simulation
environment from SoC test-bench to transistors.
Let me know if you want to comment -
Or just reply here.
If you are eligible for IEEE-SA participation, you can join P1800 and
help make this happen, let me know if you want to do that too.
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