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Hi Eddy,
It is hard to give suggestions without knowing some simulation details of your circuit. Is your circuit running slow because Xyce is taking too many steps or it is because each step is very expensive, or Xyce output is taking too much time? You can shorten your simulation and look at the Timing statics of Xyce run at the end of the simulation. It tells you how many accepted/failed steps Xyce takes, and how much time Xyce spends on device evaluation, linear solver, etc..
How many time steps for each clock cycle in your simulation? If it is too many, look at the waveform to see if it indicates any stability issues (for example, artificial point-to-point ringing). If so and if you circuit is not autonomous (oscillators), you can try a more stable time integrator gear by using:
.options timeint method=gear
Or if you need an even more stable method (BE), use
.options timeint maxord=1
These options would normally take care of the stability related performance issue. See Xyce user’s guide 7.3.4 for details.
In addition to Eric’s suggestion to turn off local truncation error (LTE) control, you can also try different local truncation error control by setting newlte in the timeint option. Some newlte option is more aggressive and is well suited for digital circuits. See Xyce user’s guide 7.3.5.
If Xyce takes reasonable number of step per clock cycle, see if any part, such as device evaluation or linear solver, is taking large part of the run time.
You mentioned that most of time is spent at the beginning transient calculation phase, it suggests that Xyce is taking a lot of time steps at the beginning of the simulation (relative to the length of the simulation).
If you would like us to take a look at your circuit and simulation, please feel free to send the circuit for us to debug. Please send it to xyce-de...@sandia.gov. Not all of us get emails from google group.
Thanks,
Ting
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Hi Eddy,
Thanks for providing the timing statistics and snapshot of some waveforms. It gives more information about the simulation.
The 3rd picture shows typical point-to-point ringing during the sharp transition (red waveform). This indicates stability issue. If gear does not fix the problem, try more stable method BE (maxord = 1). It should quickly damp out the overshooting. How many time steps Xyce takes on average for a clock cycle in your simulation?
BTW, loosening the tolerance may not always be a good idea to speedup a simulation. It could work in some cases. But it could also make the artificial point-to-point ringing worse for Trap method. The ringing is due to marginal stability of Trap method. Small numerical error can cause ringing and a loose tolerance can make it worse. In general, we should be careful if we loosen reltol in the simulation.
From timing statistics, you can see that majority of the time is spent on device evaluation (residual and Jacobian) and it takes more than 70% of the simulation time. The linear solver only takes about 22%. What device models are you using? You can get the information from the Device Count Summary at the beginning of the simulation. We have seen efficiency problems in device evaluations for certain devices due to different reasons previously and have fixed some of them. Please let us know and we will see if there is any efficiency problem in device evaluation. Could you also provide all the options lines you used in the simulation if you cannot send us the netlist.
Also, with a fast clock cycle and a long simulation length, the simulation has about 1.28 million cycles. According to the current timing statics, we can estimate how much time each step takes. Even with a reasonable number of time steps per cycle, the simulation is going to take many hours. Why do you need such a long simulation length? Does the circuit have some slow behavior that is orders of magnitude slower than the clock speed? If so, a plain transient simulation is not well suited for this case. Advance simulation methods, such as envelope methods normally available in RF simulators (e.g., Spectre RF), would be much faster in this case.
Thanks,
Ting
From: Eddy Wu <ed...@imagica.technology>
Sent: Friday, January 12, 2024 12:39 PM
To: XYCE <XY...@sandia.gov>
Cc: xyce-users <xyce-...@googlegroups.com>
Subject: [EXTERNAL] Re: [xyce-users] Re: General guidelines for long transient simulations
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Hi Eddy,
Thanks for the update. Yes. Using tighter tolerance with Trap method would reduce artificial ringing. Using a more stable method (gear, BE) is another way to reduce ringing. With the same tolerance, a more stable method should have less ringing. This is briefly mentioned in Xyce users’ guide and Kundert’s paper has more detailed explanation.
According to new information you provide here, the number of time steps per cycle is already reasonable. The artificial ringing led to some unnecessary steps at the sharp transition, but it damps out.
I assume that you use level 9 MOSFET in Xyce which is BSIM3. It is a hand written model and we have not seen performance related issue for device evaluation in this model previously. What other devices are used in the simulation? I wonder why >70% time is spent in device evaluation even with dist strategy=2.
Most simulation options are fine. Some minor things. The abstol of 1e-2 is too loose. The default is 1e-6. But abstol has a much less effect in LTE than reltol. Do you have a lot of floating nodes? The two addresistor preprocess lines are not used in this netlist. These commands in this netlist will generate another netlist with the name _xyce.cir which contains extra resistors added to the floating nodes. You will need to run _xyce.cir if you would like these extra resistors.
Thanks for explaining the reason why you need a long simulation length. With 1.28 million cycles, the simulation would have lots of output. I did a quick estimation with 100 time step per cycle. Your simulation is going to take a few months according to the current timing statistics.
Since the number of time steps per cycle is reasonable in your simulation, the main way to improve performance is to see if the cost per step can be reduced. As I mentioned before, the device evaluation takes >70% run time and linear solver takes 22%. Improving them would improve performance, but device evaluation would have a larger impact. Or it is possible that there may not be much performance issue, the simulation is slow because there are so many cycles. It is a limitation of plain transient simulation for the circuit.