OneStep::rejectStep failure

[Mehmet Cirit]

I have a buffer using level 70450 (BSIM-SOI 4.5.0 devices. During

transient analysis I get the following failure:

**** Setting up topology...

***** Device Count Summary ...
       C level 1 (Capacitor)                                17
       E level 1 (Linear Voltage Controlled Voltage Source)  3
       M level 70450 (BSIM-SOI 4.5.0)                        8
       R level 1 (Resistor)                                  8
       V level 1 (Independent Voltage Source)                8
       -------------------------------------------------------
       Total Devices                                        44
***** Setting up matrix structure...
***** Number of Unknowns = 70
***** Initializing...

***** Beginning DC Operating Point Calculation...

***** Beginning Transient Calculation...

function OneStep::rejectStep:
   Maximum number of failures at time 0
*** Xyce Abort ***
function OneStep::rejectStep:
   Maximum number of failures at time 0

Probably there is an instability in the matrix setup. Here dc convergence was achieved. I would guess it would be less likely to

have a singular matrix with the caps turned on.

I haven't tried the gmin and cmin type of aides. I will appreciate

---

Hi,

I'm encountering a failure during transient analysis with a buffer using level 70450 (BSIM-SOI 4.5.0 devices). Below are the details:

**** Setting up topology...

***** Device Count Summary ...

C level 1 (Capacitor) 17

E level 1 (Linear Voltage Controlled Voltage Source) 3

M level 70450 (BSIM-SOI 4.5.0) 8

R level 1 (Resistor) 8

V level 1 (Independent Voltage Source) 8

-------------------------------------------------------

Total Devices 44

***** Setting up matrix structure...

***** Number of Unknowns = 70

***** Initializing...

***** Beginning DC Operating Point Calculation...

***** Beginning Transient Calculation...

function OneStep::rejectStep:

Maximum number of failures at time 0

*** Xyce Abort ***

function OneStep::rejectStep:

Maximum number of failures at time 0

```

It seems there might be an instability in the matrix setup. DC convergence was achieved, and I would guess that a singular matrix would be less likely with the caps turned on. However, if I change

the corner, I get bad matrix failure as well.

Here are my options:

.options topology check_connectivity=1
.options device temp=25.000 voltlim=0 mincap=1e-17
.options output printfooter=1 printheader=1
.options linsol tr_partition=0 type=klu
.options timeint abstol=0.0005 maskivars=0 reltol=0.0005 newbpstepping=0 newlte=1

I haven't yet tried the gmin and cmin aides. Any insights would be greatly appreciated.

Thanks!

Mehmet

--

http://www.linkedin.com/in/mehmetcirit

Dr. Mehmet A. Cirit                    Phone:  (408) 647-6025

Library Technologies, Inc.        Cell:       (408) 647-6025

19959 Lanark Lane                   http://www.libtech.com

Saratoga, CA 95070                 Email: m...@libtech.com

[xyce-users]

Hi Mehmet,

We'd be happy to help you with this.   Is this a circuit you can share with us?  Otherwise it is difficult to diagnose the problem from the information in your message.  If you would rather not share it in a public forum like this, you can always send it to us directly.

BTW, I generally don't turn voltage limiting off, which is what the option "voltlim=0" does.   I doubt that will matter for this circuit, however.  Voltage limiting in the BSIM SOI models is a bit strange, and I don't think it is even implemented in the version 4.5 in Xyce.   It is implemented (correctly, now) in the version 3 BSIM SOI.

thanks,

Eric