[PATCH 0/5] arm64 (aka aarch64/armv8) support in Xvisor

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Sukanto Ghosh

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Sep 15, 2013, 4:08:43 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

This set of 5 patches adds much-awaited arm64 support in Xvisor.
Specifically this supports the folllowing environment:

Host: ARMv8 Foundation model (free download from ARM website
http://www.arm.com/products/tools/models/fast-models/foundation-model.php)
Guest: Virt-v8 (a completely device-tree based guest having generic
armv8 cpus, virtio-based devices, GIC and arch-timers).
Toolchain: Downloadable from linaro website
(http://www.linaro.org/engineering/engineering-projects/armv8#tab3)

Sukanto Ghosh (5):
[ARM] Introduce arm64 CPU support
[ARM] Introduce virt-v8 guest template for arm64 guest
[ARM] Introduce generic armv8 board
[DOCS] Add light-weight bootwrapper for ARMv8 foundation models
[TESTS] Add arm64 basic firmware for virt-v8 guest

arch/arm/board/common/guests/virt-v8x2.dtsi | 94 ++
arch/arm/board/generic-v8/brd_defterm.c | 93 ++
arch/arm/board/generic-v8/brd_main.c | 130 ++
arch/arm/board/generic-v8/brd_smp.c | 232 ++++
.../dts/foundation-v8/foundation-v8.dtsi | 122 ++
.../dts/foundation-v8/one_guest_virt_v8.dts | 41 +
arch/arm/board/generic-v8/dts/skeleton.dts | 24 +
arch/arm/board/generic-v8/include/arch_host_irq.h | 61 +
arch/arm/board/generic-v8/include/gic_config.h | 29 +
arch/arm/board/generic-v8/objects.mk | 30 +
arch/arm/board/generic-v8/openconf.cfg | 31 +
arch/arm/board/openconf.cfg | 21 +
arch/arm/configs/generic-v8-defconfig | 322 +++++
arch/arm/cpu/arm64/cpu_atomic.c | 124 ++
arch/arm/cpu/arm64/cpu_atomic64.c | 125 ++
arch/arm/cpu/arm64/cpu_cache.S | 278 ++++
arch/arm/cpu/arm64/cpu_delay.S | 32 +
arch/arm/cpu/arm64/cpu_elf.c | 66 +
arch/arm/cpu/arm64/cpu_entry.S | 665 ++++++++++
arch/arm/cpu/arm64/cpu_init.c | 105 ++
arch/arm/cpu/arm64/cpu_interrupts.c | 237 ++++
arch/arm/cpu/arm64/cpu_locks.c | 202 +++
arch/arm/cpu/arm64/cpu_smp.S | 32 +
arch/arm/cpu/arm64/cpu_stacktrace.c | 125 ++
arch/arm/cpu/arm64/cpu_vcpu_coproc.c | 306 +++++
arch/arm/cpu/arm64/cpu_vcpu_emulate.c | 506 +++++++
arch/arm/cpu/arm64/cpu_vcpu_helper.c | 991 ++++++++++++++
arch/arm/cpu/arm64/cpu_vcpu_irq.c | 201 +++
arch/arm/cpu/arm64/cpu_vcpu_mem.c | 135 ++
arch/arm/cpu/arm64/cpu_vcpu_spr.c | 359 +++++
arch/arm/cpu/arm64/include/arch_barrier.h | 48 +
arch/arm/cpu/arm64/include/arch_cache.h | 56 +
arch/arm/cpu/arm64/include/arch_config.h | 30 +
arch/arm/cpu/arm64/include/arch_cpu_irq.h | 82 ++
arch/arm/cpu/arm64/include/arch_delay.h | 39 +
arch/arm/cpu/arm64/include/arch_elf.h | 99 ++
arch/arm/cpu/arm64/include/arch_io.h | 193 +++
arch/arm/cpu/arm64/include/arch_regs.h | 152 +++
arch/arm/cpu/arm64/include/arch_sections.h | 69 +
arch/arm/cpu/arm64/include/arch_types.h | 71 +
arch/arm/cpu/arm64/include/cpu_cache.h | 76 ++
arch/arm/cpu/arm64/include/cpu_defines.h | 706 ++++++++++
arch/arm/cpu/arm64/include/cpu_generic_timer.h | 159 +++
arch/arm/cpu/arm64/include/cpu_inline_asm.h | 243 ++++
arch/arm/cpu/arm64/include/cpu_mmu_lpae.h | 55 +
arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h | 90 ++
arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h | 96 ++
arch/arm/cpu/arm64/include/cpu_vcpu_helper.h | 59 +
arch/arm/cpu/arm64/include/cpu_vcpu_mem.h | 57 +
arch/arm/cpu/arm64/include/cpu_vcpu_spr.h | 69 +
arch/arm/cpu/arm64/linker.ld | 119 ++
arch/arm/cpu/arm64/objects.mk | 52 +
arch/arm/cpu/arm64/openconf.cfg | 56 +
arch/arm/cpu/common/openconf.cfg | 4 +-
arch/arm/cpu/openconf.cfg | 24 +
docs/arm/foundation_v8_boot.S | 176 +++
tests/arm64/common/README | 9 +
tests/arm64/common/basic/Makefile.inc | 134 ++
tests/arm64/common/basic/README | 5 +
tests/arm64/common/basic/arm_asm_macro.h | 139 ++
tests/arm64/common/basic/arm_board.h | 60 +
tests/arm64/common/basic/arm_defines.h | 312 +++++
tests/arm64/common/basic/arm_entry.S | 323 +++++
tests/arm64/common/basic/arm_heap.c | 44 +
tests/arm64/common/basic/arm_heap.h | 32 +
tests/arm64/common/basic/arm_inline_asm.h | 118 ++
tests/arm64/common/basic/arm_io.h | 39 +
tests/arm64/common/basic/arm_irq.c | 122 ++
tests/arm64/common/basic/arm_irq.h | 48 +
tests/arm64/common/basic/arm_main.c | 675 ++++++++++
tests/arm64/common/basic/arm_math.c | 117 ++
tests/arm64/common/basic/arm_math.h | 60 +
tests/arm64/common/basic/arm_mmu.c | 235 ++++
tests/arm64/common/basic/arm_mmu.h | 36 +
tests/arm64/common/basic/arm_stdio.c | 360 +++++
tests/arm64/common/basic/arm_stdio.h | 38 +
tests/arm64/common/basic/arm_string.c | 357 +++++
tests/arm64/common/basic/arm_string.h | 47 +
tests/arm64/common/basic/arm_types.h | 88 ++
tests/arm64/common/basic/dhry.h | 395 ++++++
tests/arm64/common/basic/dhry_1.c | 431 ++++++
tests/arm64/common/basic/dhry_2.c | 197 +++
tests/arm64/common/basic/dhry_port.c | 83 ++
tests/arm64/common/basic/dhry_port.h | 42 +
tests/arm64/common/basic/firmware.ld | 97 ++
tests/arm64/common/basic/libfdt/cmd_fdt.c | 443 +++++++
tests/arm64/common/basic/libfdt/fdt.c | 222 ++++
tests/arm64/common/basic/libfdt/fdt.h | 62 +
tests/arm64/common/basic/libfdt/fdt_ro.c | 574 ++++++++
tests/arm64/common/basic/libfdt/fdt_rw.c | 465 +++++++
tests/arm64/common/basic/libfdt/fdt_strerror.c | 96 ++
tests/arm64/common/basic/libfdt/fdt_support.c | 1318 ++++++++++++++++++
tests/arm64/common/basic/libfdt/fdt_support.h | 123 ++
tests/arm64/common/basic/libfdt/fdt_sw.c | 256 ++++
tests/arm64/common/basic/libfdt/fdt_wip.c | 118 ++
tests/arm64/common/basic/libfdt/libfdt.h | 1237 +++++++++++++++++
tests/arm64/common/basic/libfdt/libfdt_env.h | 49 +
tests/arm64/common/basic/libfdt/libfdt_internal.h | 95 ++
tests/arm64/common/basic/pic/gic.c | 225 ++++
tests/arm64/common/basic/pic/gic.h | 56 +
tests/arm64/common/basic/serial/pl01x.c | 138 ++
tests/arm64/common/basic/serial/pl01x.h | 150 +++
tests/arm64/common/basic/serial/virtio_console.c | 70 +
tests/arm64/common/basic/serial/virtio_console.h | 57 +
tests/arm64/common/basic/timer/generic_timer.c | 166 +++
tests/arm64/common/basic/timer/generic_timer.h | 36 +
tests/arm64/common/busybox/README | 38 +
.../arm64/common/busybox/busybox-1.21.0_defconfig | 1034 +++++++++++++++
tests/arm64/common/busybox/busybox_dev.txt | 70 +
tests/arm64/virt-v8/README | 29 +
tests/arm64/virt-v8/basic/Makefile | 43 +
tests/arm64/virt-v8/basic/README | 61 +
tests/arm64/virt-v8/basic/arm_board.c | 214 +++
tests/arm64/virt-v8/basic/arm_plat.h | 63 +
tests/arm64/virt-v8/basic/gic_config.h | 41 +
tests/arm64/virt-v8/linux/README | 95 ++
tests/arm64/virt-v8/linux/cmdlist | 5 +
.../linux-3.11-virtio-console-earlyprintk.patch | 61 +
.../virt-v8/linux/linux-3.11_virt_v8_defconfig | 1399 ++++++++++++++++++++
tests/arm64/virt-v8/linux/virt-v8.dts | 153 +++
120 files changed, 22502 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/board/common/guests/virt-v8x2.dtsi
create mode 100644 arch/arm/board/generic-v8/brd_defterm.c
create mode 100644 arch/arm/board/generic-v8/brd_main.c
create mode 100644 arch/arm/board/generic-v8/brd_smp.c
create mode 100644 arch/arm/board/generic-v8/dts/foundation-v8/foundation-v8.dtsi
create mode 100644 arch/arm/board/generic-v8/dts/foundation-v8/one_guest_virt_v8.dts
create mode 100644 arch/arm/board/generic-v8/dts/skeleton.dts
create mode 100644 arch/arm/board/generic-v8/include/arch_host_irq.h
create mode 100644 arch/arm/board/generic-v8/include/gic_config.h
create mode 100644 arch/arm/board/generic-v8/objects.mk
create mode 100644 arch/arm/board/generic-v8/openconf.cfg
create mode 100644 arch/arm/configs/generic-v8-defconfig
create mode 100644 arch/arm/cpu/arm64/cpu_atomic.c
create mode 100644 arch/arm/cpu/arm64/cpu_atomic64.c
create mode 100644 arch/arm/cpu/arm64/cpu_cache.S
create mode 100644 arch/arm/cpu/arm64/cpu_delay.S
create mode 100644 arch/arm/cpu/arm64/cpu_elf.c
create mode 100644 arch/arm/cpu/arm64/cpu_entry.S
create mode 100644 arch/arm/cpu/arm64/cpu_init.c
create mode 100644 arch/arm/cpu/arm64/cpu_interrupts.c
create mode 100644 arch/arm/cpu/arm64/cpu_locks.c
create mode 100644 arch/arm/cpu/arm64/cpu_smp.S
create mode 100644 arch/arm/cpu/arm64/cpu_stacktrace.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_coproc.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_emulate.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_helper.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_irq.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_mem.c
create mode 100644 arch/arm/cpu/arm64/cpu_vcpu_spr.c
create mode 100644 arch/arm/cpu/arm64/include/arch_barrier.h
create mode 100644 arch/arm/cpu/arm64/include/arch_cache.h
create mode 100644 arch/arm/cpu/arm64/include/arch_config.h
create mode 100644 arch/arm/cpu/arm64/include/arch_cpu_irq.h
create mode 100644 arch/arm/cpu/arm64/include/arch_delay.h
create mode 100644 arch/arm/cpu/arm64/include/arch_elf.h
create mode 100644 arch/arm/cpu/arm64/include/arch_io.h
create mode 100644 arch/arm/cpu/arm64/include/arch_regs.h
create mode 100644 arch/arm/cpu/arm64/include/arch_sections.h
create mode 100644 arch/arm/cpu/arm64/include/arch_types.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_cache.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_defines.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_generic_timer.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_inline_asm.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_mmu_lpae.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_vcpu_helper.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_vcpu_mem.h
create mode 100644 arch/arm/cpu/arm64/include/cpu_vcpu_spr.h
create mode 100755 arch/arm/cpu/arm64/linker.ld
create mode 100644 arch/arm/cpu/arm64/objects.mk
create mode 100644 arch/arm/cpu/arm64/openconf.cfg
create mode 100644 docs/arm/foundation_v8_boot.S
create mode 100644 tests/arm64/common/README
create mode 100644 tests/arm64/common/basic/Makefile.inc
create mode 100644 tests/arm64/common/basic/README
create mode 100644 tests/arm64/common/basic/arm_asm_macro.h
create mode 100644 tests/arm64/common/basic/arm_board.h
create mode 100644 tests/arm64/common/basic/arm_defines.h
create mode 100644 tests/arm64/common/basic/arm_entry.S
create mode 100644 tests/arm64/common/basic/arm_heap.c
create mode 100644 tests/arm64/common/basic/arm_heap.h
create mode 100644 tests/arm64/common/basic/arm_inline_asm.h
create mode 100644 tests/arm64/common/basic/arm_io.h
create mode 100644 tests/arm64/common/basic/arm_irq.c
create mode 100644 tests/arm64/common/basic/arm_irq.h
create mode 100644 tests/arm64/common/basic/arm_main.c
create mode 100644 tests/arm64/common/basic/arm_math.c
create mode 100644 tests/arm64/common/basic/arm_math.h
create mode 100644 tests/arm64/common/basic/arm_mmu.c
create mode 100644 tests/arm64/common/basic/arm_mmu.h
create mode 100644 tests/arm64/common/basic/arm_stdio.c
create mode 100644 tests/arm64/common/basic/arm_stdio.h
create mode 100644 tests/arm64/common/basic/arm_string.c
create mode 100644 tests/arm64/common/basic/arm_string.h
create mode 100644 tests/arm64/common/basic/arm_types.h
create mode 100644 tests/arm64/common/basic/dhry.h
create mode 100644 tests/arm64/common/basic/dhry_1.c
create mode 100644 tests/arm64/common/basic/dhry_2.c
create mode 100644 tests/arm64/common/basic/dhry_port.c
create mode 100644 tests/arm64/common/basic/dhry_port.h
create mode 100755 tests/arm64/common/basic/firmware.ld
create mode 100644 tests/arm64/common/basic/libfdt/cmd_fdt.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt.h
create mode 100644 tests/arm64/common/basic/libfdt/fdt_ro.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt_rw.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt_strerror.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt_support.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt_support.h
create mode 100644 tests/arm64/common/basic/libfdt/fdt_sw.c
create mode 100644 tests/arm64/common/basic/libfdt/fdt_wip.c
create mode 100644 tests/arm64/common/basic/libfdt/libfdt.h
create mode 100644 tests/arm64/common/basic/libfdt/libfdt_env.h
create mode 100644 tests/arm64/common/basic/libfdt/libfdt_internal.h
create mode 100644 tests/arm64/common/basic/pic/gic.c
create mode 100644 tests/arm64/common/basic/pic/gic.h
create mode 100644 tests/arm64/common/basic/serial/pl01x.c
create mode 100644 tests/arm64/common/basic/serial/pl01x.h
create mode 100644 tests/arm64/common/basic/serial/virtio_console.c
create mode 100644 tests/arm64/common/basic/serial/virtio_console.h
create mode 100644 tests/arm64/common/basic/timer/generic_timer.c
create mode 100644 tests/arm64/common/basic/timer/generic_timer.h
create mode 100644 tests/arm64/common/busybox/README
create mode 100644 tests/arm64/common/busybox/busybox-1.21.0_defconfig
create mode 100644 tests/arm64/common/busybox/busybox_dev.txt
create mode 100644 tests/arm64/virt-v8/README
create mode 100644 tests/arm64/virt-v8/basic/Makefile
create mode 100644 tests/arm64/virt-v8/basic/README
create mode 100644 tests/arm64/virt-v8/basic/arm_board.c
create mode 100644 tests/arm64/virt-v8/basic/arm_plat.h
create mode 100644 tests/arm64/virt-v8/basic/gic_config.h
create mode 100644 tests/arm64/virt-v8/linux/README
create mode 100644 tests/arm64/virt-v8/linux/cmdlist
create mode 100644 tests/arm64/virt-v8/linux/linux-3.11-virtio-console-earlyprintk.patch
create mode 100644 tests/arm64/virt-v8/linux/linux-3.11_virt_v8_defconfig
create mode 100644 tests/arm64/virt-v8/linux/virt-v8.dts

--
1.7.9.5

Sukanto Ghosh

unread,

Sep 15, 2013, 4:08:44 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

This is the main patch for arm64 or armv8 or aarch64 CPU support.

This new arm64 port is very much in-line with arm32ve port because
the arm64 virtualization extensions is just 64-bit version of arm32ve
virtualization extensions.

Signed-off-by: Sukanto Ghosh <sukant...@gmail.com>
---
arch/arm/cpu/arm64/cpu_atomic.c | 124 +++
arch/arm/cpu/arm64/cpu_atomic64.c | 125 +++
arch/arm/cpu/arm64/cpu_cache.S | 278 +++++++
arch/arm/cpu/arm64/cpu_delay.S | 32 +
arch/arm/cpu/arm64/cpu_elf.c | 66 ++
arch/arm/cpu/arm64/cpu_entry.S | 665 ++++++++++++++++
arch/arm/cpu/arm64/cpu_init.c | 105 +++
arch/arm/cpu/arm64/cpu_interrupts.c | 237 ++++++
arch/arm/cpu/arm64/cpu_locks.c | 202 +++++
arch/arm/cpu/arm64/cpu_smp.S | 32 +
arch/arm/cpu/arm64/cpu_stacktrace.c | 125 +++
arch/arm/cpu/arm64/cpu_vcpu_coproc.c | 306 ++++++++
arch/arm/cpu/arm64/cpu_vcpu_emulate.c | 506 ++++++++++++
arch/arm/cpu/arm64/cpu_vcpu_helper.c | 991 ++++++++++++++++++++++++
arch/arm/cpu/arm64/cpu_vcpu_irq.c | 201 +++++
arch/arm/cpu/arm64/cpu_vcpu_mem.c | 135 ++++
arch/arm/cpu/arm64/cpu_vcpu_spr.c | 359 +++++++++
arch/arm/cpu/arm64/include/arch_barrier.h | 48 ++
arch/arm/cpu/arm64/include/arch_cache.h | 56 ++

arch/arm/cpu/arm64/include/arch_config.h | 30 +
arch/arm/cpu/arm64/include/arch_cpu_irq.h | 82 ++
arch/arm/cpu/arm64/include/arch_delay.h | 39 +

arch/arm/cpu/arm64/include/arch_elf.h | 99 +++
arch/arm/cpu/arm64/include/arch_io.h | 193 +++++
arch/arm/cpu/arm64/include/arch_regs.h | 152 ++++
arch/arm/cpu/arm64/include/arch_sections.h | 69 ++
arch/arm/cpu/arm64/include/arch_types.h | 71 ++
arch/arm/cpu/arm64/include/cpu_cache.h | 76 ++
arch/arm/cpu/arm64/include/cpu_defines.h | 706 +++++++++++++++++
arch/arm/cpu/arm64/include/cpu_generic_timer.h | 159 ++++
arch/arm/cpu/arm64/include/cpu_inline_asm.h | 243 ++++++
arch/arm/cpu/arm64/include/cpu_mmu_lpae.h | 55 ++
arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h | 90 +++
arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h | 96 +++
arch/arm/cpu/arm64/include/cpu_vcpu_helper.h | 59 ++
arch/arm/cpu/arm64/include/cpu_vcpu_mem.h | 57 ++
arch/arm/cpu/arm64/include/cpu_vcpu_spr.h | 69 ++
arch/arm/cpu/arm64/linker.ld | 119 +++
arch/arm/cpu/arm64/objects.mk | 52 ++
arch/arm/cpu/arm64/openconf.cfg | 56 ++

arch/arm/cpu/common/openconf.cfg | 4 +-
arch/arm/cpu/openconf.cfg | 24 +

42 files changed, 7191 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm64/cpu_atomic.c b/arch/arm/cpu/arm64/cpu_atomic.c
new file mode 100644
index 0000000..d5eb947
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_atomic.c
@@ -0,0 +1,124 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_atomic.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief ARM64 specific synchronization mechanisms.
+ */
+
+#include <vmm_error.h>
+#include <vmm_types.h>
+#include <vmm_compiler.h>
+#include <arch_barrier.h>
+#include <arch_atomic.h>
+
+long __lock arch_atomic_read(atomic_t *atom)
+{
+ long ret = atom->counter;
+ arch_rmb();
+ return ret;
+}
+
+void __lock arch_atomic_write(atomic_t *atom, long value)
+{
+ atom->counter = value;
+ arch_wmb();
+}
+
+void __lock arch_atomic_add(atomic_t *atom, long value)
+{
+ unsigned int tmp;
+ long result;
+
+ asm volatile("// atomic_add\n"
+"1: ldxr %w0, [%3]\n"
+" add %w0, %w0, %w4\n"
+" stxr %w1, %w0, [%3]\n"
+" cbnz %w1,1b"
+ : "=&r" (result), "=&r" (tmp), "+o" (atom->counter)
+ : "r" (&atom->counter), "Ir" (value)
+ : "cc");
+}
+
+void __lock arch_atomic_sub(atomic_t *atom, long value)
+{
+ unsigned int tmp;
+ long result;
+
+ asm volatile("// atomic_sub\n"
+"1: ldxr %w0, [%3]\n"
+" sub %w0, %w0, %w4\n"
+" stxr %w1, %w0, [%3]\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+o" (atom->counter)
+ : "r" (&atom->counter), "Ir" (value)
+ : "cc");
+}
+
+long __lock arch_atomic_add_return(atomic_t *atom, long value)
+{
+ unsigned int tmp;
+ long result;
+
+ asm volatile("// atomic_add_return\n"
+"1: ldaxr %w0, [%3]\n"
+" add %w0, %w0, %w4\n"
+" stlxr %w1, %w0, [%3]\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+o" (atom->counter)
+ : "r" (&atom->counter), "Ir" (value)
+ : "cc");
+
+ return result;
+}
+
+long __lock arch_atomic_sub_return(atomic_t *atom, long value)
+{
+ unsigned int tmp;
+ long result;
+
+ asm volatile("// atomic_sub_return\n"
+"1: ldaxr %w0, [%3]\n"
+" sub %w0, %w0, %w4\n"
+" stlxr %w1, %w0, [%3]\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+o" (atom->counter)
+ : "r" (&atom->counter), "Ir" (value)
+ : "cc");
+
+ return result;
+}
+
+long __lock arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
+{
+ unsigned int tmp;
+ long previous;
+
+ asm volatile("// atomic_cmpxchg\n"
+"1: ldaxr %w1, [%3]\n"
+" cmp %w1, %w4\n"
+" b.ne 2f\n"
+" stlxr %w0, %w5, [%3]\n"
+" cbnz %w0, 1b\n"
+"2:"
+ : "=&r" (tmp), "=&r" (previous), "+o" (atom->counter)
+ : "r" (&atom->counter), "Ir" (oldval), "r" (newval)
+ : "cc");
+
+ return previous;
+}
diff --git a/arch/arm/cpu/arm64/cpu_atomic64.c b/arch/arm/cpu/arm64/cpu_atomic64.c
new file mode 100644
index 0000000..604c990
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_atomic64.c
@@ -0,0 +1,125 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_atomic64.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief ARM specific 64 bits synchronization mechanisms.
+ *
+ * derived from linux/arch/arm64/include/asm/atomic.h
+ *
+ * Copyright (C) 1996 Russell King.
+ * Copyright (C) 2002 Deep Blue Solutions Ltd.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ */
+
+#include <vmm_error.h>
+#include <vmm_types.h>
+#include <vmm_compiler.h>
+#include <arch_cpu_irq.h>
+#include <arch_barrier.h>
+#include <arch_atomic64.h>
+
+u64 __lock arch_atomic64_read(atomic64_t *atom)
+{
+ return (*(volatile long *)&atom->counter);
+}
+
+void __lock arch_atomic64_write(atomic64_t *atom, u64 value)
+{
+ atom->counter = value;
+}
+
+void __lock arch_atomic64_add(atomic64_t *atom, u64 value)
+{
+ u64 result, tmp;
+
+ asm volatile("// atomic64_add\n"
+"1: ldxr %0, %2\n"
+" add %0, %0, %3\n"
+" stxr %w1, %0, %2\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+Q" (atom->counter)
+ : "Ir" (value)
+ : "cc");
+}
+
+void __lock arch_atomic64_sub(atomic64_t *atom, u64 value)
+{
+ u64 result, tmp;
+
+ asm volatile("// atomic64_sub\n"
+"1: ldxr %0, %2\n"
+" sub %0, %0, %3\n"
+" stxr %w1, %0, %2\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+Q" (atom->counter)
+ : "Ir" (value)
+ : "cc");
+}
+
+u64 __lock arch_atomic64_add_return(atomic64_t *atom, u64 value)
+{
+ u64 result, tmp;
+
+ asm volatile("// atomic64_add_return\n"
+"1: ldaxr %0, %2\n"
+" add %0, %0, %3\n"
+" stlxr %w1, %0, %2\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+Q" (atom->counter)
+ : "Ir" (value)
+ : "cc", "memory");
+
+ return result;
+}
+
+u64 __lock arch_atomic64_sub_return(atomic64_t *atom, u64 value)
+{
+ u64 result, tmp;
+
+ asm volatile("// atomic64_sub_return\n"
+"1: ldaxr %0, %2\n"
+" sub %0, %0, %3\n"
+" stlxr %w1, %0, %2\n"
+" cbnz %w1, 1b"
+ : "=&r" (result), "=&r" (tmp), "+Q" (atom->counter)
+ : "Ir" (value)
+ : "cc", "memory");
+
+ return result;
+}
+
+u64 __lock arch_atomic64_cmpxchg(atomic64_t *atom, u64 oldval, u64 newval)
+{
+ u64 previous;
+ unsigned long res;
+
+ asm volatile("// atomic64_cmpxchg\n"
+"1: ldaxr %1, %2\n"
+" cmp %1, %3\n"
+" b.ne 2f\n"
+" stlxr %w0, %4, %2\n"
+" cbnz %w0, 1b\n"
+"2:"
+ : "=&r" (res), "=&r" (previous), "+Q" (atom->counter)
+ : "Ir" (oldval), "r" (newval)
+ : "cc", "memory");
+
+ return previous;
+}
diff --git a/arch/arm/cpu/arm64/cpu_cache.S b/arch/arm/cpu/arm64/cpu_cache.S
new file mode 100644
index 0000000..4022136
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_cache.S
@@ -0,0 +1,278 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_cache.S
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Low-level implementation of cache ARMv8 functions
+ */
+
+/* Stack pushing/popping (register pairs only).
+ Equivalent to store decrement before, load increment after */
+
+.macro push, xreg1, xreg2
+ stp \xreg1, \xreg2, [sp, #-16]!
+.endm
+
+.macro pop, xreg1, xreg2
+ ldp \xreg1, \xreg2, [sp], #16
+.endm
+
+#define lr x30
+
+/*
+ * dcache_line_size - get the minimum D-cache line size from the CTR register
+ * on ARMv8.
+ */
+.macro dcache_line_size, reg, tmp
+ mrs \tmp, ctr_el0 /* read ctr_el0 */
+ lsr \tmp, \tmp, #16
+ and \tmp, \tmp, #0xf /* cache line size encoding */
+ mov \reg, #4 /* bytes per word */
+ lsl \reg, \reg, \tmp /* actual cache line size */
+.endm
+
+/*
+ * Registers x0 - x10 are used.
+ */
+#define ARM_ENTIRE_DCACHE_OP(cacheop) \
+ \
+ push x0, x1 /* save registers */;\
+ push x2, x3 /* save registers */;\
+ push x4, x5 /* save registers */;\
+ push x6, x7 /* save registers */;\
+ push x8, x9 /* save registers */;\
+ push x10, x11 /* save registers */;\
+ dsb sy /* ensure ordering with previous memory accesses */;\
+ \
+ mrs x0, clidr_el1 /* Read CLIDR */;\
+ ands x3, x0, #0x7000000 ;\
+ lsr x3, x3, #23 /* Cache level value (naturally aligned) */; \
+ cbz x3, 5f ;\
+ mov x8, #0 ;\
+1: ;\
+ add x2, x8, x8, lsr #1 /* Work out 3xcachelevel */; \
+ lsr x1, x0, x2 /* bottom 3 bits are the Cache type for this level */; \
+ and x1, x1, #7 /* get those 3 bits alone */; \
+ cmp x1, #2 ;\
+ blt 4f /* no cache or only instruction cache at this level */; \
+ msr csselr_el1, x8 /* write the Cache Size selection register */; \
+ isb /* isb to sync the change to the CacheSizeID reg */; \
+ mrs x1, ccsidr_el1 /* reads current Cache Size ID register */; \
+ and x2, x1, #7 /* extract the line length field */; \
+ add x2, x2, #4 /* add 4 for the line length offset (log2 16 bytes) */; \
+ mov x4, #0x3ff ;\
+ ands x4, x4, x1, lsr #3 /* x4 is the max number on the way size (right aligned) */; \
+ clz w5, w4 /* x5 is the bit position of the way size increment */; \
+ mov x6, #0x7fff ;\
+ ands x6, x6, x1, lsr #13 /* x6 is the max number of the index size (right aligned) */; \
+2: ;\
+ mov x7, x4 /* x7 working copy of the max way size (right aligned) */; \
+3: ;\
+ lsl x1, x7, x5 ;\
+ orr x9, x10, x1 /* factor way and cache number into x9 */; \
+ lsl x1, x6, x2 ;\
+ orr x9, x9, x1 /* factor index number into x9 */; \
+ dc cacheop, x9 /* clean/invalidate/flush by set/way */; \
+ subs x7, x7, #1 /* decrement the way number */; \
+ bge 3b ;\
+ subs x6, x6, #1 /* decrement the index */; \
+ bge 2b ;\
+4: ;\
+ add x8, x8, #2 /* increment the cache number */; \
+ cmp x3, x8 ;\
+ bgt 1b ;\
+5: ;\
+ pop x10, x11 /* restore registers */;\
+ pop x8, x9 /* restore registers */;\
+ pop x6, x7 /* restore registers */;\
+ pop x4, x5 /* restore registers */;\
+ pop x2, x3 /* restore registers */;\
+ pop x0, x1 /* restore registers */;\
+
+ /*
+ * Operations on entire data Cache to POC
+ */
+
+ /* clean the entire data cache */
+ .globl clean_dcache
+clean_dcache:
+ ARM_ENTIRE_DCACHE_OP(csw) /* clean all */
+ dsb sy
+ isb
+ ret
+
+ /* clean & invalidate the entire data cache */
+ .globl clean_invalidate_dcache
+clean_invalidate_dcache:
+ ARM_ENTIRE_DCACHE_OP(cisw) /* clean and invalidate all */
+ dsb sy
+ isb
+ ret
+
+ /*
+ * Operations on data cache by MVA
+ */
+
+ /* clean by mva */
+ .globl clean_dcache_mva
+clean_dcache_mva:
+ dc cvac, x0
+ dsb sy
+ isb
+ ret
+
+ /* clean by memory region by mva range
+ * x0 - start address of region
+ * x1 - end address of region
+ */
+ .globl clean_dcache_mva_range
+clean_dcache_mva_range:
+ push x2, x3
+ dcache_line_size x2, x3
+ sub x3, x2, #1
+ bic x0, x0, x3
+1:
+ dc cvac, x0
+ add x0, x0, x2
+ cmp x0, x1
+ blo 1b
+ dsb sy
+ isb
+ pop x2, x3
+ ret
+
+ /* clean and invalidate by mva */
+ .globl clean_invalidate_dcache_mva
+clean_invalidate_dcache_mva:
+ dc civac, x0
+ dsb sy
+ isb
+ ret
+
+ /* clean and invalidate a memory region by mva
+ * x0 - start address of region
+ * x1 - end address of region
+ */
+ .globl clean_invalidate_dcache_mva_range
+clean_invalidate_dcache_mva_range:
+ push x2, x3
+ dcache_line_size x2, x3
+ sub x3, x2, #1
+ bic x0, x0, x3
+1:
+ dc civac, x0 /* clean & invalidate D / U line */
+ add x0, x0, x2
+ cmp x0, x1
+ blo 1b
+ dsb sy
+ isb
+ pop x2, x3
+ ret
+
+ /*
+ * Operations on data cache line by set/way
+ */
+
+ /* clean line by set/way */
+ .globl clean_dcache_line
+clean_dcache_line:
+ dc cvac, x0
+ dsb sy
+ isb
+ ret
+
+ /* clean and invalidate line by set/way */
+ .globl clean_invalidate_dcache_line
+clean_invalidate_dcache_line:
+ dc civac, x0
+ dsb sy
+ isb
+ ret
+
+ /*
+ * Operation on entire Instruction cache
+ */
+
+ /* invalidate the entire i-cache */
+ .globl invalidate_icache
+invalidate_icache:
+ ic ialluis /* invalidate all */
+ isb
+ ret
+
+ /* invalidate i-cache by mva */
+ .globl invalidate_icache_mva
+invalidate_icache_mva:
+ ic ivau, x0
+ isb
+ ret
+
+ /*
+ * Operations on entire instruction an data cache
+ */
+
+ /* clean the entire i-cache and d-cache */
+ .globl clean_idcache
+clean_idcache:
+ b clean_dcache
+
+ /* clean and invalidate the entire i-cache and d-cache */
+ .globl clean_invalidate_idcache
+clean_invalidate_idcache:
+ str lr, [sp, #8]!
+ bl invalidate_icache
+ bl clean_invalidate_dcache
+ ldr lr, [sp], #8
+ ret
+
+ /*
+ * operation on both i-cache and d-cache by mva
+ */
+
+ /* clean both i-cache and d-cache by mva */
+ .globl clean_idcache_mva
+clean_idcache_mva:
+ b clean_dcache_mva
+
+ /* clean and invalidate both i-cache and d-cache by mva */
+ .globl clean_invalidate_idcache_mva
+clean_invalidate_idcache_mva:
+ str lr, [sp, #8]!
+ bl invalidate_icache_mva
+ bl clean_invalidate_dcache_mva
+ ldr lr, [sp], #8
+ ret
+
+ /*
+ * operation on both i-cache and d-cache line by set/way
+ */
+
+ /* clean both i-cache and d-cache line by set/way */
+ .globl clean_idcache_line
+clean_idcache_line:
+ b clean_dcache_line
+
+ /* clean and invalidate both i-cache and d-cache line by set/way */
+ .globl clean_invalidate_idcache_line
+clean_invalidate_idcache_line:
+ str lr, [sp, #8]!
+ bl invalidate_icache
+ bl clean_invalidate_dcache_line
+ ldr lr, [sp], #8
+ ret
+
diff --git a/arch/arm/cpu/arm64/cpu_delay.S b/arch/arm/cpu/arm64/cpu_delay.S
new file mode 100644
index 0000000..0ecefd3
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_delay.S
@@ -0,0 +1,32 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_delay.S
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Low-level implementation of delay functions
+ */
+
+ /*
+ * arch specific delay loop
+ */
+ .globl arch_delay_loop
+arch_delay_loop:
+ subs w0, w0, #1
+ b.hi arch_delay_loop
+ ret
+
diff --git a/arch/arm/cpu/arm64/cpu_elf.c b/arch/arm/cpu/arm64/cpu_elf.c
new file mode 100644
index 0000000..d7153ac
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_elf.c
@@ -0,0 +1,66 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_elf.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief implementation of CPU specific elf functions
+ */
+
+#include <vmm_error.h>
+#include <vmm_stdio.h>
+#include <vmm_modules.h>
+#include <libs/elf.h>
+
+int arch_elf_check_hdr(const struct elf64_hdr *x)
+{
+ /* Make sure it's an AARCH64 executable */
+ if (x->e_machine != EM_AARCH64)
+ return 0;
+
+ /* Make sure the entry address is reasonable */
+ if (x->e_entry & 3)
+ return 0;
+
+ /* Don't allow unknown ABI */
+ if ((x->e_flags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) {
+ return 0;
+ }
+
+ return 1;
+}
+
+int arch_elf_apply_relocate(struct elf64_shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relindex,
+ struct vmm_module *mod)
+{
+ vmm_printf("module %s: RELOCATION unsupported\n", mod->name);
+ return 0;
+}
+
+int arch_elf_apply_relocate_add(struct elf64_shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct vmm_module *mod)
+{
+ vmm_printf("module %s: ADD RELOCATION unsupported\n", mod->name);
+ return VMM_ENOEXEC;
+}
+
diff --git a/arch/arm/cpu/arm64/cpu_entry.S b/arch/arm/cpu/arm64/cpu_entry.S
new file mode 100644
index 0000000..55e76f8
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_entry.S
@@ -0,0 +1,665 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_entry.S
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief entry points (booting, reset, exceptions) for ARMv8 family
+ */
+
+#include <cpu_defines.h>
+
+ /*
+ * _start: Primary CPU startup code
+ * _start_secondary: Secondary CPU startup code
+ *
+ * Note: Xvisor could be loaded any where in memory by boot loaders.
+ * The _start ensures that Xvisor exectues from intended
+ * base address provided at compile time.
+ */
+ .section .entry, "ax", %progbits
+ .globl _start
+ .globl _start_secondary
+_start:
+ /*
+ * x4 -> load start
+ * x5 -> load end
+ * x6 -> execution start
+ * x7 -> execution end
+ */
+ adr x4, . /* x4 <- pc */
+ ldr x6, __exec_start
+ ldr x7, __exec_end
+ sub x3, x7, x6
+ add x5, x4, x3
+
+ /* Save boot reg0 (i.e. x0) */
+ ldr x3, __boot_reg0
+ sub x3, x3, x6
+ add x3, x3, x4
+ str x0, [x3]
+
+ /* Save load start and load end addresses */
+ ldr x0, __load_start
+ sub x0, x0, x6
+ add x0, x0, x4
+ str x4, [x0]
+ ldr x0, __load_end
+ sub x0, x0, x6
+ add x0, x0, x4
+ str x5, [x0]
+
+ /* Hang if execution start is not 4 KB aligned */
+ movn x3, #0xfff
+ mov x0, x6
+ ands x0, x0, x3
+ cmp x0, x6
+ blt _start_hang
+
+ /* Hang if execution end is not 4 KB aligned */
+ mov x0, x7
+ ands x0, x0, x3
+ cmp x0, x7
+ blt _start_hang
+
+ /* Ensure that we are in hypervisor mode */
+ mrs x0, currentEL
+ cmp w0, #PSR_MODE64_EL2t
+ bne _start_hang
+
+ /*
+ * Setup Hypervisor System Control Register
+ * (we need to at least clear the A bit for
+ * _copy routine to work properly)
+ */
+ ldr x2, __hsctlr_clear
+ mrs x3, sctlr_el2
+ and x3, x3, x2
+ msr sctlr_el2, x3
+ dsb sy
+ isb
+
+ /* Zero-out bss section */
+ ldr x1, __bss_start
+ sub x1, x1, x6
+ add x1, x1, x4
+ ldr x2, __bss_end
+ sub x2, x2, x6
+ add x2, x2, x4
+_bss_zero:
+ str xzr, [x1], #8
+ cmp x1, x2
+ blt _bss_zero
+
+ /* Determine if a valid external dtb is provided */
+ /* Get DTB address */
+ ldr x3, __boot_reg0
+ sub x3, x3, x6
+ add x3, x3, x4
+ ldr x2, [x3]
+
+ /* First check for 8B alignment */
+ tst x2, #0x7
+ bne align_4k_boundary
+
+ /* Now check for FDT_MAGIC */
+ ldr w0, [x2]
+ ldr x1, __fdt_magic
+ cmp w0, w1
+ bne align_4k_boundary
+
+ /* Now get the dtb total-size */
+ ldr w0, [x2, #4]
+ rev w0, w0 /* Byte-swap as FDt is in big-endian */
+
+ /* Compare with max supported dtb size */
+ ldr x1, __max_dtb_size
+ cmp x0, x1
+ bgt align_4k_boundary
+
+ /* Overwrite the built-in fdt with the one passed */
+ ldr x1, __builtin_dtb
+ sub x1, x1, x6
+ add x1, x1, x4
+
+ /* x0 = dtb total size */
+ /* x1 = builtin_dtb load-address */
+ /* x2 = passed dtb address */
+
+dtb_save_loop:
+ ldr x3, [x2], #8
+ str x3, [x1], #8
+ subs x0, x0, #8
+ bgt dtb_save_loop
+
+align_4k_boundary:
+ /* Relocate code if load start is not 4 KB aligned */
+ mov x0, x4
+ movn x3, #0xfff
+ ands x0, x0, x3
+ cmp x0, x4
+ b.eq _start_mmu_init
+
+_start_relocate:
+ /* Relocate copy function at end after load end address */
+ ldr x0, __copy_start
+ ldr x1, __copy_end
+ sub x2, x1, x0
+ sub x0, x0, x6
+ add x0, x0, x4
+ mov x1, x0
+ mov x0, x5
+ bl _copy
+ /*
+ * Use newly relocated copy function to relocate entire code
+ */
+ mov x1, x4
+ mov x0, x5
+ sub x2, x5, x4
+ mov x0, x4
+ movn x3, #0xfff
+ ands x0, x0, x3
+ bl _start_nextpc1
+_start_nextpc1:
+ add x30, x30, #16
+ sub x30, x30, x4
+ add x30, x30, x0
+ br x5
+ /*
+ * Update load start and load end
+ * x4 -> new load start
+ * x5 -> new load end
+ */
+ mov x0, x4
+ movn x3, #0xfff
+ ands x0, x0, x3
+ sub x1, x4, x0
+ sub x4, x4, x1
+ sub x5, x5, x1
+ ldr x0, __load_start
+ sub x0, x0, x6
+ add x0, x0, x4
+ str x4, [x0]
+ ldr x0, __load_end
+ sub x0, x0, x6
+ add x0, x0, x4
+ str x5, [x0]
+
+_start_mmu_init:
+ /* Setup SP as-per load address */
+ ldr x0, __hvc_stack_end
+ mov sp, x0
+ sub sp, sp, x6
+ add sp, sp, x4
+
+ /* Saving x4 .. x7 in callee-saved regs */
+ mov x21, x4
+ mov x22, x5
+ mov x23, x6
+ mov x24, x7
+
+ /* Setup arguments and call setup_initial_ttbl */
+ mov x0, x4
+ mov x1, x5
+ mov x2, x6
+ mov x3, x7
+
+ bl _setup_initial_ttbl
+
+ /* Restoring x4 .. x7 from callee-saved regs */
+ mov x4, x21
+ mov x5, x22
+ mov x6, x23
+ mov x7, x24
+
+ /* Update the httbr value */
+ ldr x1, __httbr_set_addr
+ sub x1, x1, x6
+ add x1, x1, x4
+ ldr x0, [x1]
+ sub x0, x0, x6
+ add x0, x0, x4
+ str x0, [x1]
+ b _common_init
+
+#ifdef CONFIG_SMP
+ .align 3
+1: .dword .
+ .dword secondary_holding_pen_release
+__leds_base:
+ .dword 0x1c010008
+
+#define MPIDR_HWID_BITMASK 0xff00ffffff
+
+ /*
+ * Secondary CPU startup code
+ */
+_start_secondary:
+ /*
+ * This provides a "holding pen" for platforms to hold all secondary
+ * cores are held until we're ready for them to initialise.
+ */
+ ldr x15, __leds_base
+ mov w14, #0
+ str w14, [x15]
+
+ mrs x0, mpidr_el1
+ ldr x1, =MPIDR_HWID_BITMASK
+ and x0, x0, x1
+
+ /* Calculate load address of secondary_holding_pen_release */
+ adr x1, 1b
+ ldp x2, x3, [x1]
+ sub x1, x1, x2
+ add x3, x3, x1
+ sevl
+pen: wfe
+ ldr x4, [x3]
+ cmp x4, x0
+ bne pen
+#endif
+
+ /*
+ * Note: From this point primary CPU startup is same as secondary CPU
+ */
+_common_init:
+ /* Disable IRQ & FIQ */
+ msr daifset, #3
+
+ /* Ensure that we are in hypervisor mode */
+ mrs x0, currentEL
+ cmp w0, #PSR_MODE64_EL2t
+ bne _start_hang
+
+ /* Setup Hypervisor MAIR0 & MAIR1 */
+ ldr x0, __hmair_set
+ msr mair_el2, x0
+
+ /* Setup Hypervisor Translation Control Register */
+ ldr x0, __htcr_set
+ msr tcr_el2, x0
+
+ /* Setup Hypervisor Translation Base Register */
+ ldr x0, __httbr_set
+ msr ttbr0_el2, x0
+
+ /* Setup Hypervisor Stage2 Translation Control Register */
+ ldr x0, __vtcr_set
+ msr vtcr_el2, x0
+
+ /* Setup HCR */
+ ldr x0, __hcr_set
+ msr hcr_el2, x0
+
+ /* Setup temporary vector containing branch to self for debug */
+ ldr x0, __vbar_val
+ msr vbar_el2, x0
+
+ /* Set Hypervisor Stack */
+ ldr x0, __hvc_stack_end
+#ifdef CONFIG_SMP
+ mov x1, #CONFIG_IRQ_STACK_SIZE
+ mrs x10, mpidr_el1
+ ldr x2, =MPIDR_HWID_BITMASK
+ and x10, x2, x10
+ mul x1, x1, x10
+ sub x0, x0, x1
+#endif
+ mov sp, x0
+
+ /* Setup Hypervisor System Control Register */
+ ldr x1, __hsctlr_set
+ mrs x3, sctlr_el2
+ orr x3, x3, x1
+ msr sctlr_el2, x3
+ dsb sy
+ isb
+
+ ldr x0, __cpu_init
+ blr x0
+
+_start_hang:
+ b .
+
+#define FDT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
+
+ .align 3
+__fdt_magic:
+ .dword FDT_MAGIC
+__builtin_dtb:
+ .dword dt_blob_start
+__max_dtb_size:
+ .dword CONFIG_ARM_MAX_DTB_SIZE
+__hmair_set:
+ .dword (MAIR_INITVAL)
+__htcr_set:
+ .dword ((0x19 << TCR_T0SZ_SHIFT) | (0x2 << TCR_PS_SHIFT) | (0x3 << TCR_SH0_SHIFT) | (0x1 << TCR_ORGN0_SHIFT) | (0x1 << TCR_IRGN0_SHIFT))
+__vtcr_set:
+ .dword ((0x1 << VTCR_SL0_SHIFT) | (0x19 << VTCR_T0SZ_SHIFT) | (0x2 << VTCR_PS_SHIFT) | (0x3 << VTCR_SH0_SHIFT) | (0x1 << VTCR_ORGN0_SHIFT) | (0x1 << VTCR_IRGN0_SHIFT))
+__hsctlr_clear:
+ .dword ~(SCTLR_A_MASK)
+__hsctlr_set:
+ .dword (SCTLR_M_MASK | SCTLR_C_MASK | SCTLR_I_MASK)
+__hcr_set:
+ .dword (HCR_AMO_MASK | HCR_IMO_MASK | HCR_FMO_MASK | HCR_VM_MASK)
+__exec_start:
+ .dword _code_start
+__exec_end:
+ .dword _code_end
+__load_start:
+ .dword _load_start
+__load_end:
+ .dword _load_end
+__bss_start:
+ .dword _bss_start
+__bss_end:
+ .dword _bss_end
+__copy_start:
+ .dword _copy
+__copy_end:
+ .dword _copy_end
+__httbr_set_addr:
+ .dword __httbr_set
+__httbr_set:
+ .dword def_ttbl
+__cpu_init:
+ .dword cpu_init
+__vbar_val:
+ .dword vectors
+__boot_reg0:
+ .dword _boot_reg0
+
+ /*
+ * Boot register 0 passed by bootloader
+ */
+ .globl _boot_reg0
+_boot_reg0:
+ .dword 0x0
+
+ /*
+ * Load start address storage
+ */
+ .globl _load_start
+_load_start:
+ .dword 0x0
+
+ /*
+ * Load end address storage
+ */
+ .globl _load_end
+_load_end:
+ .dword 0x0
+
+ /*
+ * Exception stacks.
+ */
+__hvc_stack_end:
+ .dword _hvc_stack_end
+
+ /*
+ * Copy data from source to destination
+ * (alignment handled by hardware)
+ * Arguments:
+ * x0 -> destination address
+ * x1 -> source address
+ * x2 -> byte count
+ * Return:
+ * x0 -> bytes copied
+ */
+ .section .entry, "ax", %progbits
+ .globl _copy
+_copy:
+ mov x4, x2
+ subs x2, x2, #8
+ b.mi 2f
+1: ldr x3, [x1], #8
+ subs x2, x2, #8
+ str x3, [x0], #8
+ b.pl 1b
+2: adds x2, x2, #4
+ b.mi 3f
+ ldr w3, [x1], #4
+ sub x2, x2, #4
+ str w3, [x0], #4
+3: adds x2, x2, #2
+ b.mi 4f
+ ldrh w3, [x1], #2
+ sub x2, x2, #2
+ strh w3, [x0], #2
+4: adds x2, x2, #1
+ b.mi 5f
+ ldrb w3, [x1]
+ strb w3, [x0]
+5: mov x0, x4
+ ret
+_copy_end:
+
+
+
+
+/* Stack pushing/popping (register pairs only).
+ Equivalent to store decrement before, load increment after */
+
+.macro push, xreg1, xreg2
+ stp \xreg1, \xreg2, [sp, #-16]!
+.endm
+
+.macro pop, xreg1, xreg2
+ ldp \xreg1, \xreg2, [sp], #16
+.endm
+
+
+.macro EXCEPTION_HANDLER irqname
+ .align 6
+\irqname:
+.endm
+
+
+/* Push registers on stack */
+.macro PUSH_REGS
+ sub sp, sp, #0x20 /* room for LR, SP, SPSR, ELR */
+ push x28, x29
+ push x26, x27
+ push x24, x25
+ push x22, x23
+ push x20, x21
+ push x18, x19
+ push x16, x17
+ push x14, x15
+ push x12, x13
+ push x10, x11
+ push x8, x9
+ push x6, x7
+ push x4, x5
+ push x2, x3
+ push x0, x1
+ add x21, sp, #0x110
+ mrs x22, elr_el2
+ mrs x23, spsr_el2
+ stp x30, x21, [sp, #0xF0]
+ stp x22, x23, [sp, #0x100]
+ /*
+ * Registers that may be useful after this macro is invoked:
+ *
+ * x21 - aborted SP
+ * x22 - aborted PC
+ * x23 - aborted PSTATE
+ */
+.endm
+
+/* Call C function to handle exception */
+.macro CALL_EXCEPTION_CFUNC cfunc
+ mov x0, sp
+ bl \cfunc
+.endm
+
+/* Pull registers from stack */
+.macro PULL_REGS
+ ldp x21, x22, [sp, #0x100] /* load ELR, SPSR */
+ msr elr_el2, x21
+ msr spsr_el2, x22
+ pop x0, x1
+ pop x2, x3
+ pop x4, x5
+ pop x6, x7
+ pop x8, x9
+ pop x10, x11
+ pop x12, x13
+ pop x14, x15
+ pop x16, x17
+ pop x18, x19
+ pop x20, x21
+ pop x22, x23
+ pop x24, x25
+ pop x26, x27
+ pop x28, x29
+ msr tpidr_el2, x24
+ ldp x30, x24, [sp]
+ mov sp, x24
+ mrs x24, tpidr_el2
+ eret
+.endm
+
+
+/*
+ * Exception vectors.
+ */
+.macro ventry label
+ .align 7
+ b \label
+.endm
+
+ .align 11
+ .globl vectors;
+vectors:
+ ventry hyp_sync_invalid /* Synchronous EL1t */
+ ventry hyp_irq_invalid /* IRQ EL1t */
+ ventry hyp_fiq_invalid /* FIQ EL1t */
+ ventry hyp_error_invalid /* Error EL1t */
+
+ ventry hyp_sync /* Synchronous EL1h */
+ ventry hyp_irq /* IRQ EL1h */
+ ventry hyp_fiq_invalid /* FIQ EL1h */
+ ventry hyp_error_invalid /* Error EL1h */
+
+ ventry guest_sync_a64 /* Synchronous 64-bit EL0 */
+ ventry guest_irq_a64 /* IRQ 64-bit EL0 */
+ ventry guest_fiq_a64 /* FIQ 64-bit EL0 */
+ ventry guest_error_a64 /* Error 64-bit EL0 */
+
+ ventry guest_sync_a32 /* Synchronous 32-bit EL0 */
+ ventry guest_irq_a32 /* IRQ 32-bit EL0 */
+ ventry guest_fiq_a32 /* FIQ 32-bit EL0 */
+ ventry guest_error_a32 /* Error 32-bit EL0 */
+
+
+EXCEPTION_HANDLER hyp_sync_invalid
+ PUSH_REGS
+ mov x1, EXC_HYP_SYNC_SP0
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_irq_invalid
+ PUSH_REGS
+ mov x1, EXC_HYP_IRQ_SP0
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_fiq_invalid
+ PUSH_REGS
+ mov x1, EXC_HYP_FIQ_SP0
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_error_invalid
+ PUSH_REGS
+ mov x1, EXC_HYP_SERROR_SP0
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_sync
+ PUSH_REGS
+ mov x1, EXC_HYP_SYNC_SPx
+ CALL_EXCEPTION_CFUNC do_sync
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_irq
+ PUSH_REGS
+ mov x1, EXC_HYP_IRQ_SPx
+ CALL_EXCEPTION_CFUNC do_irq
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_fiq
+ PUSH_REGS
+ mov x1, EXC_HYP_FIQ_SPx
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER hyp_error
+ PUSH_REGS
+ mov x1, EXC_HYP_SERROR_SPx
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_sync_a64
+ PUSH_REGS
+ mov x1, EXC_GUEST_SYNC_A64
+ CALL_EXCEPTION_CFUNC do_sync
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_irq_a64
+ PUSH_REGS
+ mov x1, EXC_GUEST_IRQ_A64
+ CALL_EXCEPTION_CFUNC do_irq
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_fiq_a64
+ PUSH_REGS
+ mov x1, EXC_GUEST_FIQ_A64
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_error_a64
+ PUSH_REGS
+ mov x1, EXC_GUEST_SERROR_A64
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_sync_a32
+ PUSH_REGS
+ mov x1, EXC_GUEST_SYNC_A32
+ CALL_EXCEPTION_CFUNC do_sync
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_irq_a32
+ PUSH_REGS
+ mov x1, EXC_GUEST_IRQ_A32
+ CALL_EXCEPTION_CFUNC do_irq
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_fiq_a32
+ PUSH_REGS
+ mov x1, EXC_GUEST_FIQ_A32
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
+EXCEPTION_HANDLER guest_error_a32
+ PUSH_REGS
+ mov x1, EXC_GUEST_SERROR_A32
+ CALL_EXCEPTION_CFUNC do_bad_mode
+ PULL_REGS
+
diff --git a/arch/arm/cpu/arm64/cpu_init.c b/arch/arm/cpu/arm64/cpu_init.c
new file mode 100644
index 0000000..5f7df86
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_init.c
@@ -0,0 +1,105 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_init.c
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief intialization functions for CPU
+ */
+
+#include <vmm_error.h>
+#include <vmm_smp.h>
+#include <vmm_main.h>
+#include <vmm_params.h>
+#include <vmm_devtree.h>
+#include <arch_cpu.h>
+
+extern u8 _code_start;
+extern u8 _code_end;
+extern physical_addr_t _load_start;
+extern physical_addr_t _load_end;
+
+virtual_addr_t arch_code_vaddr_start(void)
+{
+ return (virtual_addr_t) &_code_start;
+}
+
+physical_addr_t arch_code_paddr_start(void)
+{
+ return (physical_addr_t) _load_start;
+}
+
+virtual_size_t arch_code_size(void)
+{
+ return (virtual_size_t) (&_code_end - &_code_start);
+}
+
+int __init arch_cpu_early_init(void)
+{
+ char *attr;
+ struct vmm_devtree_node *node;
+
+ /*
+ * Host virtual memory, device tree, heap is up.
+ * Do necessary early stuff like iomapping devices
+ * memory or boot time memory reservation here.
+ */
+
+ node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING
+ VMM_DEVTREE_CHOSEN_NODE_NAME);
+ if (!node) {
+ return VMM_ENODEV;
+ }
+
+ attr = vmm_devtree_attrval(node, VMM_DEVTREE_BOOTARGS_ATTR_NAME);
+ if (attr) {
+ vmm_parse_early_options(attr);
+ }
+
+ return VMM_OK;
+}
+
+void arch_cpu_print_info(struct vmm_chardev *cdev)
+{
+ /* FIXME: To be implemented. */
+}
+
+int __init arch_cpu_final_init(void)
+{
+ /* All VMM API's are available here */
+ /* We can register a CPU specific resources here */
+ return VMM_OK;
+}
+
+void __init cpu_init(void)
+{
+#if defined(CONFIG_SMP)
+ u32 cpu = vmm_smp_processor_id();
+
+ if (!cpu) { /* Primary CPU */
+ vmm_init();
+ } else { /* Secondary CPUs */
+ vmm_init_secondary();
+ }
+#else
+ /* Initialize VMM (APIs only available after this) */
+ vmm_init();
+#endif
+
+ /* We will never come back here. */
+ vmm_hang();
+}
diff --git a/arch/arm/cpu/arm64/cpu_interrupts.c b/arch/arm/cpu/arm64/cpu_interrupts.c
new file mode 100644
index 0000000..64824e8
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_interrupts.c
@@ -0,0 +1,237 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_interrupts.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief source code for handling cpu interrupts
+ */
+
+#include <vmm_error.h>
+#include <vmm_smp.h>
+#include <vmm_stdio.h>
+#include <vmm_host_irq.h>
+#include <vmm_scheduler.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_spr.h>
+#include <cpu_vcpu_emulate.h>
+#include <cpu_vcpu_helper.h>
+#include <cpu_defines.h>
+
+void do_bad_mode(arch_regs_t *regs, unsigned long mode)
+{
+ u32 ec, il, iss;
+ u64 esr, far, elr;
+ struct vmm_vcpu *vcpu;
+
+ esr = mrs(esr_el2);
+ far = mrs(far_el2);
+ elr = mrs(elr_el2);
+
+ ec = (esr & ESR_EC_MASK) >> ESR_EC_SHIFT;
+ il = (esr & ESR_IL_MASK) >> ESR_IL_SHIFT;
+ iss = (esr & ESR_ISS_MASK) >> ESR_ISS_SHIFT;
+
+ vcpu = vmm_scheduler_current_vcpu();
+
+ vmm_printf("%s: CPU%d VCPU=%s unexpected exception\n",
+ __func__, vmm_smp_processor_id(),
+ (vcpu) ? vcpu->name : "(NULL)");
+ vmm_printf("%s: ESR=0x%016lx EC=0x%x IL=0x%x ISS=0x%x\n",
+ __func__, esr, ec, il, iss);
+ vmm_printf("%s: ELR=0x%016lx FAR=0x%016lx HPFAR=0x%016lx\n",
+ __func__, elr, far, mrs(hpfar_el2));
+ cpu_vcpu_dump_user_reg(regs);
+ vmm_panic("%s: please reboot ...\n", __func__);
+}
+
+void do_sync(arch_regs_t *regs, unsigned long mode)
+{
+ int rc = VMM_OK;
+ u32 ec, il, iss;
+ u64 esr, far, elr;
+ physical_addr_t fipa = 0;
+ struct vmm_vcpu *vcpu;
+
+ esr = mrs(esr_el2);
+ far = mrs(far_el2);
+ elr = mrs(elr_el2);
+
+ ec = (esr & ESR_EC_MASK) >> ESR_EC_SHIFT;
+ il = (esr & ESR_IL_MASK) >> ESR_IL_SHIFT;
+ iss = (esr & ESR_ISS_MASK) >> ESR_ISS_SHIFT;
+
+ vcpu = vmm_scheduler_current_vcpu();
+
+ /* We dont expect any faults from hypervisor code itself
+ * so, any trap we get from hypervisor mode means something
+ * unexpected has occured.
+ */
+ if ((regs->pstate & PSR_EL_MASK) == PSR_EL_2) {
+ if ((ec == EC_TRAP_HVC_A64) && (iss == 0)) {
+ vmm_scheduler_preempt_orphan(regs);
+ return;
+ }
+ vmm_printf("%s: CPU%d VCPU=%s unexpected exception\n",
+ __func__, vmm_smp_processor_id(),
+ (vcpu) ? vcpu->name : "(NULL)");
+ vmm_printf("%s: ESR=0x%016lx EC=0x%x IL=0x%x ISS=0x%x\n",
+ __func__, esr, ec, il, iss);
+ vmm_printf("%s: ELR=0x%016lx FAR=0x%016lx HPFAR=0x%016lx\n",
+ __func__, elr, far, mrs(hpfar_el2));
+ cpu_vcpu_dump_user_reg(regs);
+ vmm_panic("%s: please reboot ...\n", __func__);
+ }
+
+ vmm_scheduler_irq_enter(regs, TRUE);
+
+ switch (ec) {
+ case EC_UNKNOWN:
+ /* We dont expect to get this trap so error */
+ rc = VMM_EFAIL;
+ break;
+ case EC_TRAP_WFI_WFE:
+ /* WFI emulation */
+ rc = cpu_vcpu_emulate_wfi_wfe(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_MCR_MRC_CP15_A32:
+ /* MCR/MRC CP15 emulation */
+ rc = cpu_vcpu_emulate_mcr_mrc_cp15(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_MCRR_MRRC_CP15_A32:
+ /* MCRR/MRRC CP15 emulation */
+ rc = cpu_vcpu_emulate_mcrr_mrrc_cp15(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_MCR_MRC_CP14_A32:
+ /* MCR/MRC CP14 emulation */
+ rc = cpu_vcpu_emulate_mcr_mrc_cp14(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_LDC_STC_CP14_A32:
+ /* LDC/STC CP14 emulation */
+ rc = cpu_vcpu_emulate_ldc_stc_cp14(vcpu, regs, il, iss);
+ break;
+ case EC_SIMD_FPU:
+ /* Advanced SIMD and FPU emulation */
+ rc = cpu_vcpu_emulate_simd_fp_regs(vcpu, regs, il, iss);
+ break;
+ case EC_FPEXC_A32:
+ case EC_FPEXC_A64:
+ /* We dont expect any FP execution faults */
+ rc = VMM_EFAIL;
+ break;
+ case EC_TRAP_MRC_VMRS_CP10_A32:
+ /* MRC (or VMRS) to CP10 for MVFR0, MVFR1 or FPSID */
+ rc = cpu_vcpu_emulate_vmrs(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_MCRR_MRRC_CP14_A32:
+ /* MRRC to CP14 emulation */
+ rc = cpu_vcpu_emulate_mcrr_mrrc_cp14(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_SVC_A32:
+ case EC_TRAP_SVC_A64:
+ case EC_TRAP_SMC_A32:
+ case EC_TRAP_SMC_A64:
+ /* We dont expect to get these traps so error */
+ rc = VMM_EFAIL;
+ break;
+ case EC_TRAP_HVC_A32:
+ /* Hypercall or HVC emulation for A32 guest */
+ rc = cpu_vcpu_emulate_hvc32(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_HVC_A64:
+ /* Hypercall or HVC emulation for A64 guest */
+ rc = cpu_vcpu_emulate_hvc64(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_MSR_MRS_SYSTEM:
+ /* MSR/MRS/SystemRegs emulation */
+ rc = cpu_vcpu_emulate_msr_mrs_system(vcpu, regs, il, iss);
+ break;
+ case EC_TRAP_LWREL_INST_ABORT:
+ /* Stage2 instruction abort */
+ fipa = (mrs(hpfar_el2) & HPFAR_FIPA_MASK) >> HPFAR_FIPA_SHIFT;
+ fipa = fipa << HPFAR_FIPA_PAGE_SHIFT;
+ fipa = fipa | (mrs(far_el2) & HPFAR_FIPA_PAGE_MASK);
+ rc = cpu_vcpu_inst_abort(vcpu, regs, il, iss, fipa);
+ break;
+ case EC_TRAP_LWREL_DATA_ABORT:
+ /* Stage2 data abort */
+ fipa = (mrs(hpfar_el2) & HPFAR_FIPA_MASK) >> HPFAR_FIPA_SHIFT;
+ fipa = fipa << HPFAR_FIPA_PAGE_SHIFT;
+ fipa = fipa | (mrs(far_el2) & HPFAR_FIPA_PAGE_MASK);
+ rc = cpu_vcpu_data_abort(vcpu, regs, il, iss, fipa);
+ break;
+ case EC_CUREL_INST_ABORT:
+ case EC_CUREL_DATA_ABORT:
+ case EC_SERROR:
+ /* We dont expect to get aborts from EL2 so error */
+ rc = VMM_EFAIL;
+ break;
+ case EC_PC_UNALIGNED:
+ case EC_SP_UNALIGNED:
+ /* We dont expect to get alignment faults from EL2 */
+ rc = VMM_EFAIL;
+ break;
+ default:
+ /* Unhandled or unknown EC value so error */
+ rc = VMM_EFAIL;
+ break;
+ };
+
+ if (rc) {
+ vmm_printf("%s: CPU%d VCPU=%s sync failed (error %d)\n",
+ __func__, vmm_smp_processor_id(),
+ (vcpu) ? vcpu->name : "(NULL)", rc);
+ vmm_printf("%s: ESR=0x%016lx EC=0x%x IL=0x%x ISS=0x%x\n",
+ __func__, esr, ec, il, iss);
+ vmm_printf("%s: ELR=0x%016lx FAR=0x%016lx HPFAR=0x%016lx\n",
+ __func__, elr, far, mrs(hpfar_el2));
+ if (vcpu->state != VMM_VCPU_STATE_HALTED) {
+ cpu_vcpu_halt(vcpu, regs);
+ }
+ }
+
+ vmm_scheduler_irq_exit(regs);
+}
+
+void do_irq(arch_regs_t *regs)
+{
+ vmm_scheduler_irq_enter(regs, FALSE);
+
+ vmm_host_irq_exec(EXC_HYP_IRQ_SPx);
+
+ vmm_scheduler_irq_exit(regs);
+}
+
+void do_hyp_fiq(arch_regs_t *regs)
+{
+ vmm_scheduler_irq_enter(regs, FALSE);
+
+ vmm_host_irq_exec(CPU_EXTERNAL_FIQ);
+
+ vmm_scheduler_irq_exit(regs);
+}
+
+int __cpuinit arch_cpu_irq_setup(void)
+{
+ extern u32 vectors[];
+
+ /* Update VBAR_EL2 to point to hypervisor vector table */
+ msr_sync(vbar_el2, (virtual_addr_t)&vectors);
+
+ return VMM_OK;
+}
+
diff --git a/arch/arm/cpu/arm64/cpu_locks.c b/arch/arm/cpu/arm64/cpu_locks.c
new file mode 100644
index 0000000..2feb633
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_locks.c
@@ -0,0 +1,202 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_locks.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief ARM64 specific synchronization mechanisms.
+ */
+
+#include <vmm_error.h>
+#include <vmm_types.h>
+#include <vmm_smp.h>
+#include <vmm_compiler.h>
+#include <arch_barrier.h>
+
+bool __lock arch_spin_lock_check(arch_spinlock_t *lock)
+{
+ return (lock->lock == __ARCH_SPIN_UNLOCKED) ? FALSE : TRUE;
+}
+
+void __lock arch_spin_lock(arch_spinlock_t *lock)
+{
+ u32 cpu = vmm_smp_processor_id();
+ unsigned long tmp;
+
+ __asm__ __volatile__(
+" sevl\n"
+"1: wfe\n"
+"2: ldaxr %w0, %1\n"
+" cmp %w0, %w3\n"
+" b.ne 1b\n"
+" stxr %w0, %w2, %1\n"
+" cbnz %w0, 2b\n"
+ : "=&r" (tmp), "+Q" (lock->lock)
+ : "r" (cpu), "r" (__ARCH_SPIN_UNLOCKED)
+ : "cc", "memory");
+
+ arch_smp_mb();
+}
+
+int arch_spin_trylock(arch_spinlock_t *lock)
+{
+ u32 cpu = vmm_smp_processor_id();
+ unsigned int tmp;
+
+ asm volatile(
+" ldaxr %w0, %1\n"
+" cmp %w0, %w3\n"
+" b.ne 1f\n"
+" stxr %w0, %w2, %1\n"
+" b 2f\n"
+"1: mov %w0, #1\n"
+"2:\n"
+ : "=&r" (tmp), "+Q" (lock->lock)
+ : "r" (cpu), "r" (__ARCH_SPIN_UNLOCKED)
+ : "cc", "memory");
+
+ if (tmp == 0) {
+ arch_smp_mb(); /* do mb if we succeeded */
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+void __lock arch_spin_unlock(arch_spinlock_t *lock)
+{
+ arch_smp_mb();
+
+ __asm__ __volatile__(
+" stlr %w1, %0\n"
+ : "=Q" (lock->lock) : "r" (__ARCH_SPIN_UNLOCKED)
+ : "memory");
+}
+
+bool __lock arch_write_lock_check(arch_rwlock_t *lock)
+{
+ return (lock->lock & __ARCH_RW_LOCKED) ? TRUE : FALSE;
+}
+
+/*
+ * To take a write lock we set bit 31 to 1
+ */
+void __lock arch_write_lock(arch_rwlock_t *lock)
+{
+ unsigned int tmp;
+
+ __asm__ __volatile__(
+ " sevl\n"
+ "1: wfe\n"
+ "2: ldaxr %w0, [%1]\n"
+ " cbnz %w0, 1b\n"
+ " stxr %w0, %w2, [%1]\n"
+ " cbnz %w0, 2b\n"
+ : "=&r" (tmp)
+ : "r" (&lock->lock), "r" (__ARCH_RW_LOCKED)
+ : "memory");
+
+ arch_smp_mb();
+}
+
+int __lock arch_write_trylock(arch_rwlock_t *lock)
+{
+ unsigned int tmp;
+
+ asm volatile(
+ " ldaxr %w0, [%1]\n"
+ " cbnz %w0, 1f\n"
+ " stxr %w0, %w2, [%1]\n"
+ "1:\n"
+ : "=&r" (tmp)
+ : "r" (&lock->lock), "r" (__ARCH_RW_LOCKED)
+ : "memory");
+
+ if (tmp == 0) {
+ arch_smp_mb();
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+void __lock arch_write_unlock(arch_rwlock_t *lock)
+{
+ asm volatile(
+ " stlr %w1, [%0]\n"
+ : : "r" (&lock->lock), "r" (0) : "memory");
+}
+
+bool __lock arch_read_lock_check(arch_rwlock_t *lock)
+{
+ return (lock->lock == __ARCH_RW_UNLOCKED) ? FALSE : TRUE;
+}
+
+void __lock arch_read_lock(arch_rwlock_t *lock)
+{
+ unsigned int tmp, tmp2;
+
+ asm volatile(
+ " sevl\n"
+ "1: wfe\n"
+ "2: ldaxr %w0, [%2]\n"
+ " add %w0, %w0, #1\n"
+ " tbnz %w0, #31, 1b\n"
+ " stxr %w1, %w0, [%2]\n"
+ " cbnz %w1, 2b\n"
+ : "=&r" (tmp), "=&r" (tmp2)
+ : "r" (&lock->lock)
+ : "memory");
+}
+
+int __lock arch_read_trylock(arch_rwlock_t *lock)
+{
+ unsigned int tmp, tmp2 = 1;
+
+ asm volatile(
+ " ldaxr %w0, [%2]\n"
+ " add %w0, %w0, #1\n"
+ " tbnz %w0, #31, 1f\n"
+ " stxr %w1, %w0, [%2]\n"
+ "1:\n"
+ : "=&r" (tmp), "+r" (tmp2)
+ : "r" (&lock->lock)
+ : "memory");
+
+ if (tmp2 == 0) {
+ arch_smp_mb(); /* do mb if we succeeded */
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+void __lock arch_read_unlock(arch_rwlock_t *lock)
+{
+ unsigned int tmp, tmp2;
+
+ arch_smp_mb();
+
+ asm volatile(
+ "1: ldxr %w0, [%2]\n"
+ " sub %w0, %w0, #1\n"
+ " stlxr %w1, %w0, [%2]\n"
+ " cbnz %w1, 1b\n"
+ : "=&r" (tmp), "=&r" (tmp2)
+ : "r" (&lock->lock)
+ : "memory");
+}
diff --git a/arch/arm/cpu/arm64/cpu_smp.S b/arch/arm/cpu/arm64/cpu_smp.S
new file mode 100644
index 0000000..4885187
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_smp.S
@@ -0,0 +1,32 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_smp.S
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Low-level implementation of SMP functions
+ */
+
+ /*
+ * Retrive SMP ID of current processor
+ */
+ .globl arch_smp_id
+arch_smp_id:
+ mrs x0, mpidr_el1
+ ands x0, x0, #0xff
+ ret
+
diff --git a/arch/arm/cpu/arm64/cpu_stacktrace.c b/arch/arm/cpu/arm64/cpu_stacktrace.c
new file mode 100644
index 0000000..9567fc6
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_stacktrace.c
@@ -0,0 +1,125 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_stacktrace.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief ARM64 specific function stacktrace.
+ *
+ * Portions of this file are derived from arch/arm/kernel/stacktrace.c
+ * in linux source
+ *
+ */
+
+#include <vmm_compiler.h>
+#include <vmm_stdio.h>
+#include <vmm_error.h>
+#include <libs/kallsyms.h>
+#include <libs/stacktrace.h>
+
+struct stackframe {
+ unsigned long fp;
+ unsigned long sp;
+ unsigned long lr;
+ unsigned long pc;
+};
+
+/*
+ * AArch64 PCS assigns the frame pointer to x29.
+ *
+ * A simple function prologue looks like this:
+ * sub sp, sp, #0x10
+ * stp x29, x30, [sp]
+ * mov x29, sp
+ *
+ * A simple function epilogue looks like this:
+ * mov sp, x29
+ * ldp x29, x30, [sp]
+ * add sp, sp, #0x10
+ */
+int unwind_frame(struct stackframe *frame)
+{
+ unsigned long low;
+ unsigned long fp = frame->fp;
+
+ low = frame->sp;
+
+ // if (fp < low || fp & 0xf)
+ if (fp < low)
+ return -1;
+
+ frame->sp = fp + 0x10;
+ frame->fp = *(unsigned long *)(fp);
+ frame->pc = *(unsigned long *)(fp + 8);
+
+ return 0;
+}
+
+void walk_stackframe(struct stackframe *frame,
+ int (*fn)(struct stackframe *, void *), void *data)
+{
+ while (1) {
+ int ret;
+
+ if (fn(frame, data))
+ break;
+ ret = unwind_frame(frame);
+ if (ret < 0)
+ break;
+ }
+}
+
+struct stack_trace_data {
+ struct stack_trace *trace;
+ unsigned int skip;
+};
+
+static int save_trace(struct stackframe *frame, void *d)
+{
+ struct stack_trace_data *data = d;
+ struct stack_trace *trace = data->trace;
+ unsigned long addr = frame->pc;
+
+ if (data->skip) {
+ data->skip--;
+ return 0;
+ }
+
+ trace->entries[trace->nr_entries++] = addr;
+
+ return trace->nr_entries >= trace->max_entries;
+}
+
+void arch_save_stacktrace(struct stack_trace *trace)
+{
+ struct stack_trace_data data;
+ struct stackframe frame;
+
+ data.trace = trace;
+ data.skip = trace->skip;
+
+ register unsigned long current_sp asm ("sp");
+
+ frame.fp = (unsigned long)__builtin_frame_address(0);
+ frame.sp = current_sp;
+ frame.lr = (unsigned long)__builtin_return_address(0);
+ frame.pc = (unsigned long)arch_save_stacktrace;
+
+ walk_stackframe(&frame, save_trace, &data);
+}
+
+
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_coproc.c b/arch/arm/cpu/arm64/cpu_vcpu_coproc.c
new file mode 100644
index 0000000..1a992e0
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_coproc.c
@@ -0,0 +1,306 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_coproc.c
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief source file for coprocessor access
+ */
+
+#include <cpu_defines.h>
+#include <cpu_vcpu_spr.h>
+#include <cpu_vcpu_coproc.h>
+
+static bool cpu_vcpu_cpx_ldcstc_accept_nop(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 D, u32 CRd,
+ u32 uopt, u32 imm8)
+{
+ return TRUE;
+}
+
+static bool cpu_vcpu_cpx_ldcstc_done_nop(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8)
+{
+ return TRUE;
+}
+
+static u32 cpu_vcpu_cpx_ldcstc_read_zero(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8)
+{
+ return 0;
+}
+
+static void cpu_vcpu_cpx_ldcstc_ignore_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8, u32 data)
+{
+}
+
+static bool cpu_vcpu_cpx_read2_zero(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 CRm,
+ u32 *data, u32 *data2)
+{
+ *data = 0x0;
+ *data2 = 0x0;
+
+ return TRUE;
+}
+
+static bool cpu_vcpu_cpx_ignore_write2(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 CRm,
+ u32 data, u32 data2)
+{
+ return TRUE;
+}
+
+static bool cpu_vcpu_cpx_data_process_nop(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2,
+ u32 CRd, u32 CRn, u32 CRm)
+{
+ return TRUE;
+}
+
+static bool cpu_vcpu_cpx_ignore_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn,
+ u32 CRm, u32 data)
+{
+ return TRUE;
+}
+
+static bool cpu_vcpu_cpx_read_zero(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn,
+ u32 CRm, u32 *data)
+{
+ *data = 0x0;
+
+ return TRUE;
+}
+
+static struct cpu_vcpu_coproc cp_array[CPU_COPROC_COUNT] =
+{
+ {
+ .cpnum = 0,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 1,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 2,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 3,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 4,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 5,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 6,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 7,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 8,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 9,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 10,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL
+ },
+ {
+ .cpnum = 11,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 12,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 13,
+ .ldcstc_accept = NULL,
+ .ldcstc_done = NULL,
+ .ldcstc_read = NULL,
+ .ldcstc_write = NULL,
+ .write2 = NULL,
+ .read2 = NULL,
+ .data_process = NULL,
+ .write = NULL,
+ .read = NULL,
+ },
+ {
+ .cpnum = 14,
+ .ldcstc_accept = cpu_vcpu_cpx_ldcstc_accept_nop,
+ .ldcstc_done = cpu_vcpu_cpx_ldcstc_done_nop,
+ .ldcstc_read = cpu_vcpu_cpx_ldcstc_read_zero,
+ .ldcstc_write = cpu_vcpu_cpx_ldcstc_ignore_write,
+ .write2 = cpu_vcpu_cpx_ignore_write2,
+ .read2 = cpu_vcpu_cpx_read2_zero,
+ .data_process = cpu_vcpu_cpx_data_process_nop,
+ .write = cpu_vcpu_cpx_ignore_write,
+ .read = cpu_vcpu_cpx_read_zero,
+ },
+ {
+ .cpnum = 15,
+ .ldcstc_accept = cpu_vcpu_cpx_ldcstc_accept_nop,
+ .ldcstc_done = cpu_vcpu_cpx_ldcstc_done_nop,
+ .ldcstc_read = cpu_vcpu_cpx_ldcstc_read_zero,
+ .ldcstc_write = cpu_vcpu_cpx_ldcstc_ignore_write,
+ .write2 = cpu_vcpu_cpx_ignore_write2,
+ .read2 = cpu_vcpu_cpx_read2_zero,
+ .data_process = cpu_vcpu_cpx_data_process_nop,
+ .write = &cpu_vcpu_cpx_ignore_write,
+ .read = &cpu_vcpu_cpx_read_zero,
+ },
+};
+
+struct cpu_vcpu_coproc *cpu_vcpu_coproc_get(u32 cpnum)
+{
+ if (cpnum < CPU_COPROC_COUNT) {
+ return &cp_array[cpnum];
+ }
+ return NULL;
+}
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_emulate.c b/arch/arm/cpu/arm64/cpu_vcpu_emulate.c
new file mode 100644
index 0000000..1f85f8d
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_emulate.c
@@ -0,0 +1,506 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_emulate.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Implementation of hardware assisted instruction emulation
+ */
+
+#include <vmm_types.h>
+#include <vmm_error.h>
+#include <vmm_stdio.h>
+#include <vmm_scheduler.h>
+#include <vmm_vcpu_irq.h>
+#include <vmm_host_aspace.h>
+#include <vmm_devemu.h>
+#include <generic_timer.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_helper.h>
+#include <cpu_vcpu_spr.h>
+#include <cpu_vcpu_emulate.h>
+#include <arm_features.h>
+
+/**
+ * A conditional instruction can trap, even though its condition was
+ * FALSE. Hence emulate condition checking in software!
+ */
+static bool cpu_vcpu_condition_check(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 iss)
+{
+ bool ret = FALSE;
+ u32 cond;
+
+ /* Condition check parameters */
+ if (iss & ISS_CV_MASK) {
+ cond = (iss & ISS_COND_MASK) >> ISS_COND_SHIFT;
+ } else {
+ /* This can happen in Thumb mode: examine IT state. */
+ u32 it;
+
+ it = ((regs->pstate >> 8) & 0xFC) | ((regs->pstate >> 25) & 0x3);
+
+ /* it == 0 => unconditional. */
+ if (it == 0)
+ return TRUE;
+
+ /* The cond for this insn works out as the top 4 bits. */
+ cond = (it >> 4);
+ }
+
+ /* Emulate condition checking */
+ switch (cond >> 1) {
+ case 0:
+ ret = (regs->pstate & PSR_ZERO_MASK) ? TRUE : FALSE;
+ break;
+ case 1:
+ ret = (regs->pstate & PSR_CARRY_MASK) ? TRUE : FALSE;
+ break;
+ case 2:
+ ret = (regs->pstate & PSR_NEGATIVE_MASK) ? TRUE : FALSE;
+ break;
+ case 3:
+ ret = (regs->pstate & PSR_OVERFLOW_MASK) ? TRUE : FALSE;
+ break;
+ case 4:
+ ret = (regs->pstate & PSR_CARRY_MASK) ? TRUE : FALSE;
+ ret = (ret && !(regs->pstate & PSR_ZERO_MASK)) ?
+ TRUE : FALSE;
+ break;
+ case 5:
+ if (regs->pstate & PSR_NEGATIVE_MASK) {
+ ret = (regs->pstate & PSR_OVERFLOW_MASK) ?
+ TRUE : FALSE;
+ } else {
+ ret = (regs->pstate & PSR_OVERFLOW_MASK) ?
+ FALSE : TRUE;
+ }
+ break;
+ case 6:
+ if (regs->pstate & PSR_NEGATIVE_MASK) {
+ ret = (regs->pstate & PSR_OVERFLOW_MASK) ?
+ TRUE : FALSE;
+ } else {
+ ret = (regs->pstate & PSR_OVERFLOW_MASK) ?
+ FALSE : TRUE;
+ }
+ ret = (ret && !(regs->pstate & PSR_ZERO_MASK)) ?
+ TRUE : FALSE;
+ break;
+ case 7:
+ ret = TRUE;
+ break;
+ default:
+ break;
+ };
+
+ if ((cond & 0x1) && (cond != 0xF)) {
+ ret = !ret;
+ }
+
+ return ret;
+}
+
+/**
+ * Update ITSTATE when emulating instructions inside an IT-block
+ *
+ * When IO abort occurs from Thumb IF-THEN blocks, the ITSTATE field
+ * of the CPSR is not updated, so we do this manually.
+ */
+static void cpu_vcpu_update_itstate(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ u32 itbits, cond;
+
+ if (!(regs->pstate & PSR_IT_MASK)) {
+ return;
+ }
+
+ cond = (regs->pstate & 0xe000) >> 13;
+ itbits = (regs->pstate & 0x1c00) >> (10 - 2);
+ itbits |= (regs->pstate & (0x3 << 25)) >> 25;
+
+ /* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */
+ if ((itbits & 0x7) == 0)
+ itbits = cond = 0;
+ else
+ itbits = (itbits << 1) & 0x1f;
+
+ regs->pstate &= ~PSR_IT_MASK;
+ regs->pstate |= cond << 13;
+ regs->pstate |= (itbits & 0x1c) << (10 - 2);
+ regs->pstate |= (itbits & 0x3) << 25;
+}
+
+int cpu_vcpu_emulate_wfi_wfe(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ u64 timeout_nsecs = 0;
+
+ /* Check instruction condition */
+ if (!cpu_vcpu_condition_check(vcpu, regs, iss)) {
+ /* Skip this instruction */
+ goto done;
+ }
+
+ if (iss & ISS_WFI_WFE_TRAPPED_MASK) { /* WFE */
+ /* Yield current timeslice */
+ vmm_scheduler_yield();
+ } else { /* WFI */
+ /* Estimate wakeup timeout if possible */
+ if (arm_feature(vcpu, ARM_FEATURE_GENERIC_TIMER)) {
+ timeout_nsecs = generic_timer_wakeup_timeout();
+ }
+
+ /* Wait for irq on this vcpu */
+ vmm_vcpu_irq_wait_timeout(vcpu, timeout_nsecs);
+ }
+
+done:
+ /* Next instruction */
+ regs->pc += (il) ? 4 : 2;
+
+ /* Update ITSTATE for Thumb mode */
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ cpu_vcpu_update_itstate(vcpu, regs);
+ }
+
+ return VMM_OK;
+}
+
+int cpu_vcpu_emulate_mcr_mrc_cp15(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ int rc = VMM_OK;
+ u32 opc2, opc1, CRn, Rt, CRm;
+ u64 t;
+
+ /* Check instruction condition */
+ if (!cpu_vcpu_condition_check(vcpu, regs, iss)) {
+ /* Skip this instruction */
+ goto done;
+ }
+
+ /* More MCR/MRC parameters */
+ opc2 = (iss & ISS_MCR_MRC_OPC2_MASK) >> ISS_MCR_MRC_OPC2_SHIFT;
+ opc1 = (iss & ISS_MCR_MRC_OPC1_MASK) >> ISS_MCR_MRC_OPC1_SHIFT;
+ CRn = (iss & ISS_MCR_MRC_CRN_MASK) >> ISS_MCR_MRC_CRN_SHIFT;
+ Rt = (iss & ISS_MCR_MRC_RT_MASK) >> ISS_MCR_MRC_RT_SHIFT;
+ CRm = (iss & ISS_MCR_MRC_CRM_MASK) >> ISS_MCR_MRC_CRM_SHIFT;
+
+ if (iss & ISS_MCR_MRC_DIR_MASK) {
+ /* MRC CP15 */
+ if (!cpu_vcpu_cp15_read(vcpu, regs, opc1, opc2, CRn, CRm, &t)) {
+ rc = VMM_EFAIL;
+ }
+ if (!rc) {
+ cpu_vcpu_reg_write(vcpu, regs, Rt, t);
+ }
+ } else {
+ /* MCR CP15 */
+ t = cpu_vcpu_reg_read(vcpu, regs, Rt);
+ if (!cpu_vcpu_cp15_write(vcpu, regs, opc1, opc2, CRn, CRm, t)) {
+ rc = VMM_EFAIL;
+ }
+ }
+
+done:
+ if (!rc) {
+ /* Next instruction */
+ regs->pc += (il) ? 4 : 2;
+ /* Update ITSTATE for Thumb mode */
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ cpu_vcpu_update_itstate(vcpu, regs);
+ }
+ }
+
+ return rc;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_mcrr_mrrc_cp15(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ return VMM_EFAIL;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_mcr_mrc_cp14(struct vmm_vcpu *vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss)
+{
+ u32 Rt;
+
+ /* Check instruction condition */
+ if (!cpu_vcpu_condition_check(vcpu, regs, iss)) {
+ /* Skip this instruction */
+ goto done;
+ }
+
+ /* More MCR/MRC parameters */
+ Rt = (iss & ISS_MCR_MRC_RT_MASK) >> ISS_MCR_MRC_RT_SHIFT;
+
+ if (iss & ISS_MCR_MRC_DIR_MASK) {
+ /* MRC CP14 */
+ /* Read always zero. */
+ cpu_vcpu_reg_write(vcpu, regs, Rt, 0x0);
+ } else {
+ /* MCR CP14 */
+ /* Ignore it. */
+ }
+
+done:
+ /* Next instruction */
+ regs->pc += (il) ? 4 : 2;
+ /* Update ITSTATE for Thumb mode */
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ cpu_vcpu_update_itstate(vcpu, regs);
+ }
+
+ return VMM_OK;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_ldc_stc_cp14(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ return VMM_EFAIL;
+}
+
+int cpu_vcpu_emulate_simd_fp_regs(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ msr_sync(cptr_el2, CPTR_TTA_MASK | CPTR_RES1_MASK);
+ /* TFA bit should be removed before we try to restore the FP-state */
+ vfp_simd_restore_regs(arm_priv(vcpu)->fpregs);
+ msr(fpexc32_el2, arm_priv(vcpu)->fpexc);
+ msr(fpcr, arm_priv(vcpu)->fpcr);
+ msr(fpsr, arm_priv(vcpu)->fpsr);
+ return VMM_OK;
+}
+
+/* TODO: Can we optimize this by determining the source and target registers
+ * and avoid copying all the FPU-regs */
+int cpu_vcpu_emulate_vmrs(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ vmm_printf("\n\n%s\n", __func__);
+ msr(cptr_el2, CPTR_TTA_MASK | CPTR_RES1_MASK);
+ /* TFA bit should be removed before we try to restore the FP-state */
+ vfp_simd_restore_regs(arm_priv(vcpu)->fpregs);
+ msr(fpexc32_el2, arm_priv(vcpu)->fpexc);
+ msr(fpcr, arm_priv(vcpu)->fpcr);
+ msr(fpsr, arm_priv(vcpu)->fpsr);
+ return VMM_OK;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_mcrr_mrrc_cp14(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ return VMM_EFAIL;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_hvc32(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ return VMM_EFAIL;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_hvc64(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ return VMM_EFAIL;
+}
+
+/* TODO: To be implemented later */
+int cpu_vcpu_emulate_msr_mrs_system(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss)
+{
+ bool read = (!!(iss & ISS_SYSREG_READ));
+ int rt = ((iss & ISS_RT_MASK) >> ISS_RT_SHIFT);
+
+ switch (iss & ISS_SYSREG_MASK) {
+ case ISS_CPACR_EL1:
+ vmm_printf("Trying to access CPACR_EL1\n");
+ break;
+ case ISS_CNTFRQ_EL0:
+ vmm_printf("Trying to access CNTFRQ_EL0 \n");
+ break;
+ case ISS_CNTPCT_EL0:
+ vmm_printf("Trying to access CNTPCT_EL0 \n");
+ break;
+ case ISS_CNTKCTL_EL1:
+ vmm_printf("Trying to access CNTKCTL_EL1 \n");
+ break;
+ case ISS_CNTP_TVAL_EL0:
+ vmm_printf("Trying to access CNTP_TVAL_EL0 \n");
+ break;
+ case ISS_CNTP_CTL_EL0:
+ vmm_printf("Trying to access CNTP_CTL_EL0 \n");
+ break;
+ case ISS_CNTP_CVAL_EL0:
+ vmm_printf("Trying to access CNTP_CVAL_EL0 \n");
+ break;
+ case ISS_ACTLR_EL1:
+ if (read) {
+ cpu_vcpu_reg_write(vcpu, regs, rt, arm_priv(vcpu)->actlr);
+ } else {
+ arm_priv(vcpu)->actlr = cpu_vcpu_reg_read(vcpu, regs, rt);
+ }
+ regs->pc += 4;
+ return VMM_OK;
+ break;
+ default:
+ vmm_printf("Guest MSR/MRS Emulation @ PC:0x%X\n", regs->pc);
+ break;
+ }
+ return VMM_EFAIL;
+}
+
+static inline u32 arm_sign_extend(u32 imm, u32 len, u32 bits)
+{
+ if (imm & (1 << (len - 1))) {
+ imm = imm | (~((1 << len) - 1));
+ }
+ return imm & ((1 << bits) - 1);
+}
+
+int cpu_vcpu_emulate_load(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss,
+ physical_addr_t ipa)
+{
+ int rc;
+ u8 data8;
+ u16 data16;
+ u32 data32, sas, sse, srt;
+
+ sas = (iss & ISS_ABORT_SAS_MASK) >> ISS_ABORT_SAS_SHIFT;
+ sse = (iss & ISS_ABORT_SSE_MASK) >> ISS_ABORT_SSE_SHIFT;
+ srt = (iss & ISS_ABORT_SRT_MASK) >> ISS_ABORT_SRT_SHIFT;
+
+ sse = (sas == 2) ? 0 : sse;
+
+ switch (sas) {
+ case 0:
+ rc = vmm_devemu_emulate_read(vcpu, ipa,
+ &data8, sizeof(data8));
+ if (!rc) {
+ if (sse) {
+ cpu_vcpu_reg_write(vcpu, regs, srt,
+ arm_sign_extend(data8, 8, 32));
+ } else {
+ cpu_vcpu_reg_write(vcpu, regs, srt, data8);
+ }
+ }
+ break;
+ case 1:
+ rc = vmm_devemu_emulate_read(vcpu, ipa,
+ &data16, sizeof(data16));
+ if (!rc) {
+ if (sse) {
+ cpu_vcpu_reg_write(vcpu, regs, srt,
+ arm_sign_extend(data16, 16, 32));
+ } else {
+ cpu_vcpu_reg_write(vcpu, regs, srt, data16);
+ }
+ }
+ break;
+ case 2:
+ rc = vmm_devemu_emulate_read(vcpu, ipa,
+ &data32, sizeof(data32));
+ if (!rc) {
+ cpu_vcpu_reg_write(vcpu, regs, srt, data32);
+ }
+ break;
+ default:
+ rc = VMM_EFAIL;
+ break;
+ };
+
+ if (!rc) {
+ /* Next instruction */
+ regs->pc += (il) ? 4 : 2;
+ /* Update ITSTATE for Thumb mode */
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ cpu_vcpu_update_itstate(vcpu, regs);
+ }
+ }
+
+ return rc;
+}
+
+int cpu_vcpu_emulate_store(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss,
+ physical_addr_t ipa)
+{
+ int rc;
+ u8 data8;
+ u16 data16;
+ u32 data32, sas, srt;
+
+ sas = (iss & ISS_ABORT_SAS_MASK) >> ISS_ABORT_SAS_SHIFT;
+ srt = (iss & ISS_ABORT_SRT_MASK) >> ISS_ABORT_SRT_SHIFT;
+
+ switch (sas) {
+ case 0:
+ data8 = cpu_vcpu_reg_read(vcpu, regs, srt);
+ rc = vmm_devemu_emulate_write(vcpu, ipa,
+ &data8, sizeof(data8));
+ break;
+ case 1:
+ data16 = cpu_vcpu_reg_read(vcpu, regs, srt);
+ rc = vmm_devemu_emulate_write(vcpu, ipa,
+ &data16, sizeof(data16));
+ break;
+ case 2:
+ data32 = cpu_vcpu_reg_read(vcpu, regs, srt);
+ rc = vmm_devemu_emulate_write(vcpu, ipa,
+ &data32, sizeof(data32));
+ break;
+ default:
+ rc = VMM_EFAIL;
+ break;
+ };
+
+ if (!rc) {
+ /* Next instruction */
+ regs->pc += (il) ? 4 : 2;
+ /* Update ITSTATE for Thumb mode */
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ cpu_vcpu_update_itstate(vcpu, regs);
+ }
+ }
+
+ return rc;
+}
+
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_helper.c b/arch/arm/cpu/arm64/cpu_vcpu_helper.c
new file mode 100644
index 0000000..49070c5
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_helper.c
@@ -0,0 +1,991 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modifycpu_vcpu_helper.c
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_helper.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief source of VCPU helper functions
+ */
+
+#include <vmm_error.h>
+#include <vmm_heap.h>
+#include <vmm_smp.h>
+#include <vmm_stdio.h>
+#include <vmm_timer.h>
+#include <vmm_manager.h>
+#include <vmm_scheduler.h>
+#include <arch_barrier.h>
+#include <libs/stringlib.h>
+#include <libs/mathlib.h>
+#include <cpu_defines.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_spr.h>
+#include <cpu_vcpu_helper.h>
+#include <generic_timer.h>
+#include <arm_features.h>
+#include <mmu_lpae.h>
+
+void cpu_vcpu_halt(struct vmm_vcpu *vcpu, arch_regs_t *regs)
+{
+ if (vcpu->state != VMM_VCPU_STATE_HALTED) {
+ vmm_printf("\n");
+ cpu_vcpu_dump_user_reg(regs);
+ vmm_manager_vcpu_halt(vcpu);
+ }
+}
+
+static u32 __cpu_vcpu_regmode32_read(arch_regs_t *regs,
+ u32 mode, u32 reg)
+{
+ switch (reg) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ return regs->gpr[reg];
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ if (mode == CPSR_MODE_FIQ) {
+ return regs->gpr[16 + reg];
+ } else {
+ return regs->gpr[reg];
+ }
+ case 13:
+ switch (mode) {
+ case CPSR_MODE_USER:
+ case CPSR_MODE_SYSTEM:
+ return regs->gpr[13];
+ case CPSR_MODE_FIQ:
+ return regs->gpr[29];
+ case CPSR_MODE_IRQ:
+ return regs->gpr[17];
+ case CPSR_MODE_SUPERVISOR:
+ return regs->gpr[19];
+ case CPSR_MODE_ABORT:
+ return regs->gpr[21];
+ case CPSR_MODE_UNDEFINED:
+ return regs->gpr[23];
+ case CPSR_MODE_HYPERVISOR:
+ return regs->gpr[15];
+ default:
+ break;
+ };
+ break;
+ case 14:
+ switch (mode) {
+ case CPSR_MODE_USER:
+ case CPSR_MODE_SYSTEM:
+ return regs->gpr[14];
+ case CPSR_MODE_FIQ:
+ return regs->gpr[30];
+ case CPSR_MODE_IRQ:
+ return regs->gpr[16];
+ case CPSR_MODE_SUPERVISOR:
+ return regs->gpr[18];
+ case CPSR_MODE_ABORT:
+ return regs->gpr[20];
+ case CPSR_MODE_UNDEFINED:
+ return regs->gpr[22];
+ case CPSR_MODE_HYPERVISOR:
+ return regs->gpr[14];
+ default:
+ break;
+ };
+ break;
+ case 15:
+ return regs->pc;
+ default:
+ break;
+ };
+
+ return 0x0;
+}
+
+static void __cpu_vcpu_regmode32_write(arch_regs_t *regs,
+ u32 mode, u32 reg, u32 val)
+{
+ switch (reg) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ regs->gpr[reg] = val;
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ if (mode == CPSR_MODE_FIQ) {
+ regs->gpr[16 + reg] = val;
+ } else {
+ regs->gpr[reg] = val;
+ }
+ break;
+ case 13:
+ switch (mode) {
+ case CPSR_MODE_USER:
+ case CPSR_MODE_SYSTEM:
+ regs->gpr[13] = val;
+ break;
+ case CPSR_MODE_FIQ:
+ regs->gpr[29] = val;
+ break;
+ case CPSR_MODE_IRQ:
+ regs->gpr[17] = val;
+ break;
+ case CPSR_MODE_SUPERVISOR:
+ regs->gpr[19] = val;
+ break;
+ case CPSR_MODE_ABORT:
+ regs->gpr[21] = val;
+ break;
+ case CPSR_MODE_UNDEFINED:
+ regs->gpr[23] = val;
+ break;
+ case CPSR_MODE_HYPERVISOR:
+ regs->gpr[15] = val;
+ break;
+ default:
+ break;
+ };
+ break;
+ case 14:
+ switch (mode) {
+ case CPSR_MODE_USER:
+ case CPSR_MODE_SYSTEM:
+ regs->gpr[14] = val;
+ case CPSR_MODE_FIQ:
+ regs->gpr[30] = val;
+ case CPSR_MODE_IRQ:
+ regs->gpr[16] = val;
+ case CPSR_MODE_SUPERVISOR:
+ regs->gpr[18] = val;
+ case CPSR_MODE_ABORT:
+ regs->gpr[20] = val;
+ case CPSR_MODE_UNDEFINED:
+ regs->gpr[22] = val;
+ case CPSR_MODE_HYPERVISOR:
+ regs->gpr[14] = val;
+ default:
+ break;
+ };
+ break;
+ case 15:
+ regs->pc = val;
+ break;
+ default:
+ break;
+ };
+}
+
+u64 cpu_vcpu_reg_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 reg)
+{
+ if (regs->pstate & PSR_MODE32) {
+ return __cpu_vcpu_regmode32_read(regs,
+ regs->pstate & PSR_MODE32_MASK, reg & 0xF);
+ } else {
+ return (regs->gpr[reg]);
+ }
+}
+
+void cpu_vcpu_reg_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 reg, u64 val)
+{
+ if (regs->pstate & PSR_MODE32) {
+ __cpu_vcpu_regmode32_write(regs,
+ regs->pstate & PSR_MODE32_MASK, reg & 0xF, val);
+ } else {
+ regs->gpr[reg] = val;
+ }
+}
+
+void __cpu_vcpu_spsr32_update(struct vmm_vcpu *vcpu, u32 mode, u32 new_spsr)
+{
+ switch (mode) {
+ case CPSR_MODE_ABORT:
+ msr(spsr_abt, new_spsr);
+ arm_priv(vcpu)->spsr_abt = new_spsr;
+ break;
+ case CPSR_MODE_UNDEFINED:
+ msr(spsr_und, new_spsr);
+ arm_priv(vcpu)->spsr_und = new_spsr;
+ break;
+ case CPSR_MODE_SUPERVISOR:
+ msr(spsr_el1, new_spsr);
+ arm_priv(vcpu)->spsr_el1 = new_spsr;
+ break;
+ case CPSR_MODE_IRQ:
+ msr(spsr_irq, new_spsr);
+ arm_priv(vcpu)->spsr_irq = new_spsr;
+ break;
+ case CPSR_MODE_FIQ:
+ msr(spsr_fiq, new_spsr);
+ arm_priv(vcpu)->spsr_fiq = new_spsr;
+ break;
+ case CPSR_MODE_HYPERVISOR:
+ msr(spsr_el2, new_spsr);
+ break;
+ default:
+ break;
+ };
+}
+
+static int __cpu_vcpu_inject_und32(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ u32 old_cpsr, new_cpsr, sctlr;
+
+ /* Retrive current SCTLR */
+ sctlr = mrs(sctlr_el1);
+
+ /* Compute CPSR changes */
+ old_cpsr = new_cpsr = regs->pstate & 0xFFFFFFFFULL;
+ new_cpsr &= ~CPSR_MODE_MASK;
+ new_cpsr |= (CPSR_MODE_UNDEFINED | CPSR_IRQ_DISABLED);
+ new_cpsr &= ~(CPSR_IT2_MASK |
+ CPSR_IT1_MASK |
+ CPSR_JAZZLE_ENABLED |
+ CPSR_BE_ENABLED |
+ CPSR_THUMB_ENABLED);
+ if (sctlr & SCTLR_TE_MASK) {
+ new_cpsr |= CPSR_THUMB_ENABLED;
+ }
+ if (sctlr & SCTLR_EE_MASK) {
+ new_cpsr |= CPSR_BE_ENABLED;
+ }
+
+ /* Update CPSR, SPSR, LR and PC */
+ __cpu_vcpu_spsr32_update(vcpu, CPSR_MODE_UNDEFINED, old_cpsr);
+ __cpu_vcpu_regmode32_write(regs, CPSR_MODE_UNDEFINED, 14,
+ regs->pc - ((old_cpsr & CPSR_THUMB_ENABLED) ? 2 : 4));
+ if (sctlr & SCTLR_V_MASK) {
+ regs->pc = CPU_IRQ_HIGHVEC_BASE;
+ } else {
+ regs->pc = mrs(vbar_el1);
+ }
+ regs->pc = regs->pc & 0xFFFFFFFFULL;
+ regs->pc += 4;
+ regs->pstate &= ~0xFFFFFFFFULL;
+ regs->pstate |= (u64)new_cpsr;
+
+ return VMM_OK;
+}
+
+#define EL1_EXCEPT_SYNC_OFFSET 0x200
+
+static int __cpu_vcpu_inject_und64(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ u32 esr;
+
+ /* Save old PSTATE to SPSR_EL1 */
+ msr(spsr_el1, regs->pstate);
+
+ /* Save current PC to ELR_EL1 */
+ msr(elr_el1, regs->pc);
+
+ /* Update PSTATE */
+ regs->pstate = (PSR_MODE64_EL1h |
+ PSR_ASYNC_ABORT_DISABLED |
+ PSR_FIQ_DISABLED |
+ PSR_IRQ_DISABLED |
+ PSR_MODE64_DEBUG_DISABLED);
+
+ /* Update PC */
+ regs->pc = mrs(vbar_el1) + EL1_EXCEPT_SYNC_OFFSET;
+
+ /* Update ESR_EL1 */
+ esr = (EC_UNKNOWN << ESR_EC_SHIFT);
+ if (mrs(esr_el2) & ESR_IL_MASK) {
+ esr |= ESR_IL_MASK;
+ }
+ msr(esr_el1, esr);
+
+ return VMM_OK;
+}
+
+static int __cpu_vcpu_inject_abt32(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ bool is_pabt,
+ virtual_addr_t addr)
+{
+ u64 far;
+ u32 old_cpsr, new_cpsr, sctlr, ttbcr;
+
+ /* Retrive current SCTLR */
+ sctlr = mrs(sctlr_el1);
+
+ /* Compute CPSR changes */
+ old_cpsr = new_cpsr = regs->pstate & 0xFFFFFFFFULL;
+ new_cpsr &= ~CPSR_MODE_MASK;
+ new_cpsr |= (CPSR_MODE_ABORT |
+ CPSR_ASYNC_ABORT_DISABLED |
+ CPSR_IRQ_DISABLED);
+ new_cpsr &= ~(CPSR_IT2_MASK |
+ CPSR_IT1_MASK |
+ CPSR_JAZZLE_ENABLED |
+ CPSR_BE_ENABLED |
+ CPSR_THUMB_ENABLED);
+ if (sctlr & SCTLR_TE_MASK) {
+ new_cpsr |= CPSR_THUMB_ENABLED;
+ }
+ if (sctlr & SCTLR_EE_MASK) {
+ new_cpsr |= CPSR_BE_ENABLED;
+ }
+
+ /* Update CPSR, SPSR, LR and PC */
+ __cpu_vcpu_spsr32_update(vcpu, CPSR_MODE_ABORT, old_cpsr);
+ __cpu_vcpu_regmode32_write(regs, CPSR_MODE_ABORT, 14,
+ regs->pc - ((old_cpsr & CPSR_THUMB_ENABLED) ? 4 : 0));
+ if (sctlr & SCTLR_V_MASK) {
+ regs->pc = CPU_IRQ_HIGHVEC_BASE;
+ } else {
+ regs->pc = mrs(vbar_el1);
+ }
+ regs->pc = regs->pc & 0xFFFFFFFFULL;
+ regs->pc += (is_pabt) ? 12 : 16;
+ regs->pstate &= ~0xFFFFFFFFULL;
+ regs->pstate |= (u64)new_cpsr;
+
+ /* Update abort registers */
+ ttbcr = mrs(tcr_el1) & 0xFFFFFFFFULL;
+ if (is_pabt) {
+ /* Set IFAR and IFSR */
+ far = mrs(far_el1) & 0xFFFFFFFFULL;
+ far |= (addr << 32) & 0xFFFFFFFF00000000ULL;
+ msr(far_el1, far);
+ if (ttbcr >> 31) { /* LPAE MMU */
+ msr(ifsr32_el2, (1 << 9) | 0x34);
+ } else { /* Legacy ARMv6 MMU */
+ msr(ifsr32_el2, 0x14);
+ }
+ } else {
+ /* Set DFAR and DFSR */
+ far = mrs(far_el1) & 0xFFFFFFFF00000000ULL;
+ far |= addr & 0xFFFFFFFFULL;
+ msr(far_el1, far);
+ if (ttbcr >> 31) { /* LPAE MMU */
+ msr(esr_el1, (1 << 9) | 0x34);
+ } else { /* Legacy ARMv6 MMU */
+ msr(esr_el1, 0x14);
+ }
+ }
+
+ return VMM_OK;
+}
+
+static int __cpu_vcpu_inject_abt64(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ bool is_pabt,
+ virtual_addr_t addr)
+{
+ u32 esr, old_pstate;
+ bool is_aarch32 = (regs->pstate & PSR_MODE32) ? TRUE : FALSE;
+
+ /* Save old PSTATE to SPSR_EL1 */
+ old_pstate = regs->pstate;
+ msr(spsr_el1, old_pstate);
+
+ /* Save current PC to ELR_EL1 */
+ msr(elr_el1, regs->pc);
+
+ /* Update PSTATE */
+ regs->pstate = (PSR_MODE64_EL1h |
+ PSR_ASYNC_ABORT_DISABLED |
+ PSR_FIQ_DISABLED |
+ PSR_IRQ_DISABLED |
+ PSR_MODE64_DEBUG_DISABLED);
+
+ /* Update PC */
+ regs->pc = mrs(vbar_el1) + EL1_EXCEPT_SYNC_OFFSET;
+
+ /* Update FAR_EL1 */
+ msr(far_el1, addr);
+
+ /* Update ESR_EL1
+ * NOTE: The guest runs in AArch64 mode when in EL1. If we get
+ * an AArch32 fault or AArch64 EL0t fault then we have trapped
+ * guest user space.
+ */
+ esr = 0;
+ if (is_aarch32 || (old_pstate & PSR_MODE64_MASK) == PSR_MODE64_EL0t) {
+ if (is_pabt) {
+ esr |= (EC_TRAP_LWREL_INST_ABORT << ESR_EC_SHIFT);
+ } else {
+ esr |= (EC_TRAP_LWREL_DATA_ABORT << ESR_EC_SHIFT);
+ }
+ } else {
+ if (is_pabt) {
+ esr |= (EC_CUREL_INST_ABORT << ESR_EC_SHIFT);
+ } else {
+ esr |= (EC_CUREL_DATA_ABORT << ESR_EC_SHIFT);
+ }
+ }
+ esr |= FSC_SYNC_EXTERNAL_ABORT;
+ if (mrs(esr_el2) & ESR_IL_MASK) {
+ esr |= ESR_IL_MASK;
+ }
+ msr(esr_el1, esr);
+
+ return VMM_OK;
+}
+
+int cpu_vcpu_inject_undef(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ /* Sanity checks */
+ if (!vcpu || !regs) {
+ return VMM_EFAIL;
+ }
+ if (vcpu != vmm_scheduler_current_vcpu()) {
+ /* This function should only be called for current VCPU */
+ vmm_panic("%d not called for current vcpu\n", __func__);
+ }
+
+ if (arm_priv(vcpu)->hcr & HCR_RW_MASK) {
+ return __cpu_vcpu_inject_und64(vcpu, regs);
+ } else {
+ return __cpu_vcpu_inject_und32(vcpu, regs);
+ }
+}
+
+int cpu_vcpu_inject_pabt(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ /* Sanity checks */
+ if (!vcpu || !regs) {
+ return VMM_EFAIL;
+ }
+ if (vcpu != vmm_scheduler_current_vcpu()) {
+ /* This function should only be called for current VCPU */
+ vmm_panic("%d not called for current vcpu\n", __func__);
+ }
+
+ if (arm_priv(vcpu)->hcr & HCR_RW_MASK) {
+ return __cpu_vcpu_inject_abt64(vcpu, regs, TRUE, regs->pc);
+ } else {
+ return __cpu_vcpu_inject_abt32(vcpu, regs, TRUE, regs->pc);
+ }
+}
+
+int cpu_vcpu_inject_dabt(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr)
+{
+ /* Sanity checks */
+ if (!vcpu || !regs) {
+ return VMM_EFAIL;
+ }
+ if (vcpu != vmm_scheduler_current_vcpu()) {
+ /* This function should only be called for current VCPU */
+ vmm_panic("%d not called for current vcpu\n", __func__);
+ }
+
+ if (arm_priv(vcpu)->hcr & HCR_RW_MASK) {
+ return __cpu_vcpu_inject_abt64(vcpu, regs, FALSE, addr);
+ } else {
+ return __cpu_vcpu_inject_abt32(vcpu, regs, FALSE, addr);
+ }
+}
+
+int arch_guest_init(struct vmm_guest *guest)
+{
+ if (!guest->reset_count) {
+ guest->arch_priv = vmm_malloc(sizeof(arm_guest_priv_t));
+ if (!guest->arch_priv) {
+ return VMM_EFAIL;
+ }
+ arm_guest_priv(guest)->ttbl = mmu_lpae_ttbl_alloc(TTBL_STAGE2);
+ }
+ return VMM_OK;
+}
+
+int arch_guest_deinit(struct vmm_guest *guest)
+{
+ int rc;
+
+ if (guest->arch_priv) {
+ if ((rc = mmu_lpae_ttbl_free(arm_guest_priv(guest)->ttbl))) {
+ return rc;
+ }
+ vmm_free(guest->arch_priv);
+ }
+
+ return VMM_OK;
+}
+
+int arch_vcpu_init(struct vmm_vcpu *vcpu)
+{
+ u32 cpuid = 0;
+ const char *attr;
+ irq_flags_t flags;
+ /* Initialize User Mode Registers */
+ /* For both Orphan & Normal VCPUs */
+ memset(arm_regs(vcpu), 0, sizeof(arch_regs_t));
+ arm_regs(vcpu)->pc = vcpu->start_pc;
+ arm_regs(vcpu)->sp = vcpu->stack_va + vcpu->stack_sz - 8;
+ if (!vcpu->is_normal) {
+ arm_regs(vcpu)->pstate = PSR_MODE64_EL2h;
+ arm_regs(vcpu)->pstate |= PSR_ASYNC_ABORT_DISABLED;
+ return VMM_OK;
+ }
+ /* Following initialization for normal VCPUs only */
+ attr = vmm_devtree_attrval(vcpu->node,
+ VMM_DEVTREE_COMPATIBLE_ATTR_NAME);
+ if (strcmp(attr, "armv7a,cortex-a8") == 0) {
+ cpuid = ARM_CPUID_CORTEXA8;
+ arm_regs(vcpu)->pstate = PSR_MODE32;
+ } else if (strcmp(attr, "armv7a,cortex-a9") == 0) {
+ cpuid = ARM_CPUID_CORTEXA9;
+ arm_regs(vcpu)->pstate = PSR_MODE32;
+ } else if (strcmp(attr, "armv7a,cortex-a15") == 0) {
+ cpuid = ARM_CPUID_CORTEXA15;
+ arm_regs(vcpu)->pstate = PSR_MODE32;
+ } else if (strcmp(attr, "armv8,generic") == 0) {
+ cpuid = ARM_CPUID_ARMV8;
+ } else {
+ return VMM_EFAIL;
+ }
+ if (arm_regs(vcpu)->pstate == PSR_MODE32) {
+ /* Check if the host supports A32 mode @ EL1 */
+ if (!cpu_supports_el1_a32()) {
+ vmm_printf("Host does not support AArch32 mode\n");
+ return VMM_EFAIL;
+ }
+ arm_regs(vcpu)->pstate |= PSR_ZERO_MASK;
+ arm_regs(vcpu)->pstate |= PSR_MODE32_SUPERVISOR;
+ } else {
+ arm_regs(vcpu)->pstate |= PSR_MODE64_DEBUG_DISABLED;
+ arm_regs(vcpu)->pstate |= PSR_MODE64_EL1h;
+ }
+ arm_regs(vcpu)->pstate |= PSR_ASYNC_ABORT_DISABLED;
+ arm_regs(vcpu)->pstate |= PSR_IRQ_DISABLED;
+ arm_regs(vcpu)->pstate |= PSR_FIQ_DISABLED;
+ if (!vcpu->reset_count) {
+ /* Alloc private context */
+ vcpu->arch_priv = vmm_zalloc(sizeof(arm_priv_t));
+ if (!vcpu->arch_priv) {
+ return VMM_ENOMEM;
+ }
+ } else {
+ /* No need to init the other SPRs as their
+ * state is unknown as per AArch64 spec
+ */
+ arm_priv(vcpu)->sctlr = 0x0;
+ arm_priv(vcpu)->sp_el0 = 0x0;
+ arm_priv(vcpu)->sp_el1 = 0x0;
+ arm_priv(vcpu)->elr_el1 = 0x0;
+ arm_priv(vcpu)->spsr_el1 = 0x0;
+ arm_priv(vcpu)->spsr_abt = 0x0;
+ arm_priv(vcpu)->spsr_und = 0x0;
+ arm_priv(vcpu)->spsr_irq = 0x0;
+ arm_priv(vcpu)->spsr_fiq = 0x0;
+ }
+ arm_priv(vcpu)->last_hcpu = 0xFFFFFFFF;
+ generic_timer_vcpu_context_init(arm_gentimer_context(vcpu));
+ if (!vcpu->reset_count) {
+ /* Generic timer physical & virtual irq for the vcpu */
+ attr = vmm_devtree_attrval(vcpu->node, "gentimer_phys_irq");
+ arm_gentimer_context(vcpu)->phys_timer_irq =
+ (attr) ? (*(u32 *)attr) : 0;
+ attr = vmm_devtree_attrval(vcpu->node, "gentimer_virt_irq");
+ arm_gentimer_context(vcpu)->virt_timer_irq =
+ (attr) ? (*(u32 *)attr) : 0;
+ /* Initialize Hypervisor Configuration */
+ INIT_SPIN_LOCK(&arm_priv(vcpu)->hcr_lock);
+ arm_priv(vcpu)->hcr = (HCR_TACR_MASK |
+ HCR_TIDCP_MASK |
+ HCR_TSC_MASK |
+ HCR_TWI_MASK |
+ HCR_AMO_MASK |
+ HCR_IMO_MASK |
+ HCR_FMO_MASK |
+ HCR_SWIO_MASK |
+ HCR_VM_MASK);
+ if (!(arm_regs(vcpu)->pstate & PSR_MODE32)) {
+ arm_priv(vcpu)->hcr |= HCR_RW_MASK;
+ }
+ /* Initialize Hypervisor System Trap Register */
+ arm_priv(vcpu)->hstr = 0;
+ /* Initialize VCPU features */
+ arm_priv(vcpu)->features = 0;
+ switch (cpuid) {
+ case ARM_CPUID_CORTEXA8:
+ arm_set_feature(vcpu, ARM_FEATURE_V4T);
+ arm_set_feature(vcpu, ARM_FEATURE_V5);
+ arm_set_feature(vcpu, ARM_FEATURE_V6);
+ arm_set_feature(vcpu, ARM_FEATURE_V6K);
+ arm_set_feature(vcpu, ARM_FEATURE_V7);
+ arm_set_feature(vcpu, ARM_FEATURE_AUXCR);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP3);
+ arm_set_feature(vcpu, ARM_FEATURE_NEON);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2EE);
+ break;
+ case ARM_CPUID_CORTEXA9:
+ arm_set_feature(vcpu, ARM_FEATURE_V4T);
+ arm_set_feature(vcpu, ARM_FEATURE_V5);
+ arm_set_feature(vcpu, ARM_FEATURE_V6);
+ arm_set_feature(vcpu, ARM_FEATURE_V6K);
+ arm_set_feature(vcpu, ARM_FEATURE_V7);
+ arm_set_feature(vcpu, ARM_FEATURE_AUXCR);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP3);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP_FP16);
+ arm_set_feature(vcpu, ARM_FEATURE_NEON);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2EE);
+ arm_set_feature(vcpu, ARM_FEATURE_V7MP);
+ break;
+ case ARM_CPUID_CORTEXA15:
+ arm_set_feature(vcpu, ARM_FEATURE_V4T);
+ arm_set_feature(vcpu, ARM_FEATURE_V5);
+ arm_set_feature(vcpu, ARM_FEATURE_V6);
+ arm_set_feature(vcpu, ARM_FEATURE_V6K);
+ arm_set_feature(vcpu, ARM_FEATURE_V7);
+ arm_set_feature(vcpu, ARM_FEATURE_V7MP);
+ arm_set_feature(vcpu, ARM_FEATURE_AUXCR);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2);
+ arm_set_feature(vcpu, ARM_FEATURE_THUMB2EE);
+ arm_set_feature(vcpu, ARM_FEATURE_ARM_DIV);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP4);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP_FP16);
+ arm_set_feature(vcpu, ARM_FEATURE_NEON);
+ arm_set_feature(vcpu, ARM_FEATURE_LPAE);
+ arm_set_feature(vcpu, ARM_FEATURE_GENERIC_TIMER);
+ break;
+ case ARM_CPUID_ARMV8:
+ arm_set_feature(vcpu, ARM_FEATURE_V8);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP);
+ arm_set_feature(vcpu, ARM_FEATURE_VFP4);
+ arm_set_feature(vcpu, ARM_FEATURE_ARM_DIV);
+ arm_set_feature(vcpu, ARM_FEATURE_LPAE);
+ arm_set_feature(vcpu, ARM_FEATURE_GENERIC_TIMER);
+ break;
+ default:
+ break;
+ };
+ } else {
+ /* Clear virtual exception bits in HCR */
+ vmm_spin_lock_irqsave(&arm_priv(vcpu)->hcr_lock, flags);
+ arm_priv(vcpu)->hcr &= ~(HCR_VSE_MASK |
+ HCR_VI_MASK |
+ HCR_VF_MASK);
+ vmm_spin_unlock_irqrestore(&arm_priv(vcpu)->hcr_lock, flags);
+ }
+
+ arm_priv(vcpu)->cpuid = cpuid;
+ arm_priv(vcpu)->tcr = 0x0;
+
+ if (!vcpu->reset_count) {
+ /* Cleanup VGIC context first time */
+ arm_vgic_cleanup(vcpu);
+ }
+
+ return VMM_OK;
+}
+
+int arch_vcpu_deinit(struct vmm_vcpu *vcpu)
+{
+ /* For both Orphan & Normal VCPUs */
+ memset(arm_regs(vcpu), 0, sizeof(arch_regs_t));
+
+ /* For Orphan VCPUs do nothing else */
+ if (!vcpu->is_normal) {
+ return VMM_OK;
+ }
+
+ /* Free private context */
+ vmm_free(vcpu->arch_priv);
+ vcpu->arch_priv = NULL;
+
+ return VMM_OK;
+}
+
+static inline void cpu_vcpu_special_regs_save(struct vmm_vcpu *vcpu)
+{
+ arm_priv(vcpu)->sp_el0 = mrs(sp_el0);
+ arm_priv(vcpu)->sp_el1 = mrs(sp_el1);
+ arm_priv(vcpu)->elr_el1 = mrs(elr_el1);
+ arm_priv(vcpu)->spsr_el1 = mrs(spsr_el1);
+ arm_priv(vcpu)->spsr_abt = mrs(spsr_abt);
+ arm_priv(vcpu)->spsr_und = mrs(spsr_und);
+ arm_priv(vcpu)->spsr_irq = mrs(spsr_irq);
+ arm_priv(vcpu)->spsr_fiq = mrs(spsr_fiq);
+ arm_priv(vcpu)->spsr_irq = mrs(spsr_irq);
+ arm_priv(vcpu)->ttbr0 = mrs(ttbr0_el1);
+ arm_priv(vcpu)->ttbr1 = mrs(ttbr1_el1);
+ arm_priv(vcpu)->sctlr = mrs(sctlr_el1);
+ arm_priv(vcpu)->cpacr = mrs(cpacr_el1);
+ arm_priv(vcpu)->tcr = mrs(tcr_el1);
+ arm_priv(vcpu)->esr = mrs(esr_el1);
+ arm_priv(vcpu)->far = mrs(far_el1);
+ arm_priv(vcpu)->mair = mrs(mair_el1);
+ arm_priv(vcpu)->vbar = mrs(vbar_el1);
+ arm_priv(vcpu)->contextidr = mrs(contextidr_el1);
+ arm_priv(vcpu)->tpidr_el0 = mrs(tpidr_el0);
+ arm_priv(vcpu)->tpidr_el1 = mrs(tpidr_el1);
+ arm_priv(vcpu)->tpidrro = mrs(tpidrro_el0);
+ if (cpu_supports_thumbee()) {
+ arm_priv(vcpu)->teecr = mrs(teecr32_el1);
+ arm_priv(vcpu)->teehbr = mrs(teehbr32_el1);
+ }
+ if (cpu_supports_fpu()) {
+ if (!(mrs(cptr_el2) & CPTR_TFP_MASK)) {
+ arm_priv(vcpu)->fpexc = mrs(fpexc32_el2);
+ arm_priv(vcpu)->fpcr = mrs(fpcr);
+ arm_priv(vcpu)->fpsr = mrs(fpsr);
+ vfp_simd_save_regs(&arm_priv(vcpu)->fpregs);
+ }
+ }
+ arm_priv(vcpu)->dacr = mrs(dacr32_el2);
+ arm_priv(vcpu)->ifsr = mrs(ifsr32_el2);
+}
+
+static inline void cpu_vcpu_special_regs_restore(struct vmm_vcpu * vcpu)
+{
+ msr(sp_el0, arm_priv(vcpu)->sp_el0);
+ msr(sp_el1, arm_priv(vcpu)->sp_el1);
+ msr(elr_el1, arm_priv(vcpu)->elr_el1);
+ msr(spsr_el1, arm_priv(vcpu)->spsr_el1);
+ msr(spsr_abt, arm_priv(vcpu)->spsr_abt);
+ msr(spsr_und, arm_priv(vcpu)->spsr_und);
+ msr(spsr_irq, arm_priv(vcpu)->spsr_irq);
+ msr(spsr_fiq, arm_priv(vcpu)->spsr_fiq);
+ msr(spsr_irq, arm_priv(vcpu)->spsr_irq);
+ msr(ttbr0_el1, arm_priv(vcpu)->ttbr0);
+ msr(ttbr1_el1, arm_priv(vcpu)->ttbr1);
+ msr(sctlr_el1, arm_priv(vcpu)->sctlr);
+ msr(cpacr_el1, arm_priv(vcpu)->cpacr);
+ msr(tcr_el1, arm_priv(vcpu)->tcr);
+ msr(esr_el1, arm_priv(vcpu)->esr);
+ msr(far_el1, arm_priv(vcpu)->far);
+ msr(mair_el1, arm_priv(vcpu)->mair);
+ msr(vbar_el1, arm_priv(vcpu)->vbar);
+ msr(contextidr_el1, arm_priv(vcpu)->contextidr);
+ msr(tpidr_el0, arm_priv(vcpu)->tpidr_el0);
+ msr(tpidr_el1, arm_priv(vcpu)->tpidr_el1);
+ msr(tpidrro_el0, arm_priv(vcpu)->tpidrro);
+ if (cpu_supports_thumbee()) {
+ msr(teecr32_el1, arm_priv(vcpu)->teecr);
+ msr(teehbr32_el1, arm_priv(vcpu)->teehbr);
+ }
+ /* Note that we just disable the FP access and
+ * do not restore the FP/SIMD state
+ * unless the guest accesses FP regs
+ */
+ msr(cptr_el2, CPTR_TTA_MASK | CPTR_TFP_MASK | CPTR_RES1_MASK);
+ msr(dacr32_el2, arm_priv(vcpu)->dacr);
+ msr(ifsr32_el2, arm_priv(vcpu)->ifsr);
+}
+
+void arch_vcpu_switch(struct vmm_vcpu *tvcpu,
+ struct vmm_vcpu *vcpu,
+ arch_regs_t *regs)
+{
+ u32 ite;
+ irq_flags_t flags;
+
+ /* Save user registers & banked registers */
+ if (tvcpu) {
+ arm_regs(tvcpu)->pc = regs->pc;
+ arm_regs(tvcpu)->lr = regs->lr;
+ arm_regs(tvcpu)->sp = regs->sp;
+ for (ite = 0; ite < CPU_GPR_COUNT; ite++) {
+ arm_regs(tvcpu)->gpr[ite] = regs->gpr[ite];
+ }
+ arm_regs(tvcpu)->pstate = regs->pstate;
+ if(tvcpu->is_normal) {
+ /* Save VGIC registers */
+ arm_vgic_save(tvcpu);
+ /* Save generic timer */
+ if (arm_feature(tvcpu, ARM_FEATURE_GENERIC_TIMER)) {
+ generic_timer_vcpu_context_save(arm_gentimer_context(tvcpu));
+ }
+ /* Save special registers */
+ cpu_vcpu_special_regs_save(tvcpu);
+ /* Update last host CPU */
+ arm_priv(tvcpu)->last_hcpu = vmm_smp_processor_id();
+ }
+ }
+ /* Restore user registers & special registers */
+ regs->pc = arm_regs(vcpu)->pc;
+ regs->lr = arm_regs(vcpu)->lr;
+ regs->sp = arm_regs(vcpu)->sp;
+ for (ite = 0; ite < CPU_GPR_COUNT; ite++) {
+ regs->gpr[ite] = arm_regs(vcpu)->gpr[ite];
+ }
+ regs->pstate = arm_regs(vcpu)->pstate;
+ if (vcpu->is_normal) {
+ /* Update Stage2 MMU context */
+ mmu_lpae_stage2_chttbl(vcpu->guest->id,
+ arm_guest_priv(vcpu->guest)->ttbl);
+ msr(vpidr_el2, arm_priv(vcpu)->cpuid);
+ if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
+ msr(vmpidr_el2, (1 << 31) | vcpu->subid);
+ } else {
+ msr(vmpidr_el2, vcpu->subid);
+ }
+ /* Flush TLB if moved to new host CPU */
+ if (arm_priv(vcpu)->last_hcpu != vmm_smp_processor_id()) {
+ /* Invalidate all guest TLB enteries because
+ * we might have stale guest TLB enteries from
+ * our previous run on new_hcpu host CPU
+ */
+ inv_tlb_guest_allis();
+ /* Ensure changes are visible */
+ dsb();
+ isb();
+ }
+ /* Restore hypervisor context */
+ vmm_spin_lock_irqsave(&arm_priv(vcpu)->hcr_lock, flags);
+ msr(hcr_el2, arm_priv(vcpu)->hcr);
+ vmm_spin_unlock_irqrestore(&arm_priv(vcpu)->hcr_lock, flags);
+ msr(hstr_el2, arm_priv(vcpu)->hstr);
+ /* Restore special registers */
+ cpu_vcpu_special_regs_restore(vcpu);
+ /* Restore generic timer */
+ if(arm_feature(vcpu, ARM_FEATURE_GENERIC_TIMER)) {
+ generic_timer_vcpu_context_restore(
+ arm_gentimer_context(vcpu));
+ }
+ /* Restore VGIC registers */
+ arm_vgic_restore(vcpu);
+ }
+ /* Clear exclusive monitor */
+ clrex();
+}
+
+void arch_vcpu_preempt_orphan(void)
+{
+ /* Trigger HVC call from hypervisor mode. This will cause
+ * do_soft_irq() function to call vmm_scheduler_preempt_orphan()
+ */
+ asm volatile ("hvc #0\t\n");
+}
+
+static void __cpu_vcpu_dump_user_reg(struct vmm_chardev *cdev,
+ arch_regs_t *regs)
+{
+ u32 ite;
+ vmm_cprintf(cdev, " Core Registers\n");
+ vmm_cprintf(cdev, " SP=0x%016lX LR=0x%016lX\n",
+ regs->sp, regs->lr);
+ vmm_cprintf(cdev, " PC=0x%016lX PSTATE=0x%08lX\n",
+ regs->pc, (regs->pstate & 0xffffffff));
+ vmm_cprintf(cdev, " General Purpose Registers");
+ for (ite = 0; ite < (CPU_GPR_COUNT); ite++) {
+ if (ite % 2 == 0)
+ vmm_cprintf(cdev, "\n");
+ vmm_cprintf(cdev, " X%02d=0x%016lX ", ite, regs->gpr[ite]);
+ }
+ vmm_cprintf(cdev, "\n");
+}
+
+void cpu_vcpu_dump_user_reg(arch_regs_t *regs)
+{
+ __cpu_vcpu_dump_user_reg(NULL, regs);
+}
+
+void arch_vcpu_regs_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu)
+{
+ /* For both Normal & Orphan VCPUs */
+ __cpu_vcpu_dump_user_reg(cdev, arm_regs(vcpu));
+ /* For only Normal VCPUs */
+ if (!vcpu->is_normal) {
+ return;
+ }
+ vmm_cprintf(cdev, " TTBR_EL2: 0x%016lX\n",
+ arm_guest_priv(vcpu->guest)->ttbl->tbl_pa);
+ vmm_cprintf(cdev, " HCR_EL2: 0x%016lX\n",
+ arm_priv(vcpu)->hcr);
+ vmm_cprintf(cdev, " CPTR_EL2: 0x%016lX\n",
+ arm_priv(vcpu)->cptr);
+ vmm_cprintf(cdev, " HSTR_EL2: 0x%016lX\n",
+ arm_priv(vcpu)->hstr);
+ vmm_cprintf(cdev, " SP_EL0: 0x%016lX\n",
+ arm_priv(vcpu)->sp_el0);
+ vmm_cprintf(cdev, " SP_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->sp_el1);
+ vmm_cprintf(cdev, " ELR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->elr_el1);
+ vmm_cprintf(cdev, " SPSR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->spsr_el1);
+ vmm_cprintf(cdev, " SPSR_ABT: 0x%08lX\n",
+ arm_priv(vcpu)->spsr_abt);
+ vmm_cprintf(cdev, " SPSR_UND: 0x%08lX\n",
+ arm_priv(vcpu)->spsr_und);
+ vmm_cprintf(cdev, " SPSR_IRQ: 0x%08lX\n",
+ arm_priv(vcpu)->spsr_irq);
+ vmm_cprintf(cdev, " SPSR_FIQ: 0x%08lX\n",
+ arm_priv(vcpu)->spsr_fiq);
+ vmm_cprintf(cdev, " MIDR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->cpuid);
+ vmm_cprintf(cdev, " MPIDR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->mpidr);
+ vmm_cprintf(cdev, " SCTLR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->sctlr);
+ vmm_cprintf(cdev, " CPACR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->cpacr);
+ vmm_cprintf(cdev, " TTBR0_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->ttbr0);
+ vmm_cprintf(cdev, " TTBR1_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->ttbr1);
+ vmm_cprintf(cdev, " TCR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->tcr);
+ vmm_cprintf(cdev, " ESR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->esr);
+ vmm_cprintf(cdev, " FAR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->far);
+ vmm_cprintf(cdev, " PAR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->par);
+ vmm_cprintf(cdev, " MAIR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->mair);
+ vmm_cprintf(cdev, " VBAR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->vbar);
+ vmm_cprintf(cdev, " CONTEXTIDR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->contextidr);
+ vmm_cprintf(cdev, " TPIDR_EL0: 0x%016lX\n",
+ arm_priv(vcpu)->tpidr_el0);
+ vmm_cprintf(cdev, " TPIDR_EL1: 0x%016lX\n",
+ arm_priv(vcpu)->tpidr_el1);
+ vmm_cprintf(cdev, " TPIDRRO: 0x%016lX\n",
+ arm_priv(vcpu)->tpidrro);
+ vmm_cprintf(cdev, "\n");
+}
+
+void arch_vcpu_stat_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu)
+{
+ /* For now no arch specific stats */
+}
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_irq.c b/arch/arm/cpu/arm64/cpu_vcpu_irq.c
new file mode 100644
index 0000000..6a01abf
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_irq.c
@@ -0,0 +1,201 @@
+/**
+ * Copyright (c) 2012 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_irq.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief source code for handling vcpu interrupts
+ */
+
+#include <vmm_error.h>
+#include <vmm_scheduler.h>
+#include <vmm_vcpu_irq.h>
+#include <vmm_stdio.h>
+#include <arch_vcpu.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_helper.h>
+#include <cpu_defines.h>
+
+u32 arch_vcpu_irq_count(struct vmm_vcpu *vcpu)
+{
+ return CPU_IRQ_NR;
+}
+
+u32 arch_vcpu_irq_priority(struct vmm_vcpu *vcpu, u32 irq_no)
+{
+ u32 ret = 3;
+
+ switch (irq_no) {
+ case CPU_RESET_IRQ:
+ ret = 0;
+ break;
+ case CPU_UNDEF_INST_IRQ:
+ ret = 1;
+ break;
+ case CPU_SOFT_IRQ:
+ ret = 2;
+ break;
+ case CPU_PREFETCH_ABORT_IRQ:
+ ret = 2;
+ break;
+ case CPU_DATA_ABORT_IRQ:
+ ret = 2;
+ break;
+ case CPU_HYP_TRAP_IRQ:
+ ret = 2;
+ break;
+ case CPU_EXTERNAL_IRQ:
+ ret = 2;
+ break;
+ case CPU_EXTERNAL_FIQ:
+ ret = 2;
+ break;
+ default:
+ break;
+ };
+
+ return ret;
+}
+
+int arch_vcpu_irq_assert(struct vmm_vcpu *vcpu, u32 irq_no, u64 reason)
+{
+ u64 hcr;
+ bool update_hcr;
+ irq_flags_t flags;
+
+ /* Skip IRQ & FIQ if VGIC available */
+ if (arm_vgic_avail(vcpu) &&
+ ((irq_no == CPU_EXTERNAL_IRQ) ||
+ (irq_no == CPU_EXTERNAL_FIQ))) {
+ return VMM_OK;
+ }
+
+ vmm_spin_lock_irqsave(&arm_priv(vcpu)->hcr_lock, flags);
+
+ hcr = arm_priv(vcpu)->hcr;
+ update_hcr = FALSE;
+
+ switch(irq_no) {
+ case CPU_EXTERNAL_IRQ:
+ hcr |= HCR_VI_MASK;
+ /* VI bit will be cleared on deassertion */
+ update_hcr = TRUE;
+ break;
+ case CPU_EXTERNAL_FIQ:
+ hcr |= HCR_VF_MASK;
+ /* VF bit will be cleared on deassertion */
+ update_hcr = TRUE;
+ break;
+ default:
+ break;
+ };
+
+ if (update_hcr) {
+ arm_priv(vcpu)->hcr = hcr;
+ if (vcpu == vmm_scheduler_current_vcpu()) {
+ msr(hcr_el2, hcr);
+ }
+ }
+
+ vmm_spin_unlock_irqrestore(&arm_priv(vcpu)->hcr_lock, flags);
+
+ return VMM_OK;
+}
+
+
+int arch_vcpu_irq_execute(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 irq_no, u64 reason)
+{
+ int rc;
+ irq_flags_t flags;
+
+ /* Skip IRQ & FIQ if VGIC available */
+ if (arm_vgic_avail(vcpu) &&
+ ((irq_no == CPU_EXTERNAL_IRQ) ||
+ (irq_no == CPU_EXTERNAL_FIQ))) {
+ return VMM_OK;
+ }
+
+ /* Undefined, Data abort, and Prefetch abort
+ * can only be emulated in normal context.
+ */
+ switch(irq_no) {
+ case CPU_UNDEF_INST_IRQ:
+ rc = cpu_vcpu_inject_undef(vcpu, regs);
+ break;
+ case CPU_PREFETCH_ABORT_IRQ:
+ rc = cpu_vcpu_inject_pabt(vcpu, regs);
+ break;
+ case CPU_DATA_ABORT_IRQ:
+ rc = cpu_vcpu_inject_dabt(vcpu, regs, (virtual_addr_t)reason);
+ break;
+ default:
+ rc = VMM_OK;
+ break;
+ };
+
+ vmm_spin_lock_irqsave(&arm_priv(vcpu)->hcr_lock, flags);
+ msr(hcr_el2, arm_priv(vcpu)->hcr);
+ vmm_spin_unlock_irqrestore(&arm_priv(vcpu)->hcr_lock, flags);
+
+ return rc;
+}
+
+int arch_vcpu_irq_deassert(struct vmm_vcpu *vcpu, u32 irq_no, u64 reason)
+{
+ u64 hcr;
+ bool update_hcr;
+ irq_flags_t flags;
+
+ /* Skip IRQ & FIQ if VGIC available */
+ if (arm_vgic_avail(vcpu) &&
+ ((irq_no == CPU_EXTERNAL_IRQ) ||
+ (irq_no == CPU_EXTERNAL_FIQ))) {
+ return VMM_OK;
+ }
+
+ vmm_spin_lock_irqsave(&arm_priv(vcpu)->hcr_lock, flags);
+
+ hcr = arm_priv(vcpu)->hcr;
+ update_hcr = FALSE;
+
+ switch(irq_no) {
+ case CPU_EXTERNAL_IRQ:
+ hcr &= ~HCR_VI_MASK;
+ update_hcr = TRUE;
+ break;
+ case CPU_EXTERNAL_FIQ:
+ hcr &= ~HCR_VF_MASK;
+ update_hcr = TRUE;
+ break;
+ default:
+ break;
+ };
+
+ if (update_hcr) {
+ arm_priv(vcpu)->hcr = hcr;
+ if (vcpu == vmm_scheduler_current_vcpu()) {
+ msr(hcr_el2, hcr);
+ }
+ }
+
+ vmm_spin_unlock_irqrestore(&arm_priv(vcpu)->hcr_lock, flags);
+
+ return VMM_OK;
+}
+
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_mem.c b/arch/arm/cpu/arm64/cpu_vcpu_mem.c
new file mode 100644
index 0000000..1b58f0f
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_mem.c
@@ -0,0 +1,135 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_mem.c
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief This source file is for VCPU memory read/write emulation
+ */
+
+#include <vmm_error.h>
+#include <vmm_devemu.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_helper.h>
+#include <cpu_vcpu_mem.h>
+
+int cpu_vcpu_mem_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *dst, u32 dst_len,
+ bool force_unpriv)
+{
+ int rc;
+ u8 data8;
+ u16 data16;
+ u32 data32;
+ physical_addr_t guest_pa;
+
+ /* Determine guest physical address */
+ va2pa_at(VA2PA_STAGE1, VA2PA_EL1, VA2PA_RD, addr);
+ guest_pa = mrs(par_el1);
+ guest_pa &= PAR_PA_MASK;
+ guest_pa |= (addr & 0x00000FFF);
+
+ /* Do guest memory read */
+ switch (dst_len) {
+ case 1:
+ rc = vmm_devemu_emulate_read(vcpu, guest_pa,
+ &data8, sizeof(data8));
+ *((u8 *)dst) = (!rc) ? data8 : 0;
+ break;
+ case 2:
+ rc = vmm_devemu_emulate_read(vcpu, guest_pa,
+ &data16, sizeof(data16));
+ *((u16 *)dst) = (!rc) ? data16 : 0;
+ break;
+ case 4:
+ rc = vmm_devemu_emulate_read(vcpu, guest_pa,
+ &data32, sizeof(data32));
+ *((u32 *)dst) = (!rc) ? data32 : 0;
+ break;
+ default:
+ rc = VMM_EFAIL;
+ break;
+ };
+
+ return rc;
+}
+
+int cpu_vcpu_mem_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *src, u32 src_len,
+ bool force_unpriv)
+{
+ int rc;
+ u8 data8;
+ u16 data16;
+ u32 data32;
+ physical_addr_t guest_pa;
+
+ /* Determine guest physical address */
+ va2pa_at(VA2PA_STAGE1, VA2PA_EL1, VA2PA_WR, addr);
+ guest_pa = mrs(par_el1);
+ guest_pa &= PAR_PA_MASK;
+ guest_pa |= (addr & 0x00000FFF);
+
+ /* Do guest memory read */
+ switch (src_len) {
+ case 1:
+ data8 = *((u8 *)src);
+ rc = vmm_devemu_emulate_write(vcpu, guest_pa,
+ &data8, sizeof(data8));
+ break;
+ case 2:
+ data16 = *((u16 *)src);
+ rc = vmm_devemu_emulate_write(vcpu, guest_pa,
+ &data16, sizeof(data16));
+ break;
+ case 4:
+ data32 = *((u32 *)src);
+ rc = vmm_devemu_emulate_write(vcpu, guest_pa,
+ &data32, sizeof(data32));
+ break;
+ default:
+ rc = VMM_EFAIL;
+ break;
+ };
+
+ return rc;
+}
+
+int cpu_vcpu_mem_readex(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *dst, u32 dst_len,
+ bool force_unpriv)
+{
+ /* Not supported */
+ return VMM_EFAIL;
+}
+
+int cpu_vcpu_mem_writeex(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *src, u32 src_len,
+ bool force_unpriv)
+{
+ /* Not supported */
+ return VMM_EFAIL;
+}
+
diff --git a/arch/arm/cpu/arm64/cpu_vcpu_spr.c b/arch/arm/cpu/arm64/cpu_vcpu_spr.c
new file mode 100644
index 0000000..de22a0d
--- /dev/null
+++ b/arch/arm/cpu/arm64/cpu_vcpu_spr.c
@@ -0,0 +1,359 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_spr.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief VCPU SPR Emulation
+ * @details This source file implements SPRs for each VCPU.
+ */
+
+#include <vmm_heap.h>
+#include <vmm_error.h>
+#include <vmm_stdio.h>
+#include <vmm_devemu.h>
+#include <vmm_scheduler.h>
+#include <vmm_host_aspace.h>
+#include <vmm_guest_aspace.h>
+#include <vmm_vcpu_irq.h>
+#include <libs/stringlib.h>
+#include <cpu_inline_asm.h>
+#include <cpu_vcpu_helper.h>
+#include <cpu_vcpu_emulate.h>
+#include <cpu_vcpu_spr.h>
+#include <mmu_lpae.h>
+#include <emulate_arm.h>
+#include <emulate_thumb.h>
+#include <arm_features.h>
+
+static int cpu_vcpu_stage2_map(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ physical_addr_t fipa)
+{
+ int rc, rc1;
+ u32 reg_flags = 0x0;
+ struct cpu_page pg;
+ physical_addr_t inaddr, outaddr;
+ physical_size_t size, availsz;
+
+ memset(&pg, 0, sizeof(pg));
+
+ inaddr = fipa & TTBL_L3_MAP_MASK;
+ size = TTBL_L3_BLOCK_SIZE;
+ pg.sh = 3U;
+
+ rc = vmm_guest_physical_map(vcpu->guest, inaddr, size,
+ &outaddr, &availsz, &reg_flags);
+ if (rc) {
+ vmm_printf("%s: IPA=0x%lx size=0x%lx map failed\n",
+ __func__, inaddr, size);
+ return rc;
+ }
+
+ if (availsz < TTBL_L3_BLOCK_SIZE) {
+ vmm_printf("%s: availsz=0x%lx insufficent for IPA=0x%lx\n",
+ __func__, availsz, inaddr);
+ return VMM_EFAIL;
+ }
+
+ pg.ia = inaddr;
+ pg.sz = size;
+ pg.oa = outaddr;
+
+ if (reg_flags & (VMM_REGION_ISRAM | VMM_REGION_ISROM)) {
+ inaddr = fipa & TTBL_L2_MAP_MASK;
+ size = TTBL_L2_BLOCK_SIZE;
+ rc = vmm_guest_physical_map(vcpu->guest, inaddr, size,
+ &outaddr, &availsz, &reg_flags);
+ if (!rc && (availsz >= TTBL_L2_BLOCK_SIZE)) {
+ pg.ia = inaddr;
+ pg.sz = size;
+ pg.oa = outaddr;
+ }
+ }
+
+ if (reg_flags & VMM_REGION_VIRTUAL) {
+ pg.af = 0;
+ pg.ap = TTBL_HAP_NOACCESS;
+ } else if (reg_flags & VMM_REGION_READONLY) {
+ pg.af = 1;
+ pg.ap = TTBL_HAP_READONLY;
+ } else {
+ pg.af = 1;
+ pg.ap = TTBL_HAP_READWRITE;
+ }
+
+ /* memattr in stage 2
+ * ------------------
+ * 0x0 - strongly ordered
+ * 0x5 - normal-memory NC
+ * 0xA - normal-memory WT
+ * 0xF - normal-memory WB
+ */
+ if (reg_flags & VMM_REGION_CACHEABLE) {
+ if (reg_flags & VMM_REGION_BUFFERABLE) {
+ pg.memattr = 0xF;
+ } else {
+ pg.memattr = 0xA;
+ }
+ } else {
+ pg.memattr = 0x0;
+ }
+
+ /* Try to map the page in Stage2 */
+ rc = mmu_lpae_map_page(arm_guest_priv(vcpu->guest)->ttbl, &pg);
+ if (rc) {
+ /* On SMP Guest, two different VCPUs may try to map same
+ * Guest region in Stage2 at the same time. This may cause
+ * mmu_lpae_map_page() to fail for one of the Guest VCPUs.
+ *
+ * To take care of this situation, we recheck Stage2 mapping
+ * when mmu_lpae_map_page() fails.
+ */
+ memset(&pg, 0, sizeof(pg));
+ rc1 = mmu_lpae_get_page(arm_guest_priv(vcpu->guest)->ttbl,
+ fipa, &pg);
+ if (rc1) {
+ return rc1;
+ }
+ rc = VMM_OK;
+ }
+
+ return rc;
+}
+
+int cpu_vcpu_inst_abort(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss,
+ physical_addr_t fipa)
+{
+ switch (iss & ISS_ABORT_FSC_MASK) {
+ case FSC_TRANS_FAULT_LEVEL1:
+ case FSC_TRANS_FAULT_LEVEL2:
+ case FSC_TRANS_FAULT_LEVEL3:
+ return cpu_vcpu_stage2_map(vcpu, regs, fipa);
+ default:
+ break;
+ };
+
+ return VMM_EFAIL;
+}
+
+int cpu_vcpu_data_abort(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 il, u32 iss,
+ physical_addr_t fipa)
+{
+ u32 read_count, inst;
+ physical_addr_t inst_pa;
+
+ switch (iss & ISS_ABORT_FSC_MASK) {
+ case FSC_TRANS_FAULT_LEVEL1:
+ case FSC_TRANS_FAULT_LEVEL2:
+ case FSC_TRANS_FAULT_LEVEL3:
+ return cpu_vcpu_stage2_map(vcpu, regs, fipa);
+ case FSC_ACCESS_FAULT_LEVEL1:
+ case FSC_ACCESS_FAULT_LEVEL2:
+ case FSC_ACCESS_FAULT_LEVEL3:
+ if (!(iss & ISS_ABORT_ISV_MASK)) {
+ /* Determine instruction physical address */
+ va2pa_at(VA2PA_STAGE1, VA2PA_EL1, VA2PA_RD, regs->pc);
+ inst_pa = mrs(par_el1);
+ inst_pa &= PAR_PA_MASK;
+ inst_pa |= (regs->pc & 0x00000FFF);
+
+ /* Read the faulting instruction */
+ read_count =
+ vmm_host_memory_read(inst_pa, &inst, sizeof(inst));
+ if (read_count != sizeof(inst)) {
+ return VMM_EFAIL;
+ }
+ if (regs->pstate & PSR_THUMB_ENABLED) {
+ return emulate_thumb_inst(vcpu, regs, inst);
+ } else {
+ return emulate_arm_inst(vcpu, regs, inst);
+ }
+ }
+ if (iss & ISS_ABORT_WNR_MASK) {
+ return cpu_vcpu_emulate_store(vcpu, regs,
+ il, iss, fipa);
+ } else {
+ return cpu_vcpu_emulate_load(vcpu, regs,
+ il, iss, fipa);
+ }
+ default:
+ vmm_printf("%s: Unhandled FSC=0x%x\n",
+ __func__, iss & ISS_ABORT_FSC_MASK);
+ break;
+ };
+
+ return VMM_EFAIL;
+}
+
+bool cpu_vcpu_cp15_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 *data)
+{
+ *data = 0x0;
+ switch (CRn) {
+ case 1: /* System configuration. */
+ switch (opc2) {
+ case 1: /* Auxiliary control register. */
+ if (!arm_feature(vcpu, ARM_FEATURE_AUXCR))
+ goto bad_reg;
+ switch (arm_cpuid(vcpu)) {
+ case ARM_CPUID_CORTEXA8:
+ *data = 2;
+ break;
+ case ARM_CPUID_CORTEXA9:
+ *data = 0;
+ if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
+ *data |= (1 << 6);
+ } else {
+ *data &= ~(1 << 6);
+ }
+ break;
+ case ARM_CPUID_CORTEXA15:
+ *data = 0;
+ if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
+ *data |= (1 << 6);
+ } else {
+ *data &= ~(1 << 6);
+ }
+ break;
+ default:
+ goto bad_reg;
+ }
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ case 15:
+ switch (opc1) {
+ case 4: /* CBAR: Configuration Base Address Register */
+ switch (arm_cpuid(vcpu)) {
+ case ARM_CPUID_CORTEXA9:
+ *data = 0x1e000000;
+ break;
+ case ARM_CPUID_CORTEXA15:
+ *data = 0x2c000000;
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ break;
+ }
+ return TRUE;
+bad_reg:
+ vmm_printf("Unimplemented [mrc p15, %d, <Rt>, c%d, c%d, %d]\n",
+ opc1, CRn, CRm, opc2);
+ return FALSE;
+}
+
+bool cpu_vcpu_cp15_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 data)
+{
+ switch (CRn) {
+ case 1: /* System configuration. */
+ switch (opc2) {
+ case 1: /* Auxiliary control register. */
+ /* Not implemented. */
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ }
+ return TRUE;
+bad_reg:
+ vmm_printf("Unimplemented [mcr p15, %d, <Rt>, c%d, c%d, %d]\n",
+ opc1, CRn, CRm, opc2);
+ return FALSE;
+}
+
+bool cpu_vcpu_cp14_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 *data)
+{
+ *data = 0x0;
+ switch (opc1) {
+ case 6: /* ThumbEE registers */
+ switch (CRn) {
+ case 0: /* TEECR */
+ *data = arm_priv(vcpu)->teecr;
+ break;
+ case 1: /* TEEHBR */
+ *data = arm_priv(vcpu)->teehbr;
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ case 0: /* Debug registers */
+ case 1: /* Trace registers */
+ case 7: /* Jazelle registers */
+ default:
+ goto bad_reg;
+ };
+ return TRUE;
+bad_reg:
+ vmm_printf("Unimplemented [mrc p14, %d, <Rt>, c%d, c%d, %d]\n",
+ opc1, CRn, CRm, opc2);
+ return FALSE;
+}
+
+bool cpu_vcpu_cp14_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 data)
+{
+ switch (opc1) {
+ case 6: /* ThumbEE registers */
+ switch (CRn) {
+ case 0: /* TEECR */
+ arm_priv(vcpu)->teecr = data;
+ break;
+ case 1: /* TEEHBR */
+ arm_priv(vcpu)->teehbr = data;
+ break;
+ default:
+ goto bad_reg;
+ };
+ break;
+ case 0: /* Debug registers */
+ case 1: /* Trace registers */
+ case 7: /* Jazelle registers */
+ default:
+ goto bad_reg;
+ };
+ return TRUE;
+bad_reg:
+ vmm_printf("Unimplemented [mcr p14, %d, <Rt>, c%d, c%d, %d]\n",
+ opc1, CRn, CRm, opc2);
+ return FALSE;
+}
+
diff --git a/arch/arm/cpu/arm64/include/arch_barrier.h b/arch/arm/cpu/arm64/include/arch_barrier.h
new file mode 100644
index 0000000..c7c53fe
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_barrier.h
@@ -0,0 +1,48 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_barrier.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief architecure specific memory barriers
+ */
+#ifndef __ARCH_BARRIER_H__
+#define __ARCH_BARRIER_H__
+
+#define isb() asm volatile ("isb" : : : "memory")
+#define dsb() asm volatile ("dsb sy" : : : "memory")
+#define dmb() asm volatile ("dmb sy" : : : "memory")
+
+/* Read & Write Memory barrier */
+#define arch_mb() dmb()
+
+/* Read Memory barrier */
+#define arch_rmb() asm volatile ("dmb ld" : : : "memory")
+
+/* Write Memory barrier */
+#define arch_wmb() asm volatile ("dmb st" : : : "memory")
+
+/* SMP Read & Write Memory barrier */
+#define arch_smp_mb() asm volatile ("dmb ish" : : : "memory")
+
+/* SMP Read Memory barrier */
+#define arch_smp_rmb() asm volatile ("dmb ishld" : : : "memory")
+
+/* SMP Write Memory barrier */
+#define arch_smp_wmb() asm volatile ("dmb ishst" : : : "memory")
+
+#endif /* __ARCH_BARRIER_H__ */
diff --git a/arch/arm/cpu/arm64/include/arch_cache.h b/arch/arm/cpu/arm64/include/arch_cache.h
new file mode 100644
index 0000000..45f1d11
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_cache.h
@@ -0,0 +1,56 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_cache.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief arch specific cache operation
+ */
+#ifndef _ARCH_CACHE_H__
+#define _ARCH_CACHE_H__
+
+#include <cpu_cache.h>
+
+#define ARCH_CACHE_LINE_SIZE 64
+#define ARCH_CACHE_LINE_SHIFT 6
+
+/* Prototype:
+ * void arch_flush_cache_all(void)
+ */
+#define ARCH_HAS_FLUSH_CACHE_ALL
+#define arch_flush_cache_all() do { \
+ clean_invalidate_dcache(); \
+ } while (0)
+
+/* Prototype:
+ * void arch_flush_cache_range(virtual_addr_t start, virtual_addr_t end)
+ */
+#define ARCH_HAS_FLUSH_CACHE_RANGE
+#define arch_flush_cache_range(start, end) do { \
+ clean_invalidate_dcache_mva_range((start),(end)); \
+ } while (0)
+
+/* Prototype:
+ * void arch_flush_dcache_range(virtual_addr_t start, virtual_addr_t end)
+ */
+#define ARCH_HAS_FLUSH_DCACHE_RANGE
+#define arch_flush_dcache_range(start, end) do { \
+ clean_invalidate_dcache_mva_range((start),(end)); \
+ } while (0)
+
+
+#endif /* _ARCH_CACHE_H__ */
diff --git a/arch/arm/cpu/arm64/include/arch_config.h b/arch/arm/cpu/arm64/include/arch_config.h
new file mode 100644
index 0000000..33a7870
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_config.h
@@ -0,0 +1,30 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_config.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief config file for specifying arch specific optional features
+ *
+ */
+#ifndef _ARCH_CONFIG_H__
+#define _ARCH_CONFIG_H__
+
+//#define ARCH_HAS_MEMCPY
+//#define ARCH_HAS_MEMSET
+
+#endif /* _ARCH_CONFIG_H__ */
diff --git a/arch/arm/cpu/arm64/include/arch_cpu_irq.h b/arch/arm/cpu/arm64/include/arch_cpu_irq.h
new file mode 100644
index 0000000..b343ec1
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_cpu_irq.h
@@ -0,0 +1,82 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_cpu_irq.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief interface for controlling CPU IRQs
+ */
+#ifndef _ARCH_CPU_IRQ_H__
+#define _ARCH_CPU_IRQ_H__
+
+#include <vmm_types.h>
+#include <cpu_defines.h>
+
+/** Setup IRQ for CPU */
+int arch_cpu_irq_setup(void);
+
+/** Enable IRQ
+ * Prototype: void arch_cpu_irq_enable(void);
+ */
+#define arch_cpu_irq_enable() do { \
+ asm volatile("msr daifclr, #2":::"memory"); \
+ } while (0)
+
+/** Disable IRQ
+ * Prototype: void arch_cpu_irq_disable(void);
+ */
+#define arch_cpu_irq_disable() do { \
+ asm volatile("msr daifset, #2":::"memory"); \
+ } while (0)
+
+/** Check whether IRQs are disabled
+ * Prototype: bool arch_cpu_irq_disabled(void);
+ */
+#define arch_cpu_irq_disabled() ({ unsigned long __flgs; \
+ asm volatile (" mrs %0, daif" \
+ :"=r" (__flgs)::"memory", "cc"); \
+ (__flgs & PSR_IRQ_DISABLED) ? TRUE : FALSE; \
+ })
+
+
+/** Save IRQ flags and disable IRQ
+ * Prototype: void arch_cpu_irq_save(irq_flags_t flags);
+ */
+#define arch_cpu_irq_save(flags) do { \
+ asm volatile ( \
+ "mrs %0, daif\n\t" \
+ "msr daifset, #2" \
+ :"=r" (flags)::"memory", "cc"); \
+ } while(0)
+
+/** Restore IRQ flags
+ * Prototype: void arch_cpu_irq_restore(irq_flags_t flags);
+ */
+#define arch_cpu_irq_restore(flags) do { \
+ asm volatile ( \
+ "msr daif, %0"::"r" (flags) \
+ :"memory", "cc"); \
+ } while(0)
+
+/** Wait for IRQ
+ * Prototype: void arch_cpu_wait_for_irq(void);
+ */
+#define arch_cpu_wait_for_irq() do { \
+ asm volatile ("wfi"); \
+ } while (0)
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_delay.h b/arch/arm/cpu/arm64/include/arch_delay.h
new file mode 100644
index 0000000..88e7c9b
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_delay.h
@@ -0,0 +1,39 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_delay.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief arch specific delay routines
+ */
+#ifndef _ARCH_DELAY_H__
+#define _ARCH_DELAY_H__
+
+#include <vmm_types.h>
+
+/** Low-level delay loop */
+void arch_delay_loop(u32 count);
+
+/** Estimated cycles for given loop count
+ * Note: This can be processor specific
+ */
+static inline u32 arch_delay_loop_cycles(u32 count)
+{
+ return count * 2;
+}
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_elf.h b/arch/arm/cpu/arm64/include/arch_elf.h
new file mode 100644
index 0000000..c7078f8
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_elf.h
@@ -0,0 +1,99 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_elf.h
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief arch specific ELF routines
+ */
+#ifndef _ARCH_ELF_H__
+#define _ARCH_ELF_H__
+
+#include <vmm_types.h>
+
+/* ARM elf specific declarations */
+
+#define EF_ARM_EABI_MASK 0xff000000
+#define EF_ARM_EABI_UNKNOWN 0x00000000
+#define EF_ARM_EABI_VER1 0x01000000
+#define EF_ARM_EABI_VER2 0x02000000
+#define EF_ARM_EABI_VER3 0x03000000
+#define EF_ARM_EABI_VER4 0x04000000
+#define EF_ARM_EABI_VER5 0x05000000
+
+#define EF_ARM_BE8 0x00800000 /* ABI 4,5 */
+#define EF_ARM_LE8 0x00400000 /* ABI 4,5 */
+#define EF_ARM_MAVERICK_FLOAT 0x00000800 /* ABI 0 */
+#define EF_ARM_VFP_FLOAT 0x00000400 /* ABI 0 */
+#define EF_ARM_SOFT_FLOAT 0x00000200 /* ABI 0 */
+#define EF_ARM_OLD_ABI 0x00000100 /* ABI 0 */
+#define EF_ARM_NEW_ABI 0x00000080 /* ABI 0 */
+#define EF_ARM_ALIGN8 0x00000040 /* ABI 0 */
+#define EF_ARM_PIC 0x00000020 /* ABI 0 */
+#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ABI 2 */
+#define EF_ARM_APCS_FLOAT 0x00000010 /* ABI 0, floats in fp regs */
+#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ABI 2 */
+#define EF_ARM_APCS_26 0x00000008 /* ABI 0 */
+#define EF_ARM_SYMSARESORTED 0x00000004 /* ABI 1,2 */
+#define EF_ARM_INTERWORK 0x00000004 /* ABI 0 */
+#define EF_ARM_HASENTRY 0x00000002 /* All */
+#define EF_ARM_RELEXEC 0x00000001 /* All */
+
+#define R_ARM_NONE 0
+#define R_ARM_PC24 1
+#define R_ARM_ABS32 2
+#define R_ARM_CALL 28
+#define R_ARM_JUMP24 29
+#define R_ARM_V4BX 40
+#define R_ARM_PREL31 42
+#define R_ARM_MOVW_ABS_NC 43
+#define R_ARM_MOVT_ABS 44
+
+#define R_ARM_THM_CALL 10
+#define R_ARM_THM_JUMP24 30
+#define R_ARM_THM_MOVW_ABS_NC 47
+#define R_ARM_THM_MOVT_ABS 48
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS64
+#ifdef __ARMEB__
+#define ELF_DATA ELFDATA2MSB
+#else
+#define ELF_DATA ELFDATA2LSB
+#endif
+#define ELF_ARCH EM_AARCH64
+
+struct elf64_hdr;
+struct elf64_shdr;
+
+int arch_elf_check_hdr(const struct elf64_hdr *x);
+
+int arch_elf_apply_relocate(struct elf64_shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relindex,
+ struct vmm_module *mod);
+
+int arch_elf_apply_relocate_add(struct elf64_shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct vmm_module *mod);
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_io.h b/arch/arm/cpu/arm64/include/arch_io.h
new file mode 100644
index 0000000..130d9cd
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_io.h
@@ -0,0 +1,193 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_io.h
+ * @author Anup Patel (an...@brainfault.org)
+ * @author Jim Huang (js...@0xlab.org)
+ * @brief header file for CPU I/O or Memory read/write functions
+ */
+#ifndef _ARCH_IO_H__
+#define _ARCH_IO_H__
+
+#include <vmm_types.h>
+#include <arch_barrier.h>
+#include <cpu_inline_asm.h>
+
+#define __raw_write8(a,v) (*(volatile u8 *)(a) = (v))
+#define __raw_write16(a,v) (*(volatile u16 *)(a) = (v))
+#define __raw_write32(a,v) (*(volatile u32 *)(a) = (v))
+#define __raw_write64(a,v) (*(volatile u64 *)(a) = (v))
+
+#define __raw_read8(a) (*(volatile u8 *)(a))
+#define __raw_read16(a) (*(volatile u16 *)(a))
+#define __raw_read32(a) (*(volatile u32 *)(a))
+#define __raw_read64(a) (*(volatile u64 *)(a))
+
+#define __iormb() arch_rmb()
+#define __iowmb() arch_wmb()
+
+/*
+ * Endianness primitives
+ * ------------------------
+ */
+#define arch_cpu_to_le16(v) (v)
+
+#define arch_le16_to_cpu(v) (v)
+
+#define arch_cpu_to_be16(v) rev16(v)
+
+#define arch_be16_to_cpu(v) rev16(v)
+
+#define arch_cpu_to_le32(v) (v)
+
+#define arch_le32_to_cpu(v) (v)
+
+#define arch_cpu_to_be32(v) rev32(v)
+
+#define arch_be32_to_cpu(v) rev32(v)
+
+#define arch_cpu_to_le64(v) (v)
+
+#define arch_le64_to_cpu(v) (v)
+
+#define arch_cpu_to_be64(v) rev64(v)
+
+#define arch_be64_to_cpu(v) rev64(v)
+
+#define __io(p) ((void *)p)
+
+/*
+ * IO port access primitives
+ * -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped. Note that these are defined to perform little endian accesses
+ * only. For ARM, IO port read/write operations translate to a read/write
+ * operation to memory address. All IO port read/write operations are
+ * assumed to be little-endian.
+ */
+#define arch_outb(v, p) {__iowmb(); __raw_write8(__io(p), v); }
+#define arch_outw(v, p) {__iowmb(); __raw_write16(__io(p), v); }
+#define arch_outl(v, p) {__iowmb(); __raw_write32(__io(p), v); }
+#define arch_inb(p) ({u8 v = __raw_read8(__io(p)); __iormb(); v; })
+#define arch_inw(p) ({u16 v = __raw_read16(__io(p)); __iormb(); v; })
+#define arch_inl(p) ({u32 v = __raw_read32(__io(p)); __iormb(); v; })
+
+#define arch_outb_p(v, p) arch_outb((v), (p))
+#define arch_outw_p(v, p) arch_outw((v), (p))
+#define arch_outl_p(v, p) arch_outl((v), (p))
+#define arch_inb_p(p) arch_inb((p))
+#define arch_inw_p(p) arch_inw((p))
+#define arch_inl_p(p) arch_inl((p))
+
+static inline void arch_insb(unsigned long p, void *b, int c)
+{
+ if (c) {
+ u8 *buf = b;
+ do {
+ u8 x = arch_inb(p);
+ *buf++ = x;
+ } while (--c);
+ }
+}
+
+static inline void arch_insw(unsigned long p, void *b, int c)
+{
+ if (c) {
+ u16 *buf = b;
+ do {
+ u16 x = arch_inw(p);
+ *buf++ = x;
+ } while (--c);
+ }
+}
+
+static inline void arch_insl(unsigned long p, void *b, int c)
+{
+ if (c) {
+ u32 *buf = b;
+ do {
+ u32 x = arch_inl(p);
+ *buf++ = x;
+ } while (--c);
+ }
+}
+
+static inline void arch_outsb(unsigned long p, const void *b, int c)
+{
+ if (c) {
+ const u8 *buf = b;
+ do {
+ arch_outb(*buf++, p);
+ } while (--c);
+ }
+}
+
+static inline void arch_outsw(unsigned long p, const void *b, int c)
+{
+ if (c) {
+ const u16 *buf = b;
+ do {
+ arch_outw(*buf++, p);
+ } while (--c);
+ }
+}
+
+static inline void arch_outsl(unsigned long p, const void *b, int c)
+{
+ if (c) {
+ const u32 *buf = b;
+ do {
+ arch_outl(*buf++, p);
+ } while (--c);
+ }
+}
+
+/*
+ * Memory access primitives
+ * ------------------------
+ */
+#define arch_in_8(a) ({u8 v = __raw_read8(a); __iormb(); v; })
+
+#define arch_out_8(a, v) {__iowmb(); __raw_write8(a, v); }
+
+#define arch_in_le16(a) ({u16 v = __raw_read16(a); __iormb(); v; })
+
+#define arch_out_le16(a, v) ({__raw_write16(a, v); __iowmb(); })
+
+#define arch_in_be16(a) ({u16 v = __raw_read16(a); __iormb(); rev16(v); })
+
+#define arch_out_be16(a, v) {__iowmb(); __raw_write16(a, (rev16(v))); }
+
+#define arch_in_le32(a) ({u32 v = __raw_read32(a); __iormb(); v; })
+
+#define arch_out_le32(a, v) {__iowmb(); __raw_write32(a, v); }
+
+#define arch_in_be32(a) ({u32 v = __raw_read32(a); __iormb(); rev32(v); })
+
+#define arch_out_be32(a, v) {__iowmb(); __raw_write32(a, rev32(v)); }
+
+#define arch_in_le64(a) ({u32 v = __raw_read64(a); __iormb(); v; })
+
+#define arch_out_le64(a, v) {__iowmb(); __raw_write64(a, v); }
+
+#define arch_in_be64(a) ({u32 v = __raw_read64(a); __iormb(); rev64(v); })
+
+#define arch_out_be64(a, v) {__iowmb(); __raw_write64(a, rev64(v)); }
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_regs.h b/arch/arm/cpu/arm64/include/arch_regs.h
new file mode 100644
index 0000000..431a98b
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_regs.h
@@ -0,0 +1,152 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_regs.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief common header file for CPU registers
+ */
+#ifndef _ARCH_REGS_H__
+#define _ARCH_REGS_H__
+
+#include <vmm_types.h>
+#include <vmm_spinlocks.h>
+#include <cpu_defines.h>
+#include <generic_timer.h>
+
+struct arch_regs {
+ u64 gpr[CPU_GPR_COUNT]; /* X0 - X29 */
+ u64 lr;
+ u64 sp; /* Stack Pointer */
+ u64 pc; /* Program Counter */
+ u64 pstate; /* PState/SPSR */
+} __attribute((packed));
+
+typedef struct arch_regs arch_regs_t;
+
+struct arm_priv {
+ /* Internal CPU feature flags. */
+ u64 features;
+ /* Hypervisor context */
+ vmm_spinlock_t hcr_lock;
+ u64 hcr; /* Hypervisor Configuration */
+ u64 cptr; /* Coprocessor Trap Register */
+ u64 hstr; /* Hypervisor System Trap Register */
+ /* EL1 Registers */
+ u64 sp_el0;
+ u64 sp_el1;
+ u64 elr_el1;
+ u64 spsr_el1;
+ u32 spsr_abt;
+ u32 spsr_und;
+ u32 spsr_irq;
+ u32 spsr_fiq;
+ u64 cpuid;
+ u64 mpidr;
+ u64 sctlr; /* System control register. */
+ u64 actlr; /* Auxillary control register. */
+ u64 cpacr; /* Coprocessor access register. */
+ u64 ttbr0; /* MMU translation table base 0. */
+ u64 ttbr1; /* MMU translation table base 1. */
+ u64 tcr; /* MMU translation control register. */
+ u64 esr; /* Exception status register. */
+ u64 far; /* Fault address register. */
+ u64 par; /* Translation result. */
+ u64 mair; /* Memory attribute Index Register */
+ u64 vbar; /* Vector base address register */
+ u64 contextidr; /* Context ID. */
+ u64 tpidr_el0; /* User RW Thread register. */
+ u64 tpidr_el1; /* Privileged Thread register. */
+ u64 tpidrro; /* User RO Thread register. */
+ /* ThumbEE registers */
+ u64 teecr;
+ u32 teehbr;
+ /* VFP & SMID registers */
+ u32 fpexc;
+ u32 fpcr;
+ u32 fpsr;
+ u64 fpregs[128]; /* 32x32 floating point registers. */
+ /* 32bit only registers */
+ u32 cp15_c0_c1[8];
+ u32 cp15_c0_c2[8];
+ u32 dacr; /* MMU domain access control register */
+ u32 ifsr; /* Fault status registers. */
+ /* Last host CPU on which this VCPU ran */
+ u32 last_hcpu;
+ /* Generic timer context */
+ struct generic_timer_context gentimer_context;
+ /* VGIC context */
+ bool vgic_avail;
+ void (*vgic_save)(void *vcpu_ptr);
+ void (*vgic_restore)(void *vcpu_ptr);
+ void *vgic_priv;
+} __attribute((packed));
+
+typedef struct arm_priv arm_priv_t;
+
+struct arm_guest_priv {
+ /* Stage2 table */
+ struct cpu_ttbl *ttbl;
+};
+
+typedef struct arm_guest_priv arm_guest_priv_t;
+
+#define arm_regs(vcpu) (&((vcpu)->regs))
+#define arm_priv(vcpu) ((arm_priv_t *)((vcpu)->arch_priv))
+#define arm_guest_priv(guest) ((arm_guest_priv_t *)((guest)->arch_priv))
+
+#define arm_cpuid(vcpu) (arm_priv(vcpu)->cpuid)
+#define arm_set_feature(vcpu, feat) (arm_priv(vcpu)->features |= (0x1ULL << (feat)))
+#define arm_feature(vcpu, feat) (arm_priv(vcpu)->features & (0x1ULL << (feat)))
+
+/**
+ * Instruction emulation support macros
+ */
+#define arm_cpsr(regs) ((u32)((regs)->pstate & 0xffffffff))
+#define arm_pc(regs) ((regs)->pc)
+
+/**
+ * Generic timers support macro
+ */
+#define arm_gentimer_context(vcpu) (&(arm_priv(vcpu)->gentimer_context))
+
+/**
+ * VGIC support macros
+ */
+#define arm_vgic_setup(vcpu, __save_func, __restore_func, __priv) \
+ do { \
+ arm_priv(vcpu)->vgic_avail = TRUE; \
+ arm_priv(vcpu)->vgic_save = __save_func; \
+ arm_priv(vcpu)->vgic_restore = __restore_func; \
+ arm_priv(vcpu)->vgic_priv = __priv; \
+ } while (0)
+#define arm_vgic_cleanup(vcpu) do { \
+ arm_priv(vcpu)->vgic_avail = FALSE; \
+ arm_priv(vcpu)->vgic_save = NULL; \
+ arm_priv(vcpu)->vgic_restore = NULL; \
+ arm_priv(vcpu)->vgic_priv = NULL; \
+ } while (0)
+#define arm_vgic_avail(vcpu) (arm_priv(vcpu)->vgic_avail)
+#define arm_vgic_save(vcpu) if (arm_vgic_avail(vcpu)) { \
+ arm_priv(vcpu)->vgic_save(vcpu); \
+ }
+#define arm_vgic_restore(vcpu) if (arm_vgic_avail(vcpu)) { \
+ arm_priv(vcpu)->vgic_restore(vcpu); \
+ }
+#define arm_vgic_priv(vcpu) (arm_priv(vcpu)->vgic_priv)
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_sections.h b/arch/arm/cpu/arm64/include/arch_sections.h
new file mode 100644
index 0000000..80367ba
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_sections.h
@@ -0,0 +1,69 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_sections.h
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief interface for accessing VMM sections
+ */
+#ifndef _ARCH_SECTIONS_H__
+#define _ARCH_SECTIONS_H__
+
+#include <vmm_types.h>
+
+/** Overall code */
+virtual_addr_t arch_code_vaddr_start(void);
+physical_addr_t arch_code_paddr_start(void);
+virtual_size_t arch_code_size(void);
+
+/** Module table */
+extern u8 _modtbl_start;
+extern u8 _modtbl_end;
+static inline virtual_addr_t arch_modtbl_vaddr(void)
+{
+ return (virtual_addr_t) &_modtbl_start;
+}
+static inline virtual_size_t arch_modtbl_size(void)
+{
+ return (virtual_size_t) (&_modtbl_end - &_modtbl_start);
+}
+
+/** PerCPU section */
+extern u8 _percpu_start;
+extern u8 _percpu_end;
+static inline virtual_addr_t arch_percpu_vaddr(void)
+{
+ return (virtual_addr_t) &_percpu_start;
+}
+static inline virtual_size_t arch_percpu_size(void)
+{
+ return (virtual_size_t) (&_percpu_end - &_percpu_start);
+}
+
+/** Init section */
+extern u8 _init_start;
+extern u8 _init_end;
+static inline virtual_addr_t arch_init_vaddr(void)
+{
+ return (virtual_addr_t) &_init_start;
+}
+static inline virtual_size_t arch_init_size(void)
+{
+ return (virtual_size_t) (&_init_end - &_init_start);
+}
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/arch_types.h b/arch/arm/cpu/arm64/include/arch_types.h
new file mode 100644
index 0000000..bfb3bcb
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/arch_types.h
@@ -0,0 +1,71 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file arch_types.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief common header file for typedefs
+ */
+#ifndef _ARCH_TYPES_H__
+#define _ARCH_TYPES_H__
+
+/** cpu specific types */
+typedef unsigned int irq_flags_t;
+typedef unsigned long virtual_addr_t;
+typedef unsigned long virtual_size_t;
+typedef unsigned long physical_addr_t;
+typedef unsigned long physical_size_t;
+
+typedef struct {
+ volatile long counter;
+} atomic_t;
+
+typedef struct {
+ volatile long long counter;
+} atomic64_t;
+
+typedef struct {
+ volatile long lock;
+} arch_spinlock_t;
+
+#define __ARCH_SPIN_UNLOCKED 0xffffffffUL
+
+/* FIXME: Need memory barrier for this. */
+#define ARCH_SPIN_LOCK_INIT(_lptr) \
+ (_lptr)->lock = __ARCH_SPIN_UNLOCKED
+
+#define ARCH_SPIN_LOCK_INITIALIZER \
+ { .lock = __ARCH_SPIN_UNLOCKED, }
+typedef struct {
+ volatile long lock;
+} arch_rwlock_t;
+
+#define __ARCH_RW_LOCKED 0x80000000UL
+#define __ARCH_RW_UNLOCKED 0
+
+/* FIXME: Need memory barrier for this. */
+#define ARCH_RW_LOCK_INIT(_lptr) \
+ (_lptr)->lock = __ARCH_RW_UNLOCKED
+
+#define ARCH_RW_LOCK_INITIALIZER \
+ { .lock = __ARCH_RW_UNLOCKED, }
+
+#define ARCH_BITS_PER_LONG 64
+
+#endif /* _ARCH_TYPES_H__ */
+
+
diff --git a/arch/arm/cpu/arm64/include/cpu_cache.h b/arch/arm/cpu/arm64/include/cpu_cache.h
new file mode 100644
index 0000000..d296f97
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_cache.h
@@ -0,0 +1,76 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_cache.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief cache interface of a ARM processor
+ */
+#ifndef __CPU_CACHE_H__
+#define __CPU_CACHE_H__
+
+#include <vmm_types.h>
+
+/** Invalidate all instruction caches */
+void invalidate_icache(void);
+
+/** Invalidate instruction cache line by MVA to PoU */
+void invalidate_icache_mva(virtual_addr_t mva);
+
+/** Clean data cache */
+void clean_dcache(void);
+
+/** Clean data cache line by MVA */
+void clean_dcache_mva(virtual_addr_t mva);
+
+/** Clean data cache line by MVA range */
+void clean_dcache_mva_range(virtual_addr_t start, virtual_addr_t end);
+
+/** Clean data cache line by set/way */
+void clean_dcache_line(u32 line);
+
+/** Clean unified (instruction or data) cache */
+void clean_idcache(void);
+
+/** Clean unified cache line by MVA */
+void clean_idcache_mva(virtual_addr_t mva);
+
+/** Clean unified cache line by set/way */
+void clean_idcache_line(u32 line);
+
+/** Clean and invalidate data cache */
+void clean_invalidate_dcache(void);
+
+/** Clean and invalidate data cache line by MVA */
+void clean_invalidate_dcache_mva(virtual_addr_t mva);
+
+/** Clean and invalidate data cache lines by MVA range */
+void clean_invalidate_dcache_mva_range(virtual_addr_t start, virtual_addr_t end);
+
+/** Clean and invalidate data cache line by set/way */
+void clean_invalidate_dcache_line(u32 line);
+
+/** Clean and invalidate unified (instruction or data) cache */
+void clean_invalidate_idcache(void);
+
+/** Clean and invalidate unified cache line by MVA */
+void clean_invalidate_idcache_mva(virtual_addr_t mva);
+
+/** Clean and invalidate unified cache line by set/way */
+void clean_invalidate_idcache_line(u32 line);
+
+#endif /* __CPU_CACHE_H__ */
diff --git a/arch/arm/cpu/arm64/include/cpu_defines.h b/arch/arm/cpu/arm64/include/cpu_defines.h
new file mode 100644
index 0000000..6ded7ec
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_defines.h
@@ -0,0 +1,706 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_defines.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief common macros & defines for shared by all C & Assembly code
+ */
+#ifndef __CPU_DEFINES_H__
+#define __CPU_DEFINES_H__
+
+/* Maximum allowed VTLB entries */
+#define CPU_VCPU_VTLB_LINE_MASK 0x00000000
+#define CPU_VCPU_VTLB_LINE_SHIFT 0
+#define CPU_VCPU_VTLB_LINE_COUNT 1
+#define CPU_VCPU_VTLB_LINE_ENTRY_COUNT 128
+#define CPU_VCPU_VTLB_ENTRY_COUNT 128
+
+/* Coprocessor related macros & defines */
+#define CPU_COPROC_COUNT 16
+
+/* GPR related macros & defines */
+#define CPU_GPR_COUNT 30
+
+/* Interrupt or Exception related macros & defines */
+#define EXC_HYP_SYNC_SP0 0
+#define EXC_HYP_IRQ_SP0 1
+#define EXC_HYP_FIQ_SP0 2
+#define EXC_HYP_SERROR_SP0 3
+#define EXC_HYP_SYNC_SPx 4
+#define EXC_HYP_IRQ_SPx 5
+#define EXC_HYP_FIQ_SPx 6
+#define EXC_HYP_SERROR_SPx 7
+#define EXC_GUEST_SYNC_A64 8
+#define EXC_GUEST_IRQ_A64 9
+#define EXC_GUEST_FIQ_A64 10
+#define EXC_GUEST_SERROR_A64 11
+#define EXC_GUEST_SYNC_A32 12
+#define EXC_GUEST_IRQ_A32 13
+#define EXC_GUEST_FIQ_A32 14
+#define EXC_GUEST_SERROR_A32 15
+
+/** Placeholder interrupt/exceptions for arm_emulate */
+#define CPU_IRQ_LOWVEC_BASE 0x00000000
+#define CPU_IRQ_HIGHVEC_BASE 0xFFFF0000
+#define CPU_RESET_IRQ 0
+#define CPU_UNDEF_INST_IRQ 1
+#define CPU_SOFT_IRQ 2
+#define CPU_PREFETCH_ABORT_IRQ 3
+#define CPU_DATA_ABORT_IRQ 4
+#define CPU_HYP_TRAP_IRQ 5
+#define CPU_EXTERNAL_IRQ 6
+#define CPU_EXTERNAL_FIQ 7
+#define CPU_IRQ_NR 8
+
+/* PSR related macros & defines */
+#define PSR_MODE_MASK 0x0000001f
+
+#define PSR_EL_MASK 0x0000000C
+#define PSR_EL_0 0x00000000
+#define PSR_EL_1 0x00000004
+#define PSR_EL_2 0x00000008
+#define PSR_EL_3 0x0000000C
+#define PSR_MODE64_MASK 0x0000000f
+#define PSR_MODE64_EL0t 0x00000000
+#define PSR_MODE64_EL1t 0x00000004
+#define PSR_MODE64_EL1h 0x00000005
+#define PSR_MODE64_EL2t 0x00000008
+#define PSR_MODE64_EL2h 0x00000009
+#define PSR_MODE64_EL3t 0x0000000c
+#define PSR_MODE64_EL3h 0x0000000d
+
+#define PSR_MODE32 0x00000010
+#define PSR_MODE32_MASK 0x0000001f
+#define PSR_MODE32_USER 0x00000010
+#define PSR_MODE32_FIQ 0x00000011
+#define PSR_MODE32_IRQ 0x00000012
+#define PSR_MODE32_SUPERVISOR 0x00000013
+#define PSR_MODE32_MONITOR 0x00000016
+#define PSR_MODE32_ABORT 0x00000017
+#define PSR_MODE32_HYPERVISOR 0x0000001a
+#define PSR_MODE32_UNDEFINED 0x0000001b
+#define PSR_MODE32_SYSTEM 0x0000001f
+#define PSR_FIQ_DISABLED (1 << 6)
+#define PSR_IRQ_DISABLED (1 << 7)
+#define PSR_ASYNC_ABORT_DISABLED (1 << 8)
+#define PSR_MODE64_DEBUG_DISABLED (1 << 9)
+#define PSR_MODE32_BE_ENABLED (1 << 9)
+#define PSR_IL_MASK 0x00100000
+#define PSR_IL_SHIFT 20
+#define PSR_SS_MASK 0x00200000
+#define PSR_SS_SHIFT 21
+#define PSR_OVERFLOW_MASK (1 << 28)
+#define PSR_OVERFLOW_SHIFT 28
+#define PSR_CARRY_MASK (1 << 29)
+#define PSR_CARRY_SHIFT 29
+#define PSR_ZERO_MASK (1 << 30)
+#define PSR_ZERO_SHIFT 30
+#define PSR_NEGATIVE_MASK (1 << 31)
+#define PSR_NEGATIVE_SHIFT 31
+
+/* Fields of AArch32-PSR which will be RES0 in Aarch64 */
+/* Section 3.8.8 Unused fields of SPSR - Exception Model */
+#define PSR_THUMB_ENABLED (1 << 5)
+#define PSR_IT2_MASK 0x0000FC00
+#define PSR_IT2_SHIFT 10
+#define PSR_GE_MASK 0x000F0000
+#define PSR_GE_SHIFT 16
+#define PSR_JAZZLE_ENABLED (1 << 24)
+#define PSR_IT1_MASK 0x06000000
+#define PSR_IT1_SHIFT 25
+#define PSR_CUMMULATE_MASK (1 << 27)
+#define PSR_CUMMULATE_SHIFT 27
+
+#define PSR_NZCV_MASK (PSR_NEGATIVE_MASK |\
+ PSR_ZERO_MASK |\
+ PSR_CARRY_MASK |\
+ PSR_OVERFLOW_MASK)
+#define PSR_IT_MASK (PSR_IT2_MASK |\
+ PSR_IT1_MASK)
+#define PSR_USERBITS_MASK (PSR_NZCV_MASK |\
+ PSR_CUMMULATE_MASK |\
+ PSR_GE_MASK |\
+ PSR_IT_MASK |\
+ PSR_THUMB_ENABLED)
+#define PSR_PRIVBITS_MASK (~PSR_USERBITS_MASK)
+#define PSR_ALLBITS_MASK 0xFFFFFFFF
+
+#define CPSR_MODE_MASK PSR_MODE32_MASK
+#define CPSR_MODE_USER PSR_MODE32_USER
+#define CPSR_MODE_FIQ PSR_MODE32_FIQ
+#define CPSR_MODE_IRQ PSR_MODE32_IRQ
+#define CPSR_MODE_SUPERVISOR PSR_MODE32_SUPERVISOR
+#define CPSR_MODE_MONITOR PSR_MODE32_MONITOR
+#define CPSR_MODE_ABORT PSR_MODE32_ABORT
+#define CPSR_MODE_HYPERVISOR PSR_MODE32_HYPERVISOR
+#define CPSR_MODE_UNDEFINED PSR_MODE32_UNDEFINED
+#define CPSR_MODE_SYSTEM PSR_MODE32_SYSTEM
+#define CPSR_THUMB_ENABLED PSR_THUMB_ENABLED
+#define CPSR_FIQ_DISABLED PSR_FIQ_DISABLED
+#define CPSR_IRQ_DISABLED PSR_IRQ_DISABLED
+#define CPSR_ASYNC_ABORT_DISABLED PSR_ASYNC_ABORT_DISABLED
+#define CPSR_BE_ENABLED PSR_MODE32_BE_ENABLED
+#define CPSR_IT2_MASK PSR_IT2_MASK
+#define CPSR_IT2_SHIFT PSR_IT2_SHIFT
+#define CPSR_GE_MASK PSR_GE_MASK
+#define CPSR_GE_SHIFT PSR_GE_SHIFT
+#define CPSR_JAZZLE_ENABLED PSR_JAZZLE_ENABLED
+#define CPSR_IT1_MASK PSR_IT1_MASK
+#define CPSR_IT1_SHIFT PSR_IT1_SHIFT
+#define CPSR_CUMMULATE_MASK PSR_CUMMULATE_MASK
+#define CPSR_CUMMULATE_SHIFT PSR_CUMMULATE_SHIFT
+#define CPSR_OVERFLOW_MASK PSR_OVERFLOW_MASK
+#define CPSR_OVERFLOW_SHIFT PSR_OVERFLOW_SHIFT
+#define CPSR_CARRY_MASK PSR_CARRY_MASK
+#define CPSR_CARRY_SHIFT PSR_CARRY_SHIFT
+#define CPSR_ZERO_MASK PSR_ZERO_MASK
+#define CPSR_ZERO_SHIFT PSR_ZERO_SHIFT
+#define CPSR_NEGATIVE_MASK PSR_NEGATIVE_MASK
+#define CPSR_NEGATIVE_SHIFT PSR_NEGATIVE_SHIFT
+
+#define CPSR_NZCV_MASK PSR_NZCV_MASK
+#define CPSR_IT_MASK PSR_IT_MASK
+#define CPSR_USERBITS_MASK PSR_USERBITS_MASK
+#define CPSR_PRIVBITS_MASK PSR_PRIVBITS_MASK
+#define CPSR_ALLBITS_MASK PSR_ALLBITS_MASK
+
+/* SCTLR related macros & defines */
+#define SCTLR_TE_MASK 0x40000000
+#define SCTLR_AFE_MASK 0x20000000
+#define SCTLR_TRE_MASK 0x10000000
+#define SCTLR_NFI_MASK 0x08000000
+#define SCTLR_EE_MASK 0x02000000
+#define SCTLR_VE_MASK 0x01000000
+#define SCTLR_U_MASK 0x00400000
+#define SCTLR_FI_MASK 0x00200000
+#define SCTLR_HA_MASK 0x00020000
+#define SCTLR_RR_MASK 0x00004000
+#define SCTLR_V_MASK 0x00002000
+#define SCTLR_I_MASK 0x00001000
+#define SCTLR_Z_MASK 0x00000800
+#define SCTLR_SW_MASK 0x00000400
+#define SCTLR_B_MASK 0x00000080
+#define SCTLR_C_MASK 0x00000004
+#define SCTLR_A_MASK 0x00000002
+#define SCTLR_M_MASK 0x00000001
+
+/* CTR related macros & defines */
+#define CTR_FORMAT_MASK 0xE0000000
+#define CTR_FORMAT_SHIFT 29
+#define CTR_FORMAT_V6 0x0
+#define CTR_FORMAT_V7 0x4
+#define CTR_CWG_MASK 0x0F000000
+#define CTR_CWG_SHIFT 24
+#define CTR_ERG_MASK 0x00F00000
+#define CTR_ERG_SHIFT 20
+#define CTR_DMINLINE_MASK 0x000F0000
+#define CTR_DMINLINE_SHIFT 20
+#define CTR_L1IP_MASK 0x0000C000
+#define CTR_L1IP_SHIFT 14
+#define CTR_IMINLINE_MASK 0x0000000F
+#define CTR_IMINLINE_SHIFT 0
+#define CTR_V6_CTYPE_MASK 0x1E000000
+#define CTR_V6_CTYPE_SHIFT 25
+#define CTR_V6_S_MASK 0x01000000
+#define CTR_V6_S_SHIFT 24
+#define CTR_V6_DSIZE_MASK 0x00FFF000
+#define CTR_V6_DSIZE_SHIFT 12
+#define CTR_V6_ISIZE_MASK 0x00000FFF
+#define CTR_V6_ISIZE_SHIFT 0
+
+/* CLIDR related macros & defines */
+#define CLIDR_LOUU_MASK 0x38000000
+#define CLIDR_LOUU_SHIFT 27
+#define CLIDR_LOC_MASK 0x07000000
+#define CLIDR_LOC_SHIFT 24
+#define CLIDR_LOUIS_MASK 0x00E00000
+#define CLIDR_LOUIS_SHIFT 21
+#define CLIDR_CTYPE7_MASK 0x001C0000
+#define CLIDR_CTYPE7_SHIFT 18
+#define CLIDR_CTYPE6_MASK 0x00038000
+#define CLIDR_CTYPE6_SHIFT 15
+#define CLIDR_CTYPE5_MASK 0x00007000
+#define CLIDR_CTYPE5_SHIFT 12
+#define CLIDR_CTYPE4_MASK 0x00000E00
+#define CLIDR_CTYPE4_SHIFT 9
+#define CLIDR_CTYPE3_MASK 0x000001C0
+#define CLIDR_CTYPE3_SHIFT 6
+#define CLIDR_CTYPE2_MASK 0x00000038
+#define CLIDR_CTYPE2_SHIFT 3
+#define CLIDR_CTYPE1_MASK 0x00000007
+#define CLIDR_CTYPE1_SHIFT 0
+#define CLIDR_CTYPE_NOCACHE 0x0
+#define CLIDR_CTYPE_ICACHE 0x1
+#define CLIDR_CTYPE_DCACHE 0x2
+#define CLIDR_CTYPE_SPLITCACHE 0x3
+#define CLIDR_CTYPE_UNICACHE 0x4
+#define CLIDR_CTYPE_RESERVED1 0x5
+#define CLIDR_CTYPE_RESERVED2 0x6
+#define CLIDR_CTYPE_RESERVED3 0x7
+
+/* CSSELR related macros & defines */
+#define CSSELR_LEVEL_MASK 0x0000000E
+#define CSSELR_LEVEL_SHIFT 1
+#define CSSELR_IND_MASK 0x00000001
+#define CSSELR_IND_SHIFT 0
+
+/* CSSIDR related macros & defines */
+#define CCSIDR_WT_MASK 0x80000000
+#define CCSIDR_WT_SHIFT 31
+#define CCSIDR_WB_MASK 0x40000000
+#define CCSIDR_WB_SHIFT 30
+#define CCSIDR_RA_MASK 0x20000000
+#define CCSIDR_RA_SHIFT 29
+#define CCSIDR_WA_MASK 0x10000000
+#define CCSIDR_WA_SHIFT 28
+#define CCSIDR_NUMSETS_MASK 0x0FFFE000
+#define CCSIDR_NUMSETS_SHIFT 13
+#define CCSIDR_ASSOC_MASK 0x00001FF8
+#define CCSIDR_ASSOC_SHIFT 3
+#define CCSIDR_LINESZ_MASK 0x00000007
+#define CCSIDR_LINESZ_SHIFT 0
+
+/* HCR_EL2 */
+#define HCR_INITVAL 0x000000000
+#define HCR_ID_MASK 0x200000000
+#define HCR_ID_SHIFT 33
+#define HCR_CD_MASK 0x100000000
+#define HCR_CD_SHIFT 32
+#define HCR_RW_MASK 0x080000000
+#define HCR_RW_SHIFT 31
+#define HCR_TRVM_MASK 0x040000000
+#define HCR_TRVM_SHIFT 30
+#define HCR_HCD_MASK 0x020000000
+#define HCR_HCD_SHIFT 29
+#define HCR_TDZ_MASK 0x010000000
+#define HCR_TDZ_SHIFT 28
+#define HCR_TGE_MASK 0x008000000
+#define HCR_TGE_SHIFT 27
+#define HCR_TVM_MASK 0x004000000
+#define HCR_TVM_SHIFT 26
+#define HCR_TTLB_MASK 0x002000000
+#define HCR_TTLB_SHIFT 25
+#define HCR_TPU_MASK 0x001000000
+#define HCR_TPU_SHIFT 24
+#define HCR_TPC_MASK 0x000800000
+#define HCR_TPC_SHIFT 23
+#define HCR_TSW_MASK 0x000400000
+#define HCR_TSW_SHIFT 22
+#define HCR_TACR_MASK 0x000200000
+#define HCR_TACR_SHIFT 21
+#define HCR_TIDCP_MASK 0x000100000
+#define HCR_TIDCP_SHIFT 20
+#define HCR_TSC_MASK 0x000080000
+#define HCR_TSC_SHIFT 19
+#define HCR_TID3_MASK 0x000040000
+#define HCR_TID3_SHIFT 18
+#define HCR_TID2_MASK 0x000020000
+#define HCR_TID2_SHIFT 17
+#define HCR_TID1_MASK 0x000010000
+#define HCR_TID1_SHIFT 16
+#define HCR_TID0_MASK 0x000008000
+#define HCR_TID0_SHIFT 15
+#define HCR_TWE_MASK 0x000004000
+#define HCR_TWE_SHIFT 14
+#define HCR_TWI_MASK 0x000002000
+#define HCR_TWI_SHIFT 13
+#define HCR_DC_MASK 0x000001000
+#define HCR_DC_SHIFT 12
+#define HCR_BSU_MASK 0x000000C00
+#define HCR_BSU_SHIFT 10
+#define HCR_FB_MASK 0x000000200
+#define HCR_FB_SHIFT 9
+#define HCR_VSE_MASK 0x000000100
+#define HCR_VSE_SHIFT 8
+#define HCR_VI_MASK 0x000000080
+#define HCR_VI_SHIFT 7
+#define HCR_VF_MASK 0x000000040
+#define HCR_VF_SHIFT 6
+#define HCR_AMO_MASK 0x000000020
+#define HCR_AMO_SHIFT 5
+#define HCR_IMO_MASK 0x000000010
+#define HCR_IMO_SHIFT 4
+#define HCR_FMO_MASK 0x000000008
+#define HCR_FMO_SHIFT 3
+#define HCR_PTW_MASK 0x000000004
+#define HCR_PTW_SHIFT 2
+#define HCR_SWIO_MASK 0x000000002
+#define HCR_SWIO_SHIFT 1
+#define HCR_VM_MASK 0x000000001
+#define HCR_VM_SHIFT 0
+
+/* CPTR_EL2 */
+#define CPTR_INITVAL 0x00000000LU
+#define CPTR_TCPAC_MASK 0x80000000LU
+#define CPTR_TCPAC_SHIFT 31
+#define CPTR_TTA_MASK 0x00100000LU
+#define CPTR_TTA_SHIFT 20
+#define CPTR_TFP_MASK 0x00000400LU
+#define CPTR_TFP_SHIFT 10
+#define CPTR_RES1_MASK 0x000033FFLU
+
+/* HSTR_EL2 */
+#define HSTR_INITVAL 0x00000000LU
+#define HSTR_TTEE_MASK 0x00010000LU
+#define HSTR_TTEE_SHIFT 16
+#define HSTR_T_MASK 0x0000BFEFLU
+#define HSTR_T_SHIFT 0
+#define HSTR_T15_MASK 0x00008000LU
+#define HSTR_T15_SHIFT 15
+#define HSTR_T13_MASK 0x00002000LU
+#define HSTR_T13_SHIFT 13
+#define HSTR_T12_MASK 0x00001000LU
+#define HSTR_T12_SHIFT 12
+#define HSTR_T11_MASK 0x00000800LU
+#define HSTR_T11_SHIFT 11
+#define HSTR_T10_MASK 0x00000400LU
+#define HSTR_T10_SHIFT 10
+#define HSTR_T9_MASK 0x00000200LU
+#define HSTR_T9_SHIFT 9
+#define HSTR_T8_MASK 0x00000100LU
+#define HSTR_T8_SHIFT 8
+#define HSTR_T7_MASK 0x00000080LU
+#define HSTR_T7_SHIFT 7
+#define HSTR_T6_MASK 0x00000040LU
+#define HSTR_T6_SHIFT 6
+#define HSTR_T5_MASK 0x00000020LU
+#define HSTR_T5_SHIFT 5
+#define HSTR_T3_MASK 0x00000008LU
+#define HSTR_T3_SHIFT 3
+#define HSTR_T2_MASK 0x00000004LU
+#define HSTR_T2_SHIFT 2
+#define HSTR_T1_MASK 0x00000002LU
+#define HSTR_T1_SHIFT 1
+#define HSTR_T0_MASK 0x00000001LU
+#define HSTR_T0_SHIFT 0
+
+/* HPFAR_EL2 */
+#define HPFAR_INITVAL 0x00000000UL
+#define HPFAR_FIPA_MASK 0xFFFFFFFFFFFFFFF0UL
+#define HPFAR_FIPA_SHIFT 4
+#define HPFAR_FIPA_PAGE_MASK 0x00000FFFUL
+#define HPFAR_FIPA_PAGE_SHIFT 12
+
+/* ESR_EL2 */
+#define ESR_INITVAL 0x00000000LU
+#define ESR_EC_MASK 0xFC000000LU
+#define ESR_EC_SHIFT 26
+#define ESR_IL_MASK 0x02000000LU
+#define ESR_IL_SHIFT 25
+#define ESR_ISS_MASK 0x01FFFFFFLU
+#define ESR_ISS_SHIFT 0
+
+/* Exception Class (EC) Values */
+#define EC_UNKNOWN 0x00
+#define EC_TRAP_WFI_WFE 0x01
+#define EC_TRAP_MCR_MRC_CP15_A32 0x03
+#define EC_TRAP_MCRR_MRRC_CP15_A32 0x04
+#define EC_TRAP_MCR_MRC_CP14_A32 0x05
+#define EC_TRAP_LDC_STC_CP14_A32 0x06
+#define EC_SIMD_FPU 0x07
+#define EC_TRAP_MRC_VMRS_CP10_A32 0x08
+#define EC_TRAP_MCRR_MRRC_CP14_A32 0x0C
+#define EC_TRAP_IL 0x0E
+#define EC_TRAP_SVC_A32 0x11
+#define EC_TRAP_HVC_A32 0x12
+#define EC_TRAP_SMC_A32 0x13
+#define EC_TRAP_SVC_A64 0x15
+#define EC_TRAP_HVC_A64 0x16
+#define EC_TRAP_SMC_A64 0x17
+#define EC_TRAP_MSR_MRS_SYSTEM 0x18
+#define EC_TRAP_LWREL_INST_ABORT 0x20
+#define EC_CUREL_INST_ABORT 0x21
+#define EC_PC_UNALIGNED 0x22
+#define EC_TRAP_LWREL_DATA_ABORT 0x24
+#define EC_CUREL_DATA_ABORT 0x25
+#define EC_SP_UNALIGNED 0x26
+#define EC_FPEXC_A32 0x28
+#define EC_FPEXC_A64 0x2C
+#define EC_SERROR 0x2F
+#define EC_DBG_EXC_MASK 0x30
+
+/* Condition Field ISS Encodings */
+#define ISS_CV_MASK 0x01000000
+#define ISS_CV_SHIFT 24
+#define ISS_COND_MASK 0x00F00000
+#define ISS_COND_SHIFT 20
+
+/* MRS/MSR Trap ISS Encodings */
+#define ISS_SYSREG_ENC(op0, op2, op1, crn, crm) (((op0) << 20) | \
+ ((op2) << 17) | ((op1) << 14) | \
+ ((crn) << 10) | ((crm) << 1))
+
+#define ISS_SYSREG_MASK 0xfffffc1e
+#define ISS_RT_MASK 0x000003e0
+#define ISS_RT_SHIFT 5
+#define ISS_DIR_MASK 0x00000001
+#define ISS_SYSREG_READ 0x00000001
+
+#define ISS_CPACR_EL1 ISS_SYSREG_ENC(3,2,0,1,0)
+#define ISS_CNTFRQ_EL0 ISS_SYSREG_ENC(3,0,3,14,0)
+#define ISS_CNTPCT_EL0 ISS_SYSREG_ENC(3,1,3,14,0)
+#define ISS_CNTVCT_EL0 ISS_SYSREG_ENC(3,2,3,14,0)
+#define ISS_CNTKCTL_EL1 ISS_SYSREG_ENC(3,0,0,14,1)
+#define ISS_CNTP_TVAL_EL0 ISS_SYSREG_ENC(3,0,3,14,2)
+#define ISS_CNTP_CTL_EL0 ISS_SYSREG_ENC(3,1,3,14,2)
+#define ISS_CNTP_CVAL_EL0 ISS_SYSREG_ENC(3,2,3,14,2)
+#define ISS_CNTV_TVAL_EL0 ISS_SYSREG_ENC(3,0,3,14,3)
+#define ISS_CNTV_CTL_EL0 ISS_SYSREG_ENC(3,1,3,14,3)
+#define ISS_CNTV_CVAL_EL0 ISS_SYSREG_ENC(3,2,3,14,3)
+#define ISS_ACTLR_EL1 ISS_SYSREG_ENC(3,1,0,1,0)
+#define ISS_ACTLR_EL2 ISS_SYSREG_ENC(3,1,0,1,4)
+#define ISS_ACTLR_EL3 ISS_SYSREG_ENC(3,1,0,1,6)
+
+/* WFI/WFE ISS Encodings */
+#define ISS_WFI_WFE_TRAPPED_MASK 0x00000001
+#define ISS_WFI_WFE_TRAPPED_SHIFT 0
+
+/* MCR/MRC ISS Encodings */
+#define ISS_MCR_MRC_OPC2_MASK 0x000E0000
+#define ISS_MCR_MRC_OPC2_SHIFT 17
+#define ISS_MCR_MRC_OPC1_MASK 0x0001C000
+#define ISS_MCR_MRC_OPC1_SHIFT 14
+#define ISS_MCR_MRC_CRN_MASK 0x00003C00
+#define ISS_MCR_MRC_CRN_SHIFT 10
+#define ISS_MCR_MRC_RT_MASK 0x000001E0
+#define ISS_MCR_MRC_RT_SHIFT 5
+#define ISS_MCR_MRC_CRM_MASK 0x0000001E
+#define ISS_MCR_MRC_CRM_SHIFT 1
+#define ISS_MCR_MRC_DIR_MASK 0x00000001
+#define ISS_MCR_MRC_DIR_SHIFT 0
+
+/* Instruction/Data Abort ISS Encodings */
+#define ISS_ABORT_ISV_MASK 0x01000000
+#define ISS_ABORT_ISV_SHIFT 24
+#define ISS_ABORT_SAS_MASK 0x00C00000
+#define ISS_ABORT_SAS_SHIFT 22
+#define ISS_ABORT_SSE_MASK 0x00200000
+#define ISS_ABORT_SSE_SHIFT 21
+#define ISS_ABORT_SRT_MASK 0x001F0000
+#define ISS_ABORT_SRT_SHIFT 16
+#define ISS_ABORT_SF_MASK 0x00008000
+#define ISS_ABORT_SF_SHIFT 15
+#define ISS_ABORT_AR_MASK 0x00004000
+#define ISS_ABORT_AR_SHIFT 14
+#define ISS_ABORT_EA_MASK 0x00000200
+#define ISS_ABORT_EA_SHIFT 9
+#define ISS_ABORT_CM_MASK 0x00000100
+#define ISS_ABORT_CM_SHIFT 8
+#define ISS_ABORT_S1PTW_MASK 0x00000080
+#define ISS_ABORT_S1PTW_SHIFT 7
+#define ISS_ABORT_WNR_MASK 0x00000040
+#define ISS_ABORT_WNR_SHIFT 6
+#define ISS_ABORT_FSC_MASK 0x0000003F
+#define ISS_ABORT_FSC_SHIFT 0
+
+/* Fault Status (IFSC/DFSC) Encodings */
+#define FSC_TRANS_FAULT_LEVEL0 0x04
+#define FSC_TRANS_FAULT_LEVEL1 0x05
+#define FSC_TRANS_FAULT_LEVEL2 0x06
+#define FSC_TRANS_FAULT_LEVEL3 0x07
+#define FSC_ACCESS_FAULT_LEVEL0 0x08
+#define FSC_ACCESS_FAULT_LEVEL1 0x09
+#define FSC_ACCESS_FAULT_LEVEL2 0x0A
+#define FSC_ACCESS_FAULT_LEVEL3 0x0B
+#define FSC_PERM_FAULT_LEVEL0 0x0C
+#define FSC_PERM_FAULT_LEVEL1 0x0D
+#define FSC_PERM_FAULT_LEVEL2 0x0E
+#define FSC_PERM_FAULT_LEVEL3 0x0F
+#define FSC_SYNC_EXTERNAL_ABORT 0x10
+#define FSC_ASYNC_EXTERNAL_ABORT 0x11
+#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL0 0x14
+#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL1 0x15
+#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL2 0x16
+#define FSC_SYNC_TWALK_EXTERNAL_ABORT_LEVEL3 0x17
+#define FSC_SYNC_PARITY_ERROR 0x18
+#define FSC_ASYNC_PARITY_ERROR 0x19
+#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL0 0x1C
+#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL1 0x1D
+#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL2 0x1E
+#define FSC_SYNC_TWALK_PARITY_ERROR_LEVEL3 0x1F
+#define FSC_ALIGN_FAULT 0x21
+#define FSC_DEBUG_EVENT 0x22
+#define FSC_TLB_CONFLICT_ABORT 0x30
+#define FSC_DOMAIN_FAULT_LEVEL0 0x3C
+#define FSC_DOMAIN_FAULT_LEVEL1 0x3D
+#define FSC_DOMAIN_FAULT_LEVEL2 0x3E
+#define FSC_DOMAIN_FAULT_LEVEL3 0x3F
+
+/* HTTBR */
+#define HTTBR_INITVAL 0x0000000000000000ULL
+#define HTTBR_BADDR_MASK 0x000000FFFFFFF000ULL
+#define HTTBR_BADDR_SHIFT 12
+
+/* TCR_EL2 */
+#define TCR_INITVAL 0x80800000
+#define TCR_TBI_MASK 0x00100000
+#define TCR_TBI_SHIFT 20
+#define TCR_PS_MASK 0x00070000
+#define TCR_PS_SHIFT 16
+#define TCR_TG0_MASK 0x00004000
+#define TCR_TG0_SHIFT 14
+#define TCR_SH0_MASK 0x00003000
+#define TCR_SH0_SHIFT 12
+#define TCR_ORGN0_MASK 0x00000C00
+#define TCR_ORGN0_SHIFT 10
+#define TCR_IRGN0_MASK 0x00000300
+#define TCR_IRGN0_SHIFT 8
+#define TCR_T0SZ_MASK 0x0000003f
+#define TCR_T0SZ_SHIFT 0
+
+/* VTTBR */
+#define VTTBR_INITVAL 0x0000000000000000ULL
+#define VTTBR_VMID_MASK 0x00FF000000000000ULL
+#define VTTBR_VMID_SHIFT 48
+#define VTTBR_BADDR_MASK 0x000000FFFFFFF000ULL
+#define VTTBR_BADDR_SHIFT 12
+
+/* VTCR_EL2 */
+#define VTCR_INITVAL 0x80000000
+#define VTCR_PS_MASK 0x00070000
+#define VTCR_PS_SHIFT 16
+#define VTCR_TG0_MASK 0x00004000
+#define VTCR_TG0_SHIFT 14
+#define VTCR_SH0_MASK 0x00003000
+#define VTCR_SH0_SHIFT 12
+#define VTCR_ORGN0_MASK 0x00000C00
+#define VTCR_ORGN0_SHIFT 10
+#define VTCR_IRGN0_MASK 0x00000300
+#define VTCR_IRGN0_SHIFT 8
+#define VTCR_SL0_MASK 0x000000C0
+#define VTCR_SL0_SHIFT 6
+#define VTCR_T0SZ_MASK 0x0000003f
+#define VTCR_T0SZ_SHIFT 0
+
+/* MAIR_EL2 encodings */
+#define AINDEX_SO 0
+#define AINDEX_NORMAL_WT 1
+#define AINDEX_NORMAL_WB 2
+#define AINDEX_NORMAL_UC 3
+#define MAIR_INITVAL 0x0000000044FFBB00
+
+/* VPIDR */
+#define VPIDR_INITVAL 0x00000000
+
+/* VMPIDR */
+#define VMPIDR_INITVAL 0x00000000
+
+/* DBGVIDSR */
+#define DBGVIDSR_INITVAL 0x00000000
+#define DBGVIDSR_NS_MASK 0x80000000
+#define DBGVIDSR_NS_SHIFT 31
+#define DBGVIDSR_H_MASK 0x40000000
+#define DBGVIDSR_H_SHIFT 30
+#define DBGVIDSR_VMID_MASK 0x000000FF
+#define DBGVIDSR_VMID_SHIFT 0
+
+/* SCTLR_ELx */
+#define SCTLR_INITVAL 0x30C50878
+#define SCTLR_TE_MASK 0x40000000
+#define SCTLR_TE_SHIFT 30
+#define SCTLR_EE_MASK 0x02000000
+#define SCTLR_EE_SHIFT 25
+#define SCTLR_FI_MASK 0x00200000
+#define SCTLR_FI_SHIFT 21
+#define SCTLR_WXN_MASK 0x00080000
+#define SCTLR_WXN_SHIFT 19
+#define SCTLR_I_MASK 0x00001000
+#define SCTLR_I_SHIFT 12
+#define SCTLR_SA0_MASK 0x00000010
+#define SCTLR_SA0_SHIFT 4
+#define SCTLR_SA_MASK 0x00000008
+#define SCTLR_SA_SHIFT 3
+#define SCTLR_C_MASK 0x00000004
+#define SCTLR_C_SHIFT 2
+#define SCTLR_A_MASK 0x00000002
+#define SCTLR_A_SHIFT 1
+#define SCTLR_M_MASK 0x00000001
+#define SCTLR_M_SHIFT 0
+
+/* DBGBXVR */
+#define DBGBXVR_INITVAL 0x00000000
+#define DBGBXVR_VMID_MASK 0x000000FF
+#define DBGBXVR_VMID_SHIFT 0
+
+/* PAR_EL1 common fields */
+#define PAR_PA_MASK 0x0000FFFFFFFFF000ULL
+#define PAR_PA_SHIFT 12
+#define PAR_F_MASK 0x0000000000000001ULL
+#define PAR_F_SHIFT 0
+
+/* PAR_EL1 @ fault */
+#define PAR_STAGE_MASK 0x0000000000000200ULL
+#define PAR_STAGE_SHIFT 9
+#define PAR_STAGE1 0
+#define PAR_STAGE2 1
+#define PAR_PTW_MASK 0x0000000000000100ULL
+#define PAR_PTW_SHIFT 8
+#define PAR_FS_MASK 0x000000000000007EULL
+#define PAR_FS_SHIFT 1
+#define PAR_F_FAULT 0x0000000000000001ULL
+
+/* PAR_EL1 @ address-translation */
+#define PAR_MAIR_MASK 0xFF00000000000000ULL
+#define PAR_MAIR_SHIFT 56
+#define PAR64_NS_MASK 0x0000000000000200ULL
+#define PAR64_NS_SHIFT 9
+#define PAR64_SH_MASK 0x0000000000000180ULL
+#define PAR64_SH_SHIFT 7
+
+/* ID_PFR0_EL1 */
+#define ID_PFR0_THUMBEE_MASK 0x0000f000
+#define ID_PFR0_THUMBEE_SHIFT 12
+#define ID_PFR0_JAZELLE_MASK 0x00000f00
+#define ID_PFR0_JAZELLE_SHIFT 8
+#define ID_PFR0_THUMB2 0x00000030
+#define ID_PFR0_THUMB_MASK 0x000000f0
+#define ID_PFR0_THUMB_SHIFT 4
+#define ID_PFR0_ARM_MASK 0x0000000f
+#define ID_PFR0_ARM_SHIFT 0
+
+/* ID_PFR1_EL1 */
+#define ID_PFR1_GENTIMER_MASK 0x000f0000
+#define ID_PFR1_GENTIMER_SHIFT 16
+#define ID_PFR1_VIRTEXT_MASK 0x0000f000
+#define ID_PFR1_VIRTEXT_SHIFT 12
+#define ID_PFR1_2STACK_MASK 0x00000f00
+#define ID_PFR1_2STACK_SHIFT 8
+#define ID_PFR1_SECURE_MASK 0x000000f0
+#define ID_PFR1_SECURE_SHIFT 4
+#define ID_PFR1_PROGMODEL_MASK 0x0000000f
+#define ID_PFR1_PROGMODEL_SHIFT 0
+
+/* ID_AA64PFR0_EL1 */
+#define ID_AA64PFR0_ASIMD_MASK 0x00020000
+#define ID_AA64PFR0_ASIMD_SHIFT 17
+#define ID_AA64PFR0_FPU_MASK 0x00010000
+#define ID_AA64PFR0_FPU_SHIFT 16
+#define ID_AA64PFR0_EL3_A32 0x00002000
+#define ID_AA64PFR0_EL3_MASK 0x0000f000
+#define ID_AA64PFR0_EL3_SHIFT 12
+#define ID_AA64PFR0_EL2_A32 0x00000200
+#define ID_AA64PFR0_EL2_MASK 0x00000f00
+#define ID_AA64PFR0_EL2_SHIFT 8
+#define ID_AA64PFR0_EL1_A32 0x00000020
+#define ID_AA64PFR0_EL1_MASK 0x000000f0
+#define ID_AA64PFR0_EL1_SHIFT 4
+#define ID_AA64PFR0_EL0_A32 0x00000002
+#define ID_AA64PFR0_EL0_MASK 0x0000000f
+#define ID_AA64PFR0_EL0_SHIFT 0
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/cpu_generic_timer.h b/arch/arm/cpu/arm64/include/cpu_generic_timer.h
new file mode 100644
index 0000000..a72a0ec
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_generic_timer.h
@@ -0,0 +1,159 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_generic_timer.c
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief CPU specific functions for ARM architecture generic timers
+ */
+
+#ifndef __CPU_GENERIC_TIMER_H__
+#define __CPU_GENERIC_TIMER_H__
+
+#include <vmm_types.h>
+
+#define generic_timer_pcounter_read() mrs(cntpct_el0)
+#define generic_timer_vcounter_read() mrs(cntvct_el0)
+
+/* cntfrq_el0 is writeable by highest implemented EL.
+ * We are running at EL2 and if EL3 is not implemented,
+ * hypervisor can write to cntfrq_el0 */
+#define generic_timer_freq_writeable() (!cpu_supports_el3())
+
+static inline void generic_timer_reg_write(int reg, u32 val)
+{
+ switch (reg) {
+ case GENERIC_TIMER_REG_FREQ:
+ msr(cntfrq_el0, val);
+ break;
+ case GENERIC_TIMER_REG_HCTL:
+ msr(cnthctl_el2, val);
+ break;
+ case GENERIC_TIMER_REG_KCTL:
+ msr(cntkctl_el1, val);
+ break;
+ case GENERIC_TIMER_REG_HYP_CTRL:
+ msr(cnthp_ctl_el2, val);
+ break;
+ case GENERIC_TIMER_REG_HYP_TVAL:
+ msr(cnthp_tval_el2, val);
+ break;
+ case GENERIC_TIMER_REG_PHYS_CTRL:
+ msr(cntp_ctl_el0, val);
+ break;
+ case GENERIC_TIMER_REG_PHYS_TVAL:
+ msr(cntp_tval_el0, val);
+ break;
+ case GENERIC_TIMER_REG_VIRT_CTRL:
+ msr(cntv_ctl_el0, val);
+ break;
+ case GENERIC_TIMER_REG_VIRT_TVAL:
+ msr(cntv_tval_el0, val);
+ break;
+ default:
+ vmm_panic("Trying to write invalid generic-timer register\n");
+ }
+
+ isb();
+}
+
+static inline u32 generic_timer_reg_read(int reg)
+{
+ u32 val;
+
+ switch (reg) {
+ case GENERIC_TIMER_REG_FREQ:
+ val = mrs(cntfrq_el0);
+ break;
+ case GENERIC_TIMER_REG_HCTL:
+ val = mrs(cnthctl_el2);
+ break;
+ case GENERIC_TIMER_REG_KCTL:
+ val = mrs(cntkctl_el1);
+ break;
+ case GENERIC_TIMER_REG_HYP_CTRL:
+ val = mrs(cnthp_ctl_el2);
+ break;
+ case GENERIC_TIMER_REG_HYP_TVAL:
+ val = mrs(cnthp_tval_el2);
+ break;
+ case GENERIC_TIMER_REG_PHYS_CTRL:
+ val = mrs(cntp_ctl_el0);
+ break;
+ case GENERIC_TIMER_REG_PHYS_TVAL:
+ val = mrs(cntp_tval_el0);
+ break;
+ case GENERIC_TIMER_REG_VIRT_CTRL:
+ val = mrs(cntv_ctl_el0);
+ break;
+ case GENERIC_TIMER_REG_VIRT_TVAL:
+ val = mrs(cntv_tval_el0);
+ break;
+ default:
+ vmm_panic("Trying to read invalid generic-timer register\n");
+ }
+
+ return val;
+}
+
+static inline void generic_timer_reg_write64(int reg, u64 val)
+{
+ switch (reg) {
+ case GENERIC_TIMER_REG_HYP_CVAL:
+ msr(cnthp_cval_el2, val);
+ break;
+ case GENERIC_TIMER_REG_PHYS_CVAL:
+ msr(cntp_cval_el0, val);
+ break;
+ case GENERIC_TIMER_REG_VIRT_CVAL:
+ msr(cntv_cval_el0, val);
+ break;
+ case GENERIC_TIMER_REG_VIRT_OFF:
+ msr(cntvoff_el2, val);
+ break;
+ default:
+ vmm_panic("Trying to write invalid generic-timer register\n");
+ }
+
+ isb();
+}
+
+static inline u64 generic_timer_reg_read64(int reg)
+{
+ u64 val;
+
+ switch (reg) {
+ case GENERIC_TIMER_REG_HYP_CVAL:
+ val = mrs(cnthp_cval_el2);
+ break;
+ case GENERIC_TIMER_REG_PHYS_CVAL:
+ val = mrs(cntp_cval_el0);
+ break;
+ case GENERIC_TIMER_REG_VIRT_CVAL:
+ val = mrs(cntv_cval_el0);
+ break;
+ case GENERIC_TIMER_REG_VIRT_OFF:
+ val = mrs(cntvoff_el2);
+ break;
+ default:
+ vmm_panic("Trying to read invalid generic-timer register\n");
+ }
+
+ return val;
+}
+
+#endif /* __CPU_GENERIC_TIMER_H__ */
diff --git a/arch/arm/cpu/arm64/include/cpu_inline_asm.h b/arch/arm/cpu/arm64/include/cpu_inline_asm.h
new file mode 100644
index 0000000..8d1b472
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_inline_asm.h
@@ -0,0 +1,243 @@
+/**
+ * Copyright (c) 2012 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_inline_asm.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Frequently required inline assembly macros
+ */
+#ifndef __CPU_INLINE_ASM_H__
+#define __CPU_INLINE_ASM_H__
+
+#include <vmm_types.h>
+
+#define rev16(val) ({ u16 rval; asm volatile(\
+ " rev16 %0, %1\n\t" : "=r" (rval) : \
+ "r" (val) : "memory", "cc"); rval;})
+
+#define rev32(val) ({ u32 rval; asm volatile(\
+ " rev32 %0, %1\n\t" : "=r" (rval) : \
+ "r" (val) : "memory", "cc"); rval;})
+
+#define rev64(val) ({ u32 d1, d2; \
+ d1 = (u32)((u64)val >> 32); d2 = (u32)val; \
+ d1 = rev32(d1); d2 = rev32(d2); \
+ (((u64)d2 << 32) | ((u64)d1));})
+
+#define ldxr(addr, data) asm volatile("ldxr %0, [%1]\n\t" \
+ : "=r"(data) : "r"(addr))
+
+#define stxr(addr, data, res) asm volatile("stxr %0, %1, [%2]\n\t" \
+ : "=r"(res) : "r"(data), "r"(addr))
+
+#define clrex() asm volatile("clrex\n\t")
+
+#define mrs(spr) ({ u64 rval; asm volatile(\
+ "mrs %0," #spr :"=r"(rval)); rval; })
+
+#define msr(spr, val) asm volatile("msr " #spr ", %0" ::"r"(val))
+
+#define msr_sync(spr, val) asm volatile("msr " #spr ", %0\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" ::"r"(val))
+
+/* TLB maintainence */
+
+#define inv_tlb_hyp_all() asm volatile("tlbi alle2is\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::: "memory", "cc")
+
+#define inv_tlb_guest_allis() asm volatile("tlbi alle1is\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::: "memory", "cc")
+
+#define inv_tlb_guest_cur() asm volatile("tlbi vmalls12e1is\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::: "memory", "cc")
+
+#define inv_tlb_hyp_vais(va) asm volatile("tlbi vae2is, %0\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::"r"((va)>>12): "memory", "cc")
+
+#define inv_tlb_guest_ipa(va) asm volatile("tlbi ipas2e1is, %0\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::"r"((va)>>12): "memory", "cc")
+
+#define inv_tlb_guest_va(va) asm volatile("tlbi vaae1is, %0\n\t" \
+ "dsb sy\n\t" \
+ "isb\n\t" \
+ ::"r"((va)>>12): "memory", "cc")
+
+/* VA to PA Address Translation */
+
+#define VA2PA_STAGE1 "s1"
+#define VA2PA_STAGE12 "s12"
+#define VA2PA_EL0 "e0"
+#define VA2PA_EL1 "e1"
+#define VA2PA_EL2 "e2"
+#define VA2PA_EL3 "e3"
+#define VA2PA_RD "r"
+#define VA2PA_WR "w"
+#define va2pa_at(stage, el, rw, va) asm volatile( \
+ "at " stage el rw ", %0" \
+ : : "r"(va) : "memory", "cc");
+
+
+/* Features */
+#define cpu_supports_thumbee() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_PFR0_THUMBEE_MASK); \
+ })
+
+#define cpu_supports_thumb() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_PFR0_THUMBEE_MASK); \
+ })
+
+#define cpu_supports_thumb2() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_PFR0_THUMB_MASK) == ID_PFR0_THUMB2_MASK); \
+ })
+
+#define cpu_supports_jazelle() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_PFR0_JAZELLE_MASK); \
+ })
+
+#define cpu_supports_arm() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_PFR0_ARM_MASK); \
+ })
+
+#define cpu_supports_asimd() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_ASIMD_MASK) == 0); \
+ })
+
+#define cpu_supports_fpu() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_FPU_MASK) == 0); \
+ })
+
+#define cpu_supports_el0_a32() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_EL0_MASK) == ID_AA64PFR0_EL0_A32); \
+ })
+
+#define cpu_supports_el1_a32() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_EL1_MASK) == ID_AA64PFR0_EL1_A32); \
+ })
+
+#define cpu_supports_el2_a32() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_EL2_MASK) == ID_AA64PFR0_EL2_A32); \
+ })
+
+#define cpu_supports_el3_a32() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ ((pfr0 & ID_AA64PFR0_EL3_MASK) == ID_AA64PFR0_EL3_A32); \
+ })
+
+#define cpu_supports_el0() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_AA64PFR0_EL0_MASK); \
+ })
+
+#define cpu_supports_el1() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_AA64PFR0_EL1_MASK); \
+ })
+
+#define cpu_supports_el2() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_AA64PFR0_EL2_MASK); \
+ })
+
+#define cpu_supports_el3() ({ u64 pfr0; \
+ asm volatile("mrs %0, id_aa64pfr0_el1" \
+ : "=r"(pfr0)); \
+ (pfr0 & ID_AA64PFR0_EL3_MASK); \
+ })
+
+#define vfp_simd_save_regs(addr) { \
+ asm volatile("stnp Q0, Q1, [%0, #0x00]\n\t" \
+ "stnp Q2, Q3, [%0, #0x20]\n\t" \
+ "stnp Q4, Q5, [%0, #0x40]\n\t" \
+ "stnp Q6, Q7, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x000)); \
+ asm volatile("stnp Q8, Q9, [%0, #0x00]\n\t" \
+ "stnp Q10, Q11, [%0, #0x20]\n\t" \
+ "stnp Q12, Q13, [%0, #0x40]\n\t" \
+ "stnp Q14, Q15, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x080)); \
+ asm volatile("stnp Q16, Q17, [%0, #0x00]\n\t" \
+ "stnp Q18, Q19, [%0, #0x20]\n\t" \
+ "stnp Q20, Q21, [%0, #0x40]\n\t" \
+ "stnp Q22, Q23, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x100)); \
+ asm volatile("stnp Q24, Q25, [%0, #0x00]\n\t" \
+ "stnp Q26, Q27, [%0, #0x20]\n\t" \
+ "stnp Q28, Q29, [%0, #0x40]\n\t" \
+ "stnp Q30, Q31, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x180)); \
+ }
+
+
+#define vfp_simd_restore_regs(addr) { \
+ asm volatile("ldnp Q0, Q1, [%0, #0x00]\n\t" \
+ "ldnp Q2, Q3, [%0, #0x20]\n\t" \
+ "ldnp Q4, Q5, [%0, #0x40]\n\t" \
+ "ldnp Q6, Q7, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x000)); \
+ asm volatile("ldnp Q8, Q9, [%0, #0x00]\n\t" \
+ "ldnp Q10, Q11, [%0, #0x20]\n\t" \
+ "ldnp Q12, Q13, [%0, #0x40]\n\t" \
+ "ldnp Q14, Q15, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x080)); \
+ asm volatile("ldnp Q16, Q17, [%0, #0x00]\n\t" \
+ "ldnp Q18, Q19, [%0, #0x20]\n\t" \
+ "ldnp Q20, Q21, [%0, #0x40]\n\t" \
+ "ldnp Q22, Q23, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x100)); \
+ asm volatile("ldnp Q24, Q25, [%0, #0x00]\n\t" \
+ "ldnp Q26, Q27, [%0, #0x20]\n\t" \
+ "ldnp Q28, Q29, [%0, #0x40]\n\t" \
+ "ldnp Q30, Q31, [%0, #0x60]\n\t" \
+ :: "r"((char *)(addr) + 0x180)); \
+ }
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/cpu_mmu_lpae.h b/arch/arm/cpu/arm64/include/cpu_mmu_lpae.h
new file mode 100644
index 0000000..d75bd42
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_mmu_lpae.h
@@ -0,0 +1,55 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_mmu_lpae.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief MMU interface of LPAE enabled ARM processor
+ */
+#ifndef _CPU_MMU_LPAE_H__
+#define _CPU_MMU_LPAE_H__
+
+#include <cpu_cache.h>
+#include <cpu_inline_asm.h>
+#include <arch_barrier.h>
+
+#define TTBL_FIRST_LEVEL 1
+#define TTBL_LAST_LEVEL 3
+
+#define cpu_invalid_all_guest_tlbs() inv_tlb_guest_allis()
+#define cpu_invalid_va_hypervisor_tlb(va) inv_tlb_hyp_vais((va))
+#define cpu_invalid_all_tlbs() inv_tlb_hyp_all()
+
+#define cpu_stage2_ttbl_pa() \
+ (mrs(vttbr_el2) & VTTBR_BADDR_MASK)
+#define cpu_stage2_vmid() \
+ ((mrs(vttbr_el2) & VTTBR_VMID_MASK) >> VTTBR_VMID_SHIFT)
+#define cpu_stage2_update(ttbl_pa, vmid) \
+ do { \
+ u64 vttbr = 0x0; \
+ vttbr |= ((u64)(vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK; \
+ vttbr |= (ttbl_pa) & VTTBR_BADDR_MASK; \
+ msr(vttbr_el2, vttbr); \
+ } while(0);
+
+static inline void cpu_mmu_sync_tte(u64 *tte)
+{
+ isb();
+ dsb();
+}
+
+#endif /* _CPU_MMU_LPAE_H */
diff --git a/arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h b/arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h
new file mode 100644
index 0000000..9094765
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_vcpu_coproc.h
@@ -0,0 +1,90 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_coproc.h
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief header file for coprocessor access
+ */
+#ifndef _CPU_VCPU_COPROC_H__
+#define _CPU_VCPU_COPROC_H__
+
+#include <vmm_types.h>
+#include <vmm_manager.h>
+
+typedef bool (*cpu_coproc_ldcstc_accept)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 D, u32 CRd,
+ u32 uopt, u32 imm8);
+
+typedef bool (*cpu_coproc_ldcstc_done)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8);
+
+typedef u32 (*cpu_coproc_ldcstc_read)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8);
+
+typedef void (*cpu_coproc_ldcstc_write)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 index, u32 D, u32 CRd,
+ u32 uopt, u32 imm8, u32 data);
+
+typedef bool (*cpu_coproc_read2)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 CRm,
+ u32 *data, u32 *data2);
+
+typedef bool (*cpu_coproc_write2)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 CRm,
+ u32 data, u32 data2);
+
+typedef bool (*cpu_coproc_data_process)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2,
+ u32 CRd, u32 CRn, u32 CRm);
+
+typedef bool (*cpu_coproc_read)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u32 *data);
+
+typedef bool (*cpu_coproc_write)(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u32 data);
+
+struct cpu_vcpu_coproc {
+ u32 cpnum;
+ cpu_coproc_ldcstc_accept ldcstc_accept;
+ cpu_coproc_ldcstc_done ldcstc_done;
+ cpu_coproc_ldcstc_read ldcstc_read;
+ cpu_coproc_ldcstc_write ldcstc_write;
+ cpu_coproc_read2 read2;
+ cpu_coproc_write2 write2;
+ cpu_coproc_data_process data_process;
+ cpu_coproc_read read;
+ cpu_coproc_write write;
+};
+
+/** Retrive a coprocessor with given number */
+struct cpu_vcpu_coproc *cpu_vcpu_coproc_get(u32 cpnum);
+
+#endif /* _CPU_VCPU_COPROC_H */
diff --git a/arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h b/arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h
new file mode 100644
index 0000000..11d1256
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_vcpu_emulate.h
@@ -0,0 +1,96 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_emulate.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Inferace for hardware assisted instruction emulation
+ */
+#ifndef _CPU_VCPU_EMULATE_H__
+#define _CPU_VCPU_EMULATE_H__
+
+#include <vmm_types.h>
+#include <vmm_manager.h>
+
+/** Emulate WFI/WFE instruction */
+int cpu_vcpu_emulate_wfi_wfe(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MCR/MRC CP15 instruction */
+int cpu_vcpu_emulate_mcr_mrc_cp15(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MCRR/MRRC CP15 instruction */
+int cpu_vcpu_emulate_mcrr_mrrc_cp15(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MCR/MRC CP14 instruction */
+int cpu_vcpu_emulate_mcr_mrc_cp14(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate LDC/STC CP14 instruction */
+int cpu_vcpu_emulate_ldc_stc_cp14(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate Advanced SIMD or FPU register access */
+int cpu_vcpu_emulate_simd_fp_regs(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MRC (or VMRS) to CP10 instruction */
+int cpu_vcpu_emulate_vmrs(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MCRR/MRRC to CP14 instruction */
+int cpu_vcpu_emulate_mcrr_mrrc_cp14(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate HVC instruction (or Handle Hypercall) for A32 guest */
+int cpu_vcpu_emulate_hvc32(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate HVC instruction (or Handle Hypercall) for A64 guest */
+int cpu_vcpu_emulate_hvc64(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate MRS/MSR/System Regs access */
+int cpu_vcpu_emulate_msr_mrs_system(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss);
+
+/** Emulate Load instruction */
+int cpu_vcpu_emulate_load(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss,
+ physical_addr_t ipa);
+
+/** Emulate Store instruction */
+int cpu_vcpu_emulate_store(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss,
+ physical_addr_t ipa);
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/cpu_vcpu_helper.h b/arch/arm/cpu/arm64/include/cpu_vcpu_helper.h
new file mode 100644
index 0000000..19be3d3
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_vcpu_helper.h
@@ -0,0 +1,59 @@
+/**
+ * Copyright (c) 2012 Anup Patel.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_helper.h
+ * @author Anup Patel (an...@brainfault.org)
+ * @brief header of VCPU helper functions
+ */
+#ifndef _CPU_VCPU_HELPER_H__
+#define _CPU_VCPU_HELPER_H__
+
+#include <vmm_types.h>
+#include <vmm_manager.h>
+
+/* Function to halt VCPU */
+void cpu_vcpu_halt(struct vmm_vcpu *vcpu, arch_regs_t *regs);
+
+/* Function to read a VCPU register of current mode */
+u64 cpu_vcpu_reg_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 reg_num);
+
+/* Function to write a VCPU register of current mode */
+void cpu_vcpu_reg_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ u32 reg_num,
+ u64 reg_val);
+
+/* Function to inject undef exception to a VCPU */
+int cpu_vcpu_inject_undef(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs);
+
+/* Function to inject prefetch abort exception to a VCPU */
+int cpu_vcpu_inject_pabt(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs);
+
+/* Function to inject data abort exception to a VCPU */
+int cpu_vcpu_inject_dabt(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr);
+
+/* Function to dump user registers */
+void cpu_vcpu_dump_user_reg(arch_regs_t *regs);
+
+#endif
diff --git a/arch/arm/cpu/arm64/include/cpu_vcpu_mem.h b/arch/arm/cpu/arm64/include/cpu_vcpu_mem.h
new file mode 100644
index 0000000..5cb132f
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_vcpu_mem.h
@@ -0,0 +1,57 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_mem.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Header File for VCPU memory read/write emulation
+ */
+#ifndef _CPU_VCPU_MEM_H__
+#define _CPU_VCPU_MEM_H__
+
+#include <vmm_types.h>
+#include <vmm_manager.h>
+
+/** Read from memory for VCPU */
+int cpu_vcpu_mem_read(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *dst, u32 dst_len,
+ bool force_unpriv);
+
+/** Write to memory for VCPU */
+int cpu_vcpu_mem_write(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *src, u32 src_len,
+ bool force_unpriv);
+
+/** Read-Exclusive from memory for VCPU */
+int cpu_vcpu_mem_readex(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *dst, u32 dst_len,
+ bool force_unpriv);
+
+/** Write-Exclusive to memory for VCPU */
+int cpu_vcpu_mem_writeex(struct vmm_vcpu *vcpu,
+ arch_regs_t *regs,
+ virtual_addr_t addr,
+ void *src, u32 src_len,
+ bool force_unpriv);
+
+#endif /* _CPU_VCPU_MEM_H */
diff --git a/arch/arm/cpu/arm64/include/cpu_vcpu_spr.h b/arch/arm/cpu/arm64/include/cpu_vcpu_spr.h
new file mode 100644
index 0000000..eeb4e9b
--- /dev/null
+++ b/arch/arm/cpu/arm64/include/cpu_vcpu_spr.h
@@ -0,0 +1,69 @@
+/**
+ * Copyright (c) 2012 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file cpu_vcpu_cp15.h
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief Header File for VCPU cp15 emulation
+ */
+#ifndef _CPU_VCPU_CP15_H__
+#define _CPU_VCPU_CP15_H__
+
+#include <vmm_types.h>
+#include <vmm_manager.h>
+
+/** Handle stage2 instruction abort */
+int cpu_vcpu_inst_abort(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss,
+ physical_addr_t fipa);
+
+/** Handle stage2 data abort */
+int cpu_vcpu_data_abort(struct vmm_vcpu * vcpu,
+ arch_regs_t * regs,
+ u32 il, u32 iss,
+ physical_addr_t fipa);
+
+/** Read one SPR */
+bool cpu_vcpu_spr_read(struct vmm_vcpu * vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 *data);
+
+/** Write one SPR */
+bool cpu_vcpu_spr_write(struct vmm_vcpu * vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 data);
+
+bool cpu_vcpu_cp15_read(struct vmm_vcpu * vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 *data);
+
+bool cpu_vcpu_cp15_write(struct vmm_vcpu * vcpu,
+ arch_regs_t *regs,
+ u32 opc1, u32 opc2, u32 CRn, u32 CRm,
+ u64 data);
+
+/** Initialize SPR subsystem for a VCPU */
+int cpu_vcpu_spr_init(struct vmm_vcpu * vcpu, u32 cpuid);
+
+/** DeInitialize SPR subsystem for a VCPU */
+int cpu_vcpu_spr_deinit(struct vmm_vcpu * vcpu);
+
+#endif /* _CPU_VCPU_CP15_H */
diff --git a/arch/arm/cpu/arm64/linker.ld b/arch/arm/cpu/arm64/linker.ld
new file mode 100755
index 0000000..3673602
--- /dev/null
+++ b/arch/arm/cpu/arm64/linker.ld
@@ -0,0 +1,119 @@
+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * @file linker.ld
+ * @author Sukanto Ghosh (sukant...@gmail.com)
+ * @brief CPU specific linker script
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH("aarch64")
+ENTRY(_start)
+
+SECTIONS
+{
+ . = TEXT_START;
+
+ . = ALIGN(0x1000); /* Need this to create proper sections */
+
+ PROVIDE(_code_start = .);
+
+ .text :
+ {
+ PROVIDE(_text_start = .);
+ *(.entry)
+ *(.text)
+ . = ALIGN(8);
+ PROVIDE(_text_end = .);
+ }
+
+ .data :
+ {
+ PROVIDE(_data_start = .);
+ *(.data)
+ . = ALIGN(8);
+ PROVIDE(_data_end = .);
+ }
+
+ .rodata :
+ {
+ PROVIDE(_rodata_start = .);
+ *(.rodata .rodata.*)
+ . = ALIGN(8);
+ PROVIDE(_rodata_end = .);
+ }
+
+ .percpu :
+ {
+ PROVIDE(_percpu_start = .);
+ *(.percpu)
+ . = ALIGN(8);
+ PROVIDE(_percpu_end = .);
+ }
+
+ . = ALIGN(0x1000); /* init section is page aligned */
+
+ .init :
+ {
+ PROVIDE(_init_start = .);
+
+ *(.init.*)
+ . = ALIGN(8);
+
+ PROVIDE(_modtbl_start = .);
+ *(.modtbl)
+ . = ALIGN(8);
+ PROVIDE(_modtbl_end = .);
+
+ . = ALIGN(8);
+ PROVIDE(__setup_start = .);
+ *(.setup.init);
+ PROVIDE(__setup_end = .);
+
+ . = ALIGN(CONFIG_ARM_MAX_DTB_SIZE);
+ *(.devtree)
+ . = ALIGN(CONFIG_ARM_MAX_DTB_SIZE);
+
+ PROVIDE(_init_end = .);
+ }
+
+ . = ALIGN(0x1000); /* bss is page aligned */
+
+ .bss :
+ {
+ PROVIDE(_bss_start = .);
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN(8);
+ PROVIDE(_bss_end = .);
+ }
+
+ . = ALIGN(0x1000); /* all stacks are page aligned */
+
+ .hvc_stack :
+ {
+ PROVIDE(_hvc_stack_start = .);
+ . = . + (CONFIG_IRQ_STACK_SIZE * CONFIG_CPU_COUNT);
+ . = ALIGN(8);
+ PROVIDE(_hvc_stack_end = .);
+ }
+
+ . = ALIGN(0x1000); /* Need this to create proper pages */
+
+ PROVIDE(_code_end = .);
+}
diff --git a/arch/arm/cpu/arm64/objects.mk b/arch/arm/cpu/arm64/objects.mk
new file mode 100644
index 0000000..5ffb162
--- /dev/null
+++ b/arch/arm/cpu/arm64/objects.mk
@@ -0,0 +1,52 @@
+#/**
+# Copyright (c) 2013 Sukanto Ghosh.
+# All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# @file objects.mk
+# @author Sukanto Ghosh (sukant...@gmail.com)
+# @brief list of ARM64 cpu objects.
+# */
+
+# This selects which instruction set is used.
+# Note that GCC does not numerically define an architecture version
+# macro, but instead defines a whole series of macros which makes
+# testing for a specific architecture or later rather impossible.
+arch-$(CONFIG_ARMV8) += -mgeneral-regs-only -mlittle-endian
+
+cpu-cppflags+=-DTEXT_START=0x00000000
+cpu-cflags += $(arch-y) $(tune-y)
+cpu-asflags += $(arch-y) $(tune-y)
+cpu-ldflags +=
+
+cpu-objs-y+= cpu_entry.o
+cpu-objs-y+= cpu_cache.o
+cpu-objs-y+= cpu_init.o
+cpu-objs-y+= cpu_delay.o
+cpu-objs-y+= cpu_elf.o
+cpu-objs-$(CONFIG_ARM64_STACKTRACE)+= cpu_stacktrace.o
+cpu-objs-$(CONFIG_SMP)+= cpu_smp.o
+cpu-objs-$(CONFIG_SMP)+= cpu_locks.o
+cpu-objs-y+= cpu_atomic.o
+cpu-objs-y+= cpu_atomic64.o
+cpu-objs-y+= cpu_interrupts.o
+cpu-objs-y+= cpu_vcpu_helper.o
+cpu-objs-y+= cpu_vcpu_coproc.o
+cpu-objs-y+= cpu_vcpu_spr.o
+cpu-objs-y+= cpu_vcpu_mem.o
+cpu-objs-y+= cpu_vcpu_irq.o
+cpu-objs-y+= cpu_vcpu_emulate.o
+
diff --git a/arch/arm/cpu/arm64/openconf.cfg b/arch/arm/cpu/arm64/openconf.cfg
new file mode 100644
index 0000000..15c8012
--- /dev/null
+++ b/arch/arm/cpu/arm64/openconf.cfg
@@ -0,0 +1,56 @@
+#/**
+# Copyright (c) 2013 Sukanto Ghosh.
+# All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# @file openconf.cfg
+# @author Sukanto Ghosh (sukant...@gmail.com)
+# @brief Config file for ARM64
+#*/
+
+config CONFIG_CPU
+ string
+ default "arm64"
+
+config CONFIG_CPU_LE
+ bool
+ default y
+
+config CONFIG_CPU_BE
+ bool
+ default n
+
+config CONFIG_64BIT
+ bool
+ default y
+
+config CONFIG_ARM64_STACKTRACE
+ bool "Enable Stack Tracing"
+ default y
+ help
+ This option forces ARM compiler to use frame pointer for
+ all functions hence making stack tracing possible.
+
+ Enabling this option forces compiler to add additional
+ instructions to setup stack frame in function prolog of
+ all functions.
+
+ Disabling this option makes hypervisor slightly faster but
+ disable stack trace information printed by hypervisor.
+
+ By default, this options is always enabled. You can disable
+ this option in-case you want slightly faster and slight
+ smaller hypervisor
diff --git a/arch/arm/cpu/common/openconf.cfg b/arch/arm/cpu/common/openconf.cfg
index ffb96bc..25fd347 100644
--- a/arch/arm/cpu/common/openconf.cfg
+++ b/arch/arm/cpu/common/openconf.cfg
@@ -28,12 +28,12 @@ config CONFIG_ARM_LOCKS

config CONFIG_ARM_VGIC
bool "ARM GIC with Virtualization Extensions"
- depends on CONFIG_ARM_GIC && CONFIG_ARM32VE
+ depends on CONFIG_ARM_GIC && (CONFIG_ARM32VE || CONFIG_ARM64)
default n

config CONFIG_ARM_GENERIC_TIMER
bool "ARM Generic Timer"
- depends on CONFIG_ARM_GIC && CONFIG_ARM32VE
+ depends on CONFIG_ARM_GIC && (CONFIG_ARM32VE || CONFIG_ARM64)
default n

config CONFIG_ARM_MMU_LPAE
diff --git a/arch/arm/cpu/openconf.cfg b/arch/arm/cpu/openconf.cfg
index ccc4c6d..47b255c 100644
--- a/arch/arm/cpu/openconf.cfg
+++ b/arch/arm/cpu/openconf.cfg
@@ -72,6 +72,14 @@ choice
Select this if you are using Cortex-A15 (with virtualization
extension)

+ config CONFIG_CPU_GENERIC_V8
+ bool "generic-v8"
+ select CONFIG_SMP
+ select CONFIG_ARMV8
+ select CONFIG_ARM_MMU_LPAE
+ help
+ Select this if you are using Generic ARMv8 CPU
+
endchoice

config CONFIG_CPU_COUNT
@@ -80,6 +88,7 @@ config CONFIG_CPU_COUNT
default 4 if CONFIG_CPU_ARM11MP
default 4 if CONFIG_CPU_CORTEX_A9
default 4 if CONFIG_CPU_CORTEX_A15
+ default 8 if CONFIG_CPU_GENERIC_V8
default 1

config CONFIG_ARMV5
@@ -107,6 +116,11 @@ config CONFIG_ARMV7A_VE
select CONFIG_ARM32VE
default n

+config CONFIG_ARMV8
+ bool
+ select CONFIG_ARM64
+ default n
+
config CONFIG_ARM32
bool
default n
@@ -115,6 +129,10 @@ config CONFIG_ARM32VE
bool
default n

+config CONFIG_ARM64
+ bool
+ default n
+
menu "ARM Options"

config CONFIG_VAPOOL_SIZE_MB
@@ -138,5 +156,11 @@ source "arch/arm/cpu/arm32ve/openconf.cfg"

endif

+if CONFIG_ARM64
+
+source "arch/arm/cpu/arm64/openconf.cfg"
+
+endif
+
endmenu

--
1.7.9.5

Sukanto Ghosh

unread,

Sep 15, 2013, 4:08:45 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

There are no real development boards openly available for arm64
hence we introduce a completely paravirtualized virt-v8 guest
for folks interested in having a dummy or paravirtualized
hardware for guest.

This virt-v8 guest is a virtual machine with VirtIO-based
devices, GIC and ARMv8 generic timer.

This patch adds guest template for virt-v8 guest.

Signed-off-by: Sukanto Ghosh <sukant...@gmail.com>
---

arch/arm/board/common/guests/virt-v8x2.dtsi | 94 +++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 arch/arm/board/common/guests/virt-v8x2.dtsi

diff --git a/arch/arm/board/common/guests/virt-v8x2.dtsi b/arch/arm/board/common/guests/virt-v8x2.dtsi
new file mode 100644
index 0000000..a6f4959
--- /dev/null
+++ b/arch/arm/board/common/guests/virt-v8x2.dtsi
@@ -0,0 +1,94 @@
+
+/ {
+ templates {
+ virt-v8x2 {
+ model = "virt-v8";
+ device_type = "guest";
+
+ vcpus {
+ vcpu0 {
+ device_type = "vcpu";
+ compatible = "armv8,generic";
+ start_pc = <0x00000000>;
+ gentimer_virt_irq = <27>;
+ gentimer_phys_irq = <30>;
+ };
+
+ vcpu1 {
+ device_type = "vcpu";
+ compatible = "armv8,generic";
+ start_pc = <0x00000000>;
+ gentimer_virt_irq = <27>;
+ gentimer_phys_irq = <30>;
+ };
+ };
+
+ aspace {
+ guest_irq_count = <2048>;
+
+ mem0 {
+ manifest_type = "real";
+ address_type = "memory";
+ guest_physical_addr = <0x80000000>;
+ host_physical_addr = <0x00000000>; /* To be set by DTS including this file */
+ physical_size = <0x00000000>; /* To be set by DTS including this file */
+ device_type = "ram";
+ };
+
+ gic {
+ manifest_type = "virtual";
+ address_type = "memory";
+ guest_physical_addr = <0x2C000000>;
+ physical_size = <0x3000>;
+ device_type = "pic";
+ compatible = "vexpress,gicv2";
+ parent_irq = <6>;
+ };
+
+ nor_flash0 {
+ manifest_type = "real";
+ address_type = "memory";
+ guest_physical_addr = <0x00000000>;
+ host_physical_addr = <0x00000000>; /* To be set by DTS including this file */
+ physical_size = <0x00000000>; /* To be set by DTS including this file */
+ device_type = "rom";
+ };
+
+ virtio-net0 {
+ manifest_type = "virtual";
+ address_type = "memory";
+ device_type = "virtio";
+ compatible = "virtio,mmio";
+ virtio_type = <1>;
+ guest_physical_addr = <0x40200000>;
+ physical_size = <0x1000>;
+ switch = ""; /* To be set by DTS including this file */
+ interrupts = <40>;
+ };
+
+ virtio-blk0 {
+ manifest_type = "virtual";
+ address_type = "memory";
+ device_type = "virtio";
+ compatible = "virtio,mmio";
+ virtio_type = <2>;
+ guest_physical_addr = <0x40400000>;
+ physical_size = <0x1000>;
+ blkdev = ""; /* To be set by DTS including this file */
+ interrupts = <41>;
+ };
+
+ virtio-con0 {
+ manifest_type = "virtual";
+ address_type = "memory";
+ device_type = "virtio";
+ compatible = "virtio,mmio";
+ virtio_type = <3>;
+ guest_physical_addr = <0x40600000>;
+ physical_size = <0x1000>;
+ interrupts = <42>;
+ };
+ };
+ };
+ };
+};
--
1.7.9.5

Sukanto Ghosh

unread,

Sep 15, 2013, 4:08:46 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

With the new arm64 (or armv8) port we try to implement unified
Xvisor binary for all arm64 boards.

To achieve this we introduce generic armv8 board which is fully
device tree based (i.e. DTB-based) similar to linux arm64 port.

The only constraint with generic armv8 board support is that
actual HW board on which Xvisor runs should have GICv2 or higher
as PIC.

Signed-off-by: Sukanto Ghosh <sukant...@gmail.com>
---

arch/arm/board/generic-v8/brd_defterm.c | 93 ++++++
arch/arm/board/generic-v8/brd_main.c | 130 ++++++++
arch/arm/board/generic-v8/brd_smp.c | 232 ++++++++++++++
.../dts/foundation-v8/foundation-v8.dtsi | 122 ++++++++
.../dts/foundation-v8/one_guest_virt_v8.dts | 41 +++
arch/arm/board/generic-v8/dts/skeleton.dts | 24 ++
arch/arm/board/generic-v8/include/arch_host_irq.h | 61 ++++
arch/arm/board/generic-v8/include/gic_config.h | 29 ++
arch/arm/board/generic-v8/objects.mk | 30 ++
arch/arm/board/generic-v8/openconf.cfg | 31 ++
arch/arm/board/openconf.cfg | 21 ++
arch/arm/configs/generic-v8-defconfig | 322 ++++++++++++++++++++
12 files changed, 1136 insertions(+)

create mode 100644 arch/arm/board/generic-v8/brd_defterm.c
create mode 100644 arch/arm/board/generic-v8/brd_main.c
create mode 100644 arch/arm/board/generic-v8/brd_smp.c
create mode 100644 arch/arm/board/generic-v8/dts/foundation-v8/foundation-v8.dtsi
create mode 100644 arch/arm/board/generic-v8/dts/foundation-v8/one_guest_virt_v8.dts
create mode 100644 arch/arm/board/generic-v8/dts/skeleton.dts
create mode 100644 arch/arm/board/generic-v8/include/arch_host_irq.h
create mode 100644 arch/arm/board/generic-v8/include/gic_config.h
create mode 100644 arch/arm/board/generic-v8/objects.mk
create mode 100644 arch/arm/board/generic-v8/openconf.cfg
create mode 100644 arch/arm/configs/generic-v8-defconfig

diff --git a/arch/arm/board/generic-v8/brd_defterm.c b/arch/arm/board/generic-v8/brd_defterm.c
new file mode 100644
index 0000000..727ac95
--- /dev/null
+++ b/arch/arm/board/generic-v8/brd_defterm.c
@@ -0,0 +1,93 @@

+/**
+ * Copyright (c) 2013 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *

+ * @file brd_defterm.c

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief default serial terminal

+ */
+
+#include <vmm_error.h>
+#include <vmm_types.h>
+#include <vmm_compiler.h>

+#include <vmm_devtree.h>
+#include <vmm_host_aspace.h>
+#include <drv/pl011.h>
+
+static virtual_addr_t v2m_defterm_base;
+static u32 v2m_defterm_inclk;
+static u32 v2m_defterm_baud;
+
+int arch_defterm_putc(u8 ch)
+{
+ if (!pl011_lowlevel_can_putc(v2m_defterm_base)) {
+ return VMM_EFAIL;
+ }
+ pl011_lowlevel_putc(v2m_defterm_base, ch);

+ return VMM_OK;
+}
+

+int arch_defterm_getc(u8 * ch)
+{
+ if (!pl011_lowlevel_can_getc(v2m_defterm_base)) {
+ return VMM_EFAIL;
+ }
+ *ch = pl011_lowlevel_getc(v2m_defterm_base);

+ return VMM_OK;
+}
+

+int __init arch_defterm_init(void)
+{
+ int rc;
+ u32 *val;
+ const char *attr;

+ struct vmm_devtree_node *node;
+

+ node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING
+ VMM_DEVTREE_CHOSEN_NODE_NAME);
+ if (!node) {
+ return VMM_ENODEV;
+ }
+

+ attr = vmm_devtree_attrval(node, VMM_DEVTREE_CONSOLE_ATTR_NAME);
+ if (!attr) {

+ return VMM_ENODEV;
+ }
+

+ node = vmm_devtree_getnode(attr);

+ if (!node) {
+ return VMM_ENODEV;
+ }
+

+ rc = vmm_devtree_regmap(node, &v2m_defterm_base, 0);
+ if (rc) {

+ return rc;
+ }
+

+ rc = vmm_devtree_clock_frequency(node, &v2m_defterm_inclk);
+ if (rc) {

+ return rc;
+ }
+

+ val = vmm_devtree_attrval(node, "baudrate");
+ v2m_defterm_baud = (val) ? *val : 115200;
+
+ pl011_lowlevel_init(v2m_defterm_base,
+ v2m_defterm_baud,
+ v2m_defterm_inclk);
+ return VMM_OK;
+}
diff --git a/arch/arm/board/generic-v8/brd_main.c b/arch/arm/board/generic-v8/brd_main.c
new file mode 100644
index 0000000..dfef9e5
--- /dev/null
+++ b/arch/arm/board/generic-v8/brd_main.c
@@ -0,0 +1,130 @@

+ * @file brd_main.c

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief main source file for board specific code

+ */
+
+#include <vmm_error.h>
+#include <vmm_smp.h>

+#include <vmm_spinlocks.h>
+#include <vmm_devtree.h>
+#include <vmm_devdrv.h>
+#include <vmm_host_io.h>
+#include <vmm_host_aspace.h>
+#include <vmm_stdio.h>
+#include <arch_board.h>
+#include <arch_timer.h>
+#include <generic_timer.h>
+
+/*
+ * Reset & Shutdown
+ */
+
+int arch_board_reset(void)

+{
+ /* FIXME: To be implemented. */

+ vmm_printf("%s: not implemented\n", __func__);

+ return VMM_EFAIL;
+}
+
+/*

+ * Print board information
+ */
+
+void arch_board_print_info(struct vmm_chardev *cdev)

+{
+ /* FIXME: To be implemented. */
+}
+

+int arch_board_shutdown(void)

+{
+ /* FIXME: To be implemented. */

+ vmm_printf("%s: not implemented\n", __func__);

+ return VMM_EFAIL;
+}
+
+/*

+ * Initialization functions
+ */
+
+int __init arch_board_early_init(void)
+{
+ /* Host aspace, Heap, Device tree, and Host IRQ available.
+ *
+ * Do necessary early stuff like:
+ * iomapping devices,
+ * SOC clocking init,
+ * Setting-up system data in device tree nodes,
+ * ....
+ */

+
+ return VMM_OK;
+}
+

+int __init arch_clocksource_init(void)

+{
+ int rc;
+

+ /* Initialize generic timer as clock source */
+ rc = generic_timer_clocksource_init();
+ if (rc) {
+ vmm_printf("%s: generic clocksource init failed (error %d)\n",
+ __func__, rc);

+ }
+
+ return VMM_OK;
+}
+

+int __cpuinit arch_clockchip_init(void)

+{
+ int rc;
+

+ /* Initialize generic timer as clock source */
+ rc = generic_timer_clockchip_init();
+ if (rc) {
+ vmm_printf("%s: generic clockchip init failed (error %d)\n",
+ __func__, rc);

+ }
+
+ return VMM_OK;
+}
+

+int __init arch_board_final_init(void)
+{
+ int rc;

+ struct vmm_devtree_node *node;
+

+ /* All VMM API's are available here */

+ /* We can register a Board specific resource here */
+
+ /* Find simple-bus node */
+ node = vmm_devtree_find_compatible(NULL, NULL, "simple-bus");

+ if (!node) {
+ return VMM_ENODEV;
+ }
+

+ /* Do probing using device driver framework */
+ rc = vmm_devdrv_probe(node);
+ if (rc) {

+ return rc;
+ }
+

+ return VMM_OK;
+}
diff --git a/arch/arm/board/generic-v8/brd_smp.c b/arch/arm/board/generic-v8/brd_smp.c
new file mode 100644
index 0000000..b967b62
--- /dev/null
+++ b/arch/arm/board/generic-v8/brd_smp.c
@@ -0,0 +1,232 @@

+/**
+ * Copyright (c) 2012 Sukanto Ghosh.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *

+ * @file brd_smp.c

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief board specific smp functions

+ */
+
+#include <vmm_error.h>

+#include <vmm_types.h>
+#include <vmm_smp.h>
+#include <vmm_stdio.h>
+#include <vmm_delay.h>
+#include <vmm_cache.h>
+#include <vmm_host_io.h>
+#include <vmm_host_irq.h>
+#include <vmm_host_aspace.h>
+#include <vmm_compiler.h>
+#include <libs/libfdt.h>
+#include <libs/stringlib.h>
+#include <smp_scu.h>
+#include <gic.h>
+
+#define MPIDR_HWID_BITMASK 0xff00ffffffLU
+
+int __init arch_smp_init_cpus(void)
+{
+ int i = 0;
+ const char *aval;
+ struct dlist *l;
+ struct vmm_devtree_node *node, *cnode;

+
+ node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING

+ "cpus");
+ if (!node) {
+ return VMM_EFAIL;
+ }
+
+ list_for_each(l, &node->child_list) {
+ cnode = list_entry(l, struct vmm_devtree_node, head);
+ aval = vmm_devtree_attrval(cnode,
+ VMM_DEVTREE_DEVICE_TYPE_ATTR_NAME);
+ if (aval &&
+ !strcmp(aval, VMM_DEVTREE_DEVICE_TYPE_VAL_CPU)) {
+ vmm_set_cpu_possible(i, TRUE);
+ i++;

+ }
+ }
+
+ return VMM_OK;
+}
+

+extern u8 _start_secondary;
+volatile unsigned long secondary_holding_pen_release;
+
+/*
+ * Write secondary_holding_pen_release in a way that is guaranteed to be
+ * visible to all observers, irrespective of whether they're taking part
+ * in coherency or not. This is necessary for the hotplug code to work
+ * reliably.
+ */
+static void write_pen_release(u64 val)
+{
+ virtual_addr_t start = (virtual_addr_t)&secondary_holding_pen_release;
+ unsigned long size = sizeof(secondary_holding_pen_release);
+
+ secondary_holding_pen_release = val;
+ vmm_flush_dcache_range(start, start + size);
+}
+
+int __init arch_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int cpu = 0, rc = VMM_OK;
+ struct dlist *l;
+ struct vmm_devtree_node *node, *cnode;

+
+ node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING

+ "cpus");
+ if (!node) {
+ return VMM_EFAIL;
+ }
+
+ list_for_each(l, &node->child_list) {
+ physical_addr_t *release_addr_pa;
+ virtual_addr_t release_addr_va;
+ physical_addr_t secondary_jump_addr;
+ const char *enable_method;
+
+ cnode = list_entry(l, struct vmm_devtree_node, head);
+
+ if (cpu >= max_cpus) {
+ break;
+ }
+
+ enable_method = vmm_devtree_attrval(cnode,
+ VMM_DEVTREE_ENABLE_METHOD_ATTR_NAME);
+ if (!enable_method) {
+ vmm_printf("%s: enable-method not set\n", cnode->name);
+ continue;
+ }
+
+ /* We currently support only the "spin-table" enable-method. */
+ if (strcmp(enable_method, "spin-table")) {
+ vmm_printf("%s: enable-method \'%s\' not supported\n",
+ cnode->name, enable_method);
+ continue;
+ }
+
+ release_addr_pa = vmm_devtree_attrval(cnode,
+ VMM_DEVTREE_CPU_RELEASE_ADDR_ATTR_NAME);
+ if (!release_addr_pa) {
+ vmm_printf("%s: cpu-release-addr not set\n", cnode->name);
+ continue;
+ }
+
+ release_addr_va = vmm_host_iomap(*release_addr_pa,
+ sizeof(physical_addr_t));
+ rc = vmm_host_va2pa((virtual_addr_t)&_start_secondary,
+ &secondary_jump_addr);
+ if (rc) {
+ vmm_printf("%s: failed to iomap cpu-release-addr\n",
+ cnode->name);
+ continue;
+ }
+ vmm_writeq(secondary_jump_addr, (void *)release_addr_va);
+ vmm_host_iounmap((virtual_addr_t)release_addr_va,
+ sizeof(physical_addr_t));
+
+ /* Send an event to wake up the secondary CPU. */
+ asm volatile ("sev");
+
+ vmm_set_cpu_present(cpu, TRUE);
+
+ cpu++;

+ }
+
+ return VMM_OK;
+}
+

+int __init arch_smp_start_cpu(u32 cpu)
+{
+ int i = 0;
+ struct dlist *l;
+ physical_addr_t hwid;
+ struct vmm_devtree_node *node, *cnode;

+
+ node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING

+ "cpus");
+ if (!node) {
+ return VMM_EFAIL;
+ }
+
+ list_for_each(l, &node->child_list) {
+ if (i++ == cpu) {
+ cnode = list_entry(l, struct vmm_devtree_node, head);

+ break;
+ }
+ }
+

+ if (vmm_devtree_regaddr(cnode, &hwid, 0)) {

+ return VMM_EFAIL;
+ }
+

+ /*
+ * Non affinity bits must be set to 0 in the DT
+ */
+ if (hwid & ~MPIDR_HWID_BITMASK) {
+ vmm_printf("%s: invalid mpidr value in reg property\n",
+ cnode->name);

+ return VMM_EFAIL;
+ }
+

+ write_pen_release(hwid);
+ asm volatile ("sev");
+ vmm_udelay(1000);

+
+ return VMM_OK;
+}
+

+static vmm_irq_return_t smp_ipi_handler(int irq_no, void *dev)
+{
+ /* Call core code to handle IPI1 */
+ vmm_smp_ipi_exec();
+
+ return VMM_IRQ_HANDLED;
+}
+
+void arch_smp_ipi_trigger(const struct vmm_cpumask *dest)
+{
+ /* Send IPI1 to other cores */
+ gic_raise_softirq(dest, 1);
+}
+
+int __cpuinit arch_smp_ipi_init(void)
+{
+ int rc;

+ u32 cpu = vmm_smp_processor_id();
+
+ if (!cpu) {

+ /* Register IPI1 interrupt handler */
+ rc = vmm_host_irq_register(1, "IPI1", &smp_ipi_handler, NULL);
+ if (rc) {

+ return rc;
+ }
+

+ /* Mark IPI1 interrupt as per-cpu */
+ rc = vmm_host_irq_mark_per_cpu(1);
+ if (rc) {

+ return rc;
+ }
+ }
+

+ /* Explicitly enable IPI1 interrupt */
+ gic_enable_ppi(1);

+
+ return VMM_OK;
+}

diff --git a/arch/arm/board/generic-v8/dts/foundation-v8/foundation-v8.dtsi b/arch/arm/board/generic-v8/dts/foundation-v8/foundation-v8.dtsi
new file mode 100644
index 0000000..60eec29
--- /dev/null
+++ b/arch/arm/board/generic-v8/dts/foundation-v8/foundation-v8.dtsi
@@ -0,0 +1,122 @@
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "foundation-v8";
+
+ chosen { };
+ aliases { };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ model = "Cortex-A57";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x84000000>;
+ };
+
+ cpu1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ model = "Cortex-A57";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x84000000>;
+ };
+
+ cpu2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ model = "Cortex-A57";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x84000000>;
+ };
+
+ cpu3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ model = "Cortex-A57";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x84000000>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x10000000>; /* 256 MB */
+ };
+
+ gic { /* Generic Interrupt Controller */
+ device_type = "pic";
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ reg = <0x0 0x2C001000 0x0 0x1000 /* Dist Interface */
+ 0x0 0x2C002000 0x0 0x1000 /* CPU Interface */
+ 0x0 0x2C004000 0x0 0x2000 /* VCPU Control Interface */
+ 0x0 0x2C006000 0x0 0x2000>; /* VCPU Interface */
+ irq_start = <16>;
+ interrupts = <25>; /* VGIC Maintanence IRQ */
+ };
+
+ gen-timer { /* Generic Timer */
+ device_type = "timer";
+ compatible = "arm,armv8-timer";
+ clock-frequency = <100000000>;
+ interrupts = <26 30 27>;
+ };
+
+ motherboard {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+
+ eth0 {
+ device_type = "nic";
+ compatible = "smc91x";
+ reg = <0x1A000000 0x10000>;
+ interrupts = <47>;
+ switch = "netbridge0";
+ };
+
+ sysreg { /* System Registers */
+ device_type = "sys";
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x1C010000 0x1000>;
+ };
+
+ SERIAL0: uart0 {
+ device_type = "serial";
+ compatible = "arm,pl011";
+ reg = <0x1C090000 0x1000>;
+ clock-frequency = <24000000>;
+ baudrate = <115200>;
+ interrupts = <37>;
+ };
+ };
+
+ vmm {
+ net {
+ netbridge0 {
+ device_type = "netswitch";
+ compatible = "bridge";
+ };
+ };
+ };
+
+ /* Empty guests node */
+ guests {
+ };
+};
+
+/* Add guest templates */
+/include/ "../../../common/guests/realview-pb-a8.dtsi"
+/include/ "../../../common/guests/vexpress-a9x2.dtsi"
+/include/ "../../../common/guests/vexpress-a15x2.dtsi"
+/include/ "../../../common/guests/virt-v8x2.dtsi"
+
diff --git a/arch/arm/board/generic-v8/dts/foundation-v8/one_guest_virt_v8.dts b/arch/arm/board/generic-v8/dts/foundation-v8/one_guest_virt_v8.dts
new file mode 100644
index 0000000..12dca86
--- /dev/null
+++ b/arch/arm/board/generic-v8/dts/foundation-v8/one_guest_virt_v8.dts
@@ -0,0 +1,41 @@
+
+/dts-v1/;
+
+/include/ "foundation-v8.dtsi"
+
+/ {
+ chosen {
+ console = &SERIAL0;
+ bootcmd = /* Copy guest0 device tree from templates */
+ "devtree node copy /guests guest0 /templates/virt-v8x2",
+
+ /* Update guest0 memory regions */
+ "devtree attr set /guests/guest0/aspace/mem0 host_physical_addr physaddr 0x82000000",
+ "devtree attr set /guests/guest0/aspace/mem0 physical_size physsize 0x06000000",
+
+ /* Update guest0 flash region */
+ "devtree attr set /guests/guest0/aspace/nor_flash0 host_physical_addr physaddr 0x81000000",
+ "devtree attr set /guests/guest0/aspace/nor_flash0 physical_size physsize 0x01000000",
+
+ /* Connect guest0/virtio-net0 netport to netbridge0 */
+ "devtree attr set /guests/guest0/aspace/virtio-net0 switch string netbridge0",
+
+ /* Replace guest0 GIC emulator with vGIC emulator */
+ "devtree node copy /guests/guest0/aspace gic_cpu /guests/guest0/aspace/gic",
+ "devtree attr set /guests/guest0/aspace/gic_cpu manifest_type string real",
+ "devtree attr set /guests/guest0/aspace/gic_cpu guest_physical_addr physaddr 0x2C002000",
+ "devtree attr set /guests/guest0/aspace/gic_cpu host_physical_addr physaddr 0x2C006000",
+ "devtree attr set /guests/guest0/aspace/gic_cpu physical_size physsize 0x1000",
+ "devtree attr del /guests/guest0/aspace/gic_cpu compatible",
+ "devtree attr del /guests/guest0/aspace/gic_cpu parent_irq",
+ "devtree node copy /guests/guest0/aspace gic_dist /guests/guest0/aspace/gic",
+ "devtree attr set /guests/guest0/aspace/gic_dist guest_physical_addr physaddr 0x2C001000",
+ "devtree attr set /guests/guest0/aspace/gic_dist physical_size physsize 0x1000",
+ "devtree attr set /guests/guest0/aspace/gic_dist compatible string arm,vgic",
+ "devtree node del /guests/guest0/aspace/gic",
+
+ /* Create guest0 */
+ "guest create guest0";
+ };
+};
+
diff --git a/arch/arm/board/generic-v8/dts/skeleton.dts b/arch/arm/board/generic-v8/dts/skeleton.dts
new file mode 100644
index 0000000..1738cec
--- /dev/null
+++ b/arch/arm/board/generic-v8/dts/skeleton.dts
@@ -0,0 +1,24 @@
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "skeleton-armv8";
+
+ chosen { };
+ aliases { };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
+ vmm {
+ };
+
+ /* Empty guests node */
+ guests {
+ };
+};
+
diff --git a/arch/arm/board/generic-v8/include/arch_host_irq.h b/arch/arm/board/generic-v8/include/arch_host_irq.h
new file mode 100644
index 0000000..1ebc5be
--- /dev/null
+++ b/arch/arm/board/generic-v8/include/arch_host_irq.h
@@ -0,0 +1,61 @@

+ * @file arch_host_irq.h

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief board specific host irq functions
+ */
+#ifndef _ARCH_HOST_IRQ_H__
+#define _ARCH_HOST_IRQ_H__
+
+#include <vmm_types.h>
+#include <vmm_smp.h>
+#include <gic.h>
+
+#define ARCH_HOST_IRQ_COUNT GIC_NR_IRQS
+
+/* Get current active host irq */
+static inline u32 arch_host_irq_active(u32 cpu_irq_no)
+{
+ return gic_active_irq(0);
+}
+
+/* Initialize board specifig host irq hardware (i.e PIC) */
+static inline int arch_host_irq_init(void)
+{
+ int rc;

+ u32 cpu = vmm_smp_processor_id();

+ struct vmm_devtree_node *node;
+

+ if (!cpu) {
+ node = vmm_devtree_find_compatible(NULL, NULL,
+ "arm,cortex-a9-gic");

+ if (!node) {
+ return VMM_ENODEV;
+ }
+

+ rc = gic_devtree_init(node, NULL);
+ } else {
+ gic_secondary_init(0);

+ rc = VMM_OK;
+ }
+
+ return rc;
+}
+

+#endif
diff --git a/arch/arm/board/generic-v8/include/gic_config.h b/arch/arm/board/generic-v8/include/gic_config.h
new file mode 100644
index 0000000..7e104e6
--- /dev/null
+++ b/arch/arm/board/generic-v8/include/gic_config.h
@@ -0,0 +1,29 @@

+ * @file gic_config.h

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief GIC Configuration Header
+ */
+#ifndef __GIC_CONFIG_H__
+#define __GIC_CONFIG_H__
+
+#define GIC_NR_IRQS 256
+#define GIC_MAX_NR 1
+
+#endif /* __GIC_CONFIG_H__ */
diff --git a/arch/arm/board/generic-v8/objects.mk b/arch/arm/board/generic-v8/objects.mk
new file mode 100644
index 0000000..dc2545b
--- /dev/null
+++ b/arch/arm/board/generic-v8/objects.mk
@@ -0,0 +1,30 @@

+#/**
+# Copyright (c) 2013 Sukanto Ghosh.
+# All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# @file objects.mk
+# @author Sukanto Ghosh (sukant...@gmail.com)

+# @brief list of Generic ARMv8 board objects.
+# */
+
+board-objs-y+=brd_defterm.o
+board-objs-y+=brd_main.o
+board-objs-$(CONFIG_SMP)+=brd_smp.o
+board-objs-y+=dts/skeleton.o
+
+board-dtbs-$(CONFIG_FOUNDATION_V8_ONE_GUEST_VIRT_V8_DTS)+=dts/foundation-v8/one_guest_virt_v8.dtb
+
diff --git a/arch/arm/board/generic-v8/openconf.cfg b/arch/arm/board/generic-v8/openconf.cfg
new file mode 100644
index 0000000..086a2a1
--- /dev/null
+++ b/arch/arm/board/generic-v8/openconf.cfg
@@ -0,0 +1,31 @@

+#/**
+# Copyright (c) 2013 Sukanto Ghosh.
+# All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# @file openconf.cfg
+# @author Sukanto Ghosh (sukant...@gmail.com)

+# @brief Board config file for Generic ARMv8 board
+# */
+
+menu "Generic-v8 Options"
+
+config CONFIG_FOUNDATION_V8_ONE_GUEST_VIRT_V8_DTS
+ bool "1x virt-v8 guest DTS"
+ help
+ This option enables DTS for one virt-v8 paravirtualized guest
+
+endmenu
diff --git a/arch/arm/board/openconf.cfg b/arch/arm/board/openconf.cfg
index 6ed8d75..8f5d081 100644
--- a/arch/arm/board/openconf.cfg
+++ b/arch/arm/board/openconf.cfg
@@ -144,6 +144,17 @@ if CONFIG_CPU_CORTEX_A9
Exynos4 SOC family from Samsung
endif

+if CONFIG_CPU_GENERIC_V8
+ config CONFIG_BOARD_GENERIC_V8
+ bool "generic-v8"
+ select CONFIG_ARM_GIC
+ select CONFIG_ARM_GENERIC_TIMER
+ select CONFIG_SERIAL
+ select CONFIG_SERIAL_PL01X
+ help
+ Generic ARMv8 board.
+endif
+
endchoice

if CONFIG_BOARD_VERSATILE
@@ -236,4 +247,14 @@ source "arch/arm/board/exynos4/openconf.cfg"

endif

+if CONFIG_BOARD_GENERIC_V8
+
+config CONFIG_BOARD
+ string
+ default "generic-v8"
+
+source "arch/arm/board/generic-v8/openconf.cfg"
+
+endif
+
source "arch/arm/board/common/openconf.cfg"
diff --git a/arch/arm/configs/generic-v8-defconfig b/arch/arm/configs/generic-v8-defconfig
new file mode 100644
index 0000000..e987d8d
--- /dev/null
+++ b/arch/arm/configs/generic-v8-defconfig
@@ -0,0 +1,322 @@
+#
+# Automatically generated make config: don't edit
+# Project: Xvisor (eXtensible Versatile hypervISOR)
+# Version: 0.2.2
+# Sat Aug 24 21:09:30 2013
+#
+CONFIG_SMP=y
+CONFIG_ARCH_ARM=y
+# CONFIG_ARCH_x86 is not set
+CONFIG_ARCH="arm"
+# CONFIG_CPU_ARM926T is not set
+# CONFIG_CPU_ARM11 is not set
+# CONFIG_CPU_ARM11MP is not set
+# CONFIG_CPU_CORTEX_A8 is not set
+# CONFIG_CPU_CORTEX_A9 is not set
+# CONFIG_CPU_CORTEX_A15 is not set
+CONFIG_CPU_GENERIC_V8=y
+CONFIG_CPU_COUNT=4
+# CONFIG_ARMV5 is not set
+# CONFIG_ARMV6 is not set
+# CONFIG_ARMV6K is not set
+# CONFIG_ARMV7A is not set
+# CONFIG_ARMV7A_VE is not set
+CONFIG_ARMV8=y
+# CONFIG_ARM32 is not set
+# CONFIG_ARM32VE is not set
+CONFIG_ARM64=y
+
+#
+# ARM Options
+#
+CONFIG_VAPOOL_SIZE_MB=16
+CONFIG_ARM_VGIC=y
+CONFIG_ARM_GENERIC_TIMER=y
+CONFIG_ARM_MMU_LPAE=y
+CONFIG_ARM_MAX_DTB_SIZE=0xC000
+CONFIG_CPU="arm64"
+CONFIG_CPU_LE=y
+# CONFIG_CPU_BE is not set
+CONFIG_64BIT=y
+CONFIG_ARM64_STACKTRACE=y
+# CONFIG_BOARD_VERSATILE is not set
+# CONFIG_BOARD_IMX25 is not set
+# CONFIG_BOARD_BCM2835 is not set
+# CONFIG_BOARD_IMX31 is not set
+# CONFIG_BOARD_REALVIEW is not set
+# CONFIG_BOARD_OMAP3 is not set
+# CONFIG_BOARD_SUN4I is not set
+# CONFIG_BOARD_VEXPRESS is not set
+# CONFIG_BOARD_EXYNOS4 is not set
+CONFIG_BOARD_GENERIC_V8=y
+CONFIG_BOARD="generic-v8"
+
+#
+# Generic-V8 Options
+#
+# CONFIG_FOUNDATION_V8_SKELETON_DTS is not set
+CONFIG_FOUNDATION_V8_ONE_GUEST_VIRT_V8_DTS=y
+# CONFIG_ARM_VIC is not set
+CONFIG_ARM_GIC=y
+# CONFIG_ARM_TIMER_SP804 is not set
+# CONFIG_ARM_TWD is not set
+# CONFIG_ICST is not set
+# CONFIG_ARM_SCU is not set
+# CONFIG_VERSATILE_CLOCK is not set
+# CONFIG_VERSATILE_CLCD is not set
+# CONFIG_OMAP is not set
+# CONFIG_SAMSUNG_MCT is not set
+# CONFIG_SAMSUNG_MCT_LOCAL_TIMERS is not set
+# CONFIG_SUNXI is not set
+# CONFIG_FREESCALE_AVIC is not set
+# CONFIG_FREESCALE_EPIT is not set
+
+#
+# Hypervisor Options
+#
+
+#
+# General Configuration
+#
+MODULES=y
+# CONFIG_VERBOSE_MODE is not set
+CONFIG_BANNER_NONE=y
+# CONFIG_BANNER_BANNER4 is not set
+# CONFIG_BANNER_COLOSSAL is not set
+# CONFIG_BANNER_O8 is not set
+# CONFIG_BANNER_ROMAN is not set
+CONFIG_IRQ_STACK_SIZE=4096
+CONFIG_THREAD_STACK_SIZE=8192
+CONFIG_MAX_VCPU_COUNT=64
+CONFIG_MAX_GUEST_COUNT=16
+CONFIG_VGPA2REG_CACHE_SIZE=8
+CONFIG_WFI_TIMEOUT_SECS=10
+# CONFIG_PROFILE is not set
+
+#
+# Heap Configuration
+#
+CONFIG_HEAP_SIZE_MB=4
+CONFIG_HEAP_BUDDY=y
+
+#
+# Scheduler Configuration
+#
+# CONFIG_SCHEDALGO_RR is not set
+CONFIG_SCHEDALGO_PRR=y
+# CONFIG_TSLICE_1MS is not set
+CONFIG_TSLICE_10MS=y
+# CONFIG_TSLICE_100MS is not set
+CONFIG_TSLICE_MS=10
+
+#
+# Load Balancer Configuration
+#
+CONFIG_LOADBAL_CRUDE=y
+
+#
+# Device Support
+#
+CONFIG_RTC=y
+CONFIG_INPUT=y
+# CONFIG_FB is not set
+CONFIG_BLOCK=y
+CONFIG_BLOCKPART=y
+CONFIG_BLOCKPART_DOS=y
+CONFIG_NET=y
+CONFIG_NET_MBUF_POOL_SIZE=2048
+CONFIG_NET_MBUF_EXT_POOL_SIZE_KB=256
+
+#
+# Command Options
+#
+CONFIG_CMD_VERSION=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_SHUTDOWN=y
+CONFIG_CMD_HOST=y
+CONFIG_CMD_DEVTREE=y
+CONFIG_CMD_VCPU=y
+CONFIG_CMD_GUEST=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_THREAD=y
+CONFIG_CMD_CHARDEV=y
+CONFIG_CMD_VSERIAL=y
+CONFIG_CMD_STDIO=y
+CONFIG_CMD_HEAP=y
+CONFIG_CMD_WALLCLOCK=y
+CONFIG_CMD_MODULE=y
+CONFIG_CMD_RTCDEV=y
+CONFIG_CMD_INPUT=y
+CONFIG_CMD_BLOCKDEV=y
+CONFIG_CMD_NET=y
+
+#
+# Daemon Options
+#
+CONFIG_MTERM=y
+CONFIG_MTERM_CMD_WIDTH=256
+CONFIG_MTERM_HISTORY=y
+CONFIG_MTERM_HISTORY_SIZE=10
+
+#
+# Library Options
+#
+
+#
+# Network Stack Options
+#
+# CONFIG_NET_STACK is not set
+CONFIG_NET_STACK_LWIP=y
+
+#
+# Virtual FileSystem Options
+#
+# CONFIG_VFS is not set
+
+#
+# Device Drivers
+#
+
+#
+# Serial Port Drivers
+#
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_8250_UART is not set
+# CONFIG_SERIAL_OMAP_UART is not set
+CONFIG_SERIAL_PL01X=y
+# CONFIG_SERIAL_SAMSUNG is not set
+# CONFIG_SERIAL_IMX is not set
+
+#
+# RTC Drivers
+#
+# CONFIG_RTC_PL031 is not set
+# CONFIG_RTC_S3C is not set
+
+#
+# Block Drivers
+#
+# CONFIG_BLOCK_RBD is not set
+
+#
+# MMC/SD/SDIO drivers
+#
+# CONFIG_MMC is not set
+
+#
+# USB drivers
+#
+# CONFIG_USB is not set
+
+#
+# Input Device Support
+#
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+
+#
+# Network Drivers
+#
+CONFIG_NET_DRIVERS=y
+# CONFIG_ETHER_SMSC_911x is not set
+CONFIG_ETHER_SMSC_91x=y
+
+#
+# Clock Drivers
+#
+# CONFIG_CLKDEV_LOOKUP is not set
+
+#
+# Device Emulators
+#
+
+#
+# VirtIO Support
+#
+CONFIG_EMU_VIRTIO=y
+CONFIG_EMU_VIRTIO_MMIO=y
+
+#
+# System Emulators
+#
+CONFIG_EMU_SYS=y
+CONFIG_EMU_SYS_ARM_SYSREGS=y
+CONFIG_EMU_SYS_SP810=y
+
+#
+# PIC Emulators
+#
+CONFIG_EMU_PIC=y
+CONFIG_EMU_PIC_GIC=y
+CONFIG_EMU_PIC_PL190=y
+
+#
+# Network Interface Controller Emulators
+#
+CONFIG_EMU_NET=y
+CONFIG_EMU_NET_LAN9118=y
+CONFIG_EMU_NET_SMC91C111=y
+CONFIG_EMU_NET_VIRTIO=y
+
+#
+# Block Device Emulators
+#
+CONFIG_EMU_BLOCK=y
+CONFIG_EMU_BLOCK_VIRTIO=y
+
+#
+# Console Emulators
+#
+CONFIG_EMU_CONSOLE=y
+CONFIG_EMU_CONSOLE_VIRTIO=y
+
+#
+# Timer Emulators
+#
+CONFIG_EMU_TIMER=y
+CONFIG_EMU_TIMER_SP804=y
+CONFIG_EMU_TIMER_ARM_MPTIMER=y
+
+#
+# Serial Port Emulators
+#
+CONFIG_EMU_SERIAL=y
+CONFIG_EMU_SERIAL_PL011=y
+
+#
+# Real-Time Clock Emulators
+#
+CONFIG_EMU_RTC=y
+CONFIG_EMU_RTC_PL031=y
+
+#
+# Cache Controller Emulators
+#
+CONFIG_EMU_CACHE_L2X0=y
+
+#
+# GPIO Emulators
+#
+CONFIG_EMU_GPIO=y
+CONFIG_EMU_GPIO_PL061=y
+
+#
+# Miscellaneous Emulators
+#
+CONFIG_EMU_MISC_ZERO=y
+CONFIG_EMU_MISC_ARM11MPCORE=y
+CONFIG_EMU_MISC_A9MPCORE=y
+
+#
+# Tool Options
+#
+# CONFIG_CPATCH is not set
+# CONFIG_BBFLASH is not set
--
1.7.9.5

Sukanto Ghosh

unread,

Sep 15, 2013, 4:08:47 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

This patch adds light-weight and minimalistic bootwrapper assembly
source for booting Xvisor on ARMv8 foundation models.

In simpler words, it is a minimalistic bootloader for launching
Xvisor on ARMv8 foundation model.

Signed-off-by: Sukanto Ghosh <sukant...@gmail.com>
---

docs/arm/foundation_v8_boot.S | 176 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 176 insertions(+)
create mode 100644 docs/arm/foundation_v8_boot.S

diff --git a/docs/arm/foundation_v8_boot.S b/docs/arm/foundation_v8_boot.S
new file mode 100644
index 0000000..0cadc37
--- /dev/null
+++ b/docs/arm/foundation_v8_boot.S
@@ -0,0 +1,176 @@

+ * @file foundation_v8_boot.S

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief light-weight boot-wrapper for ARMv8 foundation models
+ */
+
+#define PSR_MODE64_EL3 0x0000000c
+#define PSR_MODE64_EL2h 0x00000009
+#define PSR_MODE64_MASK 0x0000001f

+#define PSR_FIQ_DISABLED (1 << 6)
+#define PSR_IRQ_DISABLED (1 << 7)
+#define PSR_ASYNC_ABORT_DISABLED (1 << 8)
+#define PSR_MODE64_DEBUG_DISABLED (1 << 9)
+

+ /* Boot-wrapper entry point */
+ .section .text, "ax", %progbits
+ .globl _start
+_start:
+ /* Assume EL2 mode if not in EL3 mode */
+ mrs x0, CurrentEL
+ cmp x0, #PSR_MODE64_EL3
+ b.ne _start_el2
+
+ /* Setup EL3 security control register */
+ mov x0, #0x30 /* RES1 */
+ orr x0, x0, #(1 << 0) /* Non-secure EL1 */
+ orr x0, x0, #(1 << 8) /* HVC enable */
+ orr x0, x0, #(1 << 10) /* 64-bit EL2 */
+ msr scr_el3, x0
+
+ /* Disable copro. traps to EL3 */
+ msr cptr_el3, xzr
+
+ /* Setup generic timer cntfrq */
+ ldr x0, __gentimer_freq
+ msr cntfrq_el0, x0
+
+ /* GIC Distributor Interface Init */
+ mrs x4, mpidr_el1
+ and x4, x4, #0xffff /* CPU number */
+__gic_dist_init:
+ ldr x0, __gic_dist_base /* Dist GIC base */
+ mov x1, #0 /* non-0 cpus should at least */
+ cmp x4, xzr /* program IGROUP0 */
+ bne 1f
+ mov x1, #3 /* Enable group0 & group1 */
+ str w1, [x0, #0x00] /* Ctrl Register */
+ ldr w1, [x0, #0x04] /* Type Register */
+1: and x1, x1, #0x1f /* No. of IGROUPn registers */
+ add x2, x0, #0x080 /* IGROUP0 Register */
+ movn x3, #0 /* All interrupts to group-1 */
+2: str w3, [x2], #4
+ subs x1, x1, #1
+ bge 2b
+
+__gic_cpu_init:
+ /* GIC Secured CPU Interface Init */
+ ldr x0, __gic_cpu_base /* GIC CPU base */
+ mov x1, #0x80
+ str w1, [x0, #0x4] /* GIC CPU Priority Mask */
+ mov x1, #0x3 /* Enable group0 & group1 */
+ str w1, [x0] /* GIC CPU Control */
+
+ /* Clear EL2 control register */
+ msr sctlr_el2, xzr
+
+ /* Prepare the switch to EL2 mode from EL3 mode */
+ ldr x0, __start_el2 /* Return after mode switch */
+ mov x1, #0x3c9 /* EL2_SP1 | D | A | I | F */
+ msr elr_el3, x0
+ msr spsr_el3, x1
+ eret
+
+ .align 3
+__gentimer_freq:
+ .dword GENTIMER_FREQ
+__gic_dist_base:
+ .dword GIC_DIST_BASE
+__gic_cpu_base:
+ .dword GIC_CPU_BASE
+__start_el2:
+ .dword _start_el2
+
+_start_el2:
+ /* Skip secondary loop for Primary core */
+ mrs x4, mpidr_el1
+ ands x4, x4, #0xffff
+ beq __secondary_spin_skip
+
+ /* Copy the secondary_spin(start, end) to SPIN_LOOP_ADDR */
+ adr x0, __secondary_spin_code_start
+ adr x1, __secondary_spin_code_end
+ ldr x2, __secondary_spin_loc
+
+1: ldr x4, [x0], #8
+ str x4, [x2], #8
+ cmp x1, x0
+ bge 1b
+ adr x3, __secondary_spin
+ sub x3, x3, x0
+ add x3, x3, x2
+ br x3
+
+ .align 3
+__secondary_spin_code_start:
+ .dword 0x0
+__secondary_spin_loc:
+ .dword SPIN_LOOP_ADDR
+__leds_base:
+ .dword 0x1c010008
+#ifdef DTB
+__dtb_addr:
+ .dword dtb
+#endif
+
+__secondary_spin:
+ ldr x0, __secondary_spin_loc
+ sevl
+1: wfe
+ ldr x1, [x0]
+ cmp x1, xzr
+ beq 1b
+
+ ldr x15, __leds_base
+ mov w14, #1

+ str w14, [x15]
+

+ br x1
+__secondary_spin_code_end:
+
+__secondary_spin_skip:
+#ifdef DTB
+ /* if dtb provided load the address where we placed it */
+ ldr x0, __dtb_addr
+#else
+ /* deliberately put a non-8B aligned value to x0 skip dtb checking */
+ mov x0, #1
+#endif
+ /* Jump to input binary */
+ b input_bin
+
+#define str(s) #s
+#define stringify(s) str(s)
+
+ .section .text, "ax", %progbits
+#ifdef DTB
+ /* DTB binary */
+ .globl dtb
+ .balign 0x1000
+dtb:
+ .incbin stringify(DTB)
+#endif
+ /* Input binary containing OS images */
+ .globl input_bin
+ .balign 0x10000
+input_bin:
+ .incbin stringify(IMAGE)
+ .globl input_bin_end
+input_bin_end:
--
1.7.9.5

Sukanto Ghosh

unread,

Sep 15, 2013, 4:08:48 AM9/15/13

to an...@brainfault.org, Sukanto Ghosh, xvisor...@googlegroups.com

We need a Xvisor friendly firmware/bootloader for Virt-v8 guest which
will help us launch Guest OSes on Virt-v8 guest and also help us do
some testing of virtual CPU emulated by Xvisor ARM64.

This patch adds arm64 basic firmware for Virt-v8 Guest which is very
similar to arm32 basic firmware for VExpress-A15 Guest. This firmware
is capable of booting upstream arm64 linux kernel.

Signed-off-by: Sukanto Ghosh <sukant...@gmail.com>
---

64 files changed, 13905 insertions(+)

diff --git a/tests/arm64/common/README b/tests/arm64/common/README
new file mode 100644
index 0000000..c6f8f0d
--- /dev/null
+++ b/tests/arm64/common/README
@@ -0,0 +1,9 @@
+ ARM64 common code
+
+This directory contains directories:
+
+ 1. busybox - Busybox based root filesystem for all ARM64 systems
+ 2. basic - Common code for the basic firmware
+
+Please follow the README under specific platform directory for detailed
+steps to configure, compile and run.
diff --git a/tests/arm64/common/basic/Makefile.inc b/tests/arm64/common/basic/Makefile.inc
new file mode 100644
index 0000000..c54e880
--- /dev/null
+++ b/tests/arm64/common/basic/Makefile.inc
@@ -0,0 +1,134 @@

+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# @file Makefile.inc

+# @author Sukanto Ghosh (sukant...@gmail.com)

+# @brief common makefile to build basic firmware
+# */
+
+# Include top-level configuration file if present
+-include $(build_dir)/.config
+
+ifdef CROSS_COMPILE
+FW_CROSS_COMPILE=$(CROSS_COMPILE)
+else
+FW_CROSS_COMPILE=aarch64-none-linux-gnu-
+endif
+FW_CPPFLAGS=-I. -I$(common_dir) -DTEXT_START=$(board_text_start)
+FW_CFLAGS=$(FW_CPPFLAGS) -g -Wall -Werror -nostdlib -mgeneral-regs-only -mlittle-endian
+FW_ASFLAGS=$(FW_CPPFLAGS) -g -Wall -Werror -nostdlib -mgeneral-regs-only -mlittle-endian -D__ASSEMBLY__
+FW_LDFLAGS=$(FW_CFLAGS) -Wl,--build-id=none
+FW_AS=$(FW_CROSS_COMPILE)gcc
+FW_CC=$(FW_CROSS_COMPILE)gcc
+FW_CPP=$(FW_CROSS_COMPILE)cpp
+FW_OBJCOPY=$(FW_CROSS_COMPILE)objcopy
+
+FIRMWARE_OBJS=$(obj_dir)/arm_entry.o \
+ $(obj_dir)/arm_mmu.o
+
+FIRMWARE_OBJS+=$(board_objs)
+
+FIRMWARE_OBJS+=$(obj_dir)/arm_main.o \
+ $(obj_dir)/arm_heap.o \
+ $(obj_dir)/arm_irq.o \
+ $(obj_dir)/arm_stdio.o \
+ $(obj_dir)/arm_string.o \
+ $(obj_dir)/dhry_1.o \
+ $(obj_dir)/dhry_2.o \
+ $(obj_dir)/dhry_port.o \
+ $(obj_dir)/libfdt/fdt.o \
+ $(obj_dir)/libfdt/fdt_ro.o \
+ $(obj_dir)/libfdt/fdt_rw.o \
+ $(obj_dir)/libfdt/fdt_strerror.o \
+ $(obj_dir)/libfdt/fdt_support.o \
+ $(obj_dir)/libfdt/fdt_sw.o \
+ $(obj_dir)/libfdt/fdt_wip.o
+
+FIRMWARE_CPPFLAGS=-DFIRMWARE_BOOT
+FIRMWARE_CFLAGS=$(FIRMWARE_CPPFLAGS)
+FIRMWARE_ASFLAGS=$(FIRMWARE_CPPFLAGS)
+FIRMWARE_LINK_SCRIPT=$(obj_dir)/firmware.lnk
+FIRMWARE_LDFLAGS=-Wl,-T$(FIRMWARE_LINK_SCRIPT) $(FIRMWARE_CPPFLAGS)
+
+FIRMWARE_COMMON_DEPS=$(common_dir)/arm_asm_macro.h \
+ $(common_dir)/arm_math.h \
+ $(common_dir)/arm_defines.h \
+ $(common_dir)/arm_types.h \
+ $(common_dir)/arm_board.h \
+ $(common_dir)/arm_heap.h \
+ $(common_dir)/arm_inline_asm.h \
+ $(common_dir)/arm_io.h \
+ $(common_dir)/arm_irq.h \
+ $(common_dir)/arm_mmu.h \
+ $(common_dir)/arm_stdio.h \
+ $(common_dir)/arm_string.h \
+ $(common_dir)/libfdt/fdt.h \
+ $(common_dir)/libfdt/fdt_support.h \
+ $(common_dir)/libfdt/libfdt.h \
+ $(common_dir)/libfdt/libfdt_env.h \
+ $(common_dir)/libfdt/libfdt_internal.h
+
+FIRMWARE_TARGETS = $(obj_dir)/firmware.bin
+
+.PHONY: all
+all: $(FIRMWARE_TARGETS)
+
+$(obj_dir)/firmware.bin: $(obj_dir)/firmware.elf
+ @mkdir -p `dirname $@`
+ @echo " (OBJCOPY) $(subst $(obj_dir)/,,$@)"
+ @$(FW_OBJCOPY) -O binary $< $@
+
+$(obj_dir)/firmware.elf: $(FIRMWARE_OBJS) $(FIRMWARE_LINK_SCRIPT)
+ @mkdir -p `dirname $@`
+ @echo " (LD) $(subst $(obj_dir)/,,$@)"
+ @$(FW_CC) $(FIRMWARE_OBJS) $(FW_LDFLAGS) $(FIRMWARE_LDFLAGS) -o $@
+
+$(obj_dir)/%.lnk: $(common_dir)/%.ld
+ @mkdir -p `dirname $@`
+ @echo " (CPP) $(subst $(obj_dir)/,,$@)"
+ @$(FW_CPP) $(FW_CPPFLAGS) $(FIRMWARE_CPPFLAGS) $< | grep -v "\#" > $@
+
+$(obj_dir)/%.o: %.c $(FIRMWARE_COMMON_DEPS)
+ @mkdir -p `dirname $@`
+ @echo " (CC) $(subst $(obj_dir)/,,$@)"
+ @$(FW_CC) $(FW_CFLAGS) $(FIRMWARE_CFLAGS) -c $< -o $@
+
+$(obj_dir)/%.o: $(common_dir)/%.c $(FIRMWARE_COMMON_DEPS)
+ @mkdir -p `dirname $@`
+ @echo " (CC) $(subst $(obj_dir)/,,$@)"
+ @$(FW_CC) $(FW_CFLAGS) $(FIRMWARE_CFLAGS) -c $< -o $@
+
+$(obj_dir)/%.o: %.S $(FIRMWARE_COMMON_DEPS)
+ @mkdir -p `dirname $@`
+ @echo " (AS) $(subst $(obj_dir)/,,$@)"
+ @$(FW_AS) $(FW_ASFLAGS) $(FIRMWARE_ASFLAGS) -c $< -o $@
+
+$(obj_dir)/%.o: $(common_dir)/%.S $(FIRMWARE_COMMON_DEPS)
+ @mkdir -p `dirname $@`
+ @echo " (AS) $(subst $(obj_dir)/,,$@)"
+ @$(FW_AS) $(FW_ASFLAGS) $(FIRMWARE_ASFLAGS) -c $< -o $@
+
+.PHONY: clean
+clean:
+ @echo " (RM) firmware.elf*"
+ @rm -f $(obj_dir)/firmware.elf*
+ @echo " (RM) firmware.bin*"
+ @rm -f $(obj_dir)/firmware.bin*
+ @echo " (RM) $(obj_dir)"
+ @rm -rf $(obj_dir)
+
diff --git a/tests/arm64/common/basic/README b/tests/arm64/common/basic/README
new file mode 100644
index 0000000..70e5ee4
--- /dev/null
+++ b/tests/arm64/common/basic/README
@@ -0,0 +1,5 @@
+ Common basic firmware code
+
+This directory contains souce code files that are common to all boards and
+arm64 processors.
+
diff --git a/tests/arm64/common/basic/arm_asm_macro.h b/tests/arm64/common/basic/arm_asm_macro.h
new file mode 100644
index 0000000..4ab7955
--- /dev/null
+++ b/tests/arm64/common/basic/arm_asm_macro.h
@@ -0,0 +1,139 @@
+/**
+ * Copyright (c) 2010 Sukanto Ghosh.

+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *

+ * @file arm_asm_macros.h

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief common assembly macros for ARM test code
+ */
+#ifndef __ARM_ASM_MACRO_H__
+#define __ARM_ASM_MACRO_H__
+
+#include <arm_defines.h>
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Register aliases.
+ */
+lr .req x30 /* link register */
+
+#define ENTRY(name) \
+ .globl name; \
+ .align 4; \
+ name:
+
+#define END(name) \
+ .size name, .-name

+ mrs x22, elr_el1
+ mrs x23, spsr_el1
+ stp lr, x21, [sp, #0xF0]

+ stp x22, x23, [sp, #0x100]
+ /*
+ * Registers that may be useful after this macro is invoked:
+ *
+ * x21 - aborted SP
+ * x22 - aborted PC
+ * x23 - aborted PSTATE
+ */
+.endm
+
+/* Call C function to handle exception */
+.macro CALL_EXCEPTION_CFUNC cfunc
+ mov x0, sp
+ bl \cfunc
+.endm
+
+/* Pull registers from stack */
+.macro PULL_REGS
+ ldp x21, x22, [sp, #0x100] /* load ELR, SPSR */

+ msr elr_el1, x21
+ msr spsr_el1, x22

+ pop x0, x1
+ pop x2, x3
+ pop x4, x5
+ pop x6, x7
+ pop x8, x9
+ pop x10, x11
+ pop x12, x13
+ pop x14, x15
+ pop x16, x17
+ pop x18, x19
+ pop x20, x21
+ pop x22, x23
+ pop x24, x25
+ pop x26, x27
+ pop x28, x29

+ msr tpidr_el1, x24
+ ldp lr, x24, [sp]
+ mov sp, x24
+ mrs x24, tpidr_el1
+ eret
+.endm
+
+/*

+ * Exception vectors.
+ */
+.macro ventry label
+ .align 7
+ b \label
+.endm
+
+

+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/tests/arm64/common/basic/arm_board.h b/tests/arm64/common/basic/arm_board.h
new file mode 100644
index 0000000..b0dac5f
--- /dev/null
+++ b/tests/arm64/common/basic/arm_board.h
@@ -0,0 +1,60 @@
+/**
+ * Copyright (c) 2012 Jean-Christophe Dubois.

+ * @file arm_board.h
+ * @author Jean-Christophe Dubois (j...@tribudubois.net)
+ * @brief ARM Platform misc functions Header
+ */
+#ifndef _ARM_BOARD_H__
+#define _ARM_BOARD_H__
+
+#include <arm_types.h>
+
+void arm_board_reset(void);
+void arm_board_init(void);
+char *arm_board_name(void);
+physical_addr_t arm_board_ram_start(void);
+physical_size_t arm_board_ram_size(void);
+physical_addr_t arm_board_flash_addr(void);
+u32 arm_board_linux_machine_type(void);
+void arm_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz);
+
+u32 arm_board_iosection_count(void);
+physical_addr_t arm_board_iosection_addr(int num);
+
+u32 arm_board_pic_nr_irqs(void);
+int arm_board_pic_init(void);
+u32 arm_board_pic_active_irq(void);
+int arm_board_pic_ack_irq(u32 irq);
+int arm_board_pic_eoi_irq(u32 irq);
+int arm_board_pic_mask(u32 irq);
+int arm_board_pic_unmask(u32 irq);
+
+void arm_board_timer_enable(void);
+void arm_board_timer_disable(void);
+u64 arm_board_timer_irqcount(void);
+u64 arm_board_timer_irqdelay(void);
+u64 arm_board_timer_timestamp(void);
+void arm_board_timer_change_period(u32 usecs);
+int arm_board_timer_init(u32 usecs);
+
+int arm_board_serial_init(void);
+void arm_board_serial_putc(char ch);
+char arm_board_serial_getc(void);
+
+#endif
diff --git a/tests/arm64/common/basic/arm_defines.h b/tests/arm64/common/basic/arm_defines.h
new file mode 100644
index 0000000..4084e0a
--- /dev/null
+++ b/tests/arm64/common/basic/arm_defines.h
@@ -0,0 +1,312 @@
+/**
+ * Copyright (c) 2010 Anup Patel.

+ * @file arm_defines.h

+ * @author Anup Patel (an...@brainfault.org)

+ * @brief register related macros & defines for ARM test code
+ */
+#ifndef __ARM_DEFINES_H__
+#define __ARM_DEFINES_H__

+
+/* Interrupt or Exception related macros & defines */

+#define EXC_SVC_SYNC_SP0 0
+#define EXC_SVC_IRQ_SP0 1
+#define EXC_SVC_FIQ_SP0 2
+#define EXC_SVC_SERROR_SP0 3
+#define EXC_SVC_SYNC_SPx 4
+#define EXC_SVC_IRQ_SPx 5
+#define EXC_SVC_FIQ_SPx 6
+#define EXC_SVC_SERROR_SPx 7
+#define EXC_USR_SYNC_A64 8
+#define EXC_USR_IRQ_A64 9
+#define EXC_USR_FIQ_A64 10
+#define EXC_USR_SERROR_A64 11
+#define EXC_USR_SYNC_A32 12
+#define EXC_USR_IRQ_A32 13
+#define EXC_USR_FIQ_A32 14
+#define EXC_USR_SERROR_A32 15

+
+/* PSR related macros & defines */

+#define PSR_EL_MASK 0x0000000C
+#define PSR_EL_0 0x00000000
+#define PSR_EL_1 0x00000004
+#define PSR_EL_2 0x00000008
+#define PSR_EL_3 0x0000000C

+#define PSR_MODE_MASK 0x0000000f
+#define PSR_MODE_EL0t 0x00000000
+#define PSR_MODE_EL1t 0x00000004
+#define PSR_MODE_EL1h 0x00000005
+#define PSR_MODE_EL2t 0x00000008
+#define PSR_MODE_EL2h 0x00000009
+#define PSR_MODE_EL3t 0x0000000c
+#define PSR_MODE_EL3h 0x0000000d
+

+#define PSR_FIQ_DISABLED (1 << 6)
+#define PSR_IRQ_DISABLED (1 << 7)
+#define PSR_ASYNC_ABORT_DISABLED (1 << 8)

+#define PSR_BE_ENABLED (1 << 9)
+
+#define PSR_COND_OVERFLOW (1 << 28)
+#define PSR_COND_CARRY (1 << 29)
+#define PSR_COND_ZERO (1 << 30)
+#define PSR_COND_NEGATIVE (1 << 31)

+
+/* SCTLR related macros & defines */
+#define SCTLR_TE_MASK 0x40000000
+#define SCTLR_AFE_MASK 0x20000000
+#define SCTLR_TRE_MASK 0x10000000
+#define SCTLR_NFI_MASK 0x08000000
+#define SCTLR_EE_MASK 0x02000000
+#define SCTLR_VE_MASK 0x01000000
+#define SCTLR_U_MASK 0x00400000
+#define SCTLR_FI_MASK 0x00200000
+#define SCTLR_HA_MASK 0x00020000
+#define SCTLR_RR_MASK 0x00004000
+#define SCTLR_V_MASK 0x00002000
+#define SCTLR_I_MASK 0x00001000
+#define SCTLR_Z_MASK 0x00000800
+#define SCTLR_SW_MASK 0x00000400
+#define SCTLR_B_MASK 0x00000080
+#define SCTLR_C_MASK 0x00000004
+#define SCTLR_A_MASK 0x00000002
+#define SCTLR_M_MASK 0x00000001
+

+/* TCR_EL1 */

+#define TCR_INITVAL 0x80800000
+#define TCR_TBI_MASK 0x00100000
+#define TCR_TBI_SHIFT 20
+#define TCR_PS_MASK 0x00070000
+#define TCR_PS_SHIFT 16
+#define TCR_TG0_MASK 0x00004000
+#define TCR_TG0_SHIFT 14
+#define TCR_SH0_MASK 0x00003000
+#define TCR_SH0_SHIFT 12
+#define TCR_ORGN0_MASK 0x00000C00
+#define TCR_ORGN0_SHIFT 10
+#define TCR_IRGN0_MASK 0x00000300
+#define TCR_IRGN0_SHIFT 8
+#define TCR_T0SZ_MASK 0x0000003f
+#define TCR_T0SZ_SHIFT 0
+

+/* MAIR_EL1 encodings */

+#define AINDEX_SO 0
+#define AINDEX_NORMAL_WT 1
+#define AINDEX_NORMAL_WB 2
+#define AINDEX_NORMAL_UC 3
+#define MAIR_INITVAL 0x0000000044FFBB00
+

+/* Translation table related macros & defines */
+#define TTBL_INITIAL_TABLE_COUNT 8
+#define TTBL_TABLE_SIZE 0x00001000
+#define TTBL_TABLE_SIZE_SHIFT 12
+#define TTBL_TABLE_ENTCNT 512
+#define TTBL_TABLE_ENTSZ 8
+#define TTBL_STAGE1 1
+#define TTBL_STAGE2 2
+#define TTBL_FIRST_LEVEL 1
+#define TTBL_LEVEL1 1
+#define TTBL_LEVEL2 2
+#define TTBL_LEVEL3 3
+#define TTBL_LAST_LEVEL 3
+/* L1 index Bit[39:30] */
+#define TTBL_L1_INDEX_MASK 0x000000FFC0000000ULL
+#define TTBL_L1_INDEX_SHIFT 30
+#define TTBL_L1_BLOCK_SIZE 0x0000000040000000ULL
+#define TTBL_L1_MAP_MASK (~(TTBL_L1_BLOCK_SIZE - 1))
+/* L2 index Bit[29:21] */
+#define TTBL_L2_INDEX_MASK 0x000000003FE00000ULL
+#define TTBL_L2_INDEX_SHIFT 21
+#define TTBL_L2_BLOCK_SIZE 0x0000000000200000ULL
+#define TTBL_L2_MAP_MASK (~(TTBL_L2_BLOCK_SIZE - 1))
+/* L3 index Bit[20:12] */
+#define TTBL_L3_INDEX_MASK 0x00000000001FF000ULL
+#define TTBL_L3_INDEX_SHIFT 12
+#define TTBL_L3_BLOCK_SIZE 0x0000000000001000ULL
+#define TTBL_L3_MAP_MASK (~(TTBL_L3_BLOCK_SIZE - 1))
+#define TTBL_UPPER_MASK 0xFFF0000000000000ULL
+#define TTBL_UPPER_SHIFT 52
+#define TTBL_OUTADDR_MASK 0x000000FFFFFFF000ULL
+#define TTBL_OUTADDR_SHIFT 12
+#define TTBL_AP_SRW_U 0x0
+#define TTBL_AP_S_URW 0x1
+#define TTBL_AP_SR_U 0x2
+#define TTBL_AP_S_UR 0x3
+#define TTBL_HAP_NOACCESS 0x0
+#define TTBL_HAP_READONLY 0x1
+#define TTBL_HAP_WRITEONLY 0x2
+#define TTBL_HAP_READWRITE 0x3
+#define TTBL_LOWER_MASK 0x0000000000000FFCULL
+#define TTBL_LOWER_SHIFT 2
+#define TTBL_TABLE_MASK 0x0000000000000002ULL
+#define TTBL_TABLE_SHIFT 1
+#define TTBL_VALID_MASK 0x0000000000000001ULL
+#define TTBL_VALID_SHIFT 0
+
+/* TTBL Stage1 Table Attributes */
+#define TTBL_STAGE1_TABLE_NS_MASK 0x8000000000000000ULL
+#define TTBL_STAGE1_TABLE_NS_SHIFT 63
+#define TTBL_STAGE1_TABLE_AP_MASK 0x6000000000000000ULL
+#define TTBL_STAGE1_TABLE_AP_SHIFT 61
+#define TTBL_STAGE1_TABLE_XN_MASK 0x1000000000000000ULL
+#define TTBL_STAGE1_TABLE_XN_SHIFT 60
+#define TTBL_STAGE1_TABLE_PXN_MASK 0x0800000000000000ULL
+#define TTBL_STAGE1_TABLE_PXN_SHIFT 59
+
+/* TTBL Stage1 Block Upper Attributes */
+#define TTBL_STAGE1_UPPER_XN_MASK 0x0040000000000000ULL
+#define TTBL_STAGE1_UPPER_XN_SHIFT 54
+#define TTBL_STAGE1_UPPER_PXN_MASK 0x0020000000000000ULL
+#define TTBL_STAGE1_UPPER_PXN_SHIFT 53
+#define TTBL_STAGE1_UPPER_CONT_MASK 0x0010000000000000ULL
+#define TTBL_STAGE1_UPPER_CONT_SHIFT 52
+
+/* TTBL Stage1 Block Lower Attributes */
+#define TTBL_STAGE1_LOWER_NG_MASK 0x0000000000000800ULL
+#define TTBL_STAGE1_LOWER_NG_SHIFT 11
+#define TTBL_STAGE1_LOWER_AF_MASK 0x0000000000000400ULL
+#define TTBL_STAGE1_LOWER_AF_SHIFT 10
+#define TTBL_STAGE1_LOWER_SH_MASK 0x0000000000000300ULL
+#define TTBL_STAGE1_LOWER_SH_SHIFT 8
+#define TTBL_STAGE1_LOWER_AP_MASK 0x00000000000000C0ULL
+#define TTBL_STAGE1_LOWER_AP_SHIFT 6
+#define TTBL_STAGE1_LOWER_NS_MASK 0x0000000000000020ULL
+#define TTBL_STAGE1_LOWER_NS_SHIFT 5
+#define TTBL_STAGE1_LOWER_AINDEX_MASK 0x000000000000001CULL
+#define TTBL_STAGE1_LOWER_AINDEX_SHIFT 2
+
+/* ESR_EL1 */

+/* WFI/WFE ISS Encodings */

+#define ISS_WFI_WFE_TRAPPED_MASK 0x00080000
+#define ISS_WFI_WFE_TRAPPED_SHIFT 19

+
+
+#endif
diff --git a/tests/arm64/common/basic/arm_entry.S b/tests/arm64/common/basic/arm_entry.S
new file mode 100644
index 0000000..c1a988d
--- /dev/null
+++ b/tests/arm64/common/basic/arm_entry.S
@@ -0,0 +1,323 @@

+ * @file arm_entry.S

+ * @author Sukanto Ghosh (sukant...@gmail.com)

+ * @brief Entry point code for basic firmware
+ */
+
+#include <arm_asm_macro.h>
+#include <gic_config.h>
+#include <arm_plat.h>
+
+ /*
+ * Basic firmware could be loaded any where in memory.
+ * The _start function ensures that it exectues from intended

+ * base address provided at compile time.

+ */

+ .section .text, "ax", %progbits
+ .globl _start
+_start:
+ /*

+ * x4 -> load start
+ * x5 -> load end
+ * x6 -> execution start
+ * x7 -> execution end

+ * x8 -> code size

+ */
+ adr x4, . /* x4 <- pc */

+ /* Disable IRQ & FIQ */
+ msr daifset, #3

+ ldr x6, __reloc_region_start
+ ldr x7, __reloc_region_end
+ sub x8, x7, x6
+ add x5, x4, x8
+
+ /* If not-running at EL1 then hang */
+ mrs x0, CurrentEL
+ cmp x0, #PSR_MODE_EL1t
+ ccmp x0, #PSR_MODE_EL1h, #0x4, ne
+ b.ne _start_hang
+
+ /* Set GIC priority mask bit [7] = 1 */
+ ldr x0, __gic_cpu_base /* CPU GIC base */
+ mov x1, #0x1
+ str w1, [x0] /* GIC CPU CTRL */
+ mov x1, #0xFF
+ str w1, [x0, #0x4] /* GIC CPU PMR */
+
+ /* Skip secondary spin for primary core */
+ mrs x0, mpidr_el1
+ ands x0, x0, #15 /* CPU number */
+ cmp x0, #0
+ b.eq primary_cpu_boot
+
+ /* Secondary spin loop */
+ ldr x0, __jump_addr
+ str xzr, [x0]
+secondary_cpu_spin:
+ ldr x1, [x0]
+ cbnz x1, secondary_cpu_jump
+ wfe
+ b secondary_cpu_spin
+secondary_cpu_jump:
+ br x1
+
+ .align 3
+__gic_cpu_base:
+ .dword GIC_CPU_BASE
+
+ .align 3
+ .global __jump_addr
+__jump_addr:
+ .dword ARM_PLAT_SPIN_ADDR
+
+ /* Primary core boot-up sequence */
+primary_cpu_boot:
+ /* Check if relocation required */
+ cmp x4, x6
+ b.eq _relocate_end
+
+ /*
+ * We need to clear the A bit in sctlr_el1
+ * for the relocate routine to work properly
+ */
+ mrs x3, sctlr_el1
+ ldr x2, __sctlr_mmu_clear

+ and x3, x3, x2

+ /* We also enable I/D caching */
+ ldr x2, __sctlr_mmu_val
+ orr x3, x3, x2
+ msr sctlr_el1, x3

+ dsb sy
+ isb
+

+ mov x0, x6 /* destination */
+ mov x1, x4 /* source */
+ mov x2, x8 /* byte count */
+ /* TODO: Handle overlaps */
+_relocate:

+ subs x2, x2, #8
+ b.mi 2f
+1: ldr x3, [x1], #8
+ subs x2, x2, #8
+ str x3, [x0], #8
+ b.pl 1b
+2: adds x2, x2, #4
+ b.mi 3f
+ ldr w3, [x1], #4
+ sub x2, x2, #4
+ str w3, [x0], #4
+3: adds x2, x2, #2
+ b.mi 4f
+ ldrh w3, [x1], #2
+ sub x2, x2, #2
+ strh w3, [x0], #2
+4: adds x2, x2, #1

+ b.mi _relocate_end

+ ldrb w3, [x1]
+ strb w3, [x0]

+_relocate_end:
+
+ ldr x0, __relocated
+ br x0
+
+_relocated:
+
+ /* Zero out bss & heap */
+ ldr x0, __zero_region_start
+ ldr x1, __zero_region_end
+1: subs x2, x1, x0
+ b.le 2f
+ str xzr, [x0]
+ add x0, x0, 8
+ b 1b
+2:
+ /* Set exception vectors */
+ adr x0, vectors
+ msr vbar_el1, x0
+ /* Set EL1 stack-pointer */
+ ldr x0, __el1_stack
+ mov sp, x0
+ /* Set EL0 stack-pointer */
+ ldr x0, __el0_stack
+ msr sp_el0, x0
+
+ bl arm_init
+ bl arm_main

+
+_start_hang:
+ b .
+

+ .align 3
+__relocated:
+ .dword _relocated
+
+ .globl _switch_to_user_mode
+_switch_to_user_mode:
+ msr tpidr_el1, x0
+ mov x0, #(PSR_FIQ_DISABLED | PSR_IRQ_DISABLED |\
+ PSR_ASYNC_ABORT_DISABLED | PSR_MODE_EL0t)
+ msr spsr_el1, x0
+ mrs x0, tpidr_el1
+ msr elr_el1, lr

+ eret
+
+ .align 3

+__sctlr_mmu_clear:
+ .dword ~(SCTLR_A_MASK)
+__sctlr_mmu_val:
+ .dword (SCTLR_C_MASK | SCTLR_I_MASK)
+__reloc_region_start:
+ .dword _reloc_region_start
+__reloc_region_end:
+ .dword _reloc_region_end
+__zero_region_start:
+ .dword _zero_region_start
+__zero_region_end:
+ .dword _zero_region_end
+
+ /*
+ * Stacks.
+ */
+__el0_stack:
+ .dword _usr_stack_end
+__el1_stack:
+ .dword _svc_stack_end
+
+
+ .align 11
+ENTRY(vectors)
+ ventry svc_sync_invalid /* Synchronous EL1t */
+ ventry svc_irq_invalid /* IRQ EL1t */
+ ventry svc_fiq_invalid /* FIQ EL1t */
+ ventry svc_error_invalid /* Error EL1t */
+
+ ventry svc_sync /* Synchronous EL1h */
+ ventry svc_irq /* IRQ EL1h */
+ ventry svc_fiq_invalid /* FIQ EL1h */
+ ventry svc_error_invalid /* Error EL1h */
+
+ ventry usr_sync_a64 /* Synchronous 64-bit EL0 */
+ ventry usr_irq_a64 /* IRQ 64-bit EL0 */
+ ventry usr_fiq_a64 /* FIQ 64-bit EL0 */
+ ventry usr_error_a64 /* Error 64-bit EL0 */
+
+ ventry usr_sync_a32 /* Synchronous 32-bit EL0 */
+ ventry usr_irq_a32 /* IRQ 32-bit EL0 */
+ ventry usr_fiq_a32 /* FIQ 32-bit EL0 */
+ ventry usr_error_a32 /* Error 32-bit EL0 */
+END(vectors)
+
+EXCEPTION_HANDLER svc_sync_invalid
+ PUSH_REGS
+ mov x1, EXC_SVC_SYNC_SP0