RISC-V hypervisor exception stack

[Oleksii Kurochko]

Hello,

I want to ask about the setup of the hypervisor exception stack.
According to the following code, sp points to the top of
_hvc_stack_end after allocated pieces for CONFIG_IRQ_STACK and
RISCV_SCRATCH:
/* Setup scratch space */
la a6, __hvc_stack_end
REG_L a5, (a6)
#ifdef CONFIG_SMP
li a4, CONFIG_IRQ_STACK_SIZE
la a6, __start_secondary_smp_id
REG_L a0, (a6)
REG_L a0, (a0)
mul a4, a4, a0
#else
li a4, 0
#endif
sub a5, a5, a4
li a3, RISCV_SCRATCH_SIZE
sub a5, a5, a3
csrw CSR_SSCRATCH, a5

/* Setup Hypervisor Exception Stack */
csrr tp, CSR_SSCRATCH
REG_S tp, RISCV_SCRATCH_EXCE_STACK_OFFSET(tp)
add sp, tp, zero

But SP can be changed by functions called after sp is initialized.
Thereby when an exception occurs SP will be reinitialized to the value
in RISCV_SCRATCH_EXCE_STACK_OFFSET:
REG_L sp, RISCV_SCRATCH_EXCE_STACK_OFFSET(tp)
addi sp, sp, -(RISCV_ARCH_REGS_SIZE)

Wouldn't it corrupt the stack that was before the exception occurred?

I mean that before an exception occurred the stack looked as follows:
------------------------------
RISCV_SCRATCH
------------------------------ RISCV_SCRATCH_EXCE_STACK_OFFSET
AAAAAAA
BBBBBBB
CCCCCCC
------------------------------ CURRENT_SP is here
.....
-------------------------------
Then when an exception occurs we move CURRENT_SP to
RISCV_SCRATCH_EXCE_STACK_OFFSET and overwrite AAAAAAA BBBBBBB CCCCCCC


~ Oleksii