[PATCH 0/3] Xvisor Smstateen support

[Anup Patel]

This series adds Smstateen support to Xvisor so that Xvisor can
configure Smstateen CSR for Guest whenever available.

These patches can also be found in the riscv_smstateen_v1 branch
at: https://github.com/avpatel/xvisor-next.git

Anup Patel (3):
RISC-V: Parse Smstateen extension from ISA string
RISC-V: Add Smstateen related CSR defines
RISC-V: Configure Smstateen extension for Guest

arch/riscv/cpu/generic/cpu_init.c | 2 ++
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 31 +++++++++++++++++++
arch/riscv/cpu/generic/cpu_vcpu_nested.c | 3 ++
arch/riscv/cpu/generic/include/arch_regs.h | 3 ++
arch/riscv/cpu/generic/include/cpu_hwcap.h | 1 +
.../cpu/generic/include/cpu_vcpu_helper.h | 3 ++
.../cpu/generic/include/riscv_encoding.h | 19 ++++++++++++
7 files changed, 62 insertions(+)

--
2.43.0

[Anup Patel]

Update ISA string parsing for Smstateen extension.

Signed-off-by: Anup Patel <apa...@ventanamicro.com>
---
arch/riscv/cpu/generic/cpu_init.c | 2 ++
arch/riscv/cpu/generic/include/cpu_hwcap.h | 1 +
2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu/generic/cpu_init.c b/arch/riscv/cpu/generic/cpu_init.c
index deeb610c..c2f5f201 100644
--- a/arch/riscv/cpu/generic/cpu_init.c
+++ b/arch/riscv/cpu/generic/cpu_init.c
@@ -114,6 +114,7 @@ int riscv_isa_populate_string(unsigned long xlen,
} while (false) \

SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN);
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
#undef SET_ISA_EXT_MAP
@@ -198,6 +199,7 @@ int riscv_isa_parse_string(const char *isa,
} while (false) \

SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN);
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
#undef SET_ISA_EXT_MAP
diff --git a/arch/riscv/cpu/generic/include/cpu_hwcap.h b/arch/riscv/cpu/generic/include/cpu_hwcap.h
index ab13f674..83450c23 100644
--- a/arch/riscv/cpu/generic/include/cpu_hwcap.h
+++ b/arch/riscv/cpu/generic/include/cpu_hwcap.h
@@ -58,6 +58,7 @@ enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSAIA = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SMAIA,
RISCV_ISA_EXT_SSTC,
+ RISCV_ISA_EXT_SMSTATEEN,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};

--
2.43.0

[Anup Patel]

Lets add Smstateen related CSR defines so that Xvisor context
switch can use it to program these CSRs.

Signed-off-by: Anup Patel <apa...@ventanamicro.com>
---

.../cpu/generic/include/riscv_encoding.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/riscv/cpu/generic/include/riscv_encoding.h b/arch/riscv/cpu/generic/include/riscv_encoding.h
index b3753e19..29fcbf28 100644
--- a/arch/riscv/cpu/generic/include/riscv_encoding.h
+++ b/arch/riscv/cpu/generic/include/riscv_encoding.h
@@ -374,6 +374,18 @@
#define ENVCFGH_STCE (_AC(1, UL) << 31)
#define ENVCFGH_PBMTE (_AC(1, UL) << 30)

+/* Smstateen bits */
+#define SMSTATEEN0_AIA_IMSIC_SHIFT 58
+#define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT 59
+#define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_CSRIND_SHIFT 60
+#define SMSTATEEN0_CSRIND (_ULL(1) << SMSTATEEN0_CSRIND_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT 62
+#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN0_SSTATEEN0_SHIFT 63
+#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+
/* ===== User-level CSRs ===== */

/* User Trap Setup (N-extension) */
@@ -494,6 +506,9 @@
/* Supervisor Configuration */
#define CSR_SENVCFG 0x10a

+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0 0x10c
+
/* Counter Overflow CSR */
#define CSR_SCOUNTOVF 0xda0

@@ -529,6 +544,10 @@
#define CSR_HENVCFG 0x60a
#define CSR_HENVCFGH 0x61a

+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0 0x60c
+#define CSR_HSTATEEN0H 0x61c
+
/* Virtual Supervisor Registers (H-extension) */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
--
2.43.0

[Anup Patel]

Smstateen extension must be configure for Guest whenever it is
available otherwise Guest will not access to HENVCFG CSR.

Signed-off-by: Anup Patel <apa...@ventanamicro.com>
---

arch/riscv/cpu/generic/cpu_vcpu_helper.c | 31 +++++++++++++++++++
arch/riscv/cpu/generic/cpu_vcpu_nested.c | 3 ++
arch/riscv/cpu/generic/include/arch_regs.h | 3 ++

.../cpu/generic/include/cpu_vcpu_helper.h | 3 ++
4 files changed, 40 insertions(+)

diff --git a/arch/riscv/cpu/generic/cpu_vcpu_helper.c b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
index eecda785..c3141dba 100644
--- a/arch/riscv/cpu/generic/cpu_vcpu_helper.c
+++ b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
@@ -326,6 +326,16 @@ int arch_vcpu_init(struct vmm_vcpu *vcpu)
/* By default, make CY, TM, and IR counters accessible in VU mode */
riscv_priv(vcpu)->scounteren = 7;

+ /* Initialize stateen configuration */
+ riscv_priv(vcpu)->hstateen0 = SMSTATEEN0_HSENVCFG;
+ if (riscv_isa_extension_available(riscv_priv(vcpu)->isa, SMSTATEEN))
+ riscv_priv(vcpu)->hstateen0 |= SMSTATEEN0_SSTATEEN0;
+ if (riscv_isa_extension_available(riscv_priv(vcpu)->isa, SSAIA)) {
+ riscv_priv(vcpu)->hstateen0 |= SMSTATEEN0_CSRIND;
+ riscv_priv(vcpu)->hstateen0 |= SMSTATEEN0_AIA;
+ riscv_priv(vcpu)->hstateen0 |= SMSTATEEN0_AIA_IMSIC;
+ }
+
/* Reset nested state */
cpu_vcpu_nested_reset(vcpu);

@@ -413,6 +423,8 @@ void arch_vcpu_switch(struct vmm_vcpu *tvcpu,
priv->vstval = csr_read(CSR_VSTVAL);
priv->vsatp = csr_read(CSR_VSATP);
priv->scounteren = csr_read(CSR_SCOUNTEREN);
+ if (riscv_isa_extension_available(priv->isa, SMSTATEEN))
+ priv->sstateen0 = csr_read(CSR_SSTATEEN0);
cpu_vcpu_fp_save(tvcpu, regs);
cpu_vcpu_timer_save(tvcpu);
}
@@ -432,6 +444,9 @@ void arch_vcpu_switch(struct vmm_vcpu *tvcpu,
csr_write(CSR_VSTVAL, priv->vstval);
csr_write(CSR_VSATP, priv->vsatp);
csr_write(CSR_SCOUNTEREN, priv->scounteren);
+ if (riscv_isa_extension_available(priv->isa, SMSTATEEN))
+ csr_write(CSR_SSTATEEN0, priv->sstateen0);
+ cpu_vcpu_stateen_update(vcpu, riscv_nested_virt(vcpu));
cpu_vcpu_envcfg_update(vcpu, riscv_nested_virt(vcpu));
cpu_vcpu_timer_restore(vcpu);
cpu_vcpu_fp_restore(vcpu, regs);
@@ -448,6 +463,22 @@ void arch_vcpu_post_switch(struct vmm_vcpu *vcpu,
/* For now nothing to do here. */
}

+void cpu_vcpu_stateen_update(struct vmm_vcpu *vcpu, bool nested_virt)
+{
+ u64 hstateen0;
+
+ if (!riscv_isa_extension_available(NULL, SMSTATEEN))
+ return;
+
+ hstateen0 = (nested_virt) ? 0 : riscv_priv(vcpu)->hstateen0;
+#ifdef CONFIG_32BIT
+ csr_write(CSR_HSTATEEN0, (u32)hstateen0);
+ csr_write(CSR_HSTATEEN0H, (u32)(hstateen0 >> 32));
+#else
+ csr_write(CSR_HSTATEEN0, hstateen0);
+#endif
+}
+
void cpu_vcpu_envcfg_update(struct vmm_vcpu *vcpu, bool nested_virt)
{
u64 henvcfg = (nested_virt) ? 0 : riscv_priv(vcpu)->henvcfg;
diff --git a/arch/riscv/cpu/generic/cpu_vcpu_nested.c b/arch/riscv/cpu/generic/cpu_vcpu_nested.c
index 12db30b1..6c08fd25 100644
--- a/arch/riscv/cpu/generic/cpu_vcpu_nested.c
+++ b/arch/riscv/cpu/generic/cpu_vcpu_nested.c
@@ -1980,6 +1980,9 @@ void cpu_vcpu_nested_set_virt(struct vmm_vcpu *vcpu, struct arch_regs *regs,
npriv->hcounteren = csr_swap(CSR_HCOUNTEREN, npriv->hcounteren);
npriv->hedeleg = csr_swap(CSR_HEDELEG, npriv->hedeleg);

+ /* Update stateen configuration */
+ cpu_vcpu_stateen_update(vcpu, virt);
+
/* Update environment configuration */
cpu_vcpu_envcfg_update(vcpu, virt);

diff --git a/arch/riscv/cpu/generic/include/arch_regs.h b/arch/riscv/cpu/generic/include/arch_regs.h
index 3e0d8ceb..a4046225 100644
--- a/arch/riscv/cpu/generic/include/arch_regs.h
+++ b/arch/riscv/cpu/generic/include/arch_regs.h
@@ -229,6 +229,9 @@ struct riscv_priv {
unsigned long vstval;
unsigned long vsatp;
unsigned long scounteren;
+ /* Sstateen state */
+ u64 hstateen0;
+ unsigned long sstateen0;
/* Nested state */
struct riscv_priv_nested nested;
/* FP state */
diff --git a/arch/riscv/cpu/generic/include/cpu_vcpu_helper.h b/arch/riscv/cpu/generic/include/cpu_vcpu_helper.h
index 1c2f49d1..76cd02c1 100644
--- a/arch/riscv/cpu/generic/include/cpu_vcpu_helper.h
+++ b/arch/riscv/cpu/generic/include/cpu_vcpu_helper.h
@@ -26,6 +26,9 @@
#include <vmm_types.h>
#include <vmm_manager.h>

+/** Function to update stateen configuration */
+void cpu_vcpu_stateen_update(struct vmm_vcpu *vcpu, bool nested_virt);
+
/** Function to update environment configuration */
void cpu_vcpu_envcfg_update(struct vmm_vcpu *vcpu, bool nested_virt);

--
2.43.0

[Anup Patel]

On Wed, Dec 18, 2024 at 9:04 AM Anup Patel <apa...@ventanamicro.com> wrote:
>
> This series adds Smstateen support to Xvisor so that Xvisor can
> configure Smstateen CSR for Guest whenever available.
>
> These patches can also be found in the riscv_smstateen_v1 branch
> at: https://github.com/avpatel/xvisor-next.git
>
> Anup Patel (3):
> RISC-V: Parse Smstateen extension from ISA string
> RISC-V: Add Smstateen related CSR defines
> RISC-V: Configure Smstateen extension for Guest

Applied this series to the xvisor-next repo.

Thanks,
Anup

>
> arch/riscv/cpu/generic/cpu_init.c | 2 ++
> arch/riscv/cpu/generic/cpu_vcpu_helper.c | 31 +++++++++++++++++++
> arch/riscv/cpu/generic/cpu_vcpu_nested.c | 3 ++
> arch/riscv/cpu/generic/include/arch_regs.h | 3 ++
> arch/riscv/cpu/generic/include/cpu_hwcap.h | 1 +
> .../cpu/generic/include/cpu_vcpu_helper.h | 3 ++
> .../cpu/generic/include/riscv_encoding.h | 19 ++++++++++++
> 7 files changed, 62 insertions(+)
>
> --
> 2.43.0
>

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