[PATCH] RISC-V: Pass -1 in hart_mask_base instead of hart_mask in rfence SBI.

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Rajnesh Kanwal

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Apr 23, 2025, 8:29:00 AMApr 23
to xvisor...@googlegroups.com, Rajnesh Kanwal
When selecting all the available harts, we need to pass -1 in
hart_mask_base instead of hart_mask. This fixes mmu tests in
wboxtest.

As per the spec: 3.1. Hart list parameter

hart_mask_base can be set to -1 to indicate that hart_mask shall be ignored
and all available harts must be considered

Signed-off-by: Rajnesh Kanwal <rka...@rivosinc.com>
---
arch/riscv/cpu/generic/cpu_sbi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/generic/cpu_sbi.c b/arch/riscv/cpu/generic/cpu_sbi.c
index 72a92645..959bf93d 100644
--- a/arch/riscv/cpu/generic/cpu_sbi.c
+++ b/arch/riscv/cpu/generic/cpu_sbi.c
@@ -322,7 +322,7 @@ static int __sbi_rfence_v02(unsigned long fid,
int result;

if (!hart_mask) {
- return __sbi_rfence_v02_real(fid, -1UL, 0UL,
+ return __sbi_rfence_v02_real(fid, 0UL, -1UL,
start, size, arg4);
}

--
2.43.0

Rajnesh Kanwal

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Apr 23, 2025, 8:29:05 AMApr 23
to xvisor...@googlegroups.com, apa...@ventanamicro.com, ati...@rivosinc.com, Rajnesh Kanwal

Anup Patel

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Apr 23, 2025, 8:34:57 AMApr 23
to xvisor...@googlegroups.com, Rajnesh Kanwal
On Wed, Apr 23, 2025 at 5:59 PM Rajnesh Kanwal <rka...@rivosinc.com> wrote:
>
> When selecting all the available harts, we need to pass -1 in
> hart_mask_base instead of hart_mask. This fixes mmu tests in
> wboxtest.
>
> As per the spec: 3.1. Hart list parameter
>
> hart_mask_base can be set to -1 to indicate that hart_mask shall be ignored
> and all available harts must be considered
>
> Signed-off-by: Rajnesh Kanwal <rka...@rivosinc.com>

LGTM.

Reviewed-by: Anup Patel <an...@brainfault.org>

Applied this patch to the xvisor-next repo.

Thanks,
Anup

> ---
> arch/riscv/cpu/generic/cpu_sbi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/cpu/generic/cpu_sbi.c b/arch/riscv/cpu/generic/cpu_sbi.c
> index 72a92645..959bf93d 100644
> --- a/arch/riscv/cpu/generic/cpu_sbi.c
> +++ b/arch/riscv/cpu/generic/cpu_sbi.c
> @@ -322,7 +322,7 @@ static int __sbi_rfence_v02(unsigned long fid,
> int result;
>
> if (!hart_mask) {
> - return __sbi_rfence_v02_real(fid, -1UL, 0UL,
> + return __sbi_rfence_v02_real(fid, 0UL, -1UL,
> start, size, arg4);
> }
>
> --
> 2.43.0
>
> --
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