[PATCH 1/4] ARCH: arm: Remove port for ARM32 without virtualization support

[Anup Patel]

It is very difficult to find old 32-bit ARM boards (i.e. ARMv5,
ARMv6, ARMv7a) without virtualization. Most OEMs and SBCs have
moved to ARM64 with virtualization. In fact, finding a 32-bit
ARM board with virtualization is also difficult. Recently, the
KVM ARM32 was also removed from Linux kernel due to lack of
interest.

The ARM32 port for 32-bit ARM boards without virtualization has
been the initial port with which we started Xvisor project but
time has come to say farewell to this port so that we can focus
more on ARMv7ve, ARMv8, RISC-V, and x86_64.

Signed-off-by: Anup Patel <an...@brainfault.org>
---
arch/arm/board/common/imx/cpu.c | 172 --
arch/arm/board/common/imx/gpc.c | 218 --
arch/arm/board/common/imx/imx6q-phy.c | 111 -
arch/arm/board/common/imx/mxc_dispdrv.c | 147 -
arch/arm/board/common/imx/objects.mk | 28 -
arch/arm/board/common/imx/openconf.cfg | 41 -
arch/arm/board/common/imx/pm-imx6q.c | 121 -
arch/arm/board/common/include/exynos/irqs.h | 469 ---
.../board/common/include/exynos/mach/map.h | 252 --
.../board/common/include/exynos/plat/cpu.h | 116 -
.../common/include/exynos/plat/map-base.h | 68 -
.../common/include/exynos/plat/map-s3c.h | 106 -
.../common/include/exynos/plat/map-s5p.h | 83 -
.../board/common/include/exynos/regs-clock.h | 375 ---
.../board/common/include/exynos/regs-mct.h | 77 -
.../board/common/include/exynos/regs-pmu.h | 393 ---
.../board/common/include/exynos/regs-rtc.h | 93 -
.../common/include/exynos/regs-watchdog.h | 63 -
arch/arm/board/common/include/imx-common.h | 51 -
arch/arm/board/common/include/imx-hardware.h | 34 -
arch/arm/board/common/include/imx6q-phy.h | 43 -
arch/arm/board/common/include/imx6qdl-clock.h | 227 --
arch/arm/board/common/include/mxc.h | 192 --
arch/arm/board/common/include/mxc_dispdrv.h | 55 -
arch/arm/board/common/include/omap/sdrc.h | 146 -
arch/arm/board/common/omap/objects.mk | 25 -
arch/arm/board/common/omap/openconf.cfg | 26 -
arch/arm/board/common/omap/sdrc.c | 117 -
arch/arm/board/common/openconf.cfg | 3 -
arch/arm/board/generic/exynos4.c | 111 -
arch/arm/board/generic/objects.mk | 5 -
arch/arm/board/generic/omap3.c | 531 ----
arch/arm/board/generic/openconf.cfg | 66 +-
arch/arm/board/generic/realview.c | 122 -
arch/arm/board/generic/sabrelite.c | 79 -
arch/arm/board/generic/versatile.c | 343 ---
arch/arm/configs/generic-v5-defconfig | 105 -
arch/arm/configs/generic-v6-defconfig | 121 -
arch/arm/configs/generic-v7-defconfig | 149 -
arch/arm/cpu/arm32/cpu_atomic.c | 249 --
arch/arm/cpu/arm32/cpu_atomic64.c | 262 --
arch/arm/cpu/arm32/cpu_cache_v5.S | 292 --
arch/arm/cpu/arm32/cpu_cache_v6.S | 424 ---
arch/arm/cpu/arm32/cpu_cache_v7.S | 377 ---
arch/arm/cpu/arm32/cpu_delay.S | 44 -
arch/arm/cpu/arm32/cpu_elf.c | 169 --
arch/arm/cpu/arm32/cpu_entry.S | 704 -----
arch/arm/cpu/arm32/cpu_init.c | 117 -
arch/arm/cpu/arm32/cpu_interrupts.c | 508 ----
arch/arm/cpu/arm32/cpu_memcpy.S | 82 -
arch/arm/cpu/arm32/cpu_memset.S | 88 -
arch/arm/cpu/arm32/cpu_mmu.c | 2063 -------------
arch/arm/cpu/arm32/cpu_mmu_entry.c | 312 --
arch/arm/cpu/arm32/cpu_proc_v5.S | 117 -
arch/arm/cpu/arm32/cpu_proc_v6.S | 199 --
arch/arm/cpu/arm32/cpu_proc_v7.S | 264 --
arch/arm/cpu/arm32/cpu_stacktrace.c | 131 -
arch/arm/cpu/arm32/cpu_vcpu_coproc.c | 290 --
arch/arm/cpu/arm32/cpu_vcpu_cp14.c | 255 --
arch/arm/cpu/arm32/cpu_vcpu_cp15.c | 2589 -----------------
arch/arm/cpu/arm32/cpu_vcpu_helper.c | 1189 --------
arch/arm/cpu/arm32/cpu_vcpu_hypercall_arm.c | 747 -----
arch/arm/cpu/arm32/cpu_vcpu_hypercall_thumb.c | 48 -
arch/arm/cpu/arm32/cpu_vcpu_irq.c | 190 --
arch/arm/cpu/arm32/cpu_vcpu_mem.c | 409 ---
arch/arm/cpu/arm32/cpu_vcpu_vfp.c | 360 ---
arch/arm/cpu/arm32/elf2cpatch.py | 708 -----
arch/arm/cpu/arm32/include/arch_barrier.h | 87 -
arch/arm/cpu/arm32/include/arch_cache.h | 90 -
arch/arm/cpu/arm32/include/arch_config.h | 32 -
arch/arm/cpu/arm32/include/arch_cpu_irq.h | 120 -
arch/arm/cpu/arm32/include/arch_delay.h | 36 -
arch/arm/cpu/arm32/include/arch_elf.h | 99 -
arch/arm/cpu/arm32/include/arch_io.h | 195 --
arch/arm/cpu/arm32/include/arch_regs.h | 206 --
arch/arm/cpu/arm32/include/arch_sections.h | 81 -
arch/arm/cpu/arm32/include/arch_types.h | 91 -
arch/arm/cpu/arm32/include/cpu_cache.h | 106 -
arch/arm/cpu/arm32/include/cpu_defines.h | 584 ----
arch/arm/cpu/arm32/include/cpu_emulate_psci.h | 84 -
arch/arm/cpu/arm32/include/cpu_inline_asm.h | 537 ----
arch/arm/cpu/arm32/include/cpu_mmu.h | 131 -
arch/arm/cpu/arm32/include/cpu_proc.h | 42 -
arch/arm/cpu/arm32/include/cpu_vcpu_coproc.h | 90 -
arch/arm/cpu/arm32/include/cpu_vcpu_cp14.h | 59 -
arch/arm/cpu/arm32/include/cpu_vcpu_cp15.h | 121 -
arch/arm/cpu/arm32/include/cpu_vcpu_helper.h | 77 -
.../arm32/include/cpu_vcpu_hypercall_arm.h | 147 -
.../arm32/include/cpu_vcpu_hypercall_thumb.h | 31 -
arch/arm/cpu/arm32/include/cpu_vcpu_mem.h | 57 -
arch/arm/cpu/arm32/include/cpu_vcpu_vfp.h | 58 -
arch/arm/cpu/arm32/linker.ld | 208 --
arch/arm/cpu/arm32/objects.mk | 80 -
arch/arm/cpu/arm32/openconf.cfg | 205 --
arch/arm/cpu/openconf.cfg | 94 +-
arch/arm/dts/allwinner/objects.mk | 2 -
.../dts/allwinner/sun4i-a10-cubieboard.dts | 58 -
.../arm/dts/allwinner/sun4i-a10-hackberry.dts | 61 -
arch/arm/dts/allwinner/sun4i-a10.dtsi | 469 ---
.../dts/arm/arm-realview-eb-11mp-ctrevb.dts | 198 --
arch/arm/dts/arm/arm-realview-pba8.dts | 155 -
arch/arm/dts/arm/objects.mk | 5 -
arch/arm/dts/arm/versatile-pb.dts | 168 --
.../dts/arm/vexpress-v2p-ca15-tc1-nove.dts | 322 --
arch/arm/dts/arm/vexpress-v2p-ca9.dts | 323 --
arch/arm/dts/broadcom/bcm2835-rpi-b.dts | 43 -
arch/arm/dts/broadcom/bcm2835.dtsi | 138 -
arch/arm/dts/broadcom/objects.mk | 1 -
arch/arm/dts/freescale/imx25-pdk.dts | 164 --
arch/arm/dts/freescale/imx25-pinfunc.h | 600 ----
arch/arm/dts/freescale/imx25.dtsi | 349 ---
arch/arm/dts/freescale/imx31-kzm.dts | 26 -
arch/arm/dts/freescale/imx31.dtsi | 98 -
arch/arm/dts/freescale/imx6dl-sabrelite.dts | 245 --
arch/arm/dts/freescale/imx6q-pinfunc.h | 1048 -------
arch/arm/dts/freescale/imx6q.dtsi | 929 ------
arch/arm/dts/freescale/objects.mk | 29 -
.../sabrelite/one_guest_sabrelite.dts | 38 -
.../dts/freescale/sabrelite/sabrelite.dtsi | 231 --
.../sabrelite/two_guest_sabrelite.dts | 47 -
arch/arm/dts/samsung/exynos4210-nuri.dts | 30 -
arch/arm/dts/samsung/exynos4210-smdkc210.dts | 37 -
arch/arm/dts/samsung/exynos4210.dtsi | 119 -
arch/arm/dts/samsung/exynos4212.dtsi | 113 -
arch/arm/dts/samsung/exynos4412-odroidx.dts | 30 -
arch/arm/dts/samsung/exynos4412.dtsi | 129 -
arch/arm/dts/samsung/objects.mk | 26 -
arch/arm/dts/ti/objects.mk | 25 -
arch/arm/dts/ti/omap3-beagle-xm.dts | 26 -
arch/arm/dts/ti/omap3-beagle.dts | 21 -
arch/arm/dts/ti/omap3.dtsi | 76 -
131 files changed, 3 insertions(+), 28795 deletions(-)
delete mode 100644 arch/arm/board/common/imx/cpu.c
delete mode 100644 arch/arm/board/common/imx/gpc.c
delete mode 100644 arch/arm/board/common/imx/imx6q-phy.c
delete mode 100644 arch/arm/board/common/imx/mxc_dispdrv.c
delete mode 100644 arch/arm/board/common/imx/objects.mk
delete mode 100644 arch/arm/board/common/imx/openconf.cfg
delete mode 100644 arch/arm/board/common/imx/pm-imx6q.c
delete mode 100644 arch/arm/board/common/include/exynos/irqs.h
delete mode 100644 arch/arm/board/common/include/exynos/mach/map.h
delete mode 100644 arch/arm/board/common/include/exynos/plat/cpu.h
delete mode 100644 arch/arm/board/common/include/exynos/plat/map-base.h
delete mode 100644 arch/arm/board/common/include/exynos/plat/map-s3c.h
delete mode 100644 arch/arm/board/common/include/exynos/plat/map-s5p.h
delete mode 100644 arch/arm/board/common/include/exynos/regs-clock.h
delete mode 100644 arch/arm/board/common/include/exynos/regs-mct.h
delete mode 100644 arch/arm/board/common/include/exynos/regs-pmu.h
delete mode 100644 arch/arm/board/common/include/exynos/regs-rtc.h
delete mode 100644 arch/arm/board/common/include/exynos/regs-watchdog.h
delete mode 100644 arch/arm/board/common/include/imx-common.h
delete mode 100644 arch/arm/board/common/include/imx-hardware.h
delete mode 100644 arch/arm/board/common/include/imx6q-phy.h
delete mode 100644 arch/arm/board/common/include/imx6qdl-clock.h
delete mode 100644 arch/arm/board/common/include/mxc.h
delete mode 100644 arch/arm/board/common/include/mxc_dispdrv.h
delete mode 100644 arch/arm/board/common/include/omap/sdrc.h
delete mode 100644 arch/arm/board/common/omap/objects.mk
delete mode 100644 arch/arm/board/common/omap/openconf.cfg
delete mode 100644 arch/arm/board/common/omap/sdrc.c
delete mode 100644 arch/arm/board/generic/exynos4.c
delete mode 100644 arch/arm/board/generic/omap3.c
delete mode 100644 arch/arm/board/generic/realview.c
delete mode 100644 arch/arm/board/generic/sabrelite.c
delete mode 100644 arch/arm/board/generic/versatile.c
delete mode 100644 arch/arm/configs/generic-v5-defconfig
delete mode 100644 arch/arm/configs/generic-v6-defconfig
delete mode 100644 arch/arm/configs/generic-v7-defconfig
delete mode 100644 arch/arm/cpu/arm32/cpu_atomic.c
delete mode 100644 arch/arm/cpu/arm32/cpu_atomic64.c
delete mode 100644 arch/arm/cpu/arm32/cpu_cache_v5.S
delete mode 100644 arch/arm/cpu/arm32/cpu_cache_v6.S
delete mode 100644 arch/arm/cpu/arm32/cpu_cache_v7.S
delete mode 100644 arch/arm/cpu/arm32/cpu_delay.S
delete mode 100644 arch/arm/cpu/arm32/cpu_elf.c
delete mode 100644 arch/arm/cpu/arm32/cpu_entry.S
delete mode 100644 arch/arm/cpu/arm32/cpu_init.c
delete mode 100644 arch/arm/cpu/arm32/cpu_interrupts.c
delete mode 100644 arch/arm/cpu/arm32/cpu_memcpy.S
delete mode 100644 arch/arm/cpu/arm32/cpu_memset.S
delete mode 100644 arch/arm/cpu/arm32/cpu_mmu.c
delete mode 100644 arch/arm/cpu/arm32/cpu_mmu_entry.c
delete mode 100644 arch/arm/cpu/arm32/cpu_proc_v5.S
delete mode 100644 arch/arm/cpu/arm32/cpu_proc_v6.S
delete mode 100644 arch/arm/cpu/arm32/cpu_proc_v7.S
delete mode 100644 arch/arm/cpu/arm32/cpu_stacktrace.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_coproc.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_cp14.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_cp15.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_helper.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_hypercall_arm.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_hypercall_thumb.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_irq.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_mem.c
delete mode 100644 arch/arm/cpu/arm32/cpu_vcpu_vfp.c
delete mode 100755 arch/arm/cpu/arm32/elf2cpatch.py
delete mode 100644 arch/arm/cpu/arm32/include/arch_barrier.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_cache.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_config.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_cpu_irq.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_delay.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_elf.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_io.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_regs.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_sections.h
delete mode 100644 arch/arm/cpu/arm32/include/arch_types.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_cache.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_defines.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_emulate_psci.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_inline_asm.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_mmu.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_proc.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_coproc.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_cp14.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_cp15.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_helper.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_arm.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_thumb.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_mem.h
delete mode 100644 arch/arm/cpu/arm32/include/cpu_vcpu_vfp.h
delete mode 100755 arch/arm/cpu/arm32/linker.ld
delete mode 100644 arch/arm/cpu/arm32/objects.mk
delete mode 100644 arch/arm/cpu/arm32/openconf.cfg
delete mode 100644 arch/arm/dts/allwinner/sun4i-a10-cubieboard.dts
delete mode 100644 arch/arm/dts/allwinner/sun4i-a10-hackberry.dts
delete mode 100644 arch/arm/dts/allwinner/sun4i-a10.dtsi
delete mode 100644 arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dts
delete mode 100644 arch/arm/dts/arm/arm-realview-pba8.dts
delete mode 100644 arch/arm/dts/arm/versatile-pb.dts
delete mode 100644 arch/arm/dts/arm/vexpress-v2p-ca15-tc1-nove.dts
delete mode 100644 arch/arm/dts/arm/vexpress-v2p-ca9.dts
delete mode 100644 arch/arm/dts/broadcom/bcm2835-rpi-b.dts
delete mode 100644 arch/arm/dts/broadcom/bcm2835.dtsi
delete mode 100644 arch/arm/dts/freescale/imx25-pdk.dts
delete mode 100644 arch/arm/dts/freescale/imx25-pinfunc.h
delete mode 100644 arch/arm/dts/freescale/imx25.dtsi
delete mode 100644 arch/arm/dts/freescale/imx31-kzm.dts
delete mode 100644 arch/arm/dts/freescale/imx31.dtsi
delete mode 100644 arch/arm/dts/freescale/imx6dl-sabrelite.dts
delete mode 100644 arch/arm/dts/freescale/imx6q-pinfunc.h
delete mode 100644 arch/arm/dts/freescale/imx6q.dtsi
delete mode 100644 arch/arm/dts/freescale/objects.mk
delete mode 100644 arch/arm/dts/freescale/sabrelite/one_guest_sabrelite.dts
delete mode 100644 arch/arm/dts/freescale/sabrelite/sabrelite.dtsi
delete mode 100644 arch/arm/dts/freescale/sabrelite/two_guest_sabrelite.dts
delete mode 100644 arch/arm/dts/samsung/exynos4210-nuri.dts
delete mode 100644 arch/arm/dts/samsung/exynos4210-smdkc210.dts
delete mode 100644 arch/arm/dts/samsung/exynos4210.dtsi
delete mode 100644 arch/arm/dts/samsung/exynos4212.dtsi
delete mode 100644 arch/arm/dts/samsung/exynos4412-odroidx.dts
delete mode 100644 arch/arm/dts/samsung/exynos4412.dtsi
delete mode 100644 arch/arm/dts/samsung/objects.mk
delete mode 100644 arch/arm/dts/ti/objects.mk
delete mode 100644 arch/arm/dts/ti/omap3-beagle-xm.dts
delete mode 100644 arch/arm/dts/ti/omap3-beagle.dts
delete mode 100644 arch/arm/dts/ti/omap3.dtsi

diff --git a/arch/arm/board/common/imx/cpu.c b/arch/arm/board/common/imx/cpu.c
deleted file mode 100644
index f634a934..00000000
--- a/arch/arm/board/common/imx/cpu.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/cpu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX CPU information function helpers
- */
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/sys_soc.h>
-#include <linux/device.h>
-
-#include <imx-hardware.h>
-#include <imx-common.h>
-
-unsigned int __mxc_cpu_type;
-EXPORT_SYMBOL(__mxc_cpu_type);
-
-static unsigned int imx_soc_revision;
-
-void mxc_set_cpu_type(unsigned int type)
-{
- __mxc_cpu_type = type;
-}
-
-void imx_set_soc_revision(unsigned int rev)
-{
- imx_soc_revision = rev;
-}
-
-unsigned int imx_get_soc_revision(void)
-{
- return imx_soc_revision;
-}
-
-void imx_print_silicon_rev(const char *cpu, int srev)
-{
- if (srev == IMX_CHIP_REVISION_UNKNOWN)
- pr_info("CPU identified as %s, unknown revision\n", cpu);
- else
- pr_info("CPU identified as %s, silicon rev %d.%d\n",
- cpu, (srev >> 4) & 0xf, srev & 0xf);
-}
-
-void __init imx_set_aips(void __iomem *base)
-{
- unsigned int reg;
-/*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- vmm_writel(0x77777777, base + 0x0);
- vmm_writel(0x77777777, base + 0x4);
-
-/*
- * Set all OPACRx to be non-bufferable, to not require
- * supervisor privilege level for access, allow for
- * write access and untrusted master access.
- */
- vmm_writel(0x0, base + 0x40);
- vmm_writel(0x0, base + 0x44);
- vmm_writel(0x0, base + 0x48);
- vmm_writel(0x0, base + 0x4C);
- reg = vmm_readl(base + 0x50) & 0x00FFFFFF;
- vmm_writel(reg, base + 0x50);
-}
-
-struct device * __init imx_soc_device_init(void)
-{
- struct soc_device_attribute *soc_dev_attr;
- /* struct soc_device *soc_dev; */
- struct device_node *root;
- const char *soc_id;
- char* revision = NULL;
-
- soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
- if (!soc_dev_attr)
- return NULL;
-
- soc_dev_attr->family = "Freescale i.MX";
-
- root = vmm_devtree_getnode("/");
- soc_dev_attr->machine = vmm_devtree_attrval(root, "model");
- vmm_devtree_dref_node(root);
- if (!soc_dev_attr->machine) {
- vmm_printf("Error: SOC model not found in device tree\n");
- goto free_soc;
- }
-
- switch (__mxc_cpu_type) {
- case MXC_CPU_MX1:
- soc_id = "i.MX1";
- break;
- case MXC_CPU_MX21:
- soc_id = "i.MX21";
- break;
- case MXC_CPU_MX25:
- soc_id = "i.MX25";
- break;
- case MXC_CPU_MX27:
- soc_id = "i.MX27";
- break;
- case MXC_CPU_MX31:
- soc_id = "i.MX31";
- break;
- case MXC_CPU_MX35:
- soc_id = "i.MX35";
- break;
- case MXC_CPU_MX51:
- soc_id = "i.MX51";
- break;
- case MXC_CPU_MX53:
- soc_id = "i.MX53";
- break;
- case MXC_CPU_IMX6SL:
- soc_id = "i.MX6SL";
- break;
- case MXC_CPU_IMX6DL:
- soc_id = "i.MX6DL";
- break;
- case MXC_CPU_IMX6Q:
- soc_id = "i.MX6Q";
- break;
- default:
- soc_id = "Unknown";
- }
- soc_dev_attr->soc_id = soc_id;
-
- /* Allocate a string that can contain 2 digits (up to 0xf), a dot,
- 2 other digits (also up to 0xf), and the 0 terminating character */
- if (NULL == (revision = kmalloc(6, GFP_KERNEL))) {
- vmm_printf("Failed to allocate SOC revision string space\n");
- goto free_soc;
- }
-
- snprintf(revision, 6, "%d.%d", (imx_soc_revision >> 4) & 0xf,
- imx_soc_revision & 0xf);
-
- soc_dev_attr->revision = revision;
-
- /* soc_dev = soc_device_register(soc_dev_attr); */
- /* if (IS_ERR(soc_dev)) */
- /* goto free_rev; */
-
- /* return soc_device_to_device(soc_dev); */
- vmm_printf("soc_device_register not implemented yet\n");
- return NULL;
-
-free_soc:
- kfree(soc_dev_attr);
- return NULL;
-}
diff --git a/arch/arm/board/common/imx/gpc.c b/arch/arm/board/common/imx/gpc.c
deleted file mode 100644
index 6fec2666..00000000
--- a/arch/arm/board/common/imx/gpc.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (C) 2014,2016 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/gpc.c
- *
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * @file gpc.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @author Jean Guyomarc'h (jean.gu...@openwide.fr)
- * @brief Freescale i.MX GPC function helpers
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/printk.h>
-#include <imx6qdl-clock.h>
-#include <imx-common.h>
-
-#define GPC_CNTR 0x000
-#define GPC_IMR1 0x008
-#define GPC_PGC_GPU_PDN 0x260
-#define GPC_PGC_GPU_PUPSCR 0x264
-#define GPC_PGC_GPU_PDNSCR 0x268
-#define GPC_PGC_CPU_PDN 0x2a0
-#define GPU_VPU_PUP_REQ BIT(1)
-#define GPU_VPU_PDN_REQ BIT(0)
-
-#define IMR_NUM 4
-
-#define GPC_CLK_MAX 6
-
-#define DT_COMPATIBLE "fsl,imx6q-gpc"
-
-static void __iomem *gpc_base;
-//static u32 gpc_wake_irqs[IMR_NUM];
-static u32 gpc_saved_imrs[IMR_NUM];
-static struct clk *clocks[GPC_CLK_MAX];
-static unsigned int clocks_count = 0;
-
-#if 0
-void imx_gpc_pre_suspend(void)
-{
- void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
- int i;
-
- /* Tell GPC to power off ARM core when suspend */
- writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
-
- for (i = 0; i < IMR_NUM; i++) {
- gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
- writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
- }
-}
-#endif
-
-void imx_gpc_post_resume(void)
-{
- void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
- int i;
-
- /* Keep ARM core powered on for other low-power modes */
- writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
-
- for (i = 0; i < IMR_NUM; i++)
- writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
-}
-
-/* static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) */
-/* { */
-/* unsigned int idx = d->num / 32 - 1; */
-/* u32 mask; */
-
-/* /\* Sanity check for SPI irq *\/ */
-/* if (d->num < 32) */
-/* return -EINVAL; */
-
-/* mask = 1 << d->num % 32; */
-/* gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : */
-/* gpc_wake_irqs[idx] & ~mask; */
-
-/* return 0; */
-/* } */
-
-void imx_gpc_mask_all(void)
-{
- void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
- int i;
-
- for (i = 0; i < IMR_NUM; i++) {
- gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
- writel_relaxed(~0, reg_imr1 + i * 4);
- }
-
-}
-
-void imx_gpc_restore_all(void)
-{
- void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
- int i;
-
- for (i = 0; i < IMR_NUM; i++)
- writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
-}
-
-void imx_gpc_irq_unmask(struct irq_data *d)
-{
- void __iomem *reg;
- u32 val;
-
- /* Sanity check for SPI irq */
- if (d->num < 32)
- return;
-
- reg = gpc_base + GPC_IMR1 + (d->num / 32 - 1) * 4;
- val = readl_relaxed(reg);
- val &= ~(1 << d->num % 32);
- writel_relaxed(val, reg);
-}
-
-void imx_gpc_irq_mask(struct irq_data *d)
-{
- void __iomem *reg;
- u32 val;
-
- /* Sanity check for SPI irq */
- if (d->num < 32)
- return;
-
- reg = gpc_base + GPC_IMR1 + (d->num / 32 - 1) * 4;
- val = readl_relaxed(reg);
- val |= 1 << (d->num % 32);
- writel_relaxed(val, reg);
-}
-
-void __init imx_gpc_clocks_init(void)
-{
- struct device_node *np;
- struct clk *clk;
- int i, chk;
-
- np = vmm_devtree_find_compatible(NULL, NULL, DT_COMPATIBLE);
- if (NULL == np) {
- vmm_lerror("Failed to find compatible GPC node \"%s\"\n",
- DT_COMPATIBLE);
- return;
- }
-
- for (i = 0; ; i++) {
- clk = of_clk_get(np, i);
- if (IS_ERR(clk)) {
- break; /* No more clocks */
- }
- if (i >= GPC_CLK_MAX) {
- vmm_lerror("imx-gpc", "Too many clocks for GPC node\n");
- while (i--) {
- clk_put(clocks[i]);
- }
- return;
- }
- clocks[i] = clk;
- }
- clocks_count = i;
-
- /* Start clocks */
- for (i = 0; i < clocks_count; i++) {
- chk = clk_prepare_enable(clocks[i]);
- if (chk != 0) {
- vmm_lerror("imx-gpc", "error %i, failed to enable clock %d\n",
- chk, i);
- }
- }
-}
-
-void __init imx_gpc_init(void)
-{
- struct device_node *np;
- virtual_addr_t vbase = 0;
- int i, rc;
-
- np = vmm_devtree_find_compatible(NULL, NULL, DT_COMPATIBLE);
- if (!np) {
- printk("Failed to find compatible GPC node\n");
- return;
- }
- rc = vmm_devtree_regmap(np, &vbase, 0);
- vmm_devtree_dref_node(np);
- if (VMM_OK != rc) {
- printk("Failed to map GPC registers\n");
- return;
- }
- gpc_base = (void __iomem *)vbase;
-
- /* Initially mask all interrupts */
- for (i = 0; i < IMR_NUM; i++)
- writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
-
- /* Register GPC as the secondary interrupt controller behind GIC */
- printk("FIXME: GPC is the secondary interrupt controller behind "
- "GIC\n");
- /* gic_arch_extn.irq_mask = imx_gpc_irq_mask; */
- /* gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; */
- /* gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; */
-}
diff --git a/arch/arm/board/common/imx/imx6q-phy.c b/arch/arm/board/common/imx/imx6q-phy.c
deleted file mode 100644
index 6bd04004..00000000
--- a/arch/arm/board/common/imx/imx6q-phy.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * Copyright (C) 2015 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx6q-phy.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX6 Sabrelite board specific code for PHY
- *
- * Adapted from linux/arch/arm/mach-imx/mach-imx6q.c
- *
- * The original source is licensed under GPL.
- *
- */
-
-#include <linux/kconfig.h>
-#include <linux/phy.h>
-#include <linux/micrel_phy.h>
-#include <imx6q-phy.h>
-
-
-/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
-static int ksz9021rn_phy_fixup(struct phy_device *phydev)
-{
- if (IS_BUILTIN(CONFIG_PHYLIB)) {
- /* min rx data delay */
- phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
- 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
- phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
-
- /* max rx/tx clock delay, min rx/tx control delay */
- phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
- 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
- phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
- phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
- MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
- }
-
- return 0;
-}
-
-static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
-{
- phy_write(dev, 0x0d, device);
- phy_write(dev, 0x0e, reg);
- phy_write(dev, 0x0d, (1 << 14) | device);
- phy_write(dev, 0x0e, val);
-}
-
-static int ksz9031rn_phy_fixup(struct phy_device *dev)
-{
- /*
- * min rx data delay, max rx/tx clock delay,
- * min rx/tx control delay
- */
- mmd_write_reg(dev, 2, 4, 0);
- mmd_write_reg(dev, 2, 5, 0);
- mmd_write_reg(dev, 2, 8, 0x003ff);
-
- return 0;
-}
-
-static int ar8031_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* To enable AR8031 output a 125MHz clk from CLK_25M */
- phy_write(dev, 0xd, 0x7);
- phy_write(dev, 0xe, 0x8016);
- phy_write(dev, 0xd, 0x4007);
-
- val = phy_read(dev, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(dev, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(dev, 0x1d, 0x5);
- val = phy_read(dev, 0x1e);
- val |= 0x0100;
- phy_write(dev, 0x1e, val);
-
- return 0;
-}
-
-#define PHY_ID_AR8031 0x004dd074
-
-void __init imx6q_enet_phy_init(void)
-{
- if (IS_BUILTIN(CONFIG_PHYLIB)) {
- phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
- ksz9021rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
- ksz9031rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
- ar8031_phy_fixup);
- }
-}
diff --git a/arch/arm/board/common/imx/mxc_dispdrv.c b/arch/arm/board/common/imx/mxc_dispdrv.c
deleted file mode 100644
index 70bada72..00000000
--- a/arch/arm/board/common/imx/mxc_dispdrv.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- * Modified by Jimmy Durand Wesolowski <jimmy.duran...@openwide.fr>
- * for Xvisor.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * @file mxc_dispdrv.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief mxc display driver framework.
- */
-
-/*
- * A display device driver could call mxc_dispdrv_register(drv) in its dev_probe() function.
- * Move all dev_probe() things into mxc_dispdrv_driver->init(), init() function should init
- * and feedback setting;
- * Necessary deferred operations can be done in mxc_dispdrv_driver->post_init(),
- * after dev_id and disp_id pass usage check;
- * Move all dev_remove() things into mxc_dispdrv_driver->deinit();
- * Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
- * Move all dev_resume() things into fb_notifier for RESUME, if there is;
- *
- * ipuv3 fb driver could call mxc_dispdrv_gethandle(name, setting) before a fb
- * need be added, with fbi param passing by setting, after
- * mxc_dispdrv_gethandle() return, FB driver should get the basic setting
- * about fbi info and ipuv3-hw (ipu_id and disp_id).
- *
- * @ingroup Framebuffer
- */
-#include <vmm_modules.h>
-#include <vmm_mutex.h>
-#include <vmm_heap.h>
-#include <libs/list.h>
-
-#include <mxc_dispdrv.h>
-
-static LIST_HEAD(dispdrv_list);
-static DEFINE_MUTEX(dispdrv_lock);
-
-struct mxc_dispdrv_entry {
- /* Note: drv always the first element */
- struct mxc_dispdrv_driver *drv;
- bool active;
- void *priv;
- struct list_head list;
-};
-
-struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
-{
- struct mxc_dispdrv_entry *new;
-
- vmm_mutex_lock(&dispdrv_lock);
-
- new = vmm_zalloc(sizeof(struct mxc_dispdrv_entry));
- if (!new) {
- vmm_mutex_unlock(&dispdrv_lock);
- return VMM_ERR_PTR(VMM_ENOMEM);
- }
-
- new->drv = drv;
- list_add_tail(&new->list, &dispdrv_list);
-
- vmm_mutex_unlock(&dispdrv_lock);
-
- return (struct mxc_dispdrv_handle *)new;
-}
-
-int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle)
-{
- struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
-
- if (entry) {
- vmm_mutex_lock(&dispdrv_lock);
- list_del(&entry->list);
- vmm_mutex_unlock(&dispdrv_lock);
- vmm_free(entry);
- return 0;
- } else
- return VMM_EINVALID;
-}
-
-struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
- struct mxc_dispdrv_setting *setting)
-{
- int ret, found = 0;
- struct mxc_dispdrv_entry *entry;
-
- vmm_mutex_lock(&dispdrv_lock);
- list_for_each_entry(entry, &dispdrv_list, list) {
- if (!strcmp(entry->drv->name, name) && (entry->drv->init)) {
- ret = entry->drv->init((struct mxc_dispdrv_handle *)
- entry, setting);
- if (ret >= 0) {
- entry->active = true;
- found = 1;
- break;
- }
- }
- }
- vmm_mutex_unlock(&dispdrv_lock);
-
- if (found)
- return (struct mxc_dispdrv_handle *)entry;
- else
- return VMM_ERR_PTR(VMM_ENODEV);
-}
-
-void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle)
-{
- struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
-
- vmm_mutex_lock(&dispdrv_lock);
- if (entry && entry->active && entry->drv->deinit) {
- entry->drv->deinit(handle);
- entry->active = false;
- }
- vmm_mutex_unlock(&dispdrv_lock);
-
-}
-
-int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data)
-{
- struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
-
- if (entry) {
- entry->priv = data;
- return 0;
- } else
- return VMM_EINVALID;
-}
-
-void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle)
-{
- struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
-
- if (entry) {
- return entry->priv;
- } else
- return VMM_ERR_PTR(VMM_EINVALID);
-}
diff --git a/arch/arm/board/common/imx/objects.mk b/arch/arm/board/common/imx/objects.mk
deleted file mode 100644
index 9c335d8d..00000000
--- a/arch/arm/board/common/imx/objects.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#/**
-# Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
-# @brief list of IMX platform objects.
-# */
-
-board-common-objs-$(CONFIG_ARCH_MXC)+= imx/cpu.o imx/gpc.o
-board-common-objs-$(CONFIG_IMX6Q_PM)+= imx/pm-imx6q.o
-board-common-objs-$(CONFIG_IMX6Q_PHY)+= imx/imx6q-phy.o
-board-common-objs-$(CONFIG_ARCH_MXC)+= imx/mxc_dispdrv.o
-
diff --git a/arch/arm/board/common/imx/openconf.cfg b/arch/arm/board/common/imx/openconf.cfg
deleted file mode 100644
index 62cc2a8b..00000000
--- a/arch/arm/board/common/imx/openconf.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# Copyright (c) 2014 Institut de Recherche Technologique SystemX and OpenWide.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file openconf.cfg
-# @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
-# @brief config file for IMX platform
-#
-
-config CONFIG_ARCH_MXC
- bool
- default n
-
-config CONFIG_SABRELITE_CONFIG
- bool
- default n
- select CONFIG_ARCH_MXC
- select CONFIG_IMX6Q_PM
- select CONFIG_IMX6Q_PHY if CONFIG_PHYLIB
-
-config CONFIG_IMX6Q_PM
- bool
- default n
-
-config CONFIG_IMX6Q_PHY
- bool
- default n
diff --git a/arch/arm/board/common/imx/pm-imx6q.c b/arch/arm/board/common/imx/pm-imx6q.c
deleted file mode 100644
index b95e8315..00000000
--- a/arch/arm/board/common/imx/pm-imx6q.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/pm-imx6q.c
- *
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * @file pm-imx6q.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX6Q minimal PM management
- */
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <imx-common.h>
-#include <imx-hardware.h>
-
-#define CCR 0x0
-#define BM_CCR_WB_COUNT (0x7 << 16)
-#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
-#define BM_CCR_RBC_EN (0x1 << 27)
-
-#define CLPCR 0x54
-#define BP_CLPCR_LPM 0
-#define BM_CLPCR_LPM (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define BM_CLPCR_SBYOS (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define BM_CLPCR_VSTBY (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT 9
-#define BM_CLPCR_STBY_COUNT (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
-
-#define CGPR 0x64
-#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
-
-static void __iomem *ccm_base;
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
- struct vmm_host_irq *iomuxc_irq_desc;
- u32 val = readl_relaxed(ccm_base + CLPCR);
- struct irq_data mxc_gpc_irq_data;
-
- val &= ~BM_CLPCR_LPM;
- switch (mode) {
- case WAIT_CLOCKED:
- break;
- case WAIT_UNCLOCKED:
- val |= 0x1 << BP_CLPCR_LPM;
- val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
- break;
- case STOP_POWER_ON:
- val |= 0x2 << BP_CLPCR_LPM;
- break;
- case WAIT_UNCLOCKED_POWER_OFF:
- val |= 0x1 << BP_CLPCR_LPM;
- val &= ~BM_CLPCR_VSTBY;
- val &= ~BM_CLPCR_SBYOS;
- break;
- case STOP_POWER_OFF:
- val |= 0x2 << BP_CLPCR_LPM;
- val |= 0x3 << BP_CLPCR_STBY_COUNT;
- val |= BM_CLPCR_VSTBY;
- val |= BM_CLPCR_SBYOS;
- if (cpu_is_imx6sl()) {
- val |= BM_CLPCR_BYPASS_PMIC_READY;
- val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
- } else {
- val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
- }
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Unmask the always pending IOMUXC interrupt #32 as wakeup source to
- * deassert dsm_request signal, so that we can ensure dsm_request
- * is not asserted when we're going to write CLPCR register to set LPM.
- * After setting up LPM bits, we need to mask this wakeup source.
- */
- /* FIXME: This can be avoided as we already have the IRQ number */
- iomuxc_irq_desc = vmm_host_irq_get(32);
- mxc_gpc_irq_data.num = iomuxc_irq_desc->num;
- imx_gpc_irq_unmask(&mxc_gpc_irq_data);
- writel_relaxed(val, ccm_base + CLPCR);
- imx_gpc_irq_mask(&mxc_gpc_irq_data);
-
- return 0;
-}
-
-void __init imx6q_pm_set_ccm_base(void __iomem *base)
-{
- ccm_base = base;
-}
diff --git a/arch/arm/board/common/include/exynos/irqs.h b/arch/arm/board/common/include/exynos/irqs.h
deleted file mode 100644
index a5686448..00000000
--- a/arch/arm/board/common/include/exynos/irqs.h
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-//#include <plat/irqs.h>
-
-/* PPI: Private Peripheral Interrupt */
-
-#define IRQ_PPI(x) (x + 16)
-
-/* SPI: Shared Peripheral Interrupt */
-
-#define IRQ_SPI(x) (x + 32)
-
-/* COMBINER */
-
-#define MAX_IRQ_IN_COMBINER 8
-#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
-
-/* For EXYNOS4 and EXYNOS5 */
-
-#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
-
-#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
-
-/* For EXYNOS4 SoCs */
-
-#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
-#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
-#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
-#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
-#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
-#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
-#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
-#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
-#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
-#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
-#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
-#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
-#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
-#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
-#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
-#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
-
-#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
-#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
-#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
-#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
-#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
-#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
-#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
-#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
-#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
-#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
-#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
-#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
-#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
-#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
-#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
-#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
-
-#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
-#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
-#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
-#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
-#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
-#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
-#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
-#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
-#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
-#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
-#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
-#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
-#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
-#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
-#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
-#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
-#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
-
-#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
-#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
-#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
-#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
-#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
-#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
-#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
-#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
-
-#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
-#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
-
-#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
-#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
-#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
-#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
-#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
-#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
-#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
-#define EXYNOS4_IRQ_2D IRQ_SPI(89)
-#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
-
-#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
-#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
-#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
-#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
-#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
-
-#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
-#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
-#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
-#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
-#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
-
-#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
-#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
-#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
-#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
-#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
-#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
-#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
-#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
-#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
-
-#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
-#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
-
-#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
-#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
-#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
-#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
-#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
-#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
-#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
-#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
-#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
-
-#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
-#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
-#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-
-#define EXYNOS4_MAX_COMBINER_NR 16
-
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
-
-/*
- * For Compatibility:
- * the default is for EXYNOS4, and
- * for exynos5, should be re-mapped at function
- */
-
-#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
-#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
-#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
-#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
-#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
-
-#define IRQ_WDT EXYNOS4_IRQ_WDT
-#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
-#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
-#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
-#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
-
-#define IRQ_IIC EXYNOS4_IRQ_IIC
-#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
-#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
-#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
-#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
-#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
-
-#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
-#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
-#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
-
-#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
-#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
-
-#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
-#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
-#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
-#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
-
-#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
-
-#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
-
-#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
-#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
-#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
-#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
-#define IRQ_JPEG EXYNOS4_IRQ_JPEG
-#define IRQ_2D EXYNOS4_IRQ_2D
-
-#define IRQ_MIXER EXYNOS4_IRQ_MIXER
-#define IRQ_HDMI EXYNOS4_IRQ_HDMI
-#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
-#define IRQ_MFC EXYNOS4_IRQ_MFC
-#define IRQ_SDO EXYNOS4_IRQ_SDO
-
-#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
-
-#define IRQ_ADC EXYNOS4_IRQ_ADC0
-#define IRQ_TC EXYNOS4_IRQ_PEN0
-
-#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU EXYNOS4_IRQ_PMU
-
-#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
-#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
-#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
-
-#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
-/* For EXYNOS5 SoCs */
-
-#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
-#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
-#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
-#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
-#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
-#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
-#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
-#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
-#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
-#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
-#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
-#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
-#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
-#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
-#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
-#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
-#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
-#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
-#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
-#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
-#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
-#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
-#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
-#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
-#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
-#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
-#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
-#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
-#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
-#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
-#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
-#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
-#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
-#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
-#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
-#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
-#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
-#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
-#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
-#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
-#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
-#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
-#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
-#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
-#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
-#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
-#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
-#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
-#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
-#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
-#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
-#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
-#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
-#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
-#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
-#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
-#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
-#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
-#define EXYNOS5_IRQ_2D IRQ_SPI(91)
-#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
-#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
-#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
-#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
-#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
-#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
-#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
-#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
-#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
-#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
-#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
-#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
-#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
-#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
-#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
-#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
-#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
-#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
-#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
-#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
-#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
-#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
-#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
-#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
-
-#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
-#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
-#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
-#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
-#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
-#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
-
-#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
-
-#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
-
-#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
-#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
-#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
-#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
-#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
-#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
-#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
-
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
-
-#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
-
-#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
-#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
-#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
-#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
-#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
-#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
-
-#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
-
-#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
-
-#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
-#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
-#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
-
-#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
-#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
-#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
-#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
-
-#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
-
-#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
-
-#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
-#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
-#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
-
-#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
-#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
-
-#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
-#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
-
-#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
-#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
-
-#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
-#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
-
-#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
-#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
-
-#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
-#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
-
-#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
-#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
-
-#define EXYNOS5_MAX_COMBINER_NR 32
-
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
-#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
-#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
-#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
-
-#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
- EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
-
-#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
-#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
-#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
-#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
-
-/* Set the default NR_IRQS */
-
-#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/board/common/include/exynos/mach/map.h b/arch/arm/board/common/include/exynos/mach/map.h
deleted file mode 100644
index ef1bd7bf..00000000
--- a/arch/arm/board/common/include/exynos/mach/map.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file map.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief EXYNOS4 - Memory map definitions
- *
- * Adapted from linux/arch/arm/mach-exynos/include/mach/map.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * EXYNOS4 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <exynos/plat/map-base.h>
-
-/*
- * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
- * So need to define it, and here is to avoid redefinition warning.
- */
-#define S3C_UART_OFFSET (0x10000)
-
-#include <exynos/plat/map-s5p.h>
-
-#define EXYNOS4_PA_SYSRAM0 0x02025000
-#define EXYNOS4_PA_SYSRAM1 0x02020000
-#define EXYNOS5_PA_SYSRAM 0x02020000
-
-#define EXYNOS4_PA_FIMC0 0x11800000
-#define EXYNOS4_PA_FIMC1 0x11810000
-#define EXYNOS4_PA_FIMC2 0x11820000
-#define EXYNOS4_PA_FIMC3 0x11830000
-
-#define EXYNOS4_PA_JPEG 0x11840000
-
-#define EXYNOS4_PA_G2D 0x12800000
-
-#define EXYNOS4_PA_I2S0 0x03830000
-#define EXYNOS4_PA_I2S1 0xE3100000
-#define EXYNOS4_PA_I2S2 0xE2A00000
-
-#define EXYNOS4_PA_PCM0 0x03840000
-#define EXYNOS4_PA_PCM1 0x13980000
-#define EXYNOS4_PA_PCM2 0x13990000
-
-#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
-
-#define EXYNOS4_PA_ONENAND 0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
-
-#define EXYNOS_PA_CHIPID 0x10000000
-
-#define EXYNOS4_PA_SYSCON 0x10010000
-#define EXYNOS5_PA_SYSCON 0x10050100
-
-#define EXYNOS4_PA_PMU 0x10020000
-#define EXYNOS5_PA_PMU 0x10040000
-
-#define EXYNOS4_PA_CMU 0x10030000
-#define EXYNOS5_PA_CMU 0x10010000
-
-#define EXYNOS4_PA_SYSTIMER 0x10050000
-#define EXYNOS5_PA_SYSTIMER 0x101C0000
-
-#define EXYNOS4_PA_WATCHDOG 0x10060000
-#define EXYNOS5_PA_WATCHDOG 0x101D0000
-
-#define EXYNOS4_PA_RTC 0x10070000
-
-#define EXYNOS4_PA_KEYPAD 0x100A0000
-
-#define EXYNOS4_PA_DMC0 0x10400000
-#define EXYNOS4_PA_DMC1 0x10410000
-
-#define EXYNOS4_PA_COMBINER 0x10440000
-#define EXYNOS5_PA_COMBINER 0x10440000
-
-#define EXYNOS4_PA_GIC_CPU 0x10480000
-#define EXYNOS4_PA_GIC_DIST 0x10490000
-#define EXYNOS5_PA_GIC_CPU 0x10480000
-#define EXYNOS5_PA_GIC_DIST 0x10490000
-
-#define EXYNOS4_PA_COREPERI 0x10500000
-#define EXYNOS4_PA_TWD 0x10500600
-#define EXYNOS4_PA_L2CC 0x10502000
-
-#define EXYNOS4_PA_MDMA0 0x10810000
-#define EXYNOS4_PA_MDMA1 0x12840000
-#define EXYNOS4_PA_PDMA0 0x12680000
-#define EXYNOS4_PA_PDMA1 0x12690000
-#define EXYNOS5_PA_MDMA0 0x10800000
-#define EXYNOS5_PA_MDMA1 0x11C10000
-#define EXYNOS5_PA_PDMA0 0x121A0000
-#define EXYNOS5_PA_PDMA1 0x121B0000
-
-#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
-#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
-#define EXYNOS4_PA_SPI0 0x13920000
-#define EXYNOS4_PA_SPI1 0x13930000
-#define EXYNOS4_PA_SPI2 0x13940000
-
-#define EXYNOS4_PA_GPIO1 0x11400000
-#define EXYNOS4_PA_GPIO2 0x11000000
-#define EXYNOS4_PA_GPIO3 0x03860000
-#define EXYNOS5_PA_GPIO1 0x11400000
-#define EXYNOS5_PA_GPIO2 0x13400000
-#define EXYNOS5_PA_GPIO3 0x10D10000
-#define EXYNOS5_PA_GPIO4 0x03860000
-
-#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
-
-#define EXYNOS4_PA_FIMD0 0x11C00000
-
-#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI 0x12550000
-
-#define EXYNOS4_PA_SATA 0x12560000
-#define EXYNOS4_PA_SATAPHY 0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
-
-#define EXYNOS4_PA_SROMC 0x12570000
-#define EXYNOS5_PA_SROMC 0x12250000
-
-#define EXYNOS4_PA_EHCI 0x12580000
-#define EXYNOS4_PA_OHCI 0x12590000
-#define EXYNOS4_PA_HSPHY 0x125B0000
-#define EXYNOS4_PA_MFC 0x13400000
-
-#define EXYNOS4_PA_UART 0x13800000
-#define EXYNOS5_PA_UART 0x12C00000
-
-#define EXYNOS4_PA_VP 0x12C00000
-#define EXYNOS4_PA_MIXER 0x12C10000
-#define EXYNOS4_PA_SDO 0x12C20000
-#define EXYNOS4_PA_HDMI 0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
-
-#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
-#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_ADC 0x13910000
-#define EXYNOS4_PA_ADC1 0x13911000
-
-#define EXYNOS4_PA_AC97 0x139A0000
-
-#define EXYNOS4_PA_SPDIF 0x139B0000
-
-#define EXYNOS4_PA_TIMER 0x139D0000
-#define EXYNOS5_PA_TIMER 0x12DD0000
-
-#define EXYNOS4_PA_SDRAM 0x40000000
-#define EXYNOS5_PA_SDRAM 0x40000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
-#define S3C_PA_RTC EXYNOS4_PA_RTC
-#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
-#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
-#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
-#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
-
-#define S5P_PA_EHCI EXYNOS4_PA_EHCI
-#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
-#define S5P_PA_JPEG EXYNOS4_PA_JPEG
-#define S5P_PA_G2D EXYNOS4_PA_G2D
-#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
-#define S5P_PA_HDMI EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
-#define S5P_PA_MFC EXYNOS4_PA_MFC
-#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_MIXER EXYNOS4_PA_MIXER
-#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDO EXYNOS4_PA_SDO
-#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
-#define S5P_PA_VP EXYNOS4_PA_VP
-
-#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
-#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
-
-/* Compatibility UART */
-
-#define EXYNOS4_PA_UART0 0x13800000
-#define EXYNOS4_PA_UART1 0x13810000
-#define EXYNOS4_PA_UART2 0x13820000
-#define EXYNOS4_PA_UART3 0x13830000
-#define EXYNOS4_SZ_UART SZ_256
-
-#define EXYNOS5_PA_UART0 0x12C00000
-#define EXYNOS5_PA_UART1 0x12C10000
-#define EXYNOS5_PA_UART2 0x12C20000
-#define EXYNOS5_PA_UART3 0x12C30000
-#define EXYNOS5_SZ_UART SZ_256
-
-#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/board/common/include/exynos/plat/cpu.h b/arch/arm/board/common/include/exynos/plat/cpu.h
deleted file mode 100644
index 2138a19b..00000000
--- a/arch/arm/board/common/include/exynos/plat/cpu.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief Exynos CPU support header
- *
- * Adapted from linux/arch/arm/plat-samsung/include/plat/cpu.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <b...@simtec.co.uk>
- *
- * Header file for Samsung CPU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __SAMSUNG_PLAT_CPU_H
-#define __SAMSUNG_PLAT_CPU_H
-
-#include <vmm_types.h>
-
-extern u32 samsung_cpu_id();
-
-#define S3C24XX_CPU_ID 0x32400000
-#define S3C24XX_CPU_MASK 0xFFF00000
-
-#define S3C6400_CPU_ID 0x36400000
-#define S3C6410_CPU_ID 0x36410000
-#define S3C64XX_CPU_MASK 0xFFFFF000
-
-#define S5P6440_CPU_ID 0x56440000
-#define S5P6450_CPU_ID 0x36450000
-#define S5P64XX_CPU_MASK 0xFFFFF000
-
-#define S5PC100_CPU_ID 0x43100000
-#define S5PC100_CPU_MASK 0xFFFFF000
-
-#define S5PV210_CPU_ID 0x43110000
-#define S5PV210_CPU_MASK 0xFFFFF000
-
-#define EXYNOS4210_CPU_ID 0x43210000
-#define EXYNOS4212_CPU_ID 0x43220000
-#define EXYNOS4412_CPU_ID 0xE4412200
-#define EXYNOS4_CPU_MASK 0xFFFE0000
-
-#define EXYNOS5250_SOC_ID 0x43520000
-#define EXYNOS5_SOC_MASK 0xFFFFF000
-
-#define IS_SAMSUNG_CPU(name, id, mask) \
-static inline int is_samsung_##name(void) \
-{ \
- return ((samsung_cpu_id() & mask) == (id & mask)); \
-}
-
-IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
-IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
-IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
-IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
-
-#define soc_is_s3c24xx() is_samsung_s3c24xx()
-
-#define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
-
-#define soc_is_s5p6440() is_samsung_s5p6440()
-
-#define soc_is_s5p6450() is_samsung_s5p6450()
-
-#define soc_is_s5pc100() is_samsung_s5pc100()
-
-#define soc_is_s5pv210() is_samsung_s5pv210()
-
-#define soc_is_exynos4210() is_samsung_exynos4210()
-
-#define soc_is_exynos4212() is_samsung_exynos4212()
-
-#define soc_is_exynos4412() is_samsung_exynos4412()
-
-#define EXYNOS4210_REV_0 (0x0)
-#define EXYNOS4210_REV_1_0 (0x10)
-#define EXYNOS4210_REV_1_1 (0x11)
-
-#define soc_is_exynos5250() is_samsung_exynos5250()
-
-extern void exynos_init_cpu(physical_addr_t cpuid_addr);
-
-extern unsigned int samsung_rev(void);
-
-#endif
diff --git a/arch/arm/board/common/include/exynos/plat/map-base.h b/arch/arm/board/common/include/exynos/plat/map-base.h
deleted file mode 100644
index ade89e8d..00000000
--- a/arch/arm/board/common/include/exynos/plat/map-base.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file map-base.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief S3C - Memory map definitions (virtual addresses)
- *
- * Adapded from linux/include/asm-arm/plat-s3c/map.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <b...@simtec.co.uk>
- *
- * S3C - Memory map definitions (virtual addresses)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_H
-#define __ASM_PLAT_MAP_H __FILE__
-
-/* Fit all our registers in at 0xF6000000 upwards, trying to use as
- * little of the VA space as possible so vmalloc and friends have a
- * better chance of getting memory.
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- */
-
-#define S3C_ADDR_BASE 0xF6000000
-
-#ifndef __ASSEMBLY__
-#define S3C_ADDR(x) ((void *)S3C_ADDR_BASE + (x))
-#else
-#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
-#endif
-
-#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
-#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
-#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
-#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
-#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
-#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
-
-/* This is used for the CPU specific mappings that may be needed, so that
- * they do not need to directly used S3C_ADDR() and thus make it easier to
- * modify the space for mapping.
- */
-#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
-
-#endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/board/common/include/exynos/plat/map-s3c.h b/arch/arm/board/common/include/exynos/plat/map-s3c.h
deleted file mode 100644
index 697cd48e..00000000
--- a/arch/arm/board/common/include/exynos/plat/map-s3c.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file map-s3c.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief S3C24XX - Memory map definitions
- *
- * Adapted from linux/arch/arm/plat-samsung/include/plat/map-s3c.h
- *
- * Copyright (c) 2008 Simtec Electronics
- * Ben Dooks <b...@simtec.co.uk>
- *
- * S3C24XX - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_S3C_H
-#define __ASM_PLAT_MAP_S3C_H __FILE__
-
-#define S3C24XX_VA_IRQ S3C_VA_IRQ
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C24XX_VA_UART S3C_VA_UART
-
-#define S3C24XX_VA_TIMER S3C_VA_TIMER
-#define S3C24XX_VA_CLKPWR S3C_VA_SYS
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-
-#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
-#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
-
-#define S3C2410_PA_UART (0x50000000)
-#define S3C24XX_PA_UART S3C2410_PA_UART
-
-#ifndef S3C_UART_OFFSET
-#define S3C_UART_OFFSET (0x400)
-#endif
-
-/*
- * GPIO ports
- *
- * the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 mapping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-
-#define S3C2410_PA_GPIO (0x56000000)
-#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
-
-#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
-
-#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
-#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
-
-#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
-
-/*
- * ISA style IO, for each machine to sort out mappings for,
- * if it implements it. We reserve two 16M regions for ISA.
- */
-
-#define S3C2410_ADDR(x) S3C_ADDR(x)
-
-#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
-
-/* deal with the registers that move under the 2412/2413 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
-
-#include <exynos/plat/map-s5p.h>
-
-#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/board/common/include/exynos/plat/map-s5p.h b/arch/arm/board/common/include/exynos/plat/map-s5p.h
deleted file mode 100644
index 5767430a..00000000
--- a/arch/arm/board/common/include/exynos/plat/map-s5p.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file map-s5p.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief S5P - Memory map definitions
- *
- * Adapted frome linux/arch/arm/plat-samsung/include/plat/map-s5p.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * S5P - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_S5P_H
-#define __ASM_PLAT_MAP_S5P_H __FILE__
-
-#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
-#define S5P_VA_CMU S3C_ADDR(0x02100000)
-#define S5P_VA_PMU S3C_ADDR(0x02180000)
-#define S5P_VA_GPIO S3C_ADDR(0x02200000)
-#define S5P_VA_GPIO1 S5P_VA_GPIO
-#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
-#define S5P_VA_GPIO3 S3C_ADDR(0x02280000)
-
-#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
-#define S5P_VA_DMC0 S3C_ADDR(0x02440000)
-#define S5P_VA_DMC1 S3C_ADDR(0x02480000)
-#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
-
-#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000)
-#define S5P_VA_L2CC S3C_ADDR(0x02600000)
-
-#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000)
-#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
-
-#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
-#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
-#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
-#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
-
-#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
-#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
-
-#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
-#define VA_VIC0 VA_VIC(0)
-#define VA_VIC1 VA_VIC(1)
-#define VA_VIC2 VA_VIC(2)
-#define VA_VIC3 VA_VIC(3)
-
-#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_VA_UART0 S5P_VA_UART(0)
-#define S5P_VA_UART1 S5P_VA_UART(1)
-#define S5P_VA_UART2 S5P_VA_UART(2)
-#define S5P_VA_UART3 S5P_VA_UART(3)
-
-#ifndef S3C_UART_OFFSET
-#define S3C_UART_OFFSET (0x400)
-#endif
-
-#include <exynos/plat/map-s3c.h>
-
-#endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/board/common/include/exynos/regs-clock.h b/arch/arm/board/common/include/exynos/regs-clock.h
deleted file mode 100644
index 20132570..00000000
--- a/arch/arm/board/common/include/exynos/regs-clock.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file regs-clock.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief EXYNOS4 Clock register definitions
- *
- * Adapted from linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <exynos/plat/cpu.h>
-#include <exynos/mach/map.h>
-
-#define EXYNOS_CLKREG(x) (x)
-
-#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
-#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
-#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
-
-#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
-#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
-#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
-
-#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
-#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
-
-#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
-#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
-#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
-#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
-
-#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
-#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
-#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
-#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
-#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
-#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
-#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
-#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
-#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
-#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
-#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
-#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
-
-#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
-#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
-#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
-#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
-#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
-#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
-#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
-#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
-
-#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
-#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
-#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
-#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
-#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
-#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
-#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
-#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
-#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
-#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
-#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
-#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
-#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
-#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
-#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
-#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
-#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
-#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
-#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
-
-#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
-#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
-
-#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
-#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
-#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
-#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
-#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
-#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
- EXYNOS_CLKREG(0x0C930) : \
- EXYNOS_CLKREG(0x04930))
-#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
-#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
-#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
-#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
-#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
-#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
-#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
- EXYNOS_CLKREG(0x0C960) : \
- EXYNOS_CLKREG(0x08960))
-#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
-#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
-#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
-
-#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
-#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
-#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
-#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
-#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
-#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
-#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
-
-#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
-#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
-
-#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
-#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
- EXYNOS_CLKREG(0x14004) : \
- EXYNOS_CLKREG(0x10008))
-#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
-#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
-#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
- EXYNOS_CLKREG(0x14108) : \
- EXYNOS_CLKREG(0x10108))
-#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
- EXYNOS_CLKREG(0x1410C) : \
- EXYNOS_CLKREG(0x1010C))
-
-#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
-#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
-
-#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
-#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
-#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
-
-#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
-#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
-
-#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
-#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
-
-#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
-
-#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
-#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
-#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
-#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
-
-#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
-#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
-
-#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
-#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
-
-#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
-#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
-#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
-#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
-#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
-#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
-#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
-#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
-#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
-#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
-#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
-
-#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
-#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
-#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
-#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
-#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
-#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
-
-#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
-#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
-#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
-#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
-#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
-#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
-
-#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
-#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
-
-#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
-#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
-
-#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
-#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
-#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
-#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
-
-#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
-#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
-
-/* Only for EXYNOS4210 */
-
-#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
-#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
-#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
-#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
-
-/* Only for EXYNOS4212 */
-
-#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
-
-#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
-
-#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
-#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
-
-/* For EXYNOS5250 */
-
-#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
-#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
-#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
-#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
-#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
-#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
-
-#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
-#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
-
-#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
-
-#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
-
-#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
-#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
-#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
-#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
-#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
-#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
-#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
-
-#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
-#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
-#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
-#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
-#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
-#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
-#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
-#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
-#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
-#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
-#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
-
-#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
-#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
-#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
-#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
-#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
-#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
-#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
-
-#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
-#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
-#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
-#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
-#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
-#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
-#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
-#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
-#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
-#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
-#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
-#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
-#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
-#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
-#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
-#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
-#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
-
-#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
-#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
-#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
-#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
-#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
-#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
-#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
-#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
-#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
-#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
-#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
-#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
-#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
-
-#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
-#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
-#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
-
-#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
-
-#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
-
-#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
-
-/* Compatibility defines and inclusion */
-
-#include <exynos/regs-pmu.h>
-
-#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/board/common/include/exynos/regs-mct.h b/arch/arm/board/common/include/exynos/regs-mct.h
deleted file mode 100644
index 94a8387a..00000000
--- a/arch/arm/board/common/include/exynos/regs-mct.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file regs-mct.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief EXYNOS4 MCT configutation
- *
- * Adapted from arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <exynos/mach/map.h>
-
-#define EXYNOS4_MCTREG(x) (x)
-
-#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET (0x00)
-#define MCT_L_ICNTB_OFFSET (0x08)
-#define MCT_L_TCON_OFFSET (0x20)
-#define MCT_L_INT_CSTAT_OFFSET (0x30)
-#define MCT_L_INT_ENB_OFFSET (0x34)
-#define MCT_L_WSTAT_OFFSET (0x40)
-
-#define MCT_G_TCON_START (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
-#define MCT_L_TCON_INT_START (1 << 1)
-#define MCT_L_TCON_TIMER_START (1 << 0)
-
-#define MCT_L_ICNTB_MANUAL_UPDATE (1 << 31)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/board/common/include/exynos/regs-pmu.h b/arch/arm/board/common/include/exynos/regs-pmu.h
deleted file mode 100644
index 259bba7d..00000000
--- a/arch/arm/board/common/include/exynos/regs-pmu.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file regs-pmu.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief EXYNOS4 Power management unit definition
- *
- * Adapted from arch/arm/mach-exynos4/include/mach/regs-pmu.h
- *
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - Power management unit definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_PMU_H
-#define __ASM_ARCH_REGS_PMU_H __FILE__
-
-#include <exynos/mach/map.h>
-
-#define S5P_PMUREG(x) (x)
-
-#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
-
-#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
-
-#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
-
-#define S5P_USE_STANDBY_WFI0 (1 << 16)
-#define S5P_USE_STANDBY_WFI1 (1 << 17)
-#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
-#define S5P_USE_STANDBY_WFE0 (1 << 24)
-#define S5P_USE_STANDBY_WFE1 (1 << 25)
-#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
-
-#define S5P_SWRESET S5P_PMUREG(0x0400)
-#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
-
-#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
-#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
-#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
-
-#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
-#define S5P_HDMI_PHY_ENABLE (1 << 0)
-
-#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
-#define S5P_DAC_PHY_ENABLE (1 << 0)
-
-#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
-#define S5P_MIPI_DPHY_ENABLE (1 << 0)
-#define S5P_MIPI_DPHY_SRESETN (1 << 1)
-#define S5P_MIPI_DPHY_MRESETN (1 << 2)
-
-#define S5P_INFORM0 S5P_PMUREG(0x0800)
-#define S5P_INFORM1 S5P_PMUREG(0x0804)
-#define S5P_INFORM2 S5P_PMUREG(0x0808)
-#define S5P_INFORM3 S5P_PMUREG(0x080C)
-#define S5P_INFORM4 S5P_PMUREG(0x0810)
-#define S5P_INFORM5 S5P_PMUREG(0x0814)
-#define S5P_INFORM6 S5P_PMUREG(0x0818)
-#define S5P_INFORM7 S5P_PMUREG(0x081C)
-
-#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
-#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
-#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
-#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
-#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
-#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
-#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
-#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
-#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
-#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
-#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
-#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
-#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
-#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
-#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
-#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
-#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
-#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
-#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
-#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
-#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
-#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
-#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
-#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
-#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
-#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
-#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
-#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
-#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
-#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
-#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
-#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
-#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
-#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
-#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
-#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
-#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
-#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
-#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
-#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
-#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
-#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
-#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
-#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
-#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
-#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
-#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
-#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
-#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
-#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
-#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
-#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
-#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
-#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
-#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
-#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
-#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
-#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
-#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
-#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
-#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
-#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
-#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
-
-#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
-#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
-#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
-#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
-
-#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
-#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
-#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
-#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
-#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
-#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
-#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
-#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
-#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
-#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
-#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
-
-#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
-#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
-#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
-#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
-#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
-#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
-#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
-
-#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
-#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
-#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
-#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
-#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
-#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
-
-#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
-#define S5P_CORE_LOCAL_PWR_EN 0x3
-#define S5P_INT_LOCAL_PWR_EN 0x7
-
-#define S5P_CHECK_SLEEP 0x00000BAD
-
-/* Only for EXYNOS4210 */
-#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704)
-#define S5P_USBDEVICE_PHY_ENABLE (1 << 0)
-
-#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE (1 << 0)
-
-#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
-
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
-#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
-
-#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
-
-/* Only for EXYNOS4x12 */
-#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
-#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
-#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
-#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
-#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
-#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
-#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
-#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
-#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
-#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
-#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
-#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
-#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
-#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
-#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
-#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
-#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
-#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
-#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
-#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
-#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
-#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
-#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
-#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
-#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
-#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
-#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
-#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
-
-#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
-#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
-#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
-#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
-#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
-#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
-#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
-#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
-#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
-#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
-
-/* Only for EXYNOS4412 */
-#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
-#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
-#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
-#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
-#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
-#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
-
-/* For EXYNOS5 */
-
-#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
-
-#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
-#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
-
-#define EXYNOS5_SYS_WDTRESET (1 << 20)
-
-#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
-#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
-#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
-#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
-#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
-#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
-#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
-#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
-#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
-#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
-#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
-#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
-#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
-#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
-#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
-#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
-#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
-#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
-#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
-#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
-#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
-#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
-#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
-#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
-#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
-#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
-#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
-#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
-#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
-#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
-#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
-#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
-#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
-#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
-#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
-#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
-#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
-#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
-#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
-#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
-#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
-#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
-#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
-#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
-#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
-#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
-#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
-#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
-#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
-#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
-#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
-#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
-#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
-#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
-#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
-#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
-#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
-#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
-#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
-#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
-#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
-#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
-#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
-#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
-#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
-#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
-#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
-#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
-#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
-#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
-#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
-#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
-#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
-#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
-#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
-#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
-#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
-#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
-#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
-#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
-#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
-#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
-#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
-#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
-#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
-#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
-#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
-#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
-#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
-#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
-#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
-#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
-#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
-#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
-#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
-
-#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
-#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
-#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
-#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
-#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
-#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
-#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
-#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
-#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
-#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
-#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
-#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
-#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
-#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
-#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
-#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
-#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
-#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
-
-#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
-#define EXYNOS5_USE_SC_COUNTER (1 << 0)
-
-#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
-#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
-
-#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
-#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
-
-#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
-
-#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/board/common/include/exynos/regs-rtc.h b/arch/arm/board/common/include/exynos/regs-rtc.h
deleted file mode 100644
index c401eb8f..00000000
--- a/arch/arm/board/common/include/exynos/regs-rtc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file regs-rtc.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief Exynos RTC register definition
- *
- * Adapted from linux/arch/arm/mach-s3c2410/include/mach/regs-rtc.h
- *
- * Copyright (c) 2003 Simtec Electronics <li...@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Internal RTC register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_RTC_H
-#define __ASM_ARCH_REGS_RTC_H __FILE__
-
-#define S3C2410_RTCREG(x) (x)
-#define S3C2410_INTP S3C2410_RTCREG(0x30)
-#define S3C2410_INTP_ALM (1 << 1)
-#define S3C2410_INTP_TIC (1 << 0)
-
-#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN (1 << 0)
-#define S3C2410_RTCCON_CNTSEL (1 << 2)
-#define S3C2410_RTCCON_CLKRST (1 << 3)
-#define S3C2443_RTCCON_TICSEL (1 << 4)
-#define S3C64XX_RTCCON_TICEN (1 << 8)
-
-#define S3C2410_TICNT S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE (1 << 7)
-
-/* S3C2443: tick count is 15 bit wide
- * TICNT[6:0] contains upper 7 bits
- * TICNT1[7:0] contains lower 8 bits
- */
-#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8)
-#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C)
-#define S3C2443_TICNT1_PART(x) (x & 0xff)
-
-/* S3C2416: tick count is 32 bit wide
- * TICNT[6:0] contains bits [14:8]
- * TICNT1[7:0] contains lower 8 bits
- * TICNT2[16:0] contains upper 17 bits
- */
-#define S3C2416_TICNT2 S3C2410_RTCREG(0x48)
-#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15)
-
-#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN (1 << 6)
-#define S3C2410_RTCALM_YEAREN (1 << 5)
-#define S3C2410_RTCALM_MONEN (1 << 4)
-#define S3C2410_RTCALM_DAYEN (1 << 3)
-#define S3C2410_RTCALM_HOUREN (1 << 2)
-#define S3C2410_RTCALM_MINEN (1 << 1)
-#define S3C2410_RTCALM_SECEN (1 << 0)
-
-#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
-
-#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/board/common/include/exynos/regs-watchdog.h b/arch/arm/board/common/include/exynos/regs-watchdog.h
deleted file mode 100644
index 508c3054..00000000
--- a/arch/arm/board/common/include/exynos/regs-watchdog.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file regs-watchdog.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief EXYNOS4 Watchdog timer control
- *
- * Adapted from arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <li...@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-
-#define S3C_WDOGREG(x) ((x))
-
-#define S3C2410_WTCON S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT S3C_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN (0x01)
-#define S3C2410_WTCON_INTEN (1<<2)
-#define S3C2410_WTCON_ENABLE (1<<5)
-
-#define S3C2410_WTCON_DIV16 (0<<3)
-#define S3C2410_WTCON_DIV32 (1<<3)
-#define S3C2410_WTCON_DIV64 (2<<3)
-#define S3C2410_WTCON_DIV128 (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-
diff --git a/arch/arm/board/common/include/imx-common.h b/arch/arm/board/common/include/imx-common.h
deleted file mode 100644
index 4750fe90..00000000
--- a/arch/arm/board/common/include/imx-common.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/common.h
- *
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * @file imx-common.h
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX common header
- */
-
-#ifndef __ASM_ARCH_MXC_COMMON_H__
-#define __ASM_ARCH_MXC_COMMON_H__
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-
-#define __raw_readl readl
-#define __raw_writel writel
-
-#define do_div udiv64
-
-
-void mxc_timer_init(void __iomem *, int);
-unsigned int imx_get_soc_revision(void);
-struct device *imx_soc_device_init(void);
-
-enum mxc_cpu_pwr_mode {
- WAIT_CLOCKED, /* wfi only */
- WAIT_UNCLOCKED, /* WAIT */
- WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
- STOP_POWER_ON, /* just STOP */
- STOP_POWER_OFF, /* STOP + SRPG */
-};
-
-void imx_print_silicon_rev(const char *cpu, int srev);
-void imx_gpc_init(void);
-void imx_gpc_irq_mask(struct irq_data *d);
-void imx_gpc_irq_unmask(struct irq_data *d);
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_pm_set_ccm_base(void __iomem *base);
-struct clk* imx_clk_get(unsigned int clkid);
-void imx_gpc_clocks_init(void);
-
-#endif
diff --git a/arch/arm/board/common/include/imx-hardware.h b/arch/arm/board/common/include/imx-hardware.h
deleted file mode 100644
index b20965c0..00000000
--- a/arch/arm/board/common/include/imx-hardware.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/hardware.h
- *
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, ker...@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- *
- * @file imx-hardware.h
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX hardware specific header
- */
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#define __ASM_ARCH_MXC_HARDWARE_H__
-
-#include "mxc.h"
-
-#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/board/common/include/imx6q-phy.h b/arch/arm/board/common/include/imx6q-phy.h
deleted file mode 100644
index 8ede7397..00000000
--- a/arch/arm/board/common/include/imx6q-phy.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * Copyright (C) 2015 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx6q-phy.h
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX6 Sabrelite board specific code for PHY
- *
- * Adapted from linux/arch/arm/mach-imx/mach-imx6q.c
- *
- * The original source is licensed under GPL.
- *
- */
-
-#ifndef IMX6Q_PHY_H__
-# define IMX6Q_PHY_H__
-
-# ifdef CONFIG_PHYLIB
-
-void __init imx6q_enet_phy_init(void);
-
-# else /* CONFIG_PHYLIB */
-
-static inline void __init imx6q_enet_phy_init(void)
-{
-}
-
-# endif /* CONFIG_PHYLIB */
-#endif /* IMX6Q_PHY_H__ */
diff --git a/arch/arm/board/common/include/imx6qdl-clock.h b/arch/arm/board/common/include/imx6qdl-clock.h
deleted file mode 100644
index 43134165..00000000
--- a/arch/arm/board/common/include/imx6qdl-clock.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __CLK_IMX_IMX6QDL_H
-#define __CLK_IMX_IMX6QDL_H
-
-#define IMX6QDL_CLK_DUMMY 0
-#define IMX6QDL_CLK_CKIL 1
-#define IMX6QDL_CLK_CKIH 2
-#define IMX6QDL_CLK_OSC 3
-#define IMX6QDL_CLK_PLL2_PFD0_352M 4
-#define IMX6QDL_CLK_PLL2_PFD1_594M 5
-#define IMX6QDL_CLK_PLL2_PFD2_396M 6
-#define IMX6QDL_CLK_PLL3_PFD0_720M 7
-#define IMX6QDL_CLK_PLL3_PFD1_540M 8
-#define IMX6QDL_CLK_PLL3_PFD2_508M 9
-#define IMX6QDL_CLK_PLL3_PFD3_454M 10
-#define IMX6QDL_CLK_PLL2_198M 11
-#define IMX6QDL_CLK_PLL3_120M 12
-#define IMX6QDL_CLK_PLL3_80M 13
-#define IMX6QDL_CLK_PLL3_60M 14
-#define IMX6QDL_CLK_TWD 15
-#define IMX6QDL_CLK_STEP 16
-#define IMX6QDL_CLK_PLL1_SW 17
-#define IMX6QDL_CLK_PERIPH_PRE 18
-#define IMX6QDL_CLK_PERIPH2_PRE 19
-#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
-#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
-#define IMX6QDL_CLK_AXI_SEL 22
-#define IMX6QDL_CLK_ESAI_SEL 23
-#define IMX6QDL_CLK_ASRC_SEL 24
-#define IMX6QDL_CLK_SPDIF_SEL 25
-#define IMX6QDL_CLK_GPU2D_AXI 26
-#define IMX6QDL_CLK_GPU3D_AXI 27
-#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
-#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
-#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
-#define IMX6QDL_CLK_IPU1_SEL 31
-#define IMX6QDL_CLK_IPU2_SEL 32
-#define IMX6QDL_CLK_LDB_DI0_SEL 33
-#define IMX6QDL_CLK_LDB_DI1_SEL 34
-#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
-#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
-#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
-#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
-#define IMX6QDL_CLK_IPU1_DI0_SEL 39
-#define IMX6QDL_CLK_IPU1_DI1_SEL 40
-#define IMX6QDL_CLK_IPU2_DI0_SEL 41
-#define IMX6QDL_CLK_IPU2_DI1_SEL 42
-#define IMX6QDL_CLK_HSI_TX_SEL 43
-#define IMX6QDL_CLK_PCIE_AXI_SEL 44
-#define IMX6QDL_CLK_SSI1_SEL 45
-#define IMX6QDL_CLK_SSI2_SEL 46
-#define IMX6QDL_CLK_SSI3_SEL 47
-#define IMX6QDL_CLK_USDHC1_SEL 48
-#define IMX6QDL_CLK_USDHC2_SEL 49
-#define IMX6QDL_CLK_USDHC3_SEL 50
-#define IMX6QDL_CLK_USDHC4_SEL 51
-#define IMX6QDL_CLK_ENFC_SEL 52
-#define IMX6QDL_CLK_EMI_SEL 53
-#define IMX6QDL_CLK_EMI_SLOW_SEL 54
-#define IMX6QDL_CLK_VDO_AXI_SEL 55
-#define IMX6QDL_CLK_VPU_AXI_SEL 56
-#define IMX6QDL_CLK_CKO1_SEL 57
-#define IMX6QDL_CLK_PERIPH 58
-#define IMX6QDL_CLK_PERIPH2 59
-#define IMX6QDL_CLK_PERIPH_CLK2 60
-#define IMX6QDL_CLK_PERIPH2_CLK2 61
-#define IMX6QDL_CLK_IPG 62
-#define IMX6QDL_CLK_IPG_PER 63
-#define IMX6QDL_CLK_ESAI_PRED 64
-#define IMX6QDL_CLK_ESAI_PODF 65
-#define IMX6QDL_CLK_ASRC_PRED 66
-#define IMX6QDL_CLK_ASRC_PODF 67
-#define IMX6QDL_CLK_SPDIF_PRED 68
-#define IMX6QDL_CLK_SPDIF_PODF 69
-#define IMX6QDL_CLK_CAN_ROOT 70
-#define IMX6QDL_CLK_ECSPI_ROOT 71
-#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
-#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
-#define IMX6QDL_CLK_GPU3D_SHADER 74
-#define IMX6QDL_CLK_IPU1_PODF 75
-#define IMX6QDL_CLK_IPU2_PODF 76
-#define IMX6QDL_CLK_LDB_DI0_PODF 77
-#define IMX6QDL_CLK_LDB_DI1_PODF 78
-#define IMX6QDL_CLK_IPU1_DI0_PRE 79
-#define IMX6QDL_CLK_IPU1_DI1_PRE 80
-#define IMX6QDL_CLK_IPU2_DI0_PRE 81
-#define IMX6QDL_CLK_IPU2_DI1_PRE 82
-#define IMX6QDL_CLK_HSI_TX_PODF 83
-#define IMX6QDL_CLK_SSI1_PRED 84
-#define IMX6QDL_CLK_SSI1_PODF 85
-#define IMX6QDL_CLK_SSI2_PRED 86
-#define IMX6QDL_CLK_SSI2_PODF 87
-#define IMX6QDL_CLK_SSI3_PRED 88
-#define IMX6QDL_CLK_SSI3_PODF 89
-#define IMX6QDL_CLK_UART_SERIAL_PODF 90
-#define IMX6QDL_CLK_USDHC1_PODF 91
-#define IMX6QDL_CLK_USDHC2_PODF 92
-#define IMX6QDL_CLK_USDHC3_PODF 93
-#define IMX6QDL_CLK_USDHC4_PODF 94
-#define IMX6QDL_CLK_ENFC_PRED 95
-#define IMX6QDL_CLK_ENFC_PODF 96
-#define IMX6QDL_CLK_EMI_PODF 97
-#define IMX6QDL_CLK_EMI_SLOW_PODF 98
-#define IMX6QDL_CLK_VPU_AXI_PODF 99
-#define IMX6QDL_CLK_CKO1_PODF 100
-#define IMX6QDL_CLK_AXI 101
-#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
-#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
-#define IMX6QDL_CLK_ARM 104
-#define IMX6QDL_CLK_AHB 105
-#define IMX6QDL_CLK_APBH_DMA 106
-#define IMX6QDL_CLK_ASRC 107
-#define IMX6QDL_CLK_CAN1_IPG 108
-#define IMX6QDL_CLK_CAN1_SERIAL 109
-#define IMX6QDL_CLK_CAN2_IPG 110
-#define IMX6QDL_CLK_CAN2_SERIAL 111
-#define IMX6QDL_CLK_ECSPI1 112
-#define IMX6QDL_CLK_ECSPI2 113
-#define IMX6QDL_CLK_ECSPI3 114
-#define IMX6QDL_CLK_ECSPI4 115
-#define IMX6Q_CLK_ECSPI5 116
-#define IMX6DL_CLK_I2C4 117
-#define IMX6QDL_CLK_ENET 118
-#define IMX6QDL_CLK_ESAI_EXTAL 119
-#define IMX6QDL_CLK_GPT_IPG 120
-#define IMX6QDL_CLK_GPT_IPG_PER 121
-#define IMX6QDL_CLK_GPU2D_CORE 122
-#define IMX6QDL_CLK_GPU3D_CORE 123
-#define IMX6QDL_CLK_HDMI_IAHB 124
-#define IMX6QDL_CLK_HDMI_ISFR 125
-#define IMX6QDL_CLK_I2C1 126
-#define IMX6QDL_CLK_I2C2 127
-#define IMX6QDL_CLK_I2C3 128
-#define IMX6QDL_CLK_IIM 129
-#define IMX6QDL_CLK_ENFC 130
-#define IMX6QDL_CLK_IPU1 131
-#define IMX6QDL_CLK_IPU1_DI0 132
-#define IMX6QDL_CLK_IPU1_DI1 133
-#define IMX6QDL_CLK_IPU2 134
-#define IMX6QDL_CLK_IPU2_DI0 135
-#define IMX6QDL_CLK_LDB_DI0 136
-#define IMX6QDL_CLK_LDB_DI1 137
-#define IMX6QDL_CLK_IPU2_DI1 138
-#define IMX6QDL_CLK_HSI_TX 139
-#define IMX6QDL_CLK_MLB 140
-#define IMX6QDL_CLK_MMDC_CH0_AXI 141
-#define IMX6QDL_CLK_MMDC_CH1_AXI 142
-#define IMX6QDL_CLK_OCRAM 143
-#define IMX6QDL_CLK_OPENVG_AXI 144
-#define IMX6QDL_CLK_PCIE_AXI 145
-#define IMX6QDL_CLK_PWM1 146
-#define IMX6QDL_CLK_PWM2 147
-#define IMX6QDL_CLK_PWM3 148
-#define IMX6QDL_CLK_PWM4 149
-#define IMX6QDL_CLK_PER1_BCH 150
-#define IMX6QDL_CLK_GPMI_BCH_APB 151
-#define IMX6QDL_CLK_GPMI_BCH 152
-#define IMX6QDL_CLK_GPMI_IO 153
-#define IMX6QDL_CLK_GPMI_APB 154
-#define IMX6QDL_CLK_SATA 155
-#define IMX6QDL_CLK_SDMA 156
-#define IMX6QDL_CLK_SPBA 157
-#define IMX6QDL_CLK_SSI1 158
-#define IMX6QDL_CLK_SSI2 159
-#define IMX6QDL_CLK_SSI3 160
-#define IMX6QDL_CLK_UART_IPG 161
-#define IMX6QDL_CLK_UART_SERIAL 162
-#define IMX6QDL_CLK_USBOH3 163
-#define IMX6QDL_CLK_USDHC1 164
-#define IMX6QDL_CLK_USDHC2 165
-#define IMX6QDL_CLK_USDHC3 166
-#define IMX6QDL_CLK_USDHC4 167
-#define IMX6QDL_CLK_VDO_AXI 168
-#define IMX6QDL_CLK_VPU_AXI 169
-#define IMX6QDL_CLK_CKO1 170
-#define IMX6QDL_CLK_PLL1_SYS 171
-#define IMX6QDL_CLK_PLL2_BUS 172
-#define IMX6QDL_CLK_PLL3_USB_OTG 173
-#define IMX6QDL_CLK_PLL4_AUDIO 174
-#define IMX6QDL_CLK_PLL5_VIDEO 175
-#define IMX6QDL_CLK_PLL8_MLB 176
-#define IMX6QDL_CLK_PLL7_USB_HOST 177
-#define IMX6QDL_CLK_PLL6_ENET 178
-#define IMX6QDL_CLK_SSI1_IPG 179
-#define IMX6QDL_CLK_SSI2_IPG 180
-#define IMX6QDL_CLK_SSI3_IPG 181
-#define IMX6QDL_CLK_ROM 182
-#define IMX6QDL_CLK_USBPHY1 183
-#define IMX6QDL_CLK_USBPHY2 184
-#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 185
-#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 186
-#define IMX6QDL_CLK_SATA_REF 187
-#define IMX6QDL_CLK_SATA_REF_100M 188
-#define IMX6QDL_CLK_PCIE_REF 189
-#define IMX6QDL_CLK_PCIE_REF_125M 190
-#define IMX6QDL_CLK_ENET_REF 191
-#define IMX6QDL_CLK_USBPHY1_GATE 192
-#define IMX6QDL_CLK_USBPHY2_GATE 193
-#define IMX6QDL_CLK_PLL4_POST_DIV 194
-#define IMX6QDL_CLK_PLL5_POST_DIV 195
-#define IMX6QDL_CLK_PLL5_VIDEO_DIV 196
-#define IMX6QDL_CLK_EIM_SLOW 197
-#define IMX6QDL_CLK_SPDIF 198
-#define IMX6QDL_CLK_CKO2_SEL 199
-#define IMX6QDL_CLK_CKO2_PODF 200
-#define IMX6QDL_CLK_CKO2 201
-#define IMX6QDL_CLK_CKO 202
-#define IMX6QDL_CLK_VDOA 203
-#define IMX6QDL_CLK_PLL4_AUDIO_DIV 204
-#define IMX6QDL_CLK_LVDS1_SEL 205
-#define IMX6QDL_CLK_LVDS2_SEL 206
-#define IMX6QDL_CLK_LVDS1_GATE 207
-#define IMX6QDL_CLK_LVDS2_GATE 208
-#define IMX6QDL_CLK_ESAI_IPG 209
-#define IMX6QDL_CLK_ESAI_MEM 210
-#define IMX6QDL_CLK_ASRC_IPG 211
-#define IMX6QDL_CLK_ASRC_MEM 212
-#define IMX6QDL_CLK_END 213
-
-#endif /* __CLK_IMX_IMX6QDL_H */
diff --git a/arch/arm/board/common/include/mxc.h b/arch/arm/board/common/include/mxc.h
deleted file mode 100644
index 26ed1355..00000000
--- a/arch/arm/board/common/include/mxc.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * Adapted from Linux Kernel 3.13.6 arch/arm/mach-imx/mxc.h
- *
- * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 Juergen Beisert (ker...@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- *
- * @file mxc.h
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX definitions
- */
-
-#ifndef __ASM_ARCH_MXC_H__
-#define __ASM_ARCH_MXC_H__
-
-#include <linux/types.h>
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-#define MXC_CPU_MX1 1
-#define MXC_CPU_MX21 21
-#define MXC_CPU_MX25 25
-#define MXC_CPU_MX27 27
-#define MXC_CPU_MX31 31
-#define MXC_CPU_MX35 35
-#define MXC_CPU_MX51 51
-#define MXC_CPU_MX53 53
-#define MXC_CPU_IMX6SL 0x60
-#define MXC_CPU_IMX6DL 0x61
-#define MXC_CPU_IMX6Q 0x63
-
-#define IMX_CHIP_REVISION_1_0 0x10
-#define IMX_CHIP_REVISION_1_1 0x11
-#define IMX_CHIP_REVISION_1_2 0x12
-#define IMX_CHIP_REVISION_1_3 0x13
-#define IMX_CHIP_REVISION_2_0 0x20
-#define IMX_CHIP_REVISION_2_1 0x21
-#define IMX_CHIP_REVISION_2_2 0x22
-#define IMX_CHIP_REVISION_2_3 0x23
-#define IMX_CHIP_REVISION_3_0 0x30
-#define IMX_CHIP_REVISION_3_1 0x31
-#define IMX_CHIP_REVISION_3_2 0x32
-#define IMX_CHIP_REVISION_3_3 0x33
-#define IMX_CHIP_REVISION_UNKNOWN 0xff
-
-#ifndef __ASSEMBLY__
-extern unsigned int __mxc_cpu_type;
-#endif
-
-#ifdef CONFIG_SOC_IMX1
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX1
-# endif
-# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
-#else
-# define cpu_is_mx1() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX21
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX21
-# endif
-# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
-#else
-# define cpu_is_mx21() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX25
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX25
-# endif
-# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
-#else
-# define cpu_is_mx25() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX27
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX27
-# endif
-# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
-#else
-# define cpu_is_mx27() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX31
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX31
-# endif
-# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
-#else
-# define cpu_is_mx31() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX35
-# endif
-# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
-#else
-# define cpu_is_mx35() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX51
-# endif
-# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
-#else
-# define cpu_is_mx51() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX53
-# endif
-# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
-#else
-# define cpu_is_mx53() (0)
-#endif
-
-#ifndef __ASSEMBLY__
-static inline bool cpu_is_imx6sl(void)
-{
- return __mxc_cpu_type == MXC_CPU_IMX6SL;
-}
-
-static inline bool cpu_is_imx6dl(void)
-{
- return __mxc_cpu_type == MXC_CPU_IMX6DL;
-}
-
-static inline bool cpu_is_imx6q(void)
-{
- return __mxc_cpu_type == MXC_CPU_IMX6Q;
-}
-
-struct cpu_op {
- u32 cpu_rate;
-};
-
-int tzic_enable_wake(void);
-
-extern struct cpu_op *(*get_cpu_op)(int *op);
-#endif
-
-#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
-#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
-
-#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/board/common/include/mxc_dispdrv.h b/arch/arm/board/common/include/mxc_dispdrv.h
deleted file mode 100644
index d3824563..00000000
--- a/arch/arm/board/common/include/mxc_dispdrv.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MXC_DISPDRV_H__
-#define __MXC_DISPDRV_H__
-
-#include <linux/fb.h>
-
-struct mxc_dispdrv_handle {
- struct mxc_dispdrv_driver *drv;
-};
-
-struct mxc_dispdrv_setting {
- /*input-feedback parameter*/
- struct fb_info *fbi;
- int if_fmt;
- int default_bpp;
- char *dft_mode_str;
-
- /*feedback parameter*/
- int dev_id;
- int disp_id;
-};
-
-struct mxc_dispdrv_driver {
- const char *name;
- int (*init) (struct mxc_dispdrv_handle *, struct mxc_dispdrv_setting *);
- /* deferred operations after dev_id and disp_id pass usage check */
- int (*post_init) (struct mxc_dispdrv_handle *, int dev_id, int disp_id);
- void (*deinit) (struct mxc_dispdrv_handle *);
- /* display driver enable function for extension */
- int (*enable) (struct mxc_dispdrv_handle *);
- /* display driver disable function, called at early part of fb_blank */
- void (*disable) (struct mxc_dispdrv_handle *);
- /* display driver setup function, called at early part of fb_set_par */
- int (*setup) (struct mxc_dispdrv_handle *, struct fb_info *fbi);
-};
-
-struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv);
-int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle);
-struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
- struct mxc_dispdrv_setting *setting);
-void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle);
-int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data);
-void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle);
-#endif
diff --git a/arch/arm/board/common/include/omap/sdrc.h b/arch/arm/board/common/include/omap/sdrc.h
deleted file mode 100644
index 3600eea7..00000000
--- a/arch/arm/board/common/include/omap/sdrc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file sdrc.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code for OMAP SDRC controller
- */
-
-#ifndef __OMAP_SDRC_H_
-#define __OMAP_SDRC_H_
-
-#include <vmm_types.h>
-
-/** SDRC register space size */
-#define SDRC_REG_SIZE 0x1000
-
-/** SDRC register offsets */
-#define SDRC_SYSCONFIG 0x010
-#define SDRC_CS_CFG 0x040
-#define SDRC_SHARING 0x044
-#define SDRC_ERR_TYPE 0x04C
-#define SDRC_DLLA_CTRL 0x060
-#define SDRC_DLLA_STATUS 0x064
-#define SDRC_DLLB_CTRL 0x068
-#define SDRC_DLLB_STATUS 0x06C
-#define SDRC_POWER 0x070
-#define SDRC_MCFG_0 0x080
-#define SDRC_MR_0 0x084
-#define SDRC_EMR2_0 0x08c
-#define SDRC_ACTIM_CTRL_A_0 0x09c
-#define SDRC_ACTIM_CTRL_B_0 0x0a0
-#define SDRC_RFR_CTRL_0 0x0a4
-#define SDRC_MANUAL_0 0x0a8
-#define SDRC_MCFG_1 0x0B0
-#define SDRC_MR_1 0x0B4
-#define SDRC_EMR2_1 0x0BC
-#define SDRC_ACTIM_CTRL_A_1 0x0C4
-#define SDRC_ACTIM_CTRL_B_1 0x0C8
-#define SDRC_RFR_CTRL_1 0x0D4
-#define SDRC_MANUAL_1 0x0D8
-
-#define SDRC_POWER_AUTOCOUNT_SHIFT 8
-#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
-#define SDRC_POWER_CLKCTRL_SHIFT 4
-#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
-#define SDRC_POWER_EXTCLKDIS_SHIFT 3
-#define SDRC_POWER_PWDENA_SHIFT 2
-#define SDRC_POWER_PAGEPOLICY_SHIFT 0
-#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
-
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
-
-/* Minimum frequency that the SDRC DLL can lock at */
-#define MIN_SDRC_DLL_LOCK_FREQ 83000000
-
-/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
-#define SDRC_MPURATE_SCALE 8
-
-/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
-#define SDRC_MPURATE_BASE_SHIFT 9
-
-/*
- * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
- * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
- */
-#define SDRC_MPURATE_LOOPS 96
-
-/** SMS register space size */
-#define SMS_REG_SIZE 0x1000
-
-/** SMS register offsets */
-#define SMS_SYSCONFIG 0x010
-#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
-#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
-#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
-
-/**
- * SDRC parameters for a given SDRC clock rate
- *
- * This structure holds a pre-computed set of register values for the
- * SDRC for a given SDRC clock rate and SDRAM chip.
- *
- * @rate: SDRC clock rate (in Hz)
- * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- * @mr: Value to program to SDRC_MR for this rate
- */
-struct sdrc_params {
- unsigned long rate;
- u32 actim_ctrla;
- u32 actim_ctrlb;
- u32 rfr_ctrl;
- u32 mr;
-};
-
-/** Initialize OMAP SDRC controller */
-int sdrc_init(physical_addr_t sdrc_base_pa,
- physical_addr_t sms_base_pa,
- struct sdrc_params *sdrc_cs0,
- struct sdrc_params *sdrc_cs1);
-
-#endif /* __OMAP_SDRC_H_ */
diff --git a/arch/arm/board/common/omap/objects.mk b/arch/arm/board/common/omap/objects.mk
deleted file mode 100644
index 949bbd88..00000000
--- a/arch/arm/board/common/omap/objects.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#/**
-# Copyright (c) 2011 Pranav Sawargaonkar.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
-# @brief list of OMAP platform objects.
-# */
-
-board-common-objs-$(CONFIG_OMAP)+= omap/sdrc.o
-
diff --git a/arch/arm/board/common/omap/openconf.cfg b/arch/arm/board/common/omap/openconf.cfg
deleted file mode 100644
index 5fc6183b..00000000
--- a/arch/arm/board/common/omap/openconf.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#/**
-# Copyright (c) 2012 Anup Patel.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file openconf.cfg
-# @author Anup Patel (an...@brainfault.org)
-# @brief config file for OMAP platform
-#*/
-
-config CONFIG_OMAP
- bool
- default n
diff --git a/arch/arm/board/common/omap/sdrc.c b/arch/arm/board/common/omap/sdrc.c
deleted file mode 100644
index 3554c0b9..00000000
--- a/arch/arm/board/common/omap/sdrc.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file sdrc.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code for OMAP SDRC controller
- */
-
-#include <vmm_error.h>
-#include <vmm_compiler.h>
-#include <vmm_host_io.h>
-#include <vmm_host_aspace.h>
-#include <omap/sdrc.h>
-
-static struct sdrc_params *sdrc_init_params_cs0;
-static struct sdrc_params *sdrc_init_params_cs1;
-
-static virtual_addr_t sdrc_base = 0;
-static virtual_addr_t sms_base = 0;
-
-#define SDRC_REGADDR(reg) (sdrc_base + (reg))
-#define SMS_REGADDR(reg) (sms_base + (reg))
-
-/* SDRC global register get/set */
-static inline void sdrc_write_reg(u32 val, u16 reg)
-{
- vmm_writel(val, (void *)SDRC_REGADDR(reg));
-}
-
-static inline u32 sdrc_read_reg(u16 reg)
-{
- return vmm_readl((void *)SDRC_REGADDR(reg));
-}
-
-/* SMS global register get/set */
-static inline void sms_write_reg(u32 val, u16 reg)
-{
- vmm_writel(val, (void *)SMS_REGADDR(reg));
-}
-
-static inline u32 sms_read_reg(u16 reg)
-{
- return vmm_readl((void *)SMS_REGADDR(reg));
-}
-
-int __init sdrc_init(physical_addr_t sdrc_base_pa,
- physical_addr_t sms_base_pa,
- struct sdrc_params *sdrc_cs0,
- struct sdrc_params *sdrc_cs1)
-{
- u32 l;
-
- /* This function does the task same as omap2_init_common_devices() of
- * <linux>/arch/arm/mach-omap2/io.c
- */
-
- if(!sdrc_base) {
- sdrc_base = vmm_host_iomap(sdrc_base_pa, SDRC_REG_SIZE);
- if(!sdrc_base) {
- return VMM_EFAIL;
- }
- }
- if(!sms_base) {
- sms_base = vmm_host_iomap(sms_base_pa, SMS_REG_SIZE);
- if(!sms_base) {
- return VMM_EFAIL;
- }
- }
-
- /* Initiaize SDRC as per omap2_sdrc_init() of
- * <linux>/arch/arm/mach-omap2/sdrc.c
- */
- l = sms_read_reg(SMS_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sms_write_reg(l, SMS_SYSCONFIG);
-
- l = sdrc_read_reg(SDRC_SYSCONFIG);
- l &= ~(0x3 << 3);
- l |= (0x2 << 3);
- sdrc_write_reg(l, SDRC_SYSCONFIG);
-
- sdrc_init_params_cs0 = sdrc_cs0;
- sdrc_init_params_cs1 = sdrc_cs1;
-
- /* XXX Enable SRFRONIDLEREQ here also? */
- /*
- * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
- * can cause random memory corruption
- */
- l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
- (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
- sdrc_write_reg(l, SDRC_POWER);
-
- /* FIXME: Reprogram SDRC timing parameters as per
- * _omap2_init_reprogram_sdrc() function of
- * <linux>/arch/arm/mach-omap2/io.c
- */
-
- return VMM_OK;
-}
-
diff --git a/arch/arm/board/common/openconf.cfg b/arch/arm/board/common/openconf.cfg
index 2bc394ce..6698c655 100644
--- a/arch/arm/board/common/openconf.cfg
+++ b/arch/arm/board/common/openconf.cfg
@@ -22,6 +22,3 @@
#*/

source "arch/arm/board/common/versatile/openconf.cfg"
-source "arch/arm/board/common/omap/openconf.cfg"
-source "arch/arm/board/common/imx/openconf.cfg"
-
diff --git a/arch/arm/board/generic/exynos4.c b/arch/arm/board/generic/exynos4.c
deleted file mode 100644
index 8c9d9591..00000000
--- a/arch/arm/board/generic/exynos4.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file exynos4.c
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief exynos4 board specific code
- */
-
-#include <vmm_error.h>
-#include <vmm_main.h>
-#include <vmm_stdio.h>
-#include <vmm_devtree.h>
-#include <vmm_host_io.h>
-#include <vmm_host_aspace.h>
-#include <vmm_delay.h>
-
-#include <generic_board.h>
-
-#include <exynos/regs-pmu.h>
-
-/*
- * Global board context
- */
-
-static virtual_addr_t exynos4_sys_base;
-
-/*
- * Reset & Shutdown
- */
-
-static int exynos4_reset(void)
-{
- if (exynos4_sys_base) {
- /* Trigger a Software reset */
- vmm_writel(0x1, (void *)(exynos4_sys_base + EXYNOS_SWRESET));
-
- vmm_mdelay(500);
- }
-
- return VMM_EFAIL;
-}
-
-static int exynos4_shutdown(void)
-{
- if (exynos4_sys_base) {
- /* Trigger a Software reset */
- vmm_writel(0x1, (void *)(exynos4_sys_base + EXYNOS_SWRESET));
-
- vmm_mdelay(500);
- }
-
- return VMM_EFAIL;
-}
-
-/*
- * Initialization functions
- */
-
-static int __init exynos4_early_init(struct vmm_devtree_node *node)
-{
- int rc;
-
- /* Host aspace, Heap, Device tree, and Host IRQ available.
- *
- * Do necessary early stuff like:
- * iomapping devices,
- * SOC clocking init,
- * Setting-up system data in device tree nodes,
- * ....
- */
-
- /* Map sysreg */
- node = vmm_devtree_find_compatible(NULL, NULL, "arm,a9mpcore-priv");
- if (!node) {
- return VMM_ENODEV;
- }
-
- rc = vmm_devtree_regmap(node, &exynos4_sys_base, 0);
- vmm_devtree_dref_node(node);
- if (rc) {
- return rc;
- }
-
- /* Register reset & shutdown callbacks */
- vmm_register_system_reset(exynos4_reset);
- vmm_register_system_shutdown(exynos4_shutdown);
-
- return VMM_OK;
-}
-
-static struct generic_board exynos4_info = {
- .name = "Exynos4",
- .early_init = exynos4_early_init,
-};
-
-GENERIC_BOARD_DECLARE(exynos4, "samsung,exynos4", &exynos4_info);
diff --git a/arch/arm/board/generic/objects.mk b/arch/arm/board/generic/objects.mk
index ac112158..6c3e8d93 100644
--- a/arch/arm/board/generic/objects.mk
+++ b/arch/arm/board/generic/objects.mk
@@ -21,12 +21,7 @@
# @brief list of Generic board objects.
# */

-board-objs-$(CONFIG_GENERIC_VERSATILE)+= versatile.o
-board-objs-$(CONFIG_GENERIC_REALVIEW)+= realview.o
board-objs-$(CONFIG_GENERIC_VEXPRESS)+= vexpress.o
-board-objs-$(CONFIG_GENERIC_OMAP3)+= omap3.o
-board-objs-$(CONFIG_GENERIC_SABRELITE)+= sabrelite.o
-board-objs-$(CONFIG_GENERIC_EXYNOS4)+= exynos4.o
board-objs-$(CONFIG_GENERIC_BCM2836)+= bcm2836.o
board-objs-$(CONFIG_GENERIC_FOUNDATION_V8)+= foundation-v8.o
board-objs-$(CONFIG_GENERIC_RK3399)+= rk3399.o
diff --git a/arch/arm/board/generic/omap3.c b/arch/arm/board/generic/omap3.c
deleted file mode 100644
index 49654475..00000000
--- a/arch/arm/board/generic/omap3.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file omap3.c
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @brief main source file for OMAP3 specific code
- */
-
-#include <vmm_error.h>
-#include <vmm_macros.h>
-#include <vmm_devtree.h>
-#include <vmm_devdrv.h>
-#include <vmm_host_io.h>
-#include <vmm_host_aspace.h>
-#include <generic_board.h>
-#include <omap/sdrc.h>
-
-/*
- * OMAP3 Power, Reset, and Clock Managment
- */
-
-/** OMAP3/OMAP343X PRCM Base Physical Address */
-#define OMAP3_PRCM_BASE 0x48004000
-
-/** OMAP3/OMAP343X CM Base Physical Address */
-#define OMAP3_CM_BASE 0x48004000
-#define OMAP3_CM_SIZE 0x2000
-
-/** OMAP3/OMAP343X PRM Base Physical Address */
-#define OMAP3_PRM_BASE 0x48306000
-#define OMAP3_PRM_SIZE 0x2000
-
-#define OMAP3_SYSCLK_S12M 12000000
-#define OMAP3_SYSCLK_S13M 13000000
-#define OMAP3_SYSCLK_S19_2M 19200000
-#define OMAP3_SYSCLK_S24M 24000000
-#define OMAP3_SYSCLK_S26M 26000000
-#define OMAP3_SYSCLK_S38_4M 38400000
-
-#define OMAP3_IVA2_CM 0x0000
-#define OMAP3_OCP_SYS_REG_CM 0x0800
-#define OMAP3_MPU_CM 0x0900
-#define OMAP3_CORE_CM 0x0A00
-#define OMAP3_SGX_CM 0x0B00
-#define OMAP3_WKUP_CM 0x0C00
-#define OMAP3_CLOCK_CTRL_REG_CM 0x0D00
-#define OMAP3_DSS_CM 0x0E00
-#define OMAP3_CAM_CM 0x0F00
-#define OMAP3_PER_CM 0x1000
-#define OMAP3_EMU_CM 0x1100
-#define OMAP3_GLOBAL_REG_CM 0x1200
-#define OMAP3_NEON_CM 0x1300
-#define OMAP3_USBHOST_CM 0x1400
-
-#define OMAP3_IVA2_PRM 0x0000
-#define OMAP3_OCP_SYS_REG_PRM 0x0800
-#define OMAP3_MPU_PRM 0x0900
-#define OMAP3_CORE_PRM 0x0A00
-#define OMAP3_SGX_PRM 0x0B00
-#define OMAP3_WKUP_PRM 0x0C00
-#define OMAP3_CLOCK_CTRL_REG_PRM 0x0D00
-#define OMAP3_DSS_PRM 0x0E00
-#define OMAP3_CAM_PRM 0x0F00
-#define OMAP3_PER_PRM 0x1000
-#define OMAP3_EMU_PRM 0x1100
-#define OMAP3_GLOBAL_REG_PRM 0x1200
-#define OMAP3_NEON_PRM 0x1300
-#define OMAP3_USBHOST_PRM 0x1400
-
-#define OMAP3_PRM_CLKSRC_CTRL 0x70
-#define OMAP3_PRM_CLKSRC_CTRL_SYSCLKDIV_S 6
-#define OMAP3_PRM_CLKSRC_CTRL_SYSCLKDIV_M (0x3 << 6)
-#define OMAP3_PRM_CLKSRC_CTRL_AUTOEXTCLK_S 3
-#define OMAP3_PRM_CLKSRC_CTRL_AUTOEXTCLK_M (0x3 << 3)
-#define OMAP3_PRM_CLKSRC_CTRL_SYSCLKSEL_S 0
-#define OMAP3_PRM_CLKSRC_CTRL_SYSCLKSEL_M (0x3 << 0)
-
-#define OMAP3_CM_FCLKEN_WKUP 0x00
-#define OMAP3_CM_FCLKEN_WKUP_EN_WDT2_S 5
-#define OMAP3_CM_FCLKEN_WKUP_EN_WDT2_M (1 << 5)
-#define OMAP3_CM_FCLKEN_WKUP_EN_GPIO1_S 3
-#define OMAP3_CM_FCLKEN_WKUP_EN_GPIO1_M (1 << 3)
-#define OMAP3_CM_FCLKEN_WKUP_EN_GPT1_S 0
-#define OMAP3_CM_FCLKEN_WKUP_EN_GPT1_M (1 << 0)
-
-#define OMAP3_CM_ICLKEN_WKUP 0x10
-#define OMAP3_CM_ICLKEN_WKUP_EN_WDT2_S 5
-#define OMAP3_CM_ICLKEN_WKUP_EN_WDT2_M (1 << 5)
-#define OMAP3_CM_ICLKEN_WKUP_EN_GPIO1_S 3
-#define OMAP3_CM_ICLKEN_WKUP_EN_GPIO1_M (1 << 3)
-#define OMAP3_CM_ICLKEN_WKUP_EN_32KSYNC_S 2
-#define OMAP3_CM_ICLKEN_WKUP_EN_32KSYNC_M (1 << 2)
-#define OMAP3_CM_ICLKEN_WKUP_EN_GPT1_S 0
-#define OMAP3_CM_ICLKEN_WKUP_EN_GPT1_M (1 << 0)
-
-#define OMAP3_CM_IDLEST_WKUP 0x20
-#define OMAP3_CM_IDLEST_WKUP_ST_WDT2_S 5
-#define OMAP3_CM_IDLEST_WKUP_ST_WDT2_M (1 << 5)
-#define OMAP3_CM_IDLEST_WKUP_ST_GPIO1_S 3
-#define OMAP3_CM_IDLEST_WKUP_ST_GPIO1_M (1 << 3)
-#define OMAP3_CM_IDLEST_WKUP_ST_32KSYNC_S 2
-#define OMAP3_CM_IDLEST_WKUP_ST_32KSYNC_M (1 << 2)
-#define OMAP3_CM_IDLEST_WKUP_ST_GPT1_S 0
-#define OMAP3_CM_IDLEST_WKUP_ST_GPT1_M (1 << 0)
-
-#define OMAP3_CM_AUTOIDLE_WKUP 0x30
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_WDT2_S 5
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_WDT2_M (1 << 5)
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_GPIO1_S 3
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_GPIO1_M (1 << 3)
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_32KSYNC_S 2
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_32KSYNC_M (1 << 2)
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_GPT1_S 0
-#define OMAP3_CM_AUTOIDLE_WKUP_AUTO_GPT1_M (1 << 0)
-
-#define OMAP3_CM_CLKSEL_WKUP 0x40
-#define OMAP3_CM_CLKSEL_WKUP_CLKSEL_RM_S 1
-#define OMAP3_CM_CLKSEL_WKUP_CLKSEL_RM_M (0x3 << 1)
-#define OMAP3_CM_CLKSEL_WKUP_CLKSEL_GPT1_S 0
-#define OMAP3_CM_CLKSEL_WKUP_CLKSEL_GPT1_M (1 << 0)
-
-#define OMAP3_CM_FCLKEN_PER 0x00
-#define OMAP3_CM_FCLKEN_PER_EN_GPT2_S 3
-#define OMAP3_CM_FCLKEN_PER_EN_GPT2_M (1 << 3)
-
-#define OMAP3_CM_ICLKEN_PER 0x10
-#define OMAP3_CM_ICLKEN_PER_EN_GPT2_S 3
-#define OMAP3_CM_ICLKEN_PER_EN_GPT2_M (1 << 3)
-
-#define OMAP3_CM_CLKSEL_PER 0x40
-#define OMAP3_CM_CLKSEL_PER_CLKSEL_GPT2_S 0
-#define OMAP3_CM_CLKSEL_PER_CLKSEL_GPT2_M (1 << 0)
-
-#define OMAP3_CM_ICLKEN 0x00
-#define OMAP3_CM_FCLKEN 0x10
-#define OMAP3_CM_CLKSEL 0x40
-
-static virtual_addr_t cm_base = 0;
-
-int __init cm_init(void)
-{
- if(!cm_base) {
- cm_base = vmm_host_iomap(OMAP3_CM_BASE, OMAP3_CM_SIZE);
- if(!cm_base)
- return VMM_EFAIL;
- }
- return VMM_OK;
-}
-
-u32 cm_read(u32 domain, u32 offset)
-{
- return vmm_readl((void *)(cm_base + domain + offset));
-}
-
-void cm_write(u32 domain, u32 offset, u32 val)
-{
- vmm_writel(val, (void *)(cm_base + domain + offset));
-}
-
-void cm_setbits(u32 domain, u32 offset, u32 mask)
-{
- vmm_writel(vmm_readl((void *)(cm_base + domain + offset)) | mask,
- (void *)(cm_base + domain + offset));
-}
-
-void cm_clrbits(u32 domain, u32 offset, u32 mask)
-{
- vmm_writel(vmm_readl((void *)(cm_base + domain + offset)) & (~mask),
- (void *)(cm_base + domain + offset));
-}
-
-static virtual_addr_t prm_base = 0;
-
-int __init prm_init(void)
-{
- if(!prm_base) {
- prm_base = vmm_host_iomap(OMAP3_PRM_BASE, OMAP3_PRM_SIZE);
- if(!prm_base)
- return VMM_EFAIL;
- }
- return VMM_OK;
-}
-
-u32 prm_read(u32 domain, u32 offset)
-{
- return vmm_readl((void *)(prm_base + domain + offset));
-}
-
-void prm_write(u32 domain, u32 offset, u32 val)
-{
- vmm_writel(val, (void *)(prm_base + domain + offset));
-}
-
-void prm_setbits(u32 domain, u32 offset, u32 mask)
-{
- vmm_writel(vmm_readl((void *)(prm_base + domain + offset)) | mask,
- (void *)(prm_base + domain + offset));
-}
-
-void prm_clrbits(u32 domain, u32 offset, u32 mask)
-{
- vmm_writel(vmm_readl((void *)(prm_base + domain + offset)) & (~mask),
- (void *)(prm_base + domain + offset));
-}
-
-/*
- * GPT Helper routines
- */
-
-/** OMAP3/OMAP343X S32K Base Physical Address */
-#define OMAP3_S32K_BASE 0x48320000
-
-/** OMAP3/OMAP343X GPT Base Physical Addresses */
-#define OMAP3_GPT1_BASE 0x48318000
-#define OMAP3_GPT2_BASE 0x49032000
-#define OMAP3_GPT3_BASE 0x49034000
-#define OMAP3_GPT4_BASE 0x49036000
-#define OMAP3_GPT5_BASE 0x49038000
-#define OMAP3_GPT6_BASE 0x4903A000
-#define OMAP3_GPT7_BASE 0x4903C000
-#define OMAP3_GPT8_BASE 0x4903E000
-#define OMAP3_GPT9_BASE 0x49040000
-#define OMAP3_GPT10_BASE 0x48086000
-#define OMAP3_GPT11_BASE 0x48088000
-#define OMAP3_GPT12_BASE 0x48304000
-
-struct gpt_cfg {
- physical_addr_t base_pa;
- u32 cm_domain;
- u32 clksel_offset;
- u32 clksel_mask;
- u32 iclken_offset;
- u32 iclken_mask;
- u32 fclken_offset;
- u32 fclken_mask;
- bool src_sys_clk;
- u32 clk_hz;
-};
-
-struct gpt_cfg omap3_gpt[] = {
- {
- .base_pa = OMAP3_GPT1_BASE,
- .cm_domain = OMAP3_WKUP_CM,
- .clksel_offset = OMAP3_CM_CLKSEL,
- .clksel_mask = OMAP3_CM_CLKSEL_WKUP_CLKSEL_GPT1_M,
- .iclken_offset = OMAP3_CM_ICLKEN,
- .iclken_mask = OMAP3_CM_ICLKEN_WKUP_EN_GPT1_M,
- .fclken_offset = OMAP3_CM_FCLKEN,
- .fclken_mask = OMAP3_CM_FCLKEN_WKUP_EN_GPT1_M,
- .src_sys_clk = TRUE,
- .clk_hz = 0, /* Determined at runtime */
- },
- {
- .base_pa = OMAP3_GPT2_BASE,
- .cm_domain = OMAP3_PER_CM,
- .clksel_offset = OMAP3_CM_CLKSEL,
- .clksel_mask = OMAP3_CM_CLKSEL_PER_CLKSEL_GPT2_M,
- .iclken_offset = OMAP3_CM_ICLKEN,
- .iclken_mask = OMAP3_CM_ICLKEN_PER_EN_GPT2_M,
- .fclken_offset = OMAP3_CM_FCLKEN,
- .fclken_mask = OMAP3_CM_FCLKEN_PER_EN_GPT2_M,
- .src_sys_clk = TRUE,
- .clk_hz = 0, /* Determined at runtime */
- }
-};
-
-#define S32K_FREQ_HZ 32768
-#define S32K_CR 0x10
-#define GPT_TCLR 0x024
-#define GPT_TCRR 0x028
-#define GPT_TLDR 0x02C
-#define GPT_TCLR_ST_M 0x00000001
-
-static u32 omap3_gpt_get_osc_clk_speed(u32 gpt_num, u32 sys_clk_div)
-{
- u32 osc_clk_hz = 0, regval;
- u32 start, cstart, cend, cdiff;
- virtual_addr_t gpt_va, s32k_va;
-
- /* Map gpt registers */
- gpt_va = vmm_host_iomap(omap3_gpt[gpt_num].base_pa, 0x1000);
-
- /* Map s32k registers */
- s32k_va = vmm_host_iomap(OMAP3_S32K_BASE, 0x1000);
-
- /* Start counting at 0 */
- vmm_writel(0, (void *)(gpt_va + GPT_TLDR));
-
- /* Enable GPT */
- vmm_writel(GPT_TCLR_ST_M, (void *)(gpt_va + GPT_TCLR));
-
- /* Start time in 20 cycles */
- start = 20 + vmm_readl((void *)(s32k_va + S32K_CR));
-
- /* Dead loop till start time */
- while (vmm_readl((void *)(s32k_va + S32K_CR)) < start);
-
- /* Get start sys_clk count */
- cstart = vmm_readl((void *)(gpt_va + GPT_TCRR));
-
- /* Wait for 20 cycles */
- while (vmm_readl((void *)(s32k_va + S32K_CR)) < (start + 20)) ;
- cend = vmm_readl((void *)(gpt_va + GPT_TCRR));
- cdiff = cend - cstart; /* get elapsed ticks */
- cdiff *= sys_clk_div;
-
- /* Stop Timer (TCLR[ST] = 0) */
- regval = vmm_readl((void *)(gpt_va + GPT_TCLR));
- regval &= ~GPT_TCLR_ST_M;
- vmm_writel(regval, (void *)(gpt_va + GPT_TCLR));
-
- /* Based on number of ticks assign speed */
- if (cdiff > 19000) {
- osc_clk_hz = OMAP3_SYSCLK_S38_4M;
- } else if (cdiff > 15200) {
- osc_clk_hz = OMAP3_SYSCLK_S26M;
- } else if (cdiff > 13000) {
- osc_clk_hz = OMAP3_SYSCLK_S24M;
- } else if (cdiff > 9000) {
- osc_clk_hz = OMAP3_SYSCLK_S19_2M;
- } else if (cdiff > 7600) {
- osc_clk_hz = OMAP3_SYSCLK_S13M;
- } else {
- osc_clk_hz = OMAP3_SYSCLK_S12M;
- }
-
- /* Unmap s32k registers */
- vmm_host_iounmap(s32k_va);
-
- /* Unmap gpt registers */
- vmm_host_iounmap(gpt_va);
-
- return osc_clk_hz >> (sys_clk_div - 1);
-}
-
-static void omap3_gpt_clock_enable(u32 gpt_num)
-{
- u32 sys_div;
-
- /* select clock source (1=sys_clk; 0=32K) for GPT */
- if (omap3_gpt[gpt_num].src_sys_clk) {
- sys_div = prm_read(OMAP3_GLOBAL_REG_PRM, OMAP3_PRM_CLKSRC_CTRL);
- sys_div = (sys_div & OMAP3_PRM_CLKSRC_CTRL_SYSCLKDIV_M)
- >> OMAP3_PRM_CLKSRC_CTRL_SYSCLKDIV_S;
- cm_setbits(omap3_gpt[gpt_num].cm_domain,
- omap3_gpt[gpt_num].clksel_offset,
- omap3_gpt[gpt_num].clksel_mask);
- omap3_gpt[gpt_num].clk_hz =
- omap3_gpt_get_osc_clk_speed(gpt_num, sys_div);
- } else {
- cm_clrbits(omap3_gpt[gpt_num].cm_domain,
- omap3_gpt[gpt_num].clksel_offset,
- omap3_gpt[gpt_num].clksel_mask);
- omap3_gpt[gpt_num].clk_hz = S32K_FREQ_HZ;
- }
-
- /* Enable I Clock for GPT */
- cm_setbits(omap3_gpt[gpt_num].cm_domain,
- omap3_gpt[gpt_num].iclken_offset,
- omap3_gpt[gpt_num].iclken_mask);
-
- /* Enable F Clock for GPT */
- cm_setbits(omap3_gpt[gpt_num].cm_domain,
- omap3_gpt[gpt_num].fclken_offset,
- omap3_gpt[gpt_num].fclken_mask);
-}
-
-/*
- * Initialization functions
- */
-
-/* Micron MT46H32M32LF-6 */
-/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
-static struct sdrc_params mt46h32m32lf6_sdrc_params[] = {
- [0] = {
- .rate = 166000000,
- .actim_ctrla = 0x9a9db4c6,
- .actim_ctrlb = 0x00011217,
- .rfr_ctrl = 0x0004dc01,
- .mr = 0x00000032,
- },
- [1] = {
- .rate = 165941176,
- .actim_ctrla = 0x9a9db4c6,
- .actim_ctrlb = 0x00011217,
- .rfr_ctrl = 0x0004dc01,
- .mr = 0x00000032,
- },
- [2] = {
- .rate = 83000000,
- .actim_ctrla = 0x51512283,
- .actim_ctrlb = 0x0001120c,
- .rfr_ctrl = 0x00025501,
- .mr = 0x00000032,
- },
- [3] = {
- .rate = 82970588,
- .actim_ctrla = 0x51512283,
- .actim_ctrlb = 0x0001120c,
- .rfr_ctrl = 0x00025501,
- .mr = 0x00000032,
- },
- [4] = {
- .rate = 0
- },
-};
-
-static void omap3_gpt_clk_init(struct vmm_devtree_node *node,
- const struct vmm_devtree_nodeid *match,
- void *data)
-{
- int i, rc, gpt_num = -1;
- physical_addr_t base;
-
- /* Find out GPT index */
- for (i = 0; i < array_size(omap3_gpt); i++) {
- rc = vmm_devtree_regaddr(node, &base, 0);
- if (rc) {
- continue;
- }
-
- if (base == omap3_gpt[i].base_pa) {
- gpt_num = i;
- break;
- }
- }
- if (gpt_num < 0) {
- return;
- }
-
- /* Enable clocks for GPTx */
- omap3_gpt_clock_enable(gpt_num);
-
- /* Update clock-frequency in GPTx device tree */
- vmm_devtree_setattr(node,
- VMM_DEVTREE_CLOCK_FREQ_ATTR_NAME,
- &omap3_gpt[gpt_num].clk_hz,
- VMM_DEVTREE_ATTRTYPE_UINT32,
- sizeof(omap3_gpt[gpt_num].clk_hz),
- FALSE);
-}
-
-/** OMAP3/OMAP343X SDRC Base Physical Address */
-#define OMAP3_SDRC_BASE 0x6D000000
-
-/** OMAP3/OMAP343X SMS Base Physical Address */
-#define OMAP3_SMS_BASE 0x6C000000
-
-static int __init omap3_early_init(struct vmm_devtree_node *node)
-{
- int rc;
- struct vmm_devtree_nodeid gpt_match[2];
-
- /* Host virtual memory, device tree, heap is up.
- * Do necessary early stuff like iomapping devices
- * memory or boot time memory reservation here.
- */
-
- /* The function omap3_beagle_init_early() of
- * <linux>/arch/arm/mach-omap2/board-omap3beagle.c
- * does the following:
- * 1. Initialize Clock & Power Domains using function
- * omap2_init_common_infrastructure() of
- * <linux>/arch/arm/mach-omap2/io.c
- * 2. Initialize & Reprogram Clock of SDRC using function
- * omap2_sdrc_init() of <linux>/arch/arm/mach-omap2/sdrc.c
- */
-
- /* Initialize Clock Mamagment */
- if ((rc = cm_init())) {
- return rc;
- }
-
- /* Initialize Power & Reset Mamagment */
- if ((rc = prm_init())) {
- return rc;
- }
-
- /* Enable I-clock for S32K timer
- * Note: S32K is our reference clocksource and also used
- * as clock reference for GPTs
- */
- cm_setbits(OMAP3_WKUP_CM,
- OMAP3_CM_ICLKEN_WKUP,
- OMAP3_CM_ICLKEN_WKUP_EN_32KSYNC_M);
-
- /* Initialize SDRAM Controller (SDRC) */
- if ((rc = sdrc_init(OMAP3_SDRC_BASE,
- OMAP3_SMS_BASE,
- mt46h32m32lf6_sdrc_params,
- mt46h32m32lf6_sdrc_params))) {
- return rc;
- }
-
- /* Iterate over each GPT device tree node */
- memset(gpt_match, 0, sizeof(gpt_match));
- strcpy(gpt_match[0].compatible, "ti,omap3430-timer");
- vmm_devtree_iterate_matching(NULL, gpt_match,
- omap3_gpt_clk_init, NULL);
-
- return 0;
-}
-
-static int __init omap3_final_init(struct vmm_devtree_node *node)
-{
- /* Nothing to do here. */
- return VMM_OK;
-}
-
-static struct generic_board omap3_info = {
- .name = "OMAP3",
- .early_init = omap3_early_init,
- .final_init = omap3_final_init,
-};
-
-GENERIC_BOARD_DECLARE(omap3, "ti,omap3", &omap3_info);
diff --git a/arch/arm/board/generic/openconf.cfg b/arch/arm/board/generic/openconf.cfg
index d2ea7b34..25f548e4 100644
--- a/arch/arm/board/generic/openconf.cfg
+++ b/arch/arm/board/generic/openconf.cfg
@@ -21,77 +21,15 @@
# @brief Board config file for Generic board
# */

-config CONFIG_GENERIC_VERSATILE
- bool "Versatile Platform"
- depends on CONFIG_ARMV5
- default y
- select CONFIG_VERSATILE_CLCD
- help
- This option enables Versatile platform support for
- Versatile-PB and Versatile-AB boards
-
-config CONFIG_GENERIC_IMX2X
- bool "i.MX 2X Platform"
- depends on CONFIG_ARMV5
- default n
- select CONFIG_ARCH_MXC
- help
- This option enables platform support for
- i.MX 2X (i.MX25, i.MX27, ...) boards
-
-config CONFIG_GENERIC_REALVIEW
- bool "Realview Platform"
- depends on CONFIG_ARMV6 || CONFIG_ARMV7A
- default y
- select CONFIG_REALVIEW_CONFIG
- select CONFIG_VERSATILE_CLCD
- select CONFIG_COMMON_CLK_VERSATILE
- help
- This option enables Realview platform support for
- Realview-EB-MPCore and Realview-PB-A8 boards
-
config CONFIG_GENERIC_VEXPRESS
bool "VExpress Platform"
- depends on CONFIG_ARMV7A || CONFIG_ARMV7A_VE
+ depends on CONFIG_ARMV7A_VE
default y
select CONFIG_VEXPRESS_CONFIG
select CONFIG_VERSATILE_CLCD
help
This option enables VExpress platform support for
- VExpress-A9 and VExpress-A15 boards
-
-config CONFIG_GENERIC_OMAP3
- bool "OMAP3 SOC Support"
- depends on CONFIG_ARMV7A
- select CONFIG_BBFLASH
- select CONFIG_OMAP
- help
- OMAP3xxx SOC family from TI
-
-config CONFIG_GENERIC_SABRELITE
- bool "Freescale Sabrelite Platform"
- depends on CONFIG_ARMV7A
- default y
- select CONFIG_SMP
- select CONFIG_ARCH_MXC
- select CONFIG_SABRELITE_CONFIG
- select CONFIG_COMMON_CLK_MXC
- help
- This option enables Freescale Sabrelite platform
- support for Freescale Sabrelite and
- Boundary Devices Nitrogen6x boards
-
-config CONFIG_GENERIC_EXYNOS4
- bool "Exynos 4 SOC Support"
- depends on CONFIG_ARMV7A
- select CONFIG_EXYNOS
- select CONFIG_ARM_GIC
- select CONFIG_SAMSUNG_MCT
- select CONFIG_SAMSUNG_MCT_LOCAL_TIMERS
- select CONFIG_SERIAL
- select CONFIG_SERIAL_SAMSUNG
- help
- Exynos 4 SOC family from Samsung
+ VExpress-A15 boards

config CONFIG_GENERIC_BCM2836
bool "BCM2836 SOC Support"
diff --git a/arch/arm/board/generic/realview.c b/arch/arm/board/generic/realview.c
deleted file mode 100644
index 9629fe4d..00000000
--- a/arch/arm/board/generic/realview.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- * Copyright (c) 2014 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file realview.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief realview board specific code
- */
-
-#include <vmm_error.h>
-
-#include <generic_board.h>
-
-#include <linux/realview.h>
-#include <linux/clk-provider.h>
-#include <linux/platform_data/clk-realview.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-
-#include <versatile/clcd.h>
-
-/*
- * CLCD support.
- */
-
-/*
- * Disable all display connectors on the interface module.
- */
-static void realview_clcd_disable(struct clcd_fb *fb)
-{
- realview_clcd_disable_power();
-}
-
-/*
- * Enable the relevant connector on the interface module.
- */
-static void realview_clcd_enable(struct clcd_fb *fb)
-{
- realview_clcd_enable_power();
-}
-
-/*
- * Detect which LCD panel is connected, and return the appropriate
- * clcd_panel structure. Note: we do not have any information on
- * the required timings for the 8.4in panel, so we presently assume
- * VGA timings.
- */
-static int realview_clcd_setup(struct clcd_fb *fb)
-{
- const char *panel_name;
- unsigned long framesize;
-
- framesize = 1024 * 768 * 2;
- panel_name = realview_clcd_panel_name();
-
- fb->panel = versatile_clcd_get_panel(panel_name);
- if (!fb->panel)
- return VMM_EINVALID;
-
- return versatile_clcd_setup_dma(fb, framesize);
-}
-
-static struct clcd_board clcd_system_data = {
- .name = "Realview",
- .caps = CLCD_CAP_ALL,
- .check = clcdfb_check,
- .decode = clcdfb_decode,
- .disable = realview_clcd_disable,
- .enable = realview_clcd_enable,
- .setup = realview_clcd_setup,
- .remove = versatile_clcd_remove,
-};
-
-/*
- * Initialization functions
- */
-
-static int __init realview_early_init(struct vmm_devtree_node *node)
-{
- /* Initialize sysreg */
- realview_sysreg_of_early_init();
-
- /* Intialize realview clocking */
- realview_clk_init((void *)realview_system_base(), FALSE);
-
- /* Setup CLCD (before probing) */
- node = vmm_devtree_find_compatible(NULL, NULL, "arm,pl111");
- if (node) {
- node->system_data = &clcd_system_data;
- }
- vmm_devtree_dref_node(node);
-
- return VMM_OK;
-}
-
-static int __init realview_final_init(struct vmm_devtree_node *node)
-{
- /* Nothing to do here. */
- return VMM_OK;
-}
-
-static struct generic_board realview_info = {
- .name = "Realview",
- .early_init = realview_early_init,
- .final_init = realview_final_init,
-};
-
-GENERIC_BOARD_DECLARE(realview, "arm,realview", &realview_info);
diff --git a/arch/arm/board/generic/sabrelite.c b/arch/arm/board/generic/sabrelite.c
deleted file mode 100644
index af556156..00000000
--- a/arch/arm/board/generic/sabrelite.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file sabrelite.c
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Freescale i.MX6 Sabrelite board specific code
- *
- * Adapted from linux/drivers/mfd/vexpres-sysreg.c
- *
- * Copyright (c) 2014 Anup Patel.
- *
- * The original source is licensed under GPL.
- *
- */
-#include <vmm_error.h>
-#include <vmm_devtree.h>
-#include <vmm_chardev.h>
-#include <imx6q-phy.h>
-
-#include <generic_board.h>
-
-#include <imx-common.h>
-#include <imx-hardware.h>
-
-/*
- * Initialization functions
- */
-static void __init imx6q_init_irq(void)
-{
- imx_gpc_init();
-}
-
-static void imx6_print_info(struct vmm_chardev *cdev)
-{
- imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
- imx_get_soc_revision());
-}
-
-static int __init imx6_early_init(struct vmm_devtree_node *node)
-{
- imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
- imx_get_soc_revision());
- imx_soc_device_init();
- imx6q_init_irq();
-
- return 0;
-}
-
-static int __init imx6_final_init(struct vmm_devtree_node *node)
-{
- imx_gpc_clocks_init();
- imx6q_enet_phy_init();
-
- return VMM_OK;
-}
-
-static struct generic_board imx6_info = {
- .name = "iMX6",
- .early_init = imx6_early_init,
- .final_init = imx6_final_init,
- .print_info = imx6_print_info,
-};
-
-GENERIC_BOARD_DECLARE(imx6, "fsl,imx6q", &imx6_info);
diff --git a/arch/arm/board/generic/versatile.c b/arch/arm/board/generic/versatile.c
deleted file mode 100644
index 7c5f281c..00000000
--- a/arch/arm/board/generic/versatile.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file brd_main.c
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @author Anup Patel (an...@brainfault.org)
- * @brief main source file for board specific code
- */
-
-#include <vmm_error.h>
-#include <vmm_main.h>
-#include <vmm_stdio.h>
-#include <vmm_devtree.h>
-#include <vmm_host_io.h>
-#include <vmm_host_aspace.h>
-
-#include <generic_board.h>
-
-#include <linux/fb.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/platform_data/clk-versatile.h>
-
-#include <versatile/clcd.h>
-
-/* ------------------------------------------------------------------------
- * Versatile Registers
- * ------------------------------------------------------------------------
- *
- */
-#define VERSATILE_SYS_ID_OFFSET 0x00
-#define VERSATILE_SYS_SW_OFFSET 0x04
-#define VERSATILE_SYS_LED_OFFSET 0x08
-#define VERSATILE_SYS_OSC0_OFFSET 0x0C
-
-#define VERSATILE_SYS_OSC1_OFFSET 0x10
-#define VERSATILE_SYS_OSC2_OFFSET 0x14
-#define VERSATILE_SYS_OSC3_OFFSET 0x18
-#define VERSATILE_SYS_OSC4_OFFSET 0x1C
-
-#define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c
-
-#define VERSATILE_SYS_LOCK_OFFSET 0x20
-#define VERSATILE_SYS_100HZ_OFFSET 0x24
-#define VERSATILE_SYS_CFGDATA1_OFFSET 0x28
-#define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C
-#define VERSATILE_SYS_FLAGS_OFFSET 0x30
-#define VERSATILE_SYS_FLAGSSET_OFFSET 0x30
-#define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34
-#define VERSATILE_SYS_NVFLAGS_OFFSET 0x38
-#define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38
-#define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C
-#define VERSATILE_SYS_RESETCTL_OFFSET 0x40
-#define VERSATILE_SYS_PCICTL_OFFSET 0x44
-#define VERSATILE_SYS_MCI_OFFSET 0x48
-#define VERSATILE_SYS_FLASH_OFFSET 0x4C
-#define VERSATILE_SYS_CLCD_OFFSET 0x50
-#define VERSATILE_SYS_CLCDSER_OFFSET 0x54
-#define VERSATILE_SYS_BOOTCS_OFFSET 0x58
-#define VERSATILE_SYS_24MHz_OFFSET 0x5C
-#define VERSATILE_SYS_MISC_OFFSET 0x60
-#define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80
-#define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84
-#define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88
-#define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C
-#define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90
-
-/*
- * Values for VERSATILE_SYS_RESET_CTRL
- */
-#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01
-#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02
-#define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03
-#define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04
-#define VERSATILE_SYS_CTRL_RESET_POR 0x05
-#define VERSATILE_SYS_CTRL_RESET_DoC 0x06
-
-#define VERSATILE_SYS_CTRL_LED (1 << 0)
-
-
-/* ------------------------------------------------------------------------
- * Versatile control registers
- * ------------------------------------------------------------------------
- */
-
-/*
- * VERSATILE_IDFIELD
- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4 = build value
- * 3:0 = revision number (0x1 = rev B (AHB))
- */
-
-/*
- * VERSATILE_SYS_LOCK
- * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
- * SYS_CLD, SYS_BOOTCS
- */
-#define VERSATILE_SYS_LOCK_LOCKED (1 << 16)
-#define VERSATILE_SYS_LOCKVAL 0xA05F
-#define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF
-
-/*
- * VERSATILE_SYS_FLASH
- */
-#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
-
-/*
- * VERSATILE_INTREG
- * - used to acknowledge and control MMCI and UART interrupts
- */
-#define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
-#define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
-#define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */
- /* write 1 to acknowledge and clear */
-#define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
-#define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
-
-/*
- * Global board context
- */
-
-static virtual_addr_t versatile_sys_base;
-
-/*
- * Reset & Shutdown
- */
-
-static int versatile_reset(void)
-{
- vmm_writel(0x101, (void *)(versatile_sys_base +
- VERSATILE_SYS_RESETCTL_OFFSET));
-
- return VMM_OK;
-}
-
-static int versatile_shutdown(void)
-{
- /* FIXME: TBD */
- return VMM_EFAIL;
-}
-
-/*
- * Initialization functions
- */
-
-/*
- * CLCD support.
- */
-#define SYS_CLCD_MODE_MASK (3 << 0)
-#define SYS_CLCD_MODE_888 (0 << 0)
-#define SYS_CLCD_MODE_5551 (1 << 0)
-#define SYS_CLCD_MODE_565_RLSB (2 << 0)
-#define SYS_CLCD_MODE_565_BLSB (3 << 0)
-#define SYS_CLCD_NLCDIOON (1 << 2)
-#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
-#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
-#define SYS_CLCD_ID_MASK (0x1f << 8)
-#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
-#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
-#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
-#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
-#define SYS_CLCD_ID_VGA (0x1f << 8)
-
-/*
- * Disable all display connectors on the interface module.
- */
-static void versatile_clcd_disable(struct clcd_fb *fb)
-{
- void *sys_clcd = (void *)versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
- u32 val;
-
- val = readl(sys_clcd);
- val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
- writel(val, sys_clcd);
-
-}
-
-/*
- * Enable the relevant connector on the interface module.
- */
-static void versatile_clcd_enable(struct clcd_fb *fb)
-{
- struct fb_var_screeninfo *var = &fb->fb.var;
- void *sys_clcd = (void *)versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
- u32 val;
-
- val = vmm_readl(sys_clcd);
- val &= ~SYS_CLCD_MODE_MASK;
-
- switch (var->green.length) {
- case 5:
- val |= SYS_CLCD_MODE_5551;
- break;
- case 6:
- if (var->red.offset == 0)
- val |= SYS_CLCD_MODE_565_RLSB;
- else
- val |= SYS_CLCD_MODE_565_BLSB;
- break;
- case 8:
- val |= SYS_CLCD_MODE_888;
- break;
- }
-
- /*
- * Set the MUX
- */
- vmm_writel(val, sys_clcd);
-
- /*
- * And now enable the PSUs
- */
- val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
- vmm_writel(val, sys_clcd);
-
-}
-
-/*
- * Detect which LCD panel is connected, and return the appropriate
- * clcd_panel structure. Note: we do not have any information on
- * the required timings for the 8.4in panel, so we presently assume
- * VGA timings.
- */
-static int versatile_clcd_setup(struct clcd_fb *fb)
-{
- void *sys_clcd = (void *)versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
- const char *panel_name;
- u32 val;
-
- val = vmm_readl(sys_clcd) & SYS_CLCD_ID_MASK;
- if (val == SYS_CLCD_ID_SANYO_3_8)
- panel_name = "Sanyo TM38QV67A02A";
- else if (val == SYS_CLCD_ID_SANYO_2_5) {
- panel_name = "Sanyo QVGA Portrait";
- } else if (val == SYS_CLCD_ID_EPSON_2_2)
- panel_name = "Epson L2F50113T00";
- else if (val == SYS_CLCD_ID_VGA)
- panel_name = "VGA";
- else {
- vmm_printf("CLCD: unknown LCD panel ID 0x%08x, "
- "using VGA\n", val);
- panel_name = "VGA";
- }
-
- fb->panel = versatile_clcd_get_panel(panel_name);
- if (!fb->panel)
- return VMM_EINVALID;
-
- return versatile_clcd_setup_dma(fb, 1024 * 1024);
-}
-
-static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
-{
- clcdfb_decode(fb, regs);
-
- /* Always clear BGR for RGB565: we do the routing externally */
- if (fb->fb.var.green.length == 6)
- regs->cntl &= ~CNTL_BGR;
-}
-
-static struct clcd_board clcd_system_data = {
- .name = "Versatile",
- .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
- .check = clcdfb_check,
- .decode = versatile_clcd_decode,
- .disable = versatile_clcd_disable,
- .enable = versatile_clcd_enable,
- .setup = versatile_clcd_setup,
- .remove = versatile_clcd_remove,
-};
-
-static int __init versatile_early_init(struct vmm_devtree_node *node)
-{
- int rc;
-
- /* Host aspace, Heap, Device tree, and Host IRQ available.
- *
- * Do necessary early stuff like:
- * iomapping devices,
- * SOC clocking init,
- * Setting-up system data in device tree nodes,
- * ....
- */
-
- /* Map sysreg */
- node = vmm_devtree_find_compatible(NULL, NULL, "arm,versatile-sysreg");
- if (!node) {
- return VMM_ENODEV;
- }
- rc = vmm_devtree_regmap(node, &versatile_sys_base, 0);
- vmm_devtree_dref_node(node);
- if (rc) {
- return rc;
- }
-
- /* Register reset & shutdown callbacks */
- vmm_register_system_reset(versatile_reset);
- vmm_register_system_shutdown(versatile_shutdown);
-
- /* Initialize versatile clocking */
- versatile_clk_init((void *)versatile_sys_base);
-
- /* Setup CLCD (before probing) */
- node = vmm_devtree_find_compatible(NULL, NULL, "arm,pl110,versatile");
- if (node) {
- node->system_data = &clcd_system_data;
- }
- vmm_devtree_dref_node(node);
-
- return 0;
-}
-
-static int __init versatile_final_init(struct vmm_devtree_node *node)
-{
- /* Nothing to do here. */
- return VMM_OK;
-}
-
-static struct generic_board versatile_info = {
- .name = "Versatile",
- .early_init = versatile_early_init,
- .final_init = versatile_final_init,
-};
-
-GENERIC_BOARD_DECLARE(versatile, "arm,versatile", &versatile_info);
diff --git a/arch/arm/configs/generic-v5-defconfig b/arch/arm/configs/generic-v5-defconfig
deleted file mode 100644
index d5d0d2c0..00000000
--- a/arch/arm/configs/generic-v5-defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-CONFIG_ARCH_ARM=y
-CONFIG_CPU_GENERIC_V5=y
-CONFIG_BOARD_GENERIC=y
-CONFIG_GENERIC_IMX2X=y
-CONFIG_MAX_VCPU_COUNT=48
-CONFIG_SCHEDALGO_PRR=y
-CONFIG_TSLICE_10MS=y
-CONFIG_BLOCK=y
-CONFIG_NET=y
-CONFIG_VIRTIO=y
-CONFIG_VMSG=y
-CONFIG_VSERIAL=y
-CONFIG_VSPI=y
-CONFIG_VDISK=y
-CONFIG_VDISPLAY=y
-CONFIG_VINPUT=y
-CONFIG_VSDAEMON=y
-CONFIG_VSDAEMON_CHARDEV=y
-CONFIG_VSDAEMON_MTERM=y
-CONFIG_VTEMU=y
-CONFIG_VFS=y
-CONFIG_VFS_EXT4=y
-CONFIG_VFS_FAT=y
-CONFIG_IMAGE_LOADER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_DISK=y
-CONFIG_ARM_VIC=y
-CONFIG_VERSATILE_FPGA_IRQ=y
-CONFIG_MXC_AVIC=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_MXC_EPIT=y
-CONFIG_MXC_GPT=y
-CONFIG_SERIAL=y
-CONFIG_SERIAL_8250_UART=y
-CONFIG_SERIAL_PL01X=y
-CONFIG_SERIAL_IMX=y
-CONFIG_RTC=y
-CONFIG_RTC_PL031=y
-CONFIG_BLOCK_RBD=y
-CONFIG_BLOCK_INITRD=y
-CONFIG_BLOCK_VIRTIO_HOST=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_MOUSE_PS2=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_NET_DEVICES=y
-CONFIG_ETHERNET_DRIVERS=y
-CONFIG_ETHER_SMSC_91x=y
-CONFIG_MICREL_PHY=y
-CONFIG_COMMON_CLK_VERSATILE=y
-CONFIG_COMMON_CLK_MXC=y
-CONFIG_MFD_SYSCON=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX25=y
-CONFIG_SPI=y
-CONFIG_SPI_IMX=y
-CONFIG_I2C=y
-CONFIG_I2C_IMX=y
-CONFIG_VIRTIO_HOST=y
-CONFIG_VIRTIO_HOST_MMIO=y
-CONFIG_EMU_VIRTIO_MMIO=y
-CONFIG_EMU_SYS=y
-CONFIG_EMU_SYS_ARM_SYSREGS=y
-CONFIG_EMU_SYS_SP810=y
-CONFIG_EMU_SYS_VMINFO=y
-CONFIG_EMU_PIC=y
-CONFIG_EMU_PIC_PL190=y
-CONFIG_EMU_TIMER=y
-CONFIG_EMU_TIMER_SP804=y
-CONFIG_EMU_MISC_ZERO=y
-CONFIG_EMU_PT_PLATFORM=y
-CONFIG_EMU_NET=y
-CONFIG_EMU_NET_SMC91C111=y
-CONFIG_EMU_NET_VIRTIO=y
-CONFIG_EMU_BLOCK=y
-CONFIG_EMU_BLOCK_VIRTIO=y
-CONFIG_EMU_DISPLAY=y
-CONFIG_EMU_DISPLAY_PL110=y
-CONFIG_EMU_DISPLAY_SIMPLEFB=y
-CONFIG_EMU_INPUT=y
-CONFIG_EMU_INPUT_PS2=y
-CONFIG_EMU_INPUT_PL050=y
-CONFIG_EMU_INPUT_VIRTIO=y
-CONFIG_EMU_SERIAL=y
-CONFIG_EMU_SERIAL_PL011=y
-CONFIG_EMU_CONSOLE=y
-CONFIG_EMU_CONSOLE_VIRTIO=y
-CONFIG_EMU_RPMSG=y
-CONFIG_EMU_RPMSG_VIRTIO=y
-CONFIG_EMU_RTC=y
-CONFIG_EMU_RTC_PL031=y
-CONFIG_EMU_GPIO=y
-CONFIG_EMU_GPIO_PL061=y
-CONFIG_EMU_GPIO_POWER=y
-CONFIG_EMU_GPIO_FORWARD=y
-CONFIG_EMU_SPI_PL022=y
-CONFIG_EMU_WDT=y
-CONFIG_EMU_WDT_SP805=y
diff --git a/arch/arm/configs/generic-v6-defconfig b/arch/arm/configs/generic-v6-defconfig
deleted file mode 100644
index ef8ce86a..00000000
--- a/arch/arm/configs/generic-v6-defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_ARCH_ARM=y
-CONFIG_CPU_GENERIC_V6=y
-CONFIG_SMP=y
-CONFIG_ARM_ERRATA_411920=y
-CONFIG_BOARD_GENERIC=y
-CONFIG_MAX_VCPU_COUNT=48
-CONFIG_SCHEDALGO_PRR=y
-CONFIG_TSLICE_10MS=y
-CONFIG_BLOCK=y
-CONFIG_NET=y
-CONFIG_VIRTIO=y
-CONFIG_VMSG=y
-CONFIG_VSERIAL=y
-CONFIG_VSPI=y
-CONFIG_VDISK=y
-CONFIG_VDISPLAY=y
-CONFIG_VINPUT=y
-CONFIG_VSCREEN=y
-CONFIG_VSDAEMON=y
-CONFIG_VSDAEMON_CHARDEV=y
-CONFIG_VSDAEMON_MTERM=y
-CONFIG_VTEMU=y
-CONFIG_VFS=y
-CONFIG_VFS_EXT4=y
-CONFIG_VFS_FAT=y
-CONFIG_IMAGE_LOADER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_DISK=y
-CONFIG_ARM_GIC=y
-CONFIG_MXC_AVIC=y
-CONFIG_BCM2835_INTC=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_TWD=y
-CONFIG_MXC_EPIT=y
-CONFIG_BCM2835_TIMER=y
-CONFIG_SERIAL=y
-CONFIG_SERIAL_8250_UART=y
-CONFIG_SERIAL_PL01X=y
-CONFIG_SERIAL_IMX=y
-CONFIG_RTC=y
-CONFIG_RTC_PL031=y
-CONFIG_BLOCK_RBD=y
-CONFIG_BLOCK_INITRD=y
-CONFIG_BLOCK_VIRTIO_HOST=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_BCM2835=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_DWC2_HCD=y
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_MOUSE_PS2=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_NET_DEVICES=y
-CONFIG_ETHERNET_DRIVERS=y
-CONFIG_ETHER_SMSC_911x=y
-CONFIG_ETHER_SMSC_91x=y
-CONFIG_COMMON_CLK_BCM2835=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_REALVIEW=y
-CONFIG_POWER_RESET_BCM2835=y
-CONFIG_MAILBOX=y
-CONFIG_BCM2835_MBOX=y
-CONFIG_MFD_SYSCON=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_I2C=y
-CONFIG_I2C_BCM2835=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_VIRTIO_HOST=y
-CONFIG_VIRTIO_HOST_MMIO=y
-CONFIG_EMU_VIRTIO_MMIO=y
-CONFIG_EMU_SYS=y
-CONFIG_EMU_SYS_ARM_SYSREGS=y
-CONFIG_EMU_SYS_SP810=y
-CONFIG_EMU_SYS_VMINFO=y
-CONFIG_EMU_PIC=y
-CONFIG_EMU_PIC_GIC=y
-CONFIG_EMU_TIMER=y
-CONFIG_EMU_TIMER_SP804=y
-CONFIG_EMU_TIMER_ARM_MPTIMER=y
-CONFIG_EMU_CACHE_L2X0=y
-CONFIG_EMU_MISC_ZERO=y
-CONFIG_EMU_MISC_ARM11MPCORE=y
-CONFIG_EMU_PT_PLATFORM=y
-CONFIG_EMU_NET=y
-CONFIG_EMU_NET_SMC91C111=y
-CONFIG_EMU_NET_VIRTIO=y
-CONFIG_EMU_BLOCK=y
-CONFIG_EMU_BLOCK_VIRTIO=y
-CONFIG_EMU_DISPLAY=y
-CONFIG_EMU_DISPLAY_PL110=y
-CONFIG_EMU_DISPLAY_SIMPLEFB=y
-CONFIG_EMU_INPUT=y
-CONFIG_EMU_INPUT_PS2=y
-CONFIG_EMU_INPUT_PL050=y
-CONFIG_EMU_INPUT_VIRTIO=y
-CONFIG_EMU_SERIAL=y
-CONFIG_EMU_SERIAL_PL011=y
-CONFIG_EMU_CONSOLE=y
-CONFIG_EMU_CONSOLE_VIRTIO=y
-CONFIG_EMU_RPMSG=y
-CONFIG_EMU_RPMSG_VIRTIO=y
-CONFIG_EMU_RTC=y
-CONFIG_EMU_RTC_PL031=y
-CONFIG_EMU_GPIO=y
-CONFIG_EMU_GPIO_PL061=y
-CONFIG_EMU_GPIO_POWER=y
-CONFIG_EMU_GPIO_FORWARD=y
-CONFIG_EMU_SPI_PL022=y
-CONFIG_EMU_WDT=y
-CONFIG_EMU_WDT_SP805=y
diff --git a/arch/arm/configs/generic-v7-defconfig b/arch/arm/configs/generic-v7-defconfig
deleted file mode 100644
index 9da312a6..00000000
--- a/arch/arm/configs/generic-v7-defconfig
+++ /dev/null
@@ -1,149 +0,0 @@
-CONFIG_ARCH_ARM=y
-CONFIG_CPU_GENERIC_V7=y
-CONFIG_BOARD_GENERIC=y
-CONFIG_GENERIC_OMAP3=y
-CONFIG_GENERIC_EXYNOS4=y
-CONFIG_ARM_SMP_PSCI=y
-CONFIG_ARM_SMP_IMX=y
-CONFIG_MAX_VCPU_COUNT=48
-CONFIG_SCHEDALGO_PRR=y
-CONFIG_TSLICE_10MS=y
-CONFIG_BLOCK=y
-CONFIG_NET=y
-CONFIG_VIRTIO=y
-CONFIG_VMSG=y
-CONFIG_VSERIAL=y
-CONFIG_VSPI=y
-CONFIG_VDISK=y
-CONFIG_VDISPLAY=y
-CONFIG_VINPUT=y
-CONFIG_VSCREEN=y
-CONFIG_VSDAEMON=y
-CONFIG_VSDAEMON_CHARDEV=y
-CONFIG_VSDAEMON_MTERM=y
-CONFIG_VTEMU=y
-CONFIG_VFS=y
-CONFIG_VFS_EXT4=y
-CONFIG_VFS_FAT=y
-CONFIG_IMAGE_LOADER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_DISK=y
-CONFIG_SUN4I_VIC=y
-CONFIG_OMAP_INTC=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_TWD=y
-CONFIG_MXC_EPIT=y
-CONFIG_MXC_GPT=y
-CONFIG_OMAP_S32K=y
-CONFIG_OMAP2_TIMER=y
-CONFIG_SUN4I_TIMER=y
-CONFIG_SERIAL_8250_UART=y
-CONFIG_SERIAL_OMAP_UART=y
-CONFIG_SERIAL_PL01X=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_SCIF=y
-CONFIG_RTC=y
-CONFIG_RTC_PL031=y
-CONFIG_BLOCK_RBD=y
-CONFIG_BLOCK_INITRD=y
-CONFIG_BLOCK_VIRTIO_HOST=y
-CONFIG_MTD=y
-CONFIG_MTD_M25P80=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_DWC2_HCD=y
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_MOUSE_PS2=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_IMX_IPUV3_CORE=y
-CONFIG_FB_MXC=y
-CONFIG_FB_MXC_LDB=y
-CONFIG_FB_MXC_HDMI=y
-CONFIG_FB_BACKLIGHT=y
-CONFIG_FB_BACKLIGHT_PWM=y
-CONFIG_NET_DEVICES=y
-CONFIG_ETHERNET_DRIVERS=y
-CONFIG_ETHER_SMSC_911x=y
-CONFIG_ETHER_SMSC_91x=y
-CONFIG_ETHER_ALLWINNER_SUN4I_EMAC=y
-CONFIG_MICREL_PHY=y
-CONFIG_COMMON_CLK_SUNXI=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_REALVIEW=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_RESET_SUN4I=y
-CONFIG_MFD_SYSCON=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PINCTRL_IMX6Q=y
-CONFIG_SPI=y
-CONFIG_SPI_IMX=y
-CONFIG_I2C=y
-CONFIG_PWM=y
-CONFIG_PWM_IMX=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_IMX_RESET=y
-CONFIG_VIRTIO_HOST=y
-CONFIG_VIRTIO_HOST_MMIO=y
-CONFIG_SRAM=y
-CONFIG_EMU_VIRTIO_MMIO=y
-CONFIG_EMU_SYS=y
-CONFIG_EMU_SYS_ARM_SYSREGS=y
-CONFIG_EMU_SYS_SP810=y
-CONFIG_EMU_SYS_VMINFO=y
-CONFIG_EMU_PIC=y
-CONFIG_EMU_PIC_GIC=y
-CONFIG_EMU_PIC_PL190=y
-CONFIG_EMU_TIMER=y
-CONFIG_EMU_TIMER_SP804=y
-CONFIG_EMU_TIMER_ARM_MPTIMER=y
-CONFIG_EMU_TIMER_IMX_GPT=y
-CONFIG_EMU_CACHE_L2X0=y
-CONFIG_EMU_MISC_ZERO=y
-CONFIG_EMU_MISC_ARM11MPCORE=y
-CONFIG_EMU_MISC_A9MPCORE=y
-CONFIG_EMU_MISC_IMX6_ANATOP=y
-CONFIG_EMU_MISC_IMX6_CCM=y
-CONFIG_EMU_MISC_IMX6_APBH=y
-CONFIG_EMU_PT_PLATFORM=y
-CONFIG_EMU_NET=y
-CONFIG_EMU_NET_LAN9118=y
-CONFIG_EMU_NET_SMC91C111=y
-CONFIG_EMU_NET_VIRTIO=y
-CONFIG_EMU_BLOCK=y
-CONFIG_EMU_BLOCK_VIRTIO=y
-CONFIG_EMU_DISPLAY=y
-CONFIG_EMU_DISPLAY_PL110=y
-CONFIG_EMU_DISPLAY_SIMPLEFB=y
-CONFIG_EMU_INPUT=y
-CONFIG_EMU_INPUT_PS2=y
-CONFIG_EMU_INPUT_PL050=y
-CONFIG_EMU_INPUT_VIRTIO=y
-CONFIG_EMU_SERIAL=y
-CONFIG_EMU_SERIAL_PL011=y
-CONFIG_EMU_SERIAL_IMX=y
-CONFIG_EMU_CONSOLE=y
-CONFIG_EMU_CONSOLE_VIRTIO=y
-CONFIG_EMU_RPMSG=y
-CONFIG_EMU_RPMSG_VIRTIO=y
-CONFIG_EMU_RTC=y
-CONFIG_EMU_RTC_PL031=y
-CONFIG_EMU_GPIO=y
-CONFIG_EMU_GPIO_PL061=y
-CONFIG_EMU_GPIO_POWER=y
-CONFIG_EMU_GPIO_FORWARD=y
-CONFIG_EMU_SPI_PL022=y
-CONFIG_EMU_WDT=y
-CONFIG_EMU_WDT_SP805=y
diff --git a/arch/arm/cpu/arm32/cpu_atomic.c b/arch/arm/cpu/arm32/cpu_atomic.c
deleted file mode 100644
index 29df8418..00000000
--- a/arch/arm/cpu/arm32/cpu_atomic.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_atomic.c
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @author Jean-Christophe Dubois <j...@tribudubois.net>
- * @brief ARM specific synchronization mechanisms.
- */
-
-#include <vmm_error.h>
-#include <vmm_types.h>
-#include <vmm_compiler.h>
-#include <arch_cpu_irq.h>
-#include <arch_barrier.h>
-#include <arch_atomic.h>
-
-#if defined(CONFIG_ARMV5)
-
-long __lock arch_atomic_read(atomic_t *atom)
-{
- long ret = atom->counter;
- arch_rmb();
- return ret;
-}
-
-void __lock arch_atomic_write(atomic_t *atom, long value)
-{
- atom->counter = value;
- arch_wmb();
-}
-
-void __lock arch_atomic_add(atomic_t *atom, long value)
-{
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter += value;
- arch_cpu_irq_restore(flags);
-}
-
-void __lock arch_atomic_sub(atomic_t *atom, long value)
-{
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter -= value;
- arch_cpu_irq_restore(flags);
-}
-
-long __lock arch_atomic_add_return(atomic_t *atom, long value)
-{
- long temp;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter += value;
- temp = atom->counter;
- arch_cpu_irq_restore(flags);
-
- return temp;
-}
-
-long __lock arch_atomic_sub_return(atomic_t *atom, long value)
-{
- long temp;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter -= value;
- temp = atom->counter;
- arch_cpu_irq_restore(flags);
-
- return temp;
-}
-
-long __lock arch_atomic_xchg(atomic_t *atom, long newval)
-{
- long previous;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- previous = atom->counter;
- atom->counter = newval;
- arch_cpu_irq_restore(flags);
-
- return previous;
-}
-
-long __lock arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
-{
- long previous;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- previous = atom->counter;
- if (previous == oldval) {
- atom->counter = newval;
- }
- arch_cpu_irq_restore(flags);
-
- return previous;
-}
-
-#else
-
-long __lock arch_atomic_read(atomic_t *atom)
-{
- long ret = atom->counter;
- arch_rmb();
- return ret;
-}
-
-void __lock arch_atomic_write(atomic_t *atom, long value)
-{
- atom->counter = value;
- arch_wmb();
-}
-
-void __lock arch_atomic_add(atomic_t *atom, long value)
-{
- unsigned int tmp;
- long result;
-
- __asm__ __volatile__("@ atomic_add\n"
-"1: ldrex %0, [%3]\n" /* Load atom->counter(%3) to result (%0) */
-" add %0, %0, %4\n" /* Add value (%4) to result */
-" strex %1, %0, [%3]\n" /* Save result (%0) to atom->counter (%3)
- * Result of this operation will be in tmp (%1)
- * if store operation success tmp is 0 or else 1
- */
-" teq %1, #0\n" /* Compare tmp (%1) result with 0 */
-" bne 1b" /* If fails go back to 1 and retry else return */
- :"=&r"(result), "=&r"(tmp), "+Qo"(atom->counter)
- :"r"(&atom->counter), "Ir"(value)
- :"cc");
-}
-
-void __lock arch_atomic_sub(atomic_t *atom, long value)
-{
- unsigned int tmp;
- long result;
-
- __asm__ __volatile__("@ atomic_sub\n"
-"1: ldrex %0, [%3]\n" /* Load atom->counter(%3) to result (%0) */
-" sub %0, %0, %4\n" /* Substract value (%4) to result (%0) */
-" strex %1, %0, [%3]\n" /* Save result (%0) to atom->counter (%3)
- * Result of this operation will be in tmp (%1)
- * if store operation success tmp (%1) is 0
- */
-" teq %1, #0\n" /* Compare tmp (%1) result with 0 */
-" bne 1b" /* If fails go back to 1 and retry else return */
- :"=&r"(result), "=&r"(tmp), "+Qo"(atom->counter)
- :"r"(&atom->counter), "Ir"(value)
- :"cc");
-}
-
-long __lock arch_atomic_add_return(atomic_t *atom, long value)
-{
- unsigned int tmp;
- long result;
-
- __asm__ __volatile__("@ atomic_add_return\n"
-"1: ldrex %0, [%3]\n" /* Load atom->counter(%3) to result (%0) */
-" add %0, %0, %4\n" /* Add value (%4) to result */
-" strex %1, %0, [%3]\n" /* Save result (%0) to atom->counter (%3)
- * Result of this operation will be in tmp (%1)
- * if store operation success tmp is 0 or else 1
- */
-" teq %1, #0\n" /* Compare tmp (%1) result with 0 */
-" bne 1b" /* If fails go back to 1 and retry else return */
- :"=&r"(result), "=&r"(tmp), "+Qo"(atom->counter)
- :"r"(&atom->counter), "Ir"(value)
- :"cc");
-
- return result;
-}
-
-long __lock arch_atomic_sub_return(atomic_t * atom, long value)
-{
- unsigned int tmp;
- long result;
-
- __asm__ __volatile__("@ atomic_sub_return\n"
-"1: ldrex %0, [%3]\n" /* Load atom->counter(%3) to result (%0) */
-" sub %0, %0, %4\n" /* Substract value (%4) to result (%0) */
-" strex %1, %0, [%3]\n" /* Save result (%0) to atom->counter (%3)
- * Result of this operation will be in tmp (%1)
- * if store operation success tmp is 0 or else 1
- */
-" teq %1, #0\n" /* Compare tmp (%1) result with 0 */
-" bne 1b" /* If fails go back to 1 and retry else return */
- :"=&r"(result), "=&r"(tmp), "+Qo"(atom->counter)
- :"r"(&atom->counter), "Ir"(value)
- :"cc");
-
- return result;
-}
-
-long __lock arch_atomic_xchg(atomic_t *atom, long newval)
-{
- long previous, res;
-
- do {
- __asm__ __volatile__("@ atomic_xchg\n"
- "ldrex %1, [%3]\n"
- "mov %0, #0\n"
- "strex %0, %4, [%3]\n"
- : "=&r" (res), "=&r" (previous), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (newval)
- : "cc");
- } while (res);
-
- return previous;
-}
-
-long __lock arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
-{
- long previous, res;
-
- do {
- __asm__ __volatile__("@ atomic_cmpxchg\n"
- "ldrex %1, [%3]\n"
- "mov %0, #0\n"
- "teq %1, %4\n"
- "strexeq %0, %5, [%3]\n"
- : "=&r" (res), "=&r" (previous), "+Qo" (atom->counter)
- : "r" (&atom->counter), "Ir" (oldval), "r" (newval)
- : "cc");
- } while (res);
-
- return previous;
-}
-
-#endif
diff --git a/arch/arm/cpu/arm32/cpu_atomic64.c b/arch/arm/cpu/arm32/cpu_atomic64.c
deleted file mode 100644
index 452e35e7..00000000
--- a/arch/arm/cpu/arm32/cpu_atomic64.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/**
- * Copyright (c) 2013 Jean-Christophe Dubois
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_atomic64.c
- * @author Jean-Christophe Dubois <j...@tribudubois.net>
- * @brief ARM specific 64 bits synchronization mechanisms.
- *
- * derived from linux/arch/arm/include/asm/atomic.h
- *
- * Copyright (C) 1996 Russell King.
- * Copyright (C) 2002 Deep Blue Solutions Ltd.
- */
-
-#include <vmm_error.h>
-#include <vmm_types.h>
-#include <vmm_compiler.h>
-#include <arch_cpu_irq.h>
-#include <arch_barrier.h>
-#include <arch_atomic64.h>
-
-#if defined(CONFIG_ARMV5) || defined(CONFIG_ARMV6)
-
-u64 __lock arch_atomic64_read(atomic64_t *atom)
-{
- u64 ret = atom->counter;
- arch_rmb();
- return ret;
-}
-
-void __lock arch_atomic64_write(atomic64_t *atom, u64 value)
-{
- atom->counter = value;
- arch_wmb();
-}
-
-void __lock arch_atomic64_add(atomic64_t *atom, u64 value)
-{
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter += value;
- arch_cpu_irq_restore(flags);
-}
-
-void __lock arch_atomic64_sub(atomic64_t *atom, u64 value)
-{
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter -= value;
- arch_cpu_irq_restore(flags);
-}
-
-u64 __lock arch_atomic64_add_return(atomic64_t *atom, u64 value)
-{
- u64 temp;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter += value;
- temp = atom->counter;
- arch_cpu_irq_restore(flags);
-
- return temp;
-}
-
-u64 __lock arch_atomic64_sub_return(atomic64_t *atom, u64 value)
-{
- u64 temp;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- atom->counter -= value;
- temp = atom->counter;
- arch_cpu_irq_restore(flags);
-
- return temp;
-}
-
-u64 __lock arch_atomic64_xchg(atomic64_t *atom, u64 newval)
-{
- u64 previous;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- previous = atom->counter;
- atom->counter = newval;
- arch_cpu_irq_restore(flags);
-
- return previous;
-}
-
-u64 __lock arch_atomic64_cmpxchg(atomic64_t *atom, u64 oldval, u64 newval)
-{
- u64 previous;
- irq_flags_t flags;
-
- arch_cpu_irq_save(flags);
- previous = atom->counter;
- if (previous == oldval) {
- atom->counter = newval;
- }
- arch_cpu_irq_restore(flags);
-
- return previous;
-}
-
-#else // CONFIG_ARMV5 || CONFIG_ARMV6
-
-u64 __lock arch_atomic64_read(atomic64_t *atom)
-{
- u64 result;
-
- __asm__ __volatile__("@ atomic64_read\n"
-" ldrexd %0, %H0, [%1]"
- : "=&r" (result)
- : "r" (&atom->counter), "Qo" (atom->counter)
- );
-
- return result;
-}
-
-void __lock arch_atomic64_write(atomic64_t *atom, u64 value)
-{
- u64 tmp;
-
- __asm__ __volatile__("@ atomic64_write\n"
-"1: ldrexd %0, %H0, [%2]\n"
-" strexd %0, %3, %H3, [%2]\n"
-" teq %0, #0\n"
-" bne 1b"
- : "=&r" (tmp), "=Qo" (atom->counter)
- : "r" (&atom->counter), "r" (value)
- : "cc");
-}
-
-void __lock arch_atomic64_add(atomic64_t *atom, u64 value)
-{
- u64 result;
- unsigned long tmp;
-
- __asm__ __volatile__("@ atomic64_add\n"
-"1: ldrexd %0, %H0, [%3]\n"
-" adds %0, %0, %4\n"
-" adc %H0, %H0, %H4\n"
-" strexd %1, %0, %H0, [%3]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (result), "=&r" (tmp), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (value)
- : "cc");
-}
-
-void __lock arch_atomic64_sub(atomic64_t *atom, u64 value)
-{
- u64 result;
- unsigned long tmp;
-
- __asm__ __volatile__("@ atomic64_sub\n"
-"1: ldrexd %0, %H0, [%3]\n"
-" subs %0, %0, %4\n"
-" sbc %H0, %H0, %H4\n"
-" strexd %1, %0, %H0, [%3]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (result), "=&r" (tmp), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (value)
- : "cc");
-}
-
-u64 __lock arch_atomic64_add_return(atomic64_t *atom, u64 value)
-{
- u64 result;
- unsigned long tmp;
-
- __asm__ __volatile__("@ atomic64_add_return\n"
-"1: ldrexd %0, %H0, [%3]\n"
-" adds %0, %0, %4\n"
-" adc %H0, %H0, %H4\n"
-" strexd %1, %0, %H0, [%3]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (result), "=&r" (tmp), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (value)
- : "cc");
-
- return result;
-}
-
-u64 __lock arch_atomic64_sub_return(atomic64_t *atom, u64 value)
-{
- u64 result;
- unsigned long tmp;
-
- __asm__ __volatile__("@ atomic64_sub_return\n"
-"1: ldrexd %0, %H0, [%3]\n"
-" subs %0, %0, %4\n"
-" sbc %H0, %H0, %H4\n"
-" strexd %1, %0, %H0, [%3]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (result), "=&r" (tmp), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (value)
- : "cc");
-
- return result;
-}
-
-u64 __lock arch_atomic64_xchg(atomic64_t *atom, u64 newval)
-{
- u64 previous;
- unsigned long res;
-
- do {
- __asm__ __volatile__("@ atomic64_xchg\n"
- "ldrexd %1, %H1, [%3]\n"
- "mov %0, #0\n"
- "strexd %0, %4, %H4, [%3]"
- : "=&r" (res), "=&r" (previous), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (newval)
- : "cc");
- } while (res);
-
- return previous;
-}
-
-u64 __lock arch_atomic64_cmpxchg(atomic64_t *atom, u64 oldval, u64 newval)
-{
- u64 previous;
- unsigned long res;
-
- do {
- __asm__ __volatile__("@ atomic64_cmpxchg\n"
- "ldrexd %1, %H1, [%3]\n"
- "mov %0, #0\n"
- "teq %1, %4\n"
- "teqeq %H1, %H4\n"
- "strexdeq %0, %5, %H5, [%3]"
- : "=&r" (res), "=&r" (previous), "+Qo" (atom->counter)
- : "r" (&atom->counter), "r" (oldval), "r" (newval)
- : "cc");
- } while (res);
-
- return previous;
-}
-
-#endif // CONFIG_ARMV5 || CONFIG_ARMV6
diff --git a/arch/arm/cpu/arm32/cpu_cache_v5.S b/arch/arm/cpu/arm32/cpu_cache_v5.S
deleted file mode 100644
index dcc6fc9b..00000000
--- a/arch/arm/cpu/arm32/cpu_cache_v5.S
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_cache_v5.S
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief Low-level implementation of cache ARMv5 functions
- */
-
- /*
- * Operations on entire data Cache to POC
- */
-
- /* invalidate the entire d-cache */
- .globl invalidate_dcache
-invalidate_dcache:
- /* FIXME: */
- bx lr
-
- /* clean the entire data cache */
- .globl clean_dcache
-clean_dcache:
- push {r0}
- /* FIXME: */
- mcr p15, 0, r0, c7, c10, 4
- pop {r0}
- bx lr
-
- /* clean & invalidate the entire data cache */
- .globl clean_invalidate_dcache
-clean_invalidate_dcache:
- push {r0}
- /* FIXME: */
- mcr p15, 0, r0, c7, c10, 4
- pop {r0}
- bx lr
-
- /*
- * Operations on data cache by MVA
- */
-
- /* invalidate by MVA */
- .globl invalidate_dcache_mva
-invalidate_dcache_mva:
- mcr p15, 0, r0, c7, c6, 1
- bx lr
-
- /* Invalidate by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl invalidate_dcache_mva_range
-invalidate_dcache_mva_range:
- push {r0, r1, r2, r3}
- /* FIXME: d-cache line size ?? */
- mov r2, #32
- sub r3, r2, #1
- tst r0, r3
- bic r0, r0, r3
- /* clean & invalidate D / U line */
- mcrne p15, 0, r0, c7, c14, 1
- mcrne p15, 0, r0, c7, c10, 4
- tst r1, r3
- bic r1, r1, r3
- /* clean & invalidate D / U line */
- mcrne p15, 0, r1, c7, c14, 1
- mcrne p15, 0, r1, c7, c10, 4
-1:
- /* invalidate D / U line */
- mcr p15, 0, r0, c7, c6, 1
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- pop {r0, r1, r2, r3}
- bx lr
-
- /* clean by mva */
- .globl clean_dcache_mva
-clean_dcache_mva:
- mcr p15, 0, r0, c7, c10, 1
- mcr p15, 0, r0, c7, c10, 4
- bx lr
-
- /* clean by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_dcache_mva_range
-clean_dcache_mva_range:
- push {r0, r1, r2}
- /* FIXME: d-cache line size ?? */
- mov r2, #32
-1:
- /* invalidate D / U line */
- mcr p15, 0, r0, c7, c10, 1
- mcr p15, 0, r0, c7, c10, 4
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- pop {r0, r1, r2}
- bx lr
-
- /* clean and invalidate by mva */
- .globl clean_invalidate_dcache_mva
-clean_invalidate_dcache_mva:
- mcr p15, 0, r0, c7, c14, 1
- mcr p15, 0, r0, c7, c10, 4
- bx lr
-
- /* clean and invalidate a memory region by mva
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_invalidate_dcache_mva_range
-clean_invalidate_dcache_mva_range:
- /* FIXME: */
- mcr p15, 0, r0, c7, c10, 4
- bx lr
-
- /*
- * Operations on data cache line by set/way
- */
-
- /* invalidate line by set/way */
- .globl invalidate_dcache_line
-invalidate_dcache_line:
- mcr p15, 0, r0, c7, c6, 2
- bx lr
-
- /* clean line by set/way */
- .globl clean_dcache_line
-clean_dcache_line:
- mcr p15, 0, r0, c7, c10, 2
- mcr p15, 0, r0, c7, c10, 4
- bx lr
-
- /* clean and invalidate line by set/way */
- .globl clean_invalidate_dcache_line
-clean_invalidate_dcache_line:
- mcr p15, 0, r0, c7, c14, 2
- mcr p15, 0, r0, c7, c10, 4
- bx lr
-
- /*
- * Operation on entire Instruction cache
- */
-
- /* invalidate the entire i-cache */
- .globl invalidate_icache
-invalidate_icache:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0
- pop {r0}
- bx lr
-
- /* invalidate i-cache by mva */
- .globl invalidate_icache_mva
-invalidate_icache_mva:
- mcr p15, 0, r0, c7, c5, 0
- bx lr
-
- /* invalidate the i-cache line by set/way */
- /* no such instruction so invalidate everything */
- .globl invalidate_icache_line
-invalidate_icache_line:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* invalidate all */
- pop {r0}
- bx lr
-
- /*
- * Operations on entire instruction an data cache
- */
-
- /* invalidate the entire i-cache and d-cache */
- .globl invalidate_idcache
-invalidate_idcache:
- push {lr}
- bl invalidate_icache
- bl invalidate_dcache
- pop {lr}
- bx lr
-
- /* clean the entire i-cache and d-cache */
- .globl clean_idcache
-clean_idcache:
- push {lr}
- bl clean_dcache
- pop {lr}
- bx lr
-
- /* clean and invalidate the entire i-cache and d-cache */
- .globl clean_invalidate_idcache
-clean_invalidate_idcache:
- push {lr}
- bl invalidate_icache
- bl clean_invalidate_dcache
- pop {lr}
- bx lr
-
- /*
- * operation on both i-cache and d-cache by mva
- */
-
- /* invalidate both i-cache and d-cache by mva */
- .globl invalidate_idcache_mva
-invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache by mva */
- .globl clean_idcache_mva
-clean_idcache_mva:
- push {lr}
- bl clean_dcache_mva
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache by mva */
- .globl clean_invalidate_idcache_mva
-clean_invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl clean_invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /*
- * operation on both i-cache and d-cache line by set/way
- */
-
- /* invalidate both i-cache and d-cache line by set/way */
- .globl invalidate_idcache_line
-invalidate_idcache_line:
- push {lr}
- bl invalidate_icache_line
- bl invalidate_dcache_line
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache line by set/way */
- .globl clean_idcache_line
-clean_idcache_line:
- push {lr}
- bl clean_dcache_line
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache line by set/way */
- .globl clean_invalidate_idcache_line
-clean_invalidate_idcache_line:
- push {lr}
- bl invalidate_icache
- bl clean_invalidate_dcache_line
- pop {lr}
- bx lr
-
- /*
- * branch predictor maintenence operation
- */
-
- /* invalidate entire branch predictor */
- .globl invalidate_bpredictor
-invalidate_bpredictor:
- nop
- bx lr
-
- /* invalidate branch predictor by mva */
- .globl invalidate_bpredictor_mva
-invalidate_bpredictor_mva:
- nop
- bx lr
-
diff --git a/arch/arm/cpu/arm32/cpu_cache_v6.S b/arch/arm/cpu/arm32/cpu_cache_v6.S
deleted file mode 100644
index a2c559d7..00000000
--- a/arch/arm/cpu/arm32/cpu_cache_v6.S
+++ /dev/null
@@ -1,424 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_cache_v6.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of cache ARMv6 functions
- */
-
-#define HARVARD_CACHE
-#define CACHE_LINE_SIZE 32
-#define D_CACHE_LINE_SIZE 32
-#define BTB_FLUSH_SIZE 8
-
-.macro ISB treg
- mcr p15, 0, \treg, c7, c5, 4
-.endm
-
-.macro DSB treg
- mcr p15, 0, \treg, c7, c10, 4
-.endm
-
- /*
- * Operations on entire d-cache
- */
-
- /* invalidate the entire d-cache */
- .globl invalidate_dcache
-invalidate_dcache:
- push {r0}
- mov r0, #0
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c6, 0 @ d-cache invalidate
-#else
- mcr p15, 0, r0, c7, c7, 0 @ cache unified invalidate
-#endif
- ISB r0
- pop {r0}
- bx lr
-
- /* clean the entire d-cache */
- .globl clean_dcache
-clean_dcache:
- push {r0}
- mov r0, #0
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c10, 0 @ d-cache clean
-#else
- mcr p15, 0, r0, c7, c11, 0 @ cache unified clean
-#endif
- DSB r0
- ISB r0
- pop {r0}
- mov pc, lr
-
- /* clean & invalidate the entire d-cache */
- .globl clean_invalidate_dcache
-clean_invalidate_dcache:
- push {r0}
- mov r0, #0
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c14, 0 @ d-cache clean+invalidate
-#else
- mcr p15, 0, r0, c7, c15, 0 @ unified cache clean+invalidate
-#endif
- DSB r0
- ISB r0
- pop {r0}
- mov pc, lr
-
- /*
- * Operations on d-cache by MVA
- */
-
- /* invalidate by MVA */
- .globl invalidate_dcache_mva
-invalidate_dcache_mva:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c6, 1 @ d-cache invalidate by MVA
-#else
- mcr p15, 0, r0, c7, c7, 1 @ cache unified invalidate by MVA
-#endif
- ISB r0
- mov pc, lr
-
- /* Invalidate by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl invalidate_dcache_mva_range
-invalidate_dcache_mva_range:
- push {r0, r1, r2, r3}
-#ifdef HARVARD_CACHE
- mov r2, #D_CACHE_LINE_SIZE
-#else
- mov r2, #CACHE_LINE_SIZE
-#endif
- sub r3, r2, #1
- tst r0, r3
- bic r0, r0, r3
- /* clean & invalidate D / U line */
-#ifdef HARVARD_CACHE
- mcrne p15, 0, r0, c7, c14, 1 @ d-cache clean+invalidate by MVA
-#else
- mcrne p15, 0, r0, c7, c15, 1 @ cache unified clean+invalidate by MVA
-#endif
- tst r1, r3
- bic r1, r1, r3
- /* clean & invalidate D / U line */
-#ifdef HARVARD_CACHE
- mcrne p15, 0, r1, c7, c14, 1 @ d-cache clean+invalidate by MVA
-#else
- mcrne p15, 0, r1, c7, c15, 1 @ cache unified clean+invalidate by MVA
-#endif
-1:
- /* invalidate D / U line */
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c6, 1 @ d-cache invalidate by MVA
-#else
- mcr p15, 0, r0, c7, c7, 1 @ cache unified invalidate by MVA
-#endif
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- DSB r0
- pop {r0, r1, r2, r3}
- bx lr
-
- /* clean by mva */
- .globl clean_dcache_mva
-clean_dcache_mva:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c10, 1 @ d-cache clean by MVA
-#else
- mcr p15, 0, r0, c7, c11, 1 @ cache unified clean by MVA
-#endif
- DSB r0
- ISB r0
- mov pc, lr
-
- /* clean by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_dcache_mva_range
-clean_dcache_mva_range:
- push {r0, r1, r2}
-#ifdef HARVARD_CACHE
- mov r2, #D_CACHE_LINE_SIZE
- bic r0, r0, #D_CACHE_LINE_SIZE - 1
-1:
- mcr p15, 0, r0, c7, c10, 1 @ d-cache clean by MVA
- add r0, r0, r2
- cmp r0, r1
- blo 1b
-#else
- mov r2, #CACHE_LINE_SIZE
- bic r0, r0, #CACHE_LINE_SIZE - 1
-1:
- mcr p15, 0, r0, c7, c11, 1 @ cache unified clean by MVA
- add r0, r0, r2
- cmp r0, r1
- blo 1b
-#endif
- DSB r0
- ISB r0
- pop {r0, r1, r2}
- bx lr
-
- /* clean and invalidate by mva */
- .globl clean_invalidate_dcache_mva
-clean_invalidate_dcache_mva:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c14, 1 @ d-cache clean+invalidate by MVA
-#else
- mcr p15, 0, r0, c7, c15, 1 @ cache unified clean+invalidate by MVA
-#endif
- DSB r0
- ISB r0
- mov pc, lr
-
- /* clean and invalidate a memory region by mva
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_invalidate_dcache_mva_range
-clean_invalidate_dcache_mva_range:
- push {r0, r1, r2}
-#ifdef HARVARD_CACHE
- mov r2, #D_CACHE_LINE_SIZE
- bic r0, r0, #D_CACHE_LINE_SIZE - 1
-1:
- mcr p15, 0, r0, c7, c14, 1 @ d-cache clean+invalidate by MVA
- add r0, r0, r2
- cmp r0, r1
- blo 1b
-#else
- mov r2, #CACHE_LINE_SIZE
- bic r0, r0, #CACHE_LINE_SIZE - 1
-1:
- mcr p15, 0, r0, c7, c15, 1 @ cache unified clean+invalidate by MVA
- add r0, r0, r2
- cmp r0, r1
- blo 1b
-#endif
- DSB r0
- ISB r0
- pop {r0, r1, r2}
- bx lr
-
- /*
- * Operations on data cache line by set/way
- */
-
- /* invalidate line by set/way */
- .globl invalidate_dcache_line
-invalidate_dcache_line:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c6, 2 @ d-cache invalidate by set/way
-#else
- mcr p15, 0, r0, c7, c7, 2 @ cache unified invalidate by set/way
-#endif
- ISB r0
- mov pc, lr
-
- /* clean line by set/way */
- .globl clean_dcache_line
-clean_dcache_line:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c10, 2 @ d-cache clean by set/way
-#else
- mcr p15, 0, r0, c7, c11, 2 @ cache unified clean by set/way
-#endif
- DSB r0
- ISB r0
- mov pc, lr
-
- /* clean and invalidate line by set/way */
- .globl clean_invalidate_dcache_line
-clean_invalidate_dcache_line:
-#ifdef HARVARD_CACHE
- mcr p15, 0, r0, c7, c14, 1 @ d-cache clean+invalidate by set/way
-#else
- mcr p15, 0, r0, c7, c15, 2 @ cache unified clean+invalidate by set/way
-#endif
- DSB r0
- ISB r0
- mov pc, lr
-
- /*
- * Operation on entire Instruction cache
- */
-
- /* invalidate the entire i-cache
- *
- * ARM1136 erratum 411920 - Invalidate Instruction Cache operation
- * can fail. This erratum is present in 1136, 1156 and 1176.
- * It does not affect the MPCore.
- *
- * Registers:
- * r0 - set to 0
- * r1 - corrupted
- */
- .globl invalidate_icache
-invalidate_icache:
- push {r0, r1}
- mov r0, #0
-#ifdef CONFIG_ARM_ERRATA_411920
- mrs r1, cpsr
- cpsid ifa @ disable interrupts
- mcr p15, 0, r0, c7, c5, 0 @ invalidate entire i-cache
- mcr p15, 0, r0, c7, c5, 0 @ invalidate entire i-cache
- mcr p15, 0, r0, c7, c5, 0 @ invalidate entire i-cache
- mcr p15, 0, r0, c7, c5, 0 @ invalidate entire i-cache
- msr cpsr_cx, r1 @ restore interrupts
- .rept 11 @ ARM Ltd recommends at least
- nop @ 11 NOPs
- .endr
-#else
- mcr p15, 0, r0, c7, c5, 0 @ invalidate i-cache
-#endif
- ISB r0
- pop {r0, r1}
- mov pc, lr
-
- /* invalidate i-cache by mva */
- .globl invalidate_icache_mva
-invalidate_icache_mva:
- mcr p15, 0, r0, c7, c5, 0 @ i-cache invalidate by MVA
- ISB r0
- mov pc, lr
-
- /* invalidate the i-cache line by set/way */
- .globl invalidate_icache_line
-invalidate_icache_line:
- mcr p15, 0, r0, c7, c5, 2 @ i-cache invalidate by set/way
- ISB r0
- mov pc, lr
-
- /*
- * Operations on entire instruction and data cache
- */
-
- /* invalidate the entire i-cache and d-cache */
- .globl invalidate_idcache
-invalidate_idcache:
- push {lr}
- bl invalidate_icache
- bl invalidate_dcache
- pop {lr}
- bx lr
-
- /* clean the entire i-cache and d-cache */
- .globl clean_idcache
-clean_idcache:
- push {lr}
- bl clean_dcache
- pop {lr}
- bx lr
-
- /* clean and invalidate the entire i-cache and d-cache */
- .globl clean_invalidate_idcache
-clean_invalidate_idcache:
- push {lr}
- bl clean_invalidate_dcache
- bl invalidate_icache
- pop {lr}
- mov pc, lr
-
- /*
- * operation on both i-cache and d-cache by mva
- */
-
- /* invalidate both i-cache and d-cache by mva */
- .globl invalidate_idcache_mva
-invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache by mva */
- .globl clean_idcache_mva
-clean_idcache_mva:
- push {lr}
- bl clean_dcache_mva
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache by mva */
- .globl clean_invalidate_idcache_mva
-clean_invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl clean_invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /*
- * operation on both i-cache and d-cache line by set/way
- */
-
- /* invalidate both i-cache and d-cache line by set/way */
- .globl invalidate_idcache_line
-invalidate_idcache_line:
- push {lr}
- bl invalidate_icache_line
- bl invalidate_dcache_line
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache line by set/way */
- .globl clean_idcache_line
-clean_idcache_line:
- push {lr}
- bl clean_dcache_line
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache line by set/way */
- .globl clean_invalidate_idcache_line
-clean_invalidate_idcache_line:
- push {lr}
- bl invalidate_icache
- bl clean_invalidate_dcache_line
- pop {lr}
- bx lr
-
- /*
- * branch predictor maintenence operation
- */
-
- /* invalidate entire branch predictor */
- .globl invalidate_bpredictor
-invalidate_bpredictor:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 6 /* invalidate branch predictor all */
- ISB r0
- pop {r0}
- bx lr
-
- /* invalidate branch predictor by mva */
- .globl invalidate_bpredictor_mva
-invalidate_bpredictor_mva:
- mcr p15, 0, r0, c7, c5, 7 /* invalidate branch predictor by MVA */
- ISB r0
- bx lr
-
diff --git a/arch/arm/cpu/arm32/cpu_cache_v7.S b/arch/arm/cpu/arm32/cpu_cache_v7.S
deleted file mode 100644
index 89ff616d..00000000
--- a/arch/arm/cpu/arm32/cpu_cache_v7.S
+++ /dev/null
@@ -1,377 +0,0 @@
-/**
- * Copyright (c) 2012 Ankit Jindal.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_cache_v7.S
- * @author Ankit Jindal (thats...@gmail.com)
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of cache ARMv7 functions
- */
-
-/*
- * dcache_line_size - get the minimum D-cache line size from the CTR register
- * on ARMv7.
- */
-.macro dcache_line_size, reg, tmp
- mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
- lsr \tmp, \tmp, #16
- and \tmp, \tmp, #0xf @ cache line size encoding
- mov \reg, #4 @ bytes per word
- mov \reg, \reg, lsl \tmp @ actual cache line size
-.endm
-
-/*
- * Generic mechanism for operations on the entire data or unified cache to the Point
- * of Coherence. This code is taken from 'Example code for cache maintenance operations'
- * provided in "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
- * (ARM DDI 0406)".
- * Registers r0 - r9 are used.
- */
-#define ARM_ENTIRE_DCACHE_OP(crm) \
- \
- stmfd sp!, {r0-r9} /* save registers */;\
- \
- mrc p15, 1, r0, c0, c0, 1 /* Read CLIDR */;\
- ands r3, r0, #0x7000000 ;\
- mov r3, r3, LSR #23 /* Cache level value (naturally aligned) */; \
- beq 5f ;\
- mov r8, #0 ;\
-1: ;\
- add r2, r8, r8, LSR #1 /* Work out 3xcachelevel */; \
- mov r1, r0, LSR r2 /* bottom 3 bits are the Cache type for this level */; \
- and r1, r1, #7 /* get those 3 bits alone */; \
- cmp r1, #2 ;\
- blt 4f /* no cache or only instruction cache at this level */; \
- mcr p15, 2, r8, c0, c0, 0 /* write the Cache Size selection register */; \
- isb /* isb to sync the change to the CacheSizeID reg */; \
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */; \
- and r2, r1, #7 /* extract the line length field */; \
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */; \
- ldr r4, =0x3FF ;\
- ands r4, r4, r1, LSR #3 /* r4 is the max number on the way size (right aligned) */; \
- clz r5, r4 /* r5 is the bit position of the way size increment */; \
- ldr r6, =0x00007FFF ;\
- ands r6, r6, r1, LSR #13 /* r6 is the max number of the index size (right aligned) */; \
-2: ;\
- mov r7, r4 /* r7 working copy of the max way size (right aligned) */; \
-3: ;\
- orr r9, r8, r7, LSL r5 /* factor in the way number and cache number into r9 */; \
- orr r9, r9, r6, LSL r2 /* factor in the index number */; \
- mcr p15, 0, r9, c7, crm, 2 /* clean by set/way */; \
- subs r7, r7, #1 /* decrement the way number */; \
- bge 3b ;\
- subs r6, r6, #1 /* decrement the index */; \
- bge 2b ;\
-4: ;\
- add r8, r8, #2 /* increment the cache number */; \
- cmp r3, r8 ;\
- bgt 1b ;\
- \
-5: ;\
- ldmia sp!, {r0-r9} /* restore registers */;
-
- /*
- * Operations on entire data Cache to POC
- */
-
- /* invalidate the entire d-cache */
- .globl invalidate_dcache
-invalidate_dcache:
- ARM_ENTIRE_DCACHE_OP(c6) /* invalidate all */
- isb
- bx lr
-
- /* clean the entire data cache */
- .globl clean_dcache
-clean_dcache:
- ARM_ENTIRE_DCACHE_OP(c10) /* clean all */
- dsb
- isb
- bx lr
-
- /* clean & invalidate the entire data cache */
- .globl clean_invalidate_dcache
-clean_invalidate_dcache:
- ARM_ENTIRE_DCACHE_OP(c14) /* clean and invalidate all */
- dsb
- isb
- bx lr
-
- /*
- * Operations on data cache by MVA
- */
-
- /* invalidate by MVA */
- .globl invalidate_dcache_mva
-invalidate_dcache_mva:
- mcr p15, 0, r0, c7, c6, 1
- isb
- bx lr
-
- /* Invalidate by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl invalidate_dcache_mva_range
-invalidate_dcache_mva_range:
- push {r0, r1, r2, r3}
- dcache_line_size r2, r3
- sub r3, r2, #1
- tst r0, r3
- bic r0, r0, r3
- /* clean & invalidate D / U line */
- mcrne p15, 0, r0, c7, c14, 1
- tst r1, r3
- bic r1, r1, r3
- /* clean & invalidate D / U line */
- mcrne p15, 0, r1, c7, c14, 1
-1:
- /* invalidate D / U line */
- mcr p15, 0, r0, c7, c6, 1
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- dsb st
- pop {r0, r1, r2, r3}
- bx lr
-
- /* clean by mva */
- .globl clean_dcache_mva
-clean_dcache_mva:
- mcr p15, 0, r0, c7, c10, 1
- dsb
- isb
- bx lr
-
- /* clean by memory region by mva range
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_dcache_mva_range
-clean_dcache_mva_range:
- push {r0, r1, r2, r3}
- dcache_line_size r2, r3
- sub r3, r2, #1
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c10, 1
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- dsb
- isb
- pop {r0, r1, r2, r3}
- bx lr
-
- /* clean and invalidate by mva */
- .globl clean_invalidate_dcache_mva
-clean_invalidate_dcache_mva:
- mcr p15, 0, r0, c7, c14, 1
- dsb
- isb
- bx lr
-
- /* clean and invalidate a memory region by mva
- * r0 - start address of region
- * r1 - end address of region
- */
- .globl clean_invalidate_dcache_mva_range
-clean_invalidate_dcache_mva_range:
- push {r0, r1, r2, r3}
- dcache_line_size r2, r3
- sub r3, r2, #1
- bic r0, r0, r3
-1:
- mcr p15, 0, r0, c7, c14, 1 /* clean & invalidate D / U line */
- add r0, r0, r2
- cmp r0, r1
- blo 1b
- dsb
- isb
- pop {r0, r1, r2, r3}
- bx lr
-
- /*
- * Operations on data cache line by set/way
- */
-
- /* invalidate line by set/way */
- .globl invalidate_dcache_line
-invalidate_dcache_line:
- mcr p15, 0, r0, c7, c6, 2
- isb
- bx lr
-
- /* clean line by set/way */
- .globl clean_dcache_line
-clean_dcache_line:
- mcr p15, 0, r0, c7, c10, 2
- dsb
- isb
- bx lr
-
- /* clean and invalidate line by set/way */
- .globl clean_invalidate_dcache_line
-clean_invalidate_dcache_line:
- mcr p15, 0, r0, c7, c14, 2
- dsb
- isb
- bx lr
-
- /*
- * Operation on entire Instruction cache
- */
-
- /* invalidate the entire i-cache */
- .globl invalidate_icache
-invalidate_icache:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* invalidate all */
- isb
- pop {r0}
- bx lr
-
- /* invalidate i-cache by mva */
- .globl invalidate_icache_mva
-invalidate_icache_mva:
- mcr p15, 0, r0, c7, c5, 0 /* invalidate all */
- isb
- bx lr
-
- /* invalidate the i-cache line by set/way */
- /* no such instruction so invalidate everything */
- .globl invalidate_icache_line
-invalidate_icache_line:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* invalidate all */
- isb
- pop {r0}
- bx lr
-
- /*
- * Operations on entire instruction an data cache
- */
-
- /* invalidate the entire i-cache and d-cache */
- .globl invalidate_idcache
-invalidate_idcache:
- push {lr}
- bl invalidate_icache
- bl invalidate_dcache
- pop {lr}
- bx lr
-
- /* clean the entire i-cache and d-cache */
- .globl clean_idcache
-clean_idcache:
- push {lr}
- bl clean_dcache
- pop {lr}
- bx lr
-
- /* clean and invalidate the entire i-cache and d-cache */
- .globl clean_invalidate_idcache
-clean_invalidate_idcache:
- push {lr}
- bl invalidate_icache
- bl clean_invalidate_dcache
- pop {lr}
- bx lr
-
- /*
- * operation on both i-cache and d-cache by mva
- */
-
- /* invalidate both i-cache and d-cache by mva */
- .globl invalidate_idcache_mva
-invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache by mva */
- .globl clean_idcache_mva
-clean_idcache_mva:
- push {lr}
- bl clean_dcache_mva
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache by mva */
- .globl clean_invalidate_idcache_mva
-clean_invalidate_idcache_mva:
- push {lr}
- bl invalidate_icache_mva
- bl clean_invalidate_dcache_mva
- pop {lr}
- bx lr
-
- /*
- * operation on both i-cache and d-cache line by set/way
- */
-
- /* invalidate both i-cache and d-cache line by set/way */
- .globl invalidate_idcache_line
-invalidate_idcache_line:
- push {lr}
- bl invalidate_icache_line
- bl invalidate_dcache_line
- pop {lr}
- bx lr
-
- /* clean both i-cache and d-cache line by set/way */
- .globl clean_idcache_line
-clean_idcache_line:
- push {lr}
- bl clean_dcache_line
- pop {lr}
- bx lr
-
- /* clean and invalidate both i-cache and d-cache line by set/way */
- .globl clean_invalidate_idcache_line
-clean_invalidate_idcache_line:
- push {lr}
- bl invalidate_icache
- bl clean_invalidate_dcache_line
- pop {lr}
- bx lr
-
- /*
- * branch predictor maintenence operation
- */
-
- /* invalidate entire branch predictor */
- .globl invalidate_bpredictor
-invalidate_bpredictor:
- push {r0}
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 6 /* invalidate all */
- isb
- pop {r0}
- bx lr
-
- /* invalidate branch predictor by mva */
- .globl invalidate_bpredictor_mva
-invalidate_bpredictor_mva:
- mcr p15, 0, r0, c7, c5, 7 /* invalidate all */
- isb
- bx lr
-
diff --git a/arch/arm/cpu/arm32/cpu_delay.S b/arch/arm/cpu/arm32/cpu_delay.S
deleted file mode 100644
index 44bf85a3..00000000
--- a/arch/arm/cpu/arm32/cpu_delay.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_delay.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of delay functions
- */
-
- /*
- * arch specific delay loop
- */
- .globl arch_delay_loop
-arch_delay_loop:
- subs r0, r0, #1
- bhi arch_delay_loop
- mov pc, lr
-
- /*
- * arch specific machine cycle count from delay loop count
- */
- .globl arch_delay_loop_cycles
-arch_delay_loop_cycles:
- push {r1, r2}
- mov r1, r0
- mov r2, #2
- mul r0, r1, r2
- pop {r1, r2}
- mov pc, lr
-
diff --git a/arch/arm/cpu/arm32/cpu_elf.c b/arch/arm/cpu/arm32/cpu_elf.c
deleted file mode 100644
index fbf6ef0f..00000000
--- a/arch/arm/cpu/arm32/cpu_elf.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_elf.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief implementation of CPU specific elf functions
- */
-
-#include <vmm_error.h>
-#include <vmm_stdio.h>
-#include <vmm_modules.h>
-#include <libs/elf.h>
-
-int arch_elf_check_hdr(const struct elf32_hdr *x)
-{
- /* Make sure it's an ARM executable */
- if (x->e_machine != EM_ARM)
- return 0;
-
- /* Make sure the entry address is reasonable */
- if (x->e_entry & 3)
- return 0;
-
- /* Don't allow unknown ABI */
- if ((x->e_flags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) {
- return 0;
- }
-
- return 1;
-}
-
-int arch_elf_apply_relocate(struct elf32_shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relindex,
- struct vmm_module *mod)
-{
- struct elf32_shdr *symsec = sechdrs + symindex;
- struct elf32_shdr *relsec = sechdrs + relindex;
- struct elf32_shdr *dstsec = sechdrs + relsec->sh_info;
- struct elf32_rel *rel = (void *)relsec->sh_addr;
- u32 i;
-
- for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rel); i++, rel++) {
- virtual_addr_t loc;
- struct elf32_sym *sym;
- const char *symname;
- s32 offset;
-
- offset = ELF32_R_SYM(rel->r_info);
- if ((offset < 0) ||
- (offset > (symsec->sh_size / sizeof(Elf32_Sym)))) {
- vmm_printf("%s: section %u reloc %u: "
- "bad relocation sym offset\n",
- mod->name, relindex, i);
- return VMM_ENOEXEC;
- }
-
- sym = ((Elf32_Sym *)symsec->sh_addr) + offset;
- symname = strtab + sym->st_name;
-
- if (((s32)rel->r_offset < 0) ||
- (rel->r_offset > dstsec->sh_size - sizeof(u32))) {
- vmm_printf("%s: section %u reloc %u sym '%s': out of "
- "bounds relocation, offset %d size %u\n",
- mod->name, relindex, i, symname,
- rel->r_offset, dstsec->sh_size);
- return VMM_ENOEXEC;
- }
-
- loc = dstsec->sh_addr + rel->r_offset;
-
- switch (ELF32_R_TYPE(rel->r_info)) {
- case R_ARM_NONE:
- /* ignore */
- break;
-
- case R_ARM_ABS32:
- *(u32 *)loc += sym->st_value;
- break;
-
- case R_ARM_PC24:
- case R_ARM_CALL:
- case R_ARM_JUMP24:
- offset = (*(u32 *)loc & 0x00ffffff) << 2;
- if (offset & 0x02000000)
- offset -= 0x04000000;
-
- offset += sym->st_value - loc;
- if (offset & 3 ||
- offset <= (s32)0xfe000000 ||
- offset >= (s32)0x02000000) {
- vmm_printf("%s: section %u reloc %u sym '%s': "
- "relocation %u out of range (%"PRIADDR" -> %#x)\n",
- mod->name, relindex, i, symname,
- ELF32_R_TYPE(rel->r_info), loc,
- sym->st_value);
- return VMM_ENOEXEC;
- }
-
- offset >>= 2;
-
- *(u32 *)loc &= 0xff000000;
- *(u32 *)loc |= offset & 0x00ffffff;
- break;
-
- case R_ARM_V4BX:
- /* Preserve Rm and the condition code. Alter
- * other bits to re-code instruction as
- * MOV PC,Rm.
- */
- *(u32 *)loc &= 0xf000000f;
- *(u32 *)loc |= 0x01a0f000;
- break;
-
- case R_ARM_PREL31:
- offset = *(u32 *)loc + sym->st_value - loc;
- *(u32 *)loc = offset & 0x7fffffff;
- break;
-
- case R_ARM_MOVW_ABS_NC:
- case R_ARM_MOVT_ABS:
- offset = *(u32 *)loc;
- offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
- offset = (offset ^ 0x8000) - 0x8000;
-
- offset += sym->st_value;
- if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
- offset >>= 16;
-
- *(u32 *)loc &= 0xfff0f000;
- *(u32 *)loc |= ((offset & 0xf000) << 4) |
- (offset & 0x0fff);
- break;
-
- default:
- vmm_printf("%s: unknown relocation: %u\n",
- mod->name, ELF32_R_TYPE(rel->r_info));
- return VMM_ENOEXEC;
- }
- }
- return 0;
-}
-
-int arch_elf_apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct vmm_module *mod)
-{
- vmm_printf("module %s: ADD RELOCATION unsupported\n", mod->name);
- return VMM_ENOEXEC;
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_entry.S b/arch/arm/cpu/arm32/cpu_entry.S
deleted file mode 100644
index 430827df..00000000
--- a/arch/arm/cpu/arm32/cpu_entry.S
+++ /dev/null
@@ -1,704 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * Copyright (c) 2012 Sukanto Ghosh
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_entry.S
- * @author Anup Patel (an...@brainfault.org)
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @author Sukanto Ghosh (sukant...@gmail.com)
- * @brief various entry points (booting, reset, exceptions) to xvisor
- */
-
-#include <cpu_defines.h>
-
- /*
- * _start: Primary CPU startup code
- * _start_secondary: Secondary CPU startup code
- * _start_secondary_nopen: Secondary CPU startup code without holding pen
- *
- * Note: Xvisor could be loaded any where in memory by boot loaders.
- * The _start ensures that Xvisor executes from intended base address
- * provided at compile time.
- */
- .section .entry, "ax", %progbits
- .globl _start
- .globl _start_secondary
- .globl _start_secondary_nopen
-_start:
- /* r4 -> load start
- * r5 -> load end
- * r6 -> execution start
- * r7 -> execution end
- * r10 -> core# in case of SMP
- */
- add r4, pc, #-0x8
- ldr r6, __exec_start
- ldr r7, __exec_end
- sub r3, r7, r6
- add r5, r4, r3
-
- /* Save boot reg0 (i.e. r0) */
- ldr r3, __boot_reg0
- sub r3, r3, r6
- add r3, r3, r4
- str r0, [r3]
-
- /* Save boot reg1 (i.e. r1) */
- ldr r3, __boot_reg1
- sub r3, r3, r6
- add r3, r3, r4
- str r1, [r3]
-
- /* Save boot reg2 (i.e. r2) */
- ldr r3, __boot_reg2
- sub r3, r3, r6
- add r3, r3, r4
- str r2, [r3]
-
- /* Save load start and load end */
- ldr r0, __load_start
- sub r0, r0, r6
- add r0, r0, r4
- str r4, [r0]
- ldr r0, __load_end
- sub r0, r0, r6
- add r0, r0, r4
- str r5, [r0]
-
- /* Hang if execution start is not 4KB aligned */
- mov r0, r6
- mov r0, r0, lsr #12
- mov r0, r0, lsl #12
- cmp r0, r6
- blt .
-
- /* Hang if execution end is not 4KB aligned */
- mov r0, r7
- mov r0, r0, lsr #12
- mov r0, r0, lsl #12
- cmp r0, r7
- blt .
-
- /* Zero-out bss section */
- mov r0, #0
- ldr r1, __bss_start
- sub r1, r1, r6
- add r1, r1, r4
- ldr r2, __bss_end
- sub r2, r2, r6
- add r2, r2, r4
-_bss_zero:
- str r0, [r1], #4
- cmp r1, r2
- blt _bss_zero
-
-align_4k_boundary:
- /* Relocate code if load start is not 4KB aligned */
- mov r0, r4
- mov r0, r0, lsr #12
- mov r0, r0, lsl #12
- cmp r0, r4
- /* Skip relocation if already aligned */
- beq _start_mmu_init
-
- /* Relocate copy function at end after load end address */
- ldr r0, __copy_start
- ldr r1, __copy_end
- sub r2, r1, r0 /* r2 -> __copy size */
- sub r0, r0, r6
- add r0, r0, r4 /* r0 -> load_address of copy_start */
- mov r1, r5 /* r1 -> load end */
- bl _copy /* copy the _copy function after the code */
-
- /* Use newly relocated copy function to relocate entire code
- * to 1MB boundary
- */
- mov r0, r4 /* r0 -> load start */
- mov r1, r4
- mov r1, r1, lsr #12
- mov r1, r1, lsl #12 /* r1 -> load start aligned to 4KB boundary */
- sub r2, r5, r4 /* r2 -> code size */
- bl _start_nextpc1
-_start_nextpc1:
- add lr, lr, #16 /* Adjust return address (lr) for jump to */
- sub lr, lr, r4 /* relocated address on return from _copy */
- add lr, lr, r1
- bx r5 /* call _copy */
- /* Update load start and load end */
- mov r0, r4
- mov r0, r0, lsr #12
- mov r0, r0, lsl #12 /* r0 -> load_start aligned to 4KB boundary */
- subs r1, r4, r0 /* r1 -> offset between load start and aligned address */
- subs r4, r4, r1 /* r4 -> new load start */
- subs r5, r5, r1 /* r5 -> new load end */
- ldr r0, __load_start
- sub r0, r0, r6
- add r0, r0, r4
- str r4, [r0]
- ldr r0, __load_end
- sub r0, r0, r6
- add r0, r0, r4
- str r5, [r0]
-
-_start_mmu_init:
- ldr r0, __defl1_ttbl
- sub r0, r0, r6
- add r0, r0, r4
- ldr r1, __defl1_ttbl_addr
- sub r1, r1, r6
- add r1, r1, r4
- str r0, [r1]
-
- ldr sp, __svc_stack_end
- sub sp, sp, r6
- add sp, sp, r4
-
- /* AAPCS: ensure strict 64-bits alignment for SP */
- sub sp, sp, #8
- bic sp, sp, #7
-
- mov r0, r4
- mov r1, r5
- mov r2, r6
- ldr r3, __boot_reg2
- sub r3, r3, r6
- add r3, r3, r4
- ldr r3, [r3]
- bl _setup_initial_ttbl
- b _start_secondary_nopen
-
-/*
- * CMODE - Change processor mode
- * \rs : the GPR having cpsr value
- * \mode : target processor mode
- *
- * Please note we do *not* read cpsr here
- * \rs is supposed to have cpsr before calling this
- * This macro is called from performance critical paths
- * (read exception entry/exit) and to allow optimizations
- * we do *not* read cpsr in this macro and instead
- * expect \rs to have cpsr before calling this.
- */
-#if (__ARM_ARCH_VERSION__ < 6)
-.macro CMODE rs mode
- and \rs, \rs, #~(CPSR_MODE_MASK)
- orr \rs, \rs, #\mode
- msr cpsr_c, \rs
-.endm
-#else
-.macro CMODE rs mode
- cps #\mode
-.endm
-#endif
-
-#ifdef CONFIG_SMP
- .align 3
-__start_secondary_smp_id:
- .word start_secondary_smp_id
- .align 3
-__start_secondary_pen_release:
- .word start_secondary_pen_release
-
- /*
- * Secondary CPU startup code
- */
-_start_secondary:
- /*
- * This provides a "holding pen" for platforms to hold all secondary
- * cores are held until we're ready for them to initialise.
- */
- mrc p15, 0, r0, c0, c0, 5
- ldr r1, =MPIDR_HWID_BITMASK
- and r0, r0, r1
-
- /* Calculate load address of secondary_holding_pen_release */
- ldr r1, __start_secondary_pen_release
- ldr r2, __exec_start
- ldr r3, _load_start
- sub r1, r1, r2
- add r1, r1, r3
- sev
-pen: wfe
- ldr r4, [r1]
- cmp r4, r0
- bne pen
-#endif
-
- /*
- * Note: From this point primary CPU startup is same as secondary CPU
- */
-_start_secondary_nopen:
- /*
- * Latest ARMv7 bootloaders will enter Xvisor in HYP-mode
- * if Virtualization extenstion is available as-per Linux
- * ARM32 booting protocol.
- *
- * For sanity we force-fully switch to SVC mode.
- */
- CMODE r0, CPSR_MODE_SUPERVISOR
-
- /* Setup Translation Table Base Register 0 */
- ldr r0, __defl1_ttbl
- mcr p15, 0, r0, c2, c0, 0
-
- /* Setup Domain Control Register */
- ldr r1, __dacr_mmu_val
- mcr p15, 0, r1, c3, c0, 0
-
- /* Setup System Control Register */
- bl proc_setup
- mcr p15, 0, r0, c1, c0, 0
-
- /* Jump to reset code */
- ldr pc, __reset
-
- /* We should never reach here. */
- b .
-
-#if (__ARM_ARCH_VERSION__ < 6)
-#define TTBL_L1TBL_TTE_ARCH_ATTR TTBL_L1TBL_TTE_REQ_MASK
-#else
-#define TTBL_L1TBL_TTE_ARCH_ATTR (TTBL_L1TBL_TTE_C_MASK | \
- TTBL_L1TBL_TTE_B_MASK)
-#endif
-
-#define SECTION_ATTR ((TTBL_AP_SRW_U << TTBL_L1TBL_TTE_AP_SHIFT) | \
- (TTBL_L1TBL_TTE_DOM_RESERVED << TTBL_L1TBL_TTE_DOM_SHIFT) | \
- TTBL_L1TBL_TTE_ARCH_ATTR | \
- TTBL_L1TBL_TTE_TYPE_SECTION)
-
-__mmu_section_attr:
- .word SECTION_ATTR
-__dacr_mmu_val:
- .word (TTBL_DOM_CLIENT << (2 * TTBL_L1TBL_TTE_DOM_RESERVED))
-__boot_reg0:
- .word _boot_reg0
-__boot_reg1:
- .word _boot_reg1
-__boot_reg2:
- .word _boot_reg2
-__exec_start:
- .word _code_start
-__exec_end:
- .word _code_end
-__load_start:
- .word _load_start
-__load_end:
- .word _load_end
-__bss_start:
- .word _bss_start
-__bss_end:
- .word _bss_end
-__copy_start:
- .word _copy
-__copy_end:
- .word _copy_end
-__defl1_ttbl_addr:
- .word __defl1_ttbl
-__defl1_ttbl:
- .word defl1_ttbl
-#if (__ARM_ARCH_VERSION__ < 6)
- .globl _ifar
-_ifar:
- .word 0x0
- .globl _abort_inst
-_abort_inst:
- .word 0x0
-#endif
-
- /*
- * Boot register 0 passed by bootloader
- */
- .globl _boot_reg0
-_boot_reg0:
- .word 0x0
-
- /*
- * Boot register 1 passed by bootloader
- */
- .globl _boot_reg1
-_boot_reg1:
- .word 0x0
-
- /*
- * Boot register 2 passed by bootloader
- */
- .globl _boot_reg2
-_boot_reg2:
- .word 0x0
-
- /*
- * Load start address storage
- */
- .globl _load_start
-_load_start:
- .word 0x0
-
- /*
- * Load end address storage
- */
- .globl _load_end
-_load_end:
- .word 0x0
-
- /*
- * Copy data from source to destination
- * Arguments:
- * r0 -> source address
- * r1 -> destination address
- * r2 -> byte count
- * Return:
- * r0 -> bytes copied
- */
- .section .entry, "ax", %progbits
- .globl _copy
-_copy:
- mov r3, r2
-_copy_loop:
- cmp r3, #0
- beq _copy_done
- cmp r3, #16
- bge _copy_chunk
-_copy_word:
- ldmia r0!, {r8}
- stmia r1!, {r8}
- sub r3, r3, #4
- b _copy_loop
-_copy_chunk:
- ldmia r0!, {r8 - r11}
- stmia r1!, {r8 - r11}
- sub r3, r3, #16
- b _copy_loop
-_copy_done:
- mov r0, r2
- bx lr
-_copy_end:
-
- /*
- * Exception vector start.
- */
- .section .entry, "ax", %progbits
- .globl _start_vect
-_start_vect:
- ldr pc, __reset
- ldr pc, __undefined_instruction
- ldr pc, __software_interrupt
- ldr pc, __prefetch_abort
- ldr pc, __data_abort
- ldr pc, __not_used
- ldr pc, __irq
- ldr pc, __fiq
-__reset:
- .word _reset
-__undefined_instruction:
- .word _undef_inst
-__software_interrupt:
- .word _soft_irq
-__prefetch_abort:
- .word _prefetch_abort
-__data_abort:
- .word _data_abort
-__not_used:
- .word _not_used
-__irq:
- .word _irq
-__fiq:
- .word _fiq
- .global _end_vect
-_end_vect:
- b .
-
- /*
- * Exception stacks.
- */
-__svc_stack_end:
- .word _svc_stack_end
-__und_stack_end:
- .word _und_stack_end
-__abt_stack_end:
- .word _abt_stack_end
-__irq_stack_end:
- .word _irq_stack_end
-__fiq_stack_end:
- .word _fiq_stack_end
-
- /*
- * Reset exception handler.
- * Reset hardware state before starting Xvisor.
- */
- .globl _reset
-_reset:
-#ifdef CONFIG_SMP
- /* Setup SMP ID for current processor */
- ldr r1, __start_secondary_smp_id
- ldr r0, [r1]
- bl proc_setup_smp_id
-#endif
- /* Clear a register for temporary usage */
- mov r8, #0
- /* Disable IRQ & FIQ */
- mrs r8, cpsr_all
- orr r8, r8, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
- msr cpsr_cxsf, r8
- /* Set Supervisor Mode Stack */
- CMODE r8, CPSR_MODE_SUPERVISOR
- ldr sp, __svc_stack_end
-#ifdef CONFIG_SMP
- bl arch_smp_id
- mov r10, r0
- mov r9, #CONFIG_IRQ_STACK_SIZE
- mul r9, r9, r10
- sub sp, sp, r9
-#endif
- /* Set Undefined Mode Stack */
- CMODE r8, CPSR_MODE_UNDEFINED
- ldr sp, __und_stack_end
-#ifdef CONFIG_SMP
- bl arch_smp_id
- mov r10, r0
- mov r9, #0x100
- mul r9, r9, r10
- sub sp, sp, r9
-#endif
- /* Set Abort Mode Stack */
- CMODE r8, CPSR_MODE_ABORT
- ldr sp, __abt_stack_end
-#ifdef CONFIG_SMP
- bl arch_smp_id
- mov r10, r0
- mov r9, #0x100
- mul r9, r9, r10
- sub sp, sp, r9
-#endif
- /* Set IRQ Mode Stack */
- CMODE r8, CPSR_MODE_IRQ
- ldr sp, __irq_stack_end
-#ifdef CONFIG_SMP
- bl arch_smp_id
- mov r10, r0
- mov r9, #0x100
- mul r9, r9, r10
- sub sp, sp, r9
-#endif
- /* Set FIQ Mode Stack */
- CMODE r8, CPSR_MODE_FIQ
- ldr sp, __fiq_stack_end
-#ifdef CONFIG_SMP
- bl arch_smp_id
- mov r10, r0
- mov r9, #0x100
- mul r9, r9, r10
- sub sp, sp, r9
-#endif
-
- /* AAPCS: ensure strict 64-bits alignment for SP */
- sub sp, sp, #8
- bic sp, sp, #7
-
- /* Set to Supervisor Mode */
- CMODE r8, CPSR_MODE_SUPERVISOR
- /* Call CPU init function */
- b cpu_init
- /* We should never reach here */
- b .
-
- /*
- * Helper Macros for Exception Handlers
- */
-.macro EXCEPTION_HANDLER irqname, lroffset
- .align 5
-\irqname:
- sub lr, lr, #\lroffset;
-.endm
-
-/* Save arch registers into small mode-specific stack */
-.macro PUSH_REGS mode=CPSR_MODE_SUPERVISOR
- /* Save return address and return machine state */
- .if \mode != CPSR_MODE_SUPERVISOR
- /* Temporary save return address, machine state, R0 and R1 */
- str lr, [sp, #-4];
- mrs lr, spsr_all;
- str lr, [sp, #-8];
- str r1, [sp, #-12];
- str r0, [sp, #-16];
- /* Point R0 to temporary location */
- mov r0, sp
-#if (__ARM_ARCH_VERSION__ < 6)
- mrs lr, cpsr_all;
- and lr, lr, #~(CPSR_MODE_MASK);
- orr lr, lr, #CPSR_MODE_SUPERVISOR;
- msr cpsr_c, lr;
-#else
- cps #CPSR_MODE_SUPERVISOR;
-#endif
- /* Save return address (i.e. return PC) */
- ldr r1, [r0, #-4];
- str r1, [sp, #-4]!;
- /* Save return machine state and decrement stack pointer */
- ldr r1, [r0, #-8];
- str r1, [sp, #-(4*16)];
- /* Restore R0, R1 register */
- ldr r1, [r0, #-12];
- ldr r0, [r0, #-16];
- .else
- /* Save return address (i.e. return PC) */
- str lr, [sp, #-4]!;
- /* Save return machine state and decrement stack pointer */
- mrs lr, spsr_all;
- str lr, [sp, #-(4*16)];
- .endif
-
- /* Save r0, r1, ..., r14 and decrement stack pointer */
- stmdb sp, {r0-r14}^;
- sub sp, sp, #(4*16);
-
- /* If we came from privildeged (or non-usr) mode then
- * overwrite r13, r14 with mode specific banked values
- * else skip this step
- */
- ldr r4, [sp];
- and r0, r4, #CPSR_MODE_MASK;
- cmp r0, #CPSR_MODE_USER;
- beq 100f;
- cmp r0, #CPSR_MODE_SUPERVISOR;
- beq 101f;
-
- /* We handle all exceptions, irqs, and fiqs in SVC mode so,
- * should never reach here. Just sit in infinite loop !!!!!
- */
- b .;
-
- /* Came from svc mode */
-101: add r1, sp, #(4*17);
- str r1, [sp, #(4*14)];
- str lr, [sp, #(4*15)];
-
- /* Came from usr mode */
-100: add r1, sp, #(4*17);
- str r1, [sp, #-4]!;
- mov r0, sp;
-.endm
-
-/* Call C function to handle exception */
-.macro CALL_EXCEPTION_CFUNC cfunc
- bl \cfunc;
-.endm
-
-/* Restore registers from arch registers */
-.macro PULL_REGS mode=CPSR_MODE_SUPERVISOR
- /* Get arch register pointer.
- * r12 -> pointer to arch regs
- */
- mov r12, sp;
-
- /* Restore exception stack */
- ldr sp, [r12], #4;
-
- /* Restore target CPSR */
- ldr r1, [r12], #4;
- msr spsr_cxsf, r1;
-
- /* If-else ladder for different target modes */
- and r0, r1, #CPSR_MODE_MASK;
- cmp r0, #CPSR_MODE_USER;
- beq 200f;
- cmp r0, #CPSR_MODE_SUPERVISOR;
- beq 201f;
-
- /* We handle all exceptions, irqs, and fiqs in SVC mode so,
- * should never reach here. Just sit in infinite loop !!!!!
- */
- b .;
-
- /* Going back to usr mode */
-200: ldr lr, [r12, #(4*15)];
- ldmia r12, {r0-r14}^;
- movs pc, lr
-
- /* Going back to svc mode */
-201: ldm r12, {r0-r15}^;
- mov r0, r0;
-.endm
-
- /*
- * Undefined instruction exception handler.
- */
-EXCEPTION_HANDLER _undef_inst, 4
- PUSH_REGS CPSR_MODE_UNDEFINED
- CALL_EXCEPTION_CFUNC do_undef_inst
- PULL_REGS CPSR_MODE_UNDEFINED
-
- /*
- * Software interrupt exception handler.
- */
-EXCEPTION_HANDLER _soft_irq, 4
- PUSH_REGS
- CALL_EXCEPTION_CFUNC do_soft_irq
- PULL_REGS
-
- /*
- * Prefetch abort exception handler.
- */
-EXCEPTION_HANDLER _prefetch_abort, 4
- PUSH_REGS CPSR_MODE_ABORT
-#if (__ARM_ARCH_VERSION__ < 6)
- ldr r1, _ifar;
- ldr lr, [r0, #(4 * 17)]
- str lr, [r1];
-#endif
- CALL_EXCEPTION_CFUNC do_prefetch_abort
- PULL_REGS CPSR_MODE_ABORT
-
- /*
- * Data abort exception handler.
- */
-EXCEPTION_HANDLER _data_abort, 8
- PUSH_REGS CPSR_MODE_ABORT
-#if (__ARM_ARCH_VERSION__ < 6)
- ldr r1, _abort_inst;
- ldr lr, [r0, #(4 * 17)]
- str lr, [r1];
-#endif
- CALL_EXCEPTION_CFUNC do_data_abort
- PULL_REGS CPSR_MODE_ABORT
-
- /*
- * Not used exception handler.
- */
-EXCEPTION_HANDLER _not_used, 4
- PUSH_REGS
- CALL_EXCEPTION_CFUNC do_not_used
- PULL_REGS
-
- /*
- * IRQ exception handler.
- */
-EXCEPTION_HANDLER _irq, 4
- PUSH_REGS CPSR_MODE_IRQ
- CALL_EXCEPTION_CFUNC do_irq
- PULL_REGS CPSR_MODE_IRQ
-
- /*
- * FIQ exception handler.
- */
-EXCEPTION_HANDLER _fiq, 4
- PUSH_REGS CPSR_MODE_FIQ
- CALL_EXCEPTION_CFUNC do_fiq
- PULL_REGS CPSR_MODE_FIQ
-
diff --git a/arch/arm/cpu/arm32/cpu_init.c b/arch/arm/cpu/arm32/cpu_init.c
deleted file mode 100644
index 5fe3082b..00000000
--- a/arch/arm/cpu/arm32/cpu_init.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_init.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief intialization functions for CPU
- */
-
-#include <vmm_error.h>
-#include <vmm_main.h>
-#include <vmm_params.h>
-#include <vmm_devtree.h>
-#include <arch_cpu.h>
-#include <arm_psci.h>
-#include <cpu_inline_asm.h>
-
-extern u8 _code_start;
-extern u8 _code_end;
-extern u32 _load_start;
-extern u32 _load_end;
-
-virtual_addr_t arch_code_vaddr_start(void)
-{
- return (virtual_addr_t) &_code_start;
-}
-
-physical_addr_t arch_code_paddr_start(void)
-{
- return (physical_addr_t) _load_start;
-}
-
-virtual_size_t arch_code_size(void)
-{
- return (virtual_size_t) (&_code_end - &_code_start);
-}
-
-void arch_cpu_print(struct vmm_chardev *cdev, u32 cpu)
-{
- /* FIXME: To be implemented. */
-}
-
-void arch_cpu_print_summary(struct vmm_chardev *cdev)
-{
- /* FIXME: To be implemented. */
-}
-
-int __init arch_cpu_nascent_init(void)
-{
- /* Host aspace, Heap, and Device tree available. */
-
- /* Do PSCI init */
- psci_init();
-
- return 0;
-}
-
-int __init arch_cpu_early_init(void)
-{
- const char *options;
- struct vmm_devtree_node *node;
-
- /*
- * Host virtual memory, device tree, heap, and host irq available.
- * Do necessary early stuff like iomapping devices
- * memory or boot time memory reservation here.
- */
-
- node = vmm_devtree_getnode(VMM_DEVTREE_PATH_SEPARATOR_STRING
- VMM_DEVTREE_CHOSEN_NODE_NAME);
- if (!node) {
- return VMM_ENODEV;
- }
-
- if (vmm_devtree_read_string(node,
- VMM_DEVTREE_BOOTARGS_ATTR_NAME, &options) == VMM_OK) {
- vmm_parse_early_options(options);
- }
-
- vmm_devtree_dref_node(node);
-
- return VMM_OK;
-}
-
-int __init arch_cpu_final_init(void)
-{
- /* All VMM API's are available here */
- /* We can register a CPU specific resources here */
-
- return VMM_OK;
-}
-
-void __init cpu_init(void)
-{
- /* Allow full-access to cp10 & cp11 if CPU supports FPU */
- write_cpacr(CPACR_CP_MASK(11) | CPACR_CP_MASK(10));
-
- /* Initialize VMM (APIs only available after this) */
- vmm_init();
-
- /* We will never come back here. */
- vmm_hang();
-}
diff --git a/arch/arm/cpu/arm32/cpu_interrupts.c b/arch/arm/cpu/arm32/cpu_interrupts.c
deleted file mode 100644
index f5f2c0ee..00000000
--- a/arch/arm/cpu/arm32/cpu_interrupts.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_interrupts.c
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code for handling cpu interrupts
- */
-
-#include <vmm_error.h>
-#include <vmm_smp.h>
-#include <vmm_stdio.h>
-#include <vmm_host_ram.h>
-#include <vmm_host_vapool.h>
-#include <vmm_host_aspace.h>
-#include <vmm_host_irq.h>
-#include <vmm_vcpu_irq.h>
-#include <vmm_scheduler.h>
-#include <emulate_arm.h>
-#include <emulate_thumb.h>
-#include <cpu_inline_asm.h>
-#include <cpu_mmu.h>
-#include <cpu_vcpu_hypercall_arm.h>
-#include <cpu_vcpu_hypercall_thumb.h>
-#include <cpu_vcpu_cp15.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_defines.h>
-
-void do_undef_inst(arch_regs_t *regs)
-{
- int rc = VMM_OK;
- struct vmm_vcpu *vcpu;
-
- if ((regs->cpsr & CPSR_MODE_MASK) != CPSR_MODE_USER) {
- vmm_panic("%s: unexpected exception\n", __func__);
- }
-
- vmm_scheduler_irq_enter(regs, TRUE);
-
- vcpu = vmm_scheduler_current_vcpu();
-
- /* If vcpu priviledge is user then generate exception
- * and return without emulating instruction
- */
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- vmm_vcpu_irq_assert(vcpu, CPU_UNDEF_INST_IRQ, 0x0);
- } else {
- if (regs->cpsr & CPSR_THUMB_ENABLED) {
- rc = emulate_thumb_inst(vcpu, regs,
- *((u32 *)regs->pc));
- } else {
- rc = emulate_arm_inst(vcpu, regs,
- *((u32 *)regs->pc));
- }
- }
-
- if (rc) {
- vmm_printf("%s: error %d\n", __func__, rc);
- }
-
- vmm_scheduler_irq_exit(regs);
-}
-
-void do_soft_irq(arch_regs_t *regs)
-{
- int rc = VMM_OK;
- struct vmm_vcpu * vcpu;
-
- if ((regs->cpsr & CPSR_MODE_MASK) == CPSR_MODE_SUPERVISOR) {
- regs->pc += 4;
- vmm_scheduler_preempt_orphan(regs);
- return;
- } else if ((regs->cpsr & CPSR_MODE_MASK) != CPSR_MODE_USER) {
- vmm_panic("%s: unexpected exception\n", __func__);
- }
-
- vmm_scheduler_irq_enter(regs, TRUE);
-
- vcpu = vmm_scheduler_current_vcpu();
-
- /* If vcpu priviledge is user then generate exception
- * and return without emulating instruction
- */
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- vmm_vcpu_irq_assert(vcpu, CPU_SOFT_IRQ, 0x0);
- } else {
- if (regs->cpsr & CPSR_THUMB_ENABLED) {
- rc = cpu_vcpu_hypercall_thumb(vcpu, regs,
- *((u32 *)regs->pc));
- } else {
- rc = cpu_vcpu_hypercall_arm(vcpu, regs,
- *((u32 *)regs->pc));
- }
- }
-
- if (rc) {
- vmm_printf("%s: error %d\n", __func__, rc);
- }
-
- vmm_scheduler_irq_exit(regs);
-}
-
-void do_prefetch_abort(arch_regs_t *regs)
-{
- int rc = VMM_OK;
- bool crash_dump = FALSE;
- u32 ifsr, ifar, fs;
- struct vmm_vcpu *vcpu;
- struct cpu_vcpu_cp15_fault_info info;
-
- ifsr = read_ifsr();
- ifar = read_ifar();
-
- fs = (ifsr & IFSR_FS_MASK);
-#if !defined(CONFIG_ARMV5)
- fs |= (ifsr & IFSR_FS4_MASK) >> (IFSR_FS4_SHIFT - 4);
-#endif
-
- if ((regs->cpsr & CPSR_MODE_MASK) != CPSR_MODE_USER) {
- struct cpu_l1tbl * l1;
- struct cpu_page pg;
- if (fs != IFSR_FS_TRANS_FAULT_SECTION &&
- fs != IFSR_FS_TRANS_FAULT_PAGE) {
- vmm_panic("%s: unexpected prefetch abort\n"
- "%s: pc = 0x%08x, ifsr = 0x%08x, ifar = 0x%08x\n",
- __func__, __func__, regs->pc, ifsr, ifar);
- }
- rc = cpu_mmu_get_reserved_page((virtual_addr_t)ifar, &pg);
- if (rc) {
- vmm_panic("%s: cannot find reserved page\n"
- "%s: ifsr = 0x%08x, ifar = 0x%08x\n",
- __func__, __func__, ifsr, ifar);
- }
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- vmm_panic("%s: cannot find l1 table\n"
- "%s: ifsr = 0x%08x, ifar = 0x%08x\n",
- __func__, __func__, ifsr, ifar);
- }
- rc = cpu_mmu_map_page(l1, &pg);
- if (rc) {
- vmm_panic("%s: cannot map page in l1 table\n"
- "%s: ifsr = 0x%08x, ifar = 0x%08x\n",
- __func__, __func__, ifsr, ifar);
- }
- return;
- }
-
- vcpu = vmm_scheduler_current_vcpu();
-
- if ((regs->pc & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) ==
- arm_priv(vcpu)->cp15.ovect_base) {
- regs->pc = (virtual_addr_t)arm_guest_priv(vcpu->guest)->ovect
- + (regs->pc & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
- return;
- }
-
- vmm_scheduler_irq_enter(regs, TRUE);
-
- switch(fs) {
- case IFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_1:
- case IFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_2:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case IFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_1:
- case IFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_2:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case IFSR_FS_TRANS_FAULT_SECTION:
- case IFSR_FS_TRANS_FAULT_PAGE:
- info.regs = regs;
- info.far = ifar;
- info.fs = fs;
- info.dom = 0;
- info.wnr = 0;
- info.xn = 0;
- rc = cpu_vcpu_cp15_trans_fault(vcpu, &info, FALSE);
- crash_dump = TRUE;
- break;
- case IFSR_FS_ACCESS_FAULT_SECTION:
- case IFSR_FS_ACCESS_FAULT_PAGE:
- info.regs = regs;
- info.far = ifar;
- info.fs = fs;
- info.dom = 0;
- info.wnr = 0;
- info.xn = 0;
- rc = cpu_vcpu_cp15_access_fault(vcpu, &info);
- crash_dump = TRUE;
- break;
- case IFSR_FS_DOMAIN_FAULT_SECTION:
- case IFSR_FS_DOMAIN_FAULT_PAGE:
- info.regs = regs;
- info.far = ifar;
- info.fs = fs;
- info.dom = 0;
- info.wnr = 0;
- info.xn = 0;
- rc = cpu_vcpu_cp15_domain_fault(vcpu, &info);
- crash_dump = TRUE;
- break;
- case IFSR_FS_PERM_FAULT_SECTION:
- case IFSR_FS_PERM_FAULT_PAGE:
- info.regs = regs;
- info.far = ifar;
- info.fs = fs;
- info.dom = 0;
- info.wnr = 0;
- info.xn = 0;
- rc = cpu_vcpu_cp15_perm_fault(vcpu, &info);
- crash_dump = TRUE;
- break;
- case IFSR_FS_DEBUG_EVENT:
- case IFSR_FS_SYNC_EXT_ABORT:
- case IFSR_FS_IMP_VALID_LOCKDOWN:
- case IFSR_FS_IMP_VALID_COPROC_ABORT:
- case IFSR_FS_MEM_ACCESS_SYNC_PARITY_ERROR:
- vmm_manager_vcpu_halt(vcpu);
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- default:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- };
-
- if (rc && crash_dump) {
- vmm_printf("\n");
- vmm_printf("%s: error %d\n", __func__, rc);
- vmm_printf("%s: vcpu_id = %d, ifar = 0x%x, ifsr = 0x%x\n",
- __func__, vcpu->id, ifar, ifsr);
- cpu_vcpu_dump_user_reg(vcpu, regs);
- }
-
- vmm_scheduler_irq_exit(regs);
-}
-
-void do_data_abort(arch_regs_t *regs)
-{
- int rc = VMM_OK;
- bool crash_dump = FALSE;
- u32 dfsr, dfar, fs, dom, wnr;
- struct vmm_vcpu *vcpu;
- struct cpu_l1tbl *l1;
- struct cpu_page pg;
- struct cpu_vcpu_cp15_fault_info info;
-
- dfsr = read_dfsr();
- dfar = read_dfar();
-
- fs = (dfsr & DFSR_FS_MASK);
-#if !defined(CONFIG_ARMV5)
- fs |= (dfsr & DFSR_FS4_MASK) >> (DFSR_FS4_SHIFT - 4);
-#endif
- wnr = (dfsr & DFSR_WNR_MASK) >> DFSR_WNR_SHIFT;
- dom = (dfsr & DFSR_DOM_MASK) >> DFSR_DOM_SHIFT;
-
- if ((regs->cpsr & CPSR_MODE_MASK) != CPSR_MODE_USER) {
- if (fs != DFSR_FS_TRANS_FAULT_SECTION &&
- fs != DFSR_FS_TRANS_FAULT_PAGE) {
- vmm_panic("%s: unexpected data abort (pc = 0x%08x)\n"
- "%s: dfsr = 0x%08x, dfar = 0x%08x\n",
- __func__, regs->pc, __func__, dfsr, dfar);
- }
- if (!vmm_host_vapool_isvalid(dfar)) {
- /* If we were in normal context and fault address
- * is not a VAPOOL address then just handle
- * trans fault for current normal VCPU and exit
- * else there is nothing we can do so panic.
- */
- if (vmm_scheduler_normal_context()) {
- vcpu = vmm_scheduler_current_vcpu();
- info.regs = regs;
- info.far = dfar;
- info.fs = fs;
- info.dom = dom;
- info.wnr = wnr;
- info.xn = 1;
- if (!cpu_vcpu_cp15_trans_fault(vcpu,
- &info, FALSE))
- return;
- }
- }
- rc = cpu_mmu_get_reserved_page(dfar, &pg);
- if (rc) {
- vmm_panic("%s: cannot find reserved page\n"
- "%s: dfsr = 0x%08x, dfar = 0x%08x\n",
- __func__, __func__, dfsr, dfar);
- }
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- vmm_panic("%s: cannot find l1 table\n"
- "%s: dfsr = 0x%08x, dfar = 0x%08x\n",
- __func__, __func__, dfsr, dfar);
- }
- rc = cpu_mmu_map_page(l1, &pg);
- if (rc) {
- vmm_panic("%s: cannot map page in l1 table\n"
- "%s: dfsr = 0x%08x, dfar = 0x%08x\n",
- __func__, __func__, dfsr, dfar);
- }
- return;
- }
-
- vcpu = vmm_scheduler_current_vcpu();
-
- vmm_scheduler_irq_enter(regs, TRUE);
-
- switch(fs) {
- case DFSR_FS_ALIGN_FAULT:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case DFSR_FS_ICACHE_MAINT_FAULT:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case DFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_1:
- case DFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_2:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case DFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_1:
- case DFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_2:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- case DFSR_FS_TRANS_FAULT_SECTION:
- case DFSR_FS_TRANS_FAULT_PAGE:
- info.regs = regs;
- info.far = dfar;
- info.fs = fs;
- info.dom = dom;
- info.wnr = wnr;
- info.xn = 1;
- rc = cpu_vcpu_cp15_trans_fault(vcpu, &info, FALSE);
- crash_dump = TRUE;
- break;
- case DFSR_FS_ACCESS_FAULT_SECTION:
- case DFSR_FS_ACCESS_FAULT_PAGE:
- info.regs = regs;
- info.far = dfar;
- info.fs = fs;
- info.dom = dom;
- info.wnr = wnr;
- info.xn = 1;
- rc = cpu_vcpu_cp15_access_fault(vcpu, &info);
- crash_dump = TRUE;
- break;
- case DFSR_FS_DOMAIN_FAULT_SECTION:
- case DFSR_FS_DOMAIN_FAULT_PAGE:
- info.regs = regs;
- info.far = dfar;
- info.fs = fs;
- info.dom = dom;
- info.wnr = wnr;
- info.xn = 1;
- rc = cpu_vcpu_cp15_domain_fault(vcpu, &info);
- crash_dump = TRUE;
- break;
- case DFSR_FS_PERM_FAULT_SECTION:
- case DFSR_FS_PERM_FAULT_PAGE:
- info.regs = regs;
- info.far = dfar;
- info.fs = fs;
- info.dom = dom;
- info.wnr = wnr;
- info.xn = 1;
- rc = cpu_vcpu_cp15_perm_fault(vcpu, &info);
- if ((dfar & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) !=
- arm_priv(vcpu)->cp15.ovect_base) {
- crash_dump = FALSE;
- }
- break;
- case DFSR_FS_DEBUG_EVENT:
- case DFSR_FS_SYNC_EXT_ABORT:
- case DFSR_FS_IMP_VALID_LOCKDOWN:
- case DFSR_FS_IMP_VALID_COPROC_ABORT:
- case DFSR_FS_MEM_ACCESS_SYNC_PARITY_ERROR:
- case DFSR_FS_ASYNC_EXT_ABORT:
- case DFSR_FS_MEM_ACCESS_ASYNC_PARITY_ERROR:
- vmm_manager_vcpu_halt(vcpu);
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- default:
- rc = VMM_EFAIL;
- crash_dump = TRUE;
- break;
- };
-
- if (rc && crash_dump) {
- vmm_printf("\n");
- vmm_printf("%s: error %d\n", __func__, rc);
- vmm_printf("%s: vcpu_id = %d, dfar = 0x%x, dfsr = 0x%x\n",
- __func__, vcpu->id, dfar, dfsr);
- cpu_vcpu_dump_user_reg(vcpu, regs);
- }
-
- vmm_scheduler_irq_exit(regs);
-}
-
-void do_not_used(arch_regs_t *regs)
-{
- vmm_panic("%s: unexpected exception\n", __func__);
-}
-
-void do_irq(arch_regs_t *regs)
-{
- vmm_scheduler_irq_enter(regs, FALSE);
-
- vmm_host_active_irq_exec(CPU_EXTERNAL_IRQ);
-
- vmm_scheduler_irq_exit(regs);
-}
-
-void do_fiq(arch_regs_t *regs)
-{
- vmm_scheduler_irq_enter(regs, FALSE);
-
- vmm_host_active_irq_exec(CPU_EXTERNAL_FIQ);
-
- vmm_scheduler_irq_exit(regs);
-}
-
-int __cpuinit arch_cpu_irq_setup(void)
-{
- static const struct cpu_page zero_filled_cpu_page = { 0 };
- extern u32 _start_vect[];
-
- int rc;
- u32 *vectors;
- u32 count, cpu = vmm_smp_processor_id();
- struct cpu_page vec_page;
-
-#if defined(CONFIG_ARM32_HIGHVEC)
- /* Enable high vectors in SCTLR */
- write_sctlr(read_sctlr() | SCTLR_V_MASK);
- vectors = (u32 *)CPU_IRQ_HIGHVEC_BASE;
-#else
- if (cpu_supports_securex()) {
- write_vbar(CPU_IRQ_LOWVEC_BASE);
- }
- write_sctlr(read_sctlr() & ~SCTLR_V_MASK);
- vectors = (u32 *)CPU_IRQ_LOWVEC_BASE;
-#endif
-
- /* For secondary CPUs nothing else to be done. */
- if (cpu) {
- return VMM_OK;
- }
-
- /* If vectors are at correct location then do nothing */
- if ((u32) _start_vect == (u32) vectors) {
- return VMM_OK;
- }
-
- /* If vectors are not mapped in virtual memory then map them. */
- vec_page = zero_filled_cpu_page;
- rc = cpu_mmu_get_reserved_page((virtual_addr_t)vectors, &vec_page);
- if (rc) {
- if (!vmm_host_ram_alloc(&vec_page.pa,
- TTBL_L2TBL_SMALL_PAGE_SIZE,
- VMM_PAGE_SHIFT)) {
- return VMM_ENOMEM;
- }
-
- vec_page.va = (virtual_addr_t)vectors;
- vec_page.sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- vec_page.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- vec_page.ap = TTBL_AP_SR_U;
- vec_page.c = 1;
-
- if ((rc = cpu_mmu_map_reserved_page(&vec_page))) {
- return rc;
- }
- }
-
- /*
- * Copy the vector's insn and data word.
- */
- count = vmm_host_memory_write(vec_page.pa, (void *)&_start_vect[0],
- CPU_IRQ_NR * sizeof(u32) * 2, FALSE);
- if (count != (CPU_IRQ_NR * sizeof(u32) * 2)) {
- return VMM_EFAIL;
- }
-
- return VMM_OK;
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_memcpy.S b/arch/arm/cpu/arm32/cpu_memcpy.S
deleted file mode 100644
index dd002144..00000000
--- a/arch/arm/cpu/arm32/cpu_memcpy.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_memcpy.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of memcpy function
- */
-
- .text
- .align 5
- .word 0
- .globl memcpy
-memcpy:
- push {r0, r3, r4, r5, r6, lr}
- orr r4, r0, r1
-
- ands r3, r4, #15
- beq memcpy_aligned16
-
- ands r3, r4, #7
- beq memcpy_aligned8
-
- ands r3, r4, #3
- beq memcpy_aligned4
-
- b memcpy_unaligned
-
-memcpy_aligned16:
-3: cmp r2, #16
- blt memcpy_aligned8
-
- ldmia r1!, {r3, r4, r5, r6}
- stmia r0!, {r3, r4, r5, r6}
- sub r2, r2, #16
- b 3b
-
-memcpy_aligned8:
-2: cmp r2, #8
- blt memcpy_aligned4
-
- ldmia r1!, {r3, r4}
- stmia r0!, {r3, r4}
- sub r2, r2, #8
- b 2b
-
-memcpy_aligned4:
-1: cmp r2, #4
- blt memcpy_unaligned
-
- ldr r3, [r1], #4
- str r3, [r0], #4
- sub r2, r2, #4
- b 1b
-
-memcpy_unaligned:
-0: cmp r2, #0
- beq memcpy_done
-
- ldrb r3, [r1], #1
- strb r3, [r0], #1
- sub r2, r2, #1
- b 0b
-
-memcpy_done:
- pop {r0, r3, r4, r5, r6, lr}
- mov pc, lr
-
diff --git a/arch/arm/cpu/arm32/cpu_memset.S b/arch/arm/cpu/arm32/cpu_memset.S
deleted file mode 100644
index f0e159c2..00000000
--- a/arch/arm/cpu/arm32/cpu_memset.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_memset.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of memset function
- */
-
- .text
- .align 5
- .word 0
- .globl memset
-memset:
- push {r0, r3, r4, r5, r6, r7, lr}
-
- mov r3, r1
- lsl r3, #8
- orr r3, r3, r1
- lsl r3, #8
- orr r3, r3, r1
- lsl r3, #8
- orr r3, r3, r1
- mov r4, r3
- mov r5, r3
- mov r6, r3
-
- ands r7, r0, #15
- beq memset_aligned16
-
- ands r7, r0, #7
- beq memset_aligned8
-
- ands r7, r0, #3
- beq memset_aligned4
-
- b memset_unaligned
-
-memset_aligned16:
-3: cmp r2, #16
- blt memset_aligned8
-
- stmia r0!, {r3, r4, r5, r6}
- sub r2, r2, #16
- b 3b
-
-memset_aligned8:
-2: cmp r2, #8
- blt memset_aligned4
-
- stmia r0!, {r3, r4}
- sub r2, r2, #8
- b 2b
-
-memset_aligned4:
-1: cmp r2, #4
- blt memset_unaligned
-
- str r3, [r0], #4
- sub r2, r2, #4
- b 1b
-
-memset_unaligned:
-0: cmp r2, #0
- beq memset_done
-
- strb r1, [r0], #1
- sub r2, r2, #1
- b 0b
-
-memset_done:
- pop {r0, r3, r4, r5, r6, r7, lr}
- mov pc, lr
-
diff --git a/arch/arm/cpu/arm32/cpu_mmu.c b/arch/arm/cpu/arm32/cpu_mmu.c
deleted file mode 100644
index be5d60a6..00000000
--- a/arch/arm/cpu/arm32/cpu_mmu.c
+++ /dev/null
@@ -1,2063 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_mmu.c
- * @author Anup Patel (an...@brainfault.org)
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief Implementation of memory managment unit for ARM processors
- */
-
-#include <vmm_error.h>
-#include <vmm_types.h>
-#include <vmm_smp.h>
-#include <vmm_stdio.h>
-#include <vmm_spinlocks.h>
-#include <vmm_host_vapool.h>
-#include <vmm_host_aspace.h>
-#include <arch_barrier.h>
-#include <arch_cpu_irq.h>
-#include <arch_sections.h>
-#include <libs/stringlib.h>
-#include <cpu_defines.h>
-#include <cpu_proc.h>
-#include <cpu_cache.h>
-#include <cpu_inline_asm.h>
-#include <cpu_mmu.h>
-
-#define TTBL_MAX_L1TBL_COUNT (CONFIG_MAX_VCPU_COUNT)
-
-#define TTBL_MAX_L2TBL_COUNT (TTBL_MAX_L1TBL_COUNT * 16)
-
-#define TTBL_MAX_L2TBL_SIZE (TTBL_L2TBL_SIZE * TTBL_MAX_L2TBL_COUNT)
-
-#define TTBL_POOL_MAX_SIZE ((TTBL_MAX_L1TBL_COUNT * TTBL_L1TBL_SIZE) + \
- TTBL_MAX_L2TBL_SIZE)
-
-#if TTBL_POOL_MAX_SIZE >= (CONFIG_VAPOOL_SIZE_MB * 1024 * 1024)
-#error "TTBL pool too big !!! Please reduce CONFIG_MAX_VCPU_COUNT"
-#endif
-
-u8 __attribute__((aligned(TTBL_L1TBL_SIZE))) defl1_ttbl[TTBL_L1TBL_SIZE];
-u8 __attribute__ ((aligned(TTBL_L2TBL_SIZE))) defl2_ttbl[TTBL_INITIAL_L2TBL_SIZE] = { 0 };
-int defl2_ttbl_used[TTBL_INITIAL_L2TBL_COUNT];
-virtual_addr_t defl2_ttbl_mapva[TTBL_INITIAL_L2TBL_COUNT];
-
-struct cpu_mmu_ctrl {
- /* Initialized by primary CPU aspace init */
- vmm_spinlock_t defl1_lock;
- struct cpu_l1tbl defl1;
- virtual_addr_t l1_base_va;
- physical_addr_t l1_base_pa;
- struct cpu_l1tbl l1_array[TTBL_MAX_L1TBL_COUNT];
- virtual_addr_t l2_base_va;
- physical_addr_t l2_base_pa;
- virtual_addr_t il2_base_va;
- physical_addr_t il2_base_pa;
- struct cpu_l2tbl l2_array[TTBL_MAX_L2TBL_COUNT];
- struct cpu_l2tbl il2_array[TTBL_INITIAL_L2TBL_COUNT];
- vmm_spinlock_t l1_alloc_lock;
- u32 l1_next_contextid;
- u32 l1_alloc_count;
- struct dlist l1tbl_list;
- struct dlist free_l1tbl_list;
- vmm_spinlock_t l2_alloc_lock;
- u32 l2_alloc_count;
- struct dlist free_l2tbl_list;
- /* Initialized by memory read/write init */
- u32 mem_rw_l1_offset[CONFIG_CPU_COUNT];
- u32 mem_rw_l2_offset[CONFIG_CPU_COUNT];
-};
-
-static struct cpu_mmu_ctrl mmuctrl;
-
-static inline void cpu_mmu_sync_tte(u32 *tte)
-{
- clean_dcache_mva((virtual_addr_t)tte);
-}
-
-/** Find L2 page table at given physical address from L1 page table */
-static struct cpu_l2tbl *cpu_mmu_l2tbl_find_tbl_pa(physical_addr_t tbl_pa)
-{
- int index;
-
- tbl_pa &= ~(TTBL_L2TBL_SIZE - 1);
-
- if ((mmuctrl.il2_base_pa <= tbl_pa) &&
- (tbl_pa < (mmuctrl.il2_base_pa + TTBL_INITIAL_L2TBL_SIZE))) {
- tbl_pa = tbl_pa - mmuctrl.il2_base_pa;
- index = tbl_pa >> TTBL_L2TBL_SIZE_SHIFT;
- if (index < TTBL_INITIAL_L2TBL_COUNT) {
- return &mmuctrl.il2_array[index];
- }
- }
-
- if ((mmuctrl.l2_base_pa <= tbl_pa) &&
- (tbl_pa < (mmuctrl.l2_base_pa + TTBL_MAX_L2TBL_SIZE))) {
- tbl_pa = tbl_pa - mmuctrl.l2_base_pa;
- index = tbl_pa >> TTBL_L2TBL_SIZE_SHIFT;
- if (index < TTBL_MAX_L2TBL_COUNT) {
- return &mmuctrl.l2_array[index];
- }
- }
-
- return NULL;
-}
-
-/** Check whether a L2 page table is attached or not */
-int cpu_mmu_l2tbl_is_attached(struct cpu_l2tbl *l2)
-{
- if (!l2) {
- return 0;
- }
- return (l2->l1) ? 1 : 0;
-}
-
-/** Detach a L2 page table */
-int cpu_mmu_l2tbl_detach(struct cpu_l2tbl *l2)
-{
- u32 *l1_tte;
- u32 l1_tte_type;
-
- /* Sanity check */
- if (!l2) {
- return VMM_EFAIL;
- }
-
- /* if it is not attached already, nothing to do */
- if (!cpu_mmu_l2tbl_is_attached(l2)) {
- return VMM_OK;
- }
-
- l1_tte = (u32 *) (l2->l1->tbl_va +
- ((l2->map_va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_FAULT) {
- return VMM_EFAIL;
- }
-
- *l1_tte = 0x0;
- cpu_mmu_sync_tte(l1_tte);
- l2->l1->tte_cnt--;
- l2->l1->l2tbl_cnt--;
- l2->l1 = NULL;
- l2->tte_cnt = 0;
-
- memset((void *)l2->tbl_va, 0, TTBL_L2TBL_SIZE);
-
- /* remove the L2 page table from the list it is attached */
- list_del(&l2->head);
-
- return VMM_OK;
-}
-
-/** Attach a L2 page table to a particular L1 page table */
-int cpu_mmu_l2tbl_attach(struct cpu_l1tbl *l1, struct cpu_l2tbl *l2, u32 new_imp,
- u32 new_domain, virtual_addr_t new_map_va, bool force)
-{
- u32 *l1_tte, l1_tte_new;
- u32 l1_tte_type;
-
- /* Sanity check */
- if (!l2 || !l1) {
- return VMM_EFAIL;
- }
-
- /* If the L2 page is already attached */
- if (cpu_mmu_l2tbl_is_attached(l2)) {
- return VMM_EFAIL;
- }
-
- l1_tte = (u32 *) (l1->tbl_va +
- ((new_map_va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
- if ((l1_tte_type != TTBL_L1TBL_TTE_TYPE_FAULT) && !force) {
- return VMM_EFAIL;
- }
-
- l2->l1 = l1;
-#if defined(CONFIG_ARMV5)
- l2->imp = 0;
-#else
- l2->imp =
- new_imp & (TTBL_L1TBL_TTE_IMP_MASK >> TTBL_L1TBL_TTE_IMP_SHIFT);
-#endif
- l2->domain =
- new_domain & (TTBL_L1TBL_TTE_DOM_MASK >> TTBL_L1TBL_TTE_DOM_SHIFT);
- l2->map_va = new_map_va & TTBL_L1TBL_TTE_OFFSET_MASK;
-
-#if defined(CONFIG_ARMV5)
- l1_tte_new = TTBL_L1TBL_TTE_REQ_MASK;
- l1_tte_new |= (l2->domain) << TTBL_L1TBL_TTE_DOM_SHIFT;
- l1_tte_new |= (l2->tbl_pa & TTBL_L1TBL_TTE_BASE10_MASK);
- l1_tte_new |= TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL;
-#else
- l1_tte_new = 0x0;
- l1_tte_new |= (l2->imp) << TTBL_L1TBL_TTE_IMP_SHIFT;
- l1_tte_new |= (l2->domain) << TTBL_L1TBL_TTE_DOM_SHIFT;
- l1_tte_new |= (l2->tbl_pa & TTBL_L1TBL_TTE_BASE10_MASK);
- l1_tte_new |= TTBL_L1TBL_TTE_TYPE_L2TBL;
-#endif
-
- *l1_tte = l1_tte_new;
- cpu_mmu_sync_tte(l1_tte);
-
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_FAULT) {
- l1->tte_cnt++;
- }
- l1->l2tbl_cnt++;
-
- list_add(&l2->head, &l1->l2tbl_list);
-
- return VMM_OK;
-}
-
-/** Allocate a L2 page table of given type */
-struct cpu_l2tbl *cpu_mmu_l2tbl_alloc(void)
-{
- irq_flags_t flags;
- struct cpu_l2tbl *l2;
-
- vmm_spin_lock_irqsave(&mmuctrl.l2_alloc_lock, flags);
- if (list_empty(&mmuctrl.free_l2tbl_list)) {
- vmm_spin_unlock_irqrestore(&mmuctrl.l2_alloc_lock, flags);
- return NULL;
- }
- l2 = list_entry(list_first(&mmuctrl.free_l2tbl_list),
- struct cpu_l2tbl, head);
- list_del(&l2->head);
- mmuctrl.l2_alloc_count++;
- vmm_spin_unlock_irqrestore(&mmuctrl.l2_alloc_lock, flags);
-
- INIT_LIST_HEAD(&l2->head);
- l2->l1 = NULL;
- l2->imp = 0;
- l2->domain = 0;
- l2->map_va = 0;
- l2->tte_cnt = 0;
- memset((void *)l2->tbl_va, 0, TTBL_L2TBL_SIZE);
-
- return l2;
-}
-
-/** Free a L2 page table */
-int cpu_mmu_l2tbl_free(struct cpu_l2tbl *l2)
-{
- int rc;
- irq_flags_t flags;
-
- if (!l2) {
- return VMM_EFAIL;
- }
-
- if (cpu_mmu_l2tbl_is_attached(l2)) {
- rc = cpu_mmu_l2tbl_detach(l2);
- if (rc) {
- return rc;
- }
- }
-
- INIT_LIST_HEAD(&l2->head);
- l2->l1 = NULL;
-
- vmm_spin_lock_irqsave(&mmuctrl.l2_alloc_lock, flags);
- list_add_tail(&l2->head, &mmuctrl.free_l2tbl_list);
- mmuctrl.l2_alloc_count--;
- vmm_spin_unlock_irqrestore(&mmuctrl.l2_alloc_lock, flags);
-
- return VMM_OK;
-}
-
-/** Find L1 page table at given physical address */
-struct cpu_l1tbl *cpu_mmu_l1tbl_find_tbl_pa(physical_addr_t tbl_pa)
-{
- u32 tmp;
-
- if (tbl_pa == mmuctrl.defl1.tbl_pa) {
- return &mmuctrl.defl1;
- }
-
- tmp = (tbl_pa - mmuctrl.l1_base_pa) >> TTBL_L1TBL_SIZE_SHIFT;
-
- if (tmp < TTBL_MAX_L1TBL_COUNT) {
- return &mmuctrl.l1_array[tmp];
- }
-
- return NULL;
-}
-
-u32 cpu_mmu_best_page_size(virtual_addr_t va, physical_addr_t pa, u32 availsz)
-{
- if (!(va & (TTBL_L1TBL_SECTION_PAGE_SIZE - 1)) &&
- !(pa & (TTBL_L1TBL_SECTION_PAGE_SIZE - 1)) &&
- (TTBL_L1TBL_SECTION_PAGE_SIZE <= availsz)) {
- return TTBL_L1TBL_SECTION_PAGE_SIZE;
- }
-
- if (!(va & (TTBL_L2TBL_LARGE_PAGE_SIZE - 1)) &&
- !(pa & (TTBL_L2TBL_LARGE_PAGE_SIZE - 1)) &&
- (TTBL_L2TBL_LARGE_PAGE_SIZE <= availsz)) {
- return TTBL_L2TBL_LARGE_PAGE_SIZE;
- }
-
- return TTBL_L2TBL_SMALL_PAGE_SIZE;
-}
-
-int cpu_mmu_get_page(struct cpu_l1tbl *l1,
- virtual_addr_t va, struct cpu_page *pg)
-{
- int ret = VMM_EFAIL;
- u32 *l1_tte, *l2_tte;
- u32 l1_tte_type;
-#if !defined(CONFIG_ARMV5)
- u32 l1_sec_type;
-#endif
- physical_addr_t l2base;
- struct cpu_l2tbl *l2;
- struct cpu_page r;
-
- if (!l1) {
- return ret;
- }
-
- if (!pg) {
- pg = &r;
- }
-
- l1_tte = (u32 *) (l1->tbl_va +
- ((va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
-
-#if defined(CONFIG_ARMV5)
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_SECTION:
- pg->va = va & TTBL_L1TBL_TTE_OFFSET_MASK;
- pg->ap = (*l1_tte & TTBL_L1TBL_TTE_AP_MASK) >>
- TTBL_L1TBL_TTE_AP_SHIFT;
- pg->c = (*l1_tte & TTBL_L1TBL_TTE_C_MASK) >>
- TTBL_L1TBL_TTE_C_SHIFT;
- pg->b = (*l1_tte & TTBL_L1TBL_TTE_B_MASK) >>
- TTBL_L1TBL_TTE_B_SHIFT;
- pg->pa = *l1_tte & TTBL_L1TBL_TTE_BASE20_MASK;
- pg->sz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- pg->dom = (*l1_tte & TTBL_L1TBL_TTE_DOM_MASK) >>
- TTBL_L1TBL_TTE_DOM_SHIFT;
- ret = VMM_OK;
- break;
- case TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2_tte = (u32 *) ((va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- if (!(l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base))) {
- break;
- }
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- pg->va = va & TTBL_L2TBL_TTE_BASE12_MASK;
- pg->dom = (*l1_tte & TTBL_L1TBL_TTE_DOM_MASK) >>
- TTBL_L1TBL_TTE_DOM_SHIFT;
- pg->ap = (*l2_tte & TTBL_L2TBL_TTE_V5_AP0_MASK) >>
- TTBL_L2TBL_TTE_V5_AP0_SHIFT;
- pg->c = (*l2_tte & TTBL_L2TBL_TTE_C_MASK) >>
- TTBL_L2TBL_TTE_C_SHIFT;
- pg->b = (*l2_tte & TTBL_L2TBL_TTE_B_MASK) >>
- TTBL_L2TBL_TTE_B_SHIFT;
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE:
- pg->pa = *l2_tte & TTBL_L2TBL_TTE_BASE16_MASK;
- pg->sz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- ret = VMM_OK;
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL:
- pg->pa = *l2_tte & TTBL_L2TBL_TTE_BASE12_MASK;
- pg->sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- ret = VMM_OK;
- break;
- default:
- ret = VMM_ENOTAVAIL;
- break;
- }
- break;
- default:
- memset(pg, 0, sizeof(struct cpu_page));
- ret = VMM_ENOTAVAIL;
- break;
- }
-#else
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_SECTION:
- pg->va = va & TTBL_L1TBL_TTE_OFFSET_MASK;
- pg->ns = (*l1_tte & TTBL_L1TBL_TTE_NS2_MASK) >>
- TTBL_L1TBL_TTE_NS2_SHIFT;
- pg->ng = (*l1_tte & TTBL_L1TBL_TTE_NG_MASK) >>
- TTBL_L1TBL_TTE_NG_SHIFT;
- pg->s = (*l1_tte & TTBL_L1TBL_TTE_S_MASK) >>
- TTBL_L1TBL_TTE_S_SHIFT;
- pg->ap = (*l1_tte & TTBL_L1TBL_TTE_AP2_MASK) >>
- (TTBL_L1TBL_TTE_AP2_SHIFT - 2);
- pg->tex = (*l1_tte & TTBL_L1TBL_TTE_TEX_MASK) >>
- TTBL_L1TBL_TTE_TEX_SHIFT;
- pg->ap |= (*l1_tte & TTBL_L1TBL_TTE_AP_MASK) >>
- TTBL_L1TBL_TTE_AP_SHIFT;
- pg->imp = (*l1_tte & TTBL_L1TBL_TTE_IMP_MASK) >>
- TTBL_L1TBL_TTE_IMP_SHIFT;
- pg->xn = (*l1_tte & TTBL_L1TBL_TTE_XN_MASK) >>
- TTBL_L1TBL_TTE_XN_SHIFT;
- pg->c = (*l1_tte & TTBL_L1TBL_TTE_C_MASK) >>
- TTBL_L1TBL_TTE_C_SHIFT;
- pg->b = (*l1_tte & TTBL_L1TBL_TTE_B_MASK) >>
- TTBL_L1TBL_TTE_B_SHIFT;
- l1_sec_type = (*l1_tte & TTBL_L1TBL_TTE_SECTYPE_MASK) >>
- TTBL_L1TBL_TTE_SECTYPE_SHIFT;
- if (l1_sec_type) {
- pg->pa = *l1_tte & TTBL_L1TBL_TTE_BASE24_MASK;
- pg->sz = TTBL_L1TBL_SUPSECTION_PAGE_SIZE;
- pg->dom = 0;
- } else {
- pg->pa = *l1_tte & TTBL_L1TBL_TTE_BASE20_MASK;
- pg->sz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- pg->dom = (*l1_tte & TTBL_L1TBL_TTE_DOM_MASK) >>
- TTBL_L1TBL_TTE_DOM_SHIFT;
- }
- ret = VMM_OK;
- break;
- case TTBL_L1TBL_TTE_TYPE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2_tte = (u32 *) ((va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (l2) {
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- pg->va = va & TTBL_L2TBL_TTE_BASE12_MASK;
- pg->imp = (*l1_tte & TTBL_L1TBL_TTE_IMP_MASK) >>
- TTBL_L1TBL_TTE_IMP_SHIFT;
- pg->dom = (*l1_tte & TTBL_L1TBL_TTE_DOM_MASK) >>
- TTBL_L1TBL_TTE_DOM_SHIFT;
- pg->ns = (*l1_tte & TTBL_L1TBL_TTE_NS1_MASK) >>
- TTBL_L1TBL_TTE_NS1_SHIFT;
- pg->ng = (*l2_tte & TTBL_L2TBL_TTE_NG_MASK) >>
- TTBL_L2TBL_TTE_NG_SHIFT;
- pg->s = (*l2_tte & TTBL_L2TBL_TTE_S_MASK) >>
- TTBL_L2TBL_TTE_S_SHIFT;
- pg->ap = (*l2_tte & TTBL_L2TBL_TTE_AP2_MASK) >>
- (TTBL_L2TBL_TTE_AP2_SHIFT - 2);
- pg->ap |= (*l2_tte & TTBL_L2TBL_TTE_AP_MASK) >>
- TTBL_L2TBL_TTE_AP_SHIFT;
- pg->c = (*l2_tte & TTBL_L2TBL_TTE_C_MASK) >>
- TTBL_L2TBL_TTE_C_SHIFT;
- pg->b = (*l2_tte & TTBL_L2TBL_TTE_B_MASK) >>
- TTBL_L2TBL_TTE_B_SHIFT;
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE:
- pg->pa = *l2_tte & TTBL_L2TBL_TTE_BASE16_MASK;
- pg->xn = (*l2_tte & TTBL_L2TBL_TTE_LXN_MASK) >>
- TTBL_L2TBL_TTE_LXN_SHIFT;
- pg->tex = (*l2_tte & TTBL_L2TBL_TTE_LTEX_MASK) >>
- TTBL_L2TBL_TTE_LTEX_SHIFT;
- pg->sz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- ret = VMM_OK;
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL_X:
- case TTBL_L2TBL_TTE_TYPE_SMALL_XN:
- pg->pa = *l2_tte & TTBL_L2TBL_TTE_BASE12_MASK;
- pg->tex = (*l2_tte & TTBL_L2TBL_TTE_STEX_MASK) >>
- TTBL_L2TBL_TTE_STEX_SHIFT;
- pg->xn = *l2_tte & TTBL_L2TBL_TTE_SXN_MASK;
- pg->sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- ret = VMM_OK;
- break;
- default:
- ret = VMM_ENOTAVAIL;
- break;
- }
- }
- break;
- default:
- memset(pg, 0, sizeof(struct cpu_page));
- ret = VMM_ENOTAVAIL;
- break;
- };
-#endif
-
- return ret;
-}
-
-int cpu_mmu_get_l2tbl(struct cpu_l1tbl *l1,
- virtual_addr_t va, struct cpu_l2tbl **l2)
-{
- int ret = VMM_EFAIL;
- u32 *l1_tte;
- u32 l1_tte_type;
- physical_addr_t l2base;
-
- if (!l1 || !l2) {
- return ret;
- }
-
- l1_tte = (u32 *) (l1->tbl_va +
- ((va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
-
- *l2 = NULL;
-
-#if defined(CONFIG_ARMV5)
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- *l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (!(*l2)) {
- ret = VMM_ENOTAVAIL;
- } else {
- ret = VMM_OK;
- }
- break;
- default:
- ret = VMM_ENOTAVAIL;
- break;
- }
-#else
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- *l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (!(*l2)) {
- ret = VMM_ENOTAVAIL;
- } else {
- ret = VMM_OK;
- }
- break;
- default:
- ret = VMM_ENOTAVAIL;
- break;
- };
-#endif
-
- return ret;
-}
-
-int cpu_mmu_unmap_page(struct cpu_l1tbl *l1, struct cpu_page *pg)
-{
- int ret = VMM_EFAIL;
- u32 ite, *l1_tte, *l2_tte;
- u32 l1_tte_type;
-#if !defined(CONFIG_ARMV5)
- u32 l1_sec_type, found = 0;
-#endif
- physical_addr_t l2base, pgpa, chkpa;
- virtual_size_t chksz;
- struct cpu_l2tbl *l2 = NULL;
-
- if (!l1 || !pg) {
- return ret;
- }
-
- l1_tte = (u32 *) (l1->tbl_va +
- ((pg->va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
-
-#if defined(CONFIG_ARMV5)
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_FAULT:
- break;
- case TTBL_L1TBL_TTE_TYPE_SECTION:
- pgpa = pg->pa & TTBL_L1TBL_TTE_BASE20_MASK;
- chkpa = *l1_tte & TTBL_L1TBL_TTE_BASE20_MASK;
- chksz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- *l1_tte = 0x0;
- cpu_mmu_sync_tte(l1_tte);
- l1->tte_cnt--;
- ret = VMM_OK;
- }
- break;
- case TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- if (!(l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base))) {
- break;
- }
- l2_tte = (u32 *) ((pg->va & ~TTBL_L1TBL_TTE_OFFSET_MASK)
- >> TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE:
- l2_tte = l2_tte - ((u32) l2_tte % 64) / 4;
- pgpa = pg->pa & TTBL_L2TBL_TTE_BASE16_MASK;
- chkpa = *l2_tte & TTBL_L2TBL_TTE_BASE16_MASK;
- chksz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- for (ite = 0; ite < 16; ite++) {
- l2_tte[ite] = 0x0;
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt--;
- }
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL:
- pgpa = pg->pa & TTBL_L2TBL_TTE_BASE12_MASK;
- chkpa = *l2_tte & TTBL_L2TBL_TTE_BASE12_MASK;
- chksz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- *l2_tte = 0x0;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt--;
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-#else
- found = 0;
- switch (l1_tte_type) {
- case TTBL_L1TBL_TTE_TYPE_FAULT:
- break;
- case TTBL_L1TBL_TTE_TYPE_SECTION:
- l1_sec_type = (*l1_tte & TTBL_L1TBL_TTE_SECTYPE_MASK) >>
- TTBL_L1TBL_TTE_SECTYPE_SHIFT;
- if (l1_sec_type) {
- l1_tte = l1_tte - ((u32)l1_tte % 64) / 4;
- pgpa = pg->pa & TTBL_L1TBL_TTE_BASE24_MASK;
- chkpa = *l1_tte & TTBL_L1TBL_TTE_BASE24_MASK;
- chksz = TTBL_L1TBL_SUPSECTION_PAGE_SIZE;
- found = 1;
- } else {
- pgpa = pg->pa & TTBL_L1TBL_TTE_BASE20_MASK;
- chkpa = *l1_tte & TTBL_L1TBL_TTE_BASE20_MASK;
- chksz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- found = 2;
- }
- break;
- case TTBL_L1TBL_TTE_TYPE_L2TBL:
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2_tte = (u32 *) ((pg->va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (l2) {
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE:
- l2_tte = l2_tte - ((u32)l2_tte % 64) / 4;
- pgpa = pg->pa & TTBL_L2TBL_TTE_BASE16_MASK;
- chkpa = *l2_tte & TTBL_L2TBL_TTE_BASE16_MASK;
- chksz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- found = 3;
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL_X:
- case TTBL_L2TBL_TTE_TYPE_SMALL_XN:
- pgpa = pg->pa & TTBL_L2TBL_TTE_BASE12_MASK;
- chkpa = *l2_tte & TTBL_L2TBL_TTE_BASE12_MASK;
- chksz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- found = 4;
- break;
- default:
- break;
- }
- }
- break;
- default:
- break;
- };
-
- switch (found) {
- case 1: /* Super Section */
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- for (ite = 0; ite < 16; ite++) {
- l1_tte[ite] = 0x0;
- cpu_mmu_sync_tte(&l1_tte[ite]);
- l1->tte_cnt--;
- }
- ret = VMM_OK;
- }
- break;
- case 2: /* Section */
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- *l1_tte = 0x0;
- cpu_mmu_sync_tte(l1_tte);
- l1->tte_cnt--;
- ret = VMM_OK;
- }
- break;
- case 3: /* Large Page */
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- for (ite = 0; ite < 16; ite++) {
- l2_tte[ite] = 0x0;
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt--;
- }
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case 4: /* Small Page */
- if ((pgpa == chkpa) && (pg->sz == chksz)) {
- *l2_tte = 0x0;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt--;
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- default:
- break;
- }
-#endif
-
- if (!ret) {
- /* If given L1 page table is current then
- * invalidate tlb line
- */
- if(read_ttbr0() == l1->tbl_pa) {
- invalid_tlb_mva(pg->va);
- dsb();
- isb();
- }
- }
-
- return ret;
-}
-
-int cpu_mmu_unmap_l2tbl_page(struct cpu_l2tbl *l2,
- virtual_addr_t pgva, virtual_size_t pgsz,
- bool invalidate_tlb)
-{
- int ret = VMM_EFAIL;
- u32 ite, *l2_tte;
- struct cpu_l1tbl *l1;
-
- if (!l2 || !l2->l1) {
- return ret;
- }
- if (pgva < l2->map_va) {
- return VMM_EINVALID;
- }
- if (((l2->map_va + TTBL_L1TBL_SECTION_PAGE_SIZE) > l2->map_va) &&
- ((l2->map_va + TTBL_L1TBL_SECTION_PAGE_SIZE) <= pgva)) {
- return VMM_EINVALID;
- }
-
- l1 = l2->l1;
-
-#if defined(CONFIG_ARMV5)
- l2_tte = (u32 *) ((pgva & ~TTBL_L1TBL_TTE_OFFSET_MASK)
- >> TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE: /* Large Page */
- l2_tte = l2_tte - ((u32) l2_tte % 64) / 4;
- if (pgsz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- for (ite = 0; ite < 16; ite++) {
- l2_tte[ite] = 0x0;
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt--;
- }
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL: /* Small Page */
- if (pgsz == TTBL_L2TBL_SMALL_PAGE_SIZE) {
- *l2_tte = 0x0;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt--;
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case TTBL_L2TBL_TTE_TYPE_FAULT:
- ret = VMM_OK;
- break;
- default:
- break;
- }
-#else
- l2_tte = (u32 *) ((pgva & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- switch (*l2_tte & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE: /* Large Page */
- l2_tte = l2_tte - ((u32)l2_tte % 64) / 4;
- if (pgsz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- for (ite = 0; ite < 16; ite++) {
- l2_tte[ite] = 0x0;
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt--;
- }
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL_X: /* Small Page */
- case TTBL_L2TBL_TTE_TYPE_SMALL_XN:
- if (pgsz == TTBL_L2TBL_SMALL_PAGE_SIZE) {
- *l2_tte = 0x0;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt--;
- if (!l2->tte_cnt) {
- cpu_mmu_l2tbl_free(l2);
- }
- ret = VMM_OK;
- }
- break;
- case TTBL_L2TBL_TTE_TYPE_FAULT:
- ret = VMM_OK;
- break;
- default:
- break;
- }
-#endif
-
- if (ret == VMM_OK && invalidate_tlb) {
- /* If given L1 page table is current then
- * invalidate tlb line
- */
- if (read_ttbr0() == l1->tbl_pa) {
- invalid_tlb_mva(pgva);
- dsb();
- isb();
- }
- }
-
- return ret;
-}
-
-int cpu_mmu_map_page(struct cpu_l1tbl *l1, struct cpu_page *pg)
-{
- int rc = VMM_OK;
- u32 *l1_tte, *l2_tte;
- u32 ite, l1_tte_type;
- virtual_addr_t pgva;
- virtual_size_t pgsz, minpgsz;
- physical_addr_t l2base, pgpa;
- struct cpu_page upg;
- struct cpu_l2tbl *l2;
-
- if (!l1 || !pg) {
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
-
- /* Get the l1 TBL location */
- l1_tte = (u32 *) (l1->tbl_va +
- ((pg->va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
-
- /* Get l1 TLB value */
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
-
- /* If the l1 TBL is already set */
- if (l1_tte_type != TTBL_L1TBL_TTE_TYPE_FAULT) {
- /* we need to check that the requested area is not already
- * mapped
- */
-#if defined(CONFIG_ARMV5)
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL) {
-#else
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_L2TBL) {
-#endif
- minpgsz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- } else {
- minpgsz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
- pgva = pg->va & ~(pg->sz - 1);
- pgva = pgva & ~(minpgsz - 1);
- pgpa = pg->pa & ~(pg->sz - 1);
- pgpa = pgpa & ~(minpgsz - 1);
- pgsz = pg->sz;
- while (pgsz) {
- if (!cpu_mmu_get_page(l1, pgva, &upg)) {
- if (pgva != upg.va ||
- pgpa != upg.pa ||
- minpgsz != upg.sz) {
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
- }
- pgva += minpgsz;
- pgpa += minpgsz;
- pgsz = (pgsz < minpgsz) ? 0 : (pgsz - minpgsz);
- }
- }
-
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_FAULT) {
- /* The L1 is not already set */
- switch (pg->sz) {
- case TTBL_L2TBL_LARGE_PAGE_SIZE: /* 64K Large Page */
- case TTBL_L2TBL_SMALL_PAGE_SIZE: /* 4K Small Page */
- /* If small page requested, then alloc a level 2 TBL */
- if (!(l2 = cpu_mmu_l2tbl_alloc())) {
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
- /* And attach it to the L1 TBL */
- rc = cpu_mmu_l2tbl_attach(l1, l2, pg->imp, pg->dom,
- pg->va, FALSE);
- if (rc) {
- goto mmu_map_return;
- }
- break;
- default:
- break;
- };
- }
-
- /* Now set up the mapping based on requested page size */
-#if defined(CONFIG_ARMV5)
- switch (pg->sz) {
- case TTBL_L1TBL_SECTION_PAGE_SIZE: /* 1M Section Page */
- *l1_tte = TTBL_L1TBL_TTE_REQ_MASK;
- *l1_tte |= (pg->pa & TTBL_L1TBL_TTE_BASE20_MASK);
- *l1_tte |=
- (pg->dom << TTBL_L1TBL_TTE_DOM_SHIFT) &
- TTBL_L1TBL_TTE_DOM_MASK;
- *l1_tte |=
- (pg->ap << TTBL_L1TBL_TTE_AP_SHIFT) &
- TTBL_L1TBL_TTE_AP_MASK;
- *l1_tte |=
- (pg->c << TTBL_L1TBL_TTE_C_SHIFT) & TTBL_L1TBL_TTE_C_MASK;
- *l1_tte |=
- (pg->b << TTBL_L1TBL_TTE_B_SHIFT) & TTBL_L1TBL_TTE_B_MASK;
- *l1_tte |= TTBL_L1TBL_TTE_TYPE_SECTION;
- cpu_mmu_sync_tte(l1_tte);
- l1->tte_cnt++;
- break;
- case TTBL_L2TBL_LARGE_PAGE_SIZE: /* 64K Large Page */
- case TTBL_L2TBL_SMALL_PAGE_SIZE: /* 4K Small Page */
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- if (!(l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base))) {
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
- l2_tte =
- (u32 *) ((pg->va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- if (pg->sz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- l2_tte -= ((u32) l2_tte % 64) >> 2;
- *l2_tte = (pg->pa & TTBL_L2TBL_TTE_BASE16_MASK);
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_LARGE;
- } else {
- *l2_tte = (pg->pa & TTBL_L2TBL_TTE_BASE12_MASK);
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_SMALL;
- }
- *l2_tte |=
- (pg->ap << TTBL_L2TBL_TTE_V5_AP0_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP0_MASK;
- *l2_tte |=
- (pg->ap << TTBL_L2TBL_TTE_V5_AP1_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP1_MASK;
- *l2_tte |=
- (pg->ap << TTBL_L2TBL_TTE_V5_AP2_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP2_MASK;
- *l2_tte |=
- (pg->ap << TTBL_L2TBL_TTE_V5_AP3_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP3_MASK;
- *l2_tte |=
- (pg->c << TTBL_L2TBL_TTE_C_SHIFT) & TTBL_L2TBL_TTE_C_MASK;
- *l2_tte |=
- (pg->b << TTBL_L2TBL_TTE_B_SHIFT) & TTBL_L2TBL_TTE_B_MASK;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt++;
- if (pg->sz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- for (ite = 1; ite < 16; ite++) {
- l2_tte[ite] = l2_tte[0];
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt++;
- }
- }
- break;
- default:
- break;
- };
-#else
- switch (pg->sz) {
- case TTBL_L1TBL_SUPSECTION_PAGE_SIZE: /* 16M Super Section Page */
- case TTBL_L1TBL_SECTION_PAGE_SIZE: /* 1M Section Page */
- if (pg->sz == TTBL_L1TBL_SECTION_PAGE_SIZE) {
- *l1_tte = 0x0;
- *l1_tte |= (pg->pa & TTBL_L1TBL_TTE_BASE20_MASK);
- *l1_tte |= (pg->dom << TTBL_L1TBL_TTE_DOM_SHIFT) &
- TTBL_L1TBL_TTE_DOM_MASK;
- } else {
- l1_tte = l1_tte - ((u32)l1_tte % 64) / 4;
- *l1_tte = 0x0;
- *l1_tte |= (pg->pa & TTBL_L1TBL_TTE_BASE24_MASK);
- *l1_tte |= (0x1 << TTBL_L1TBL_TTE_SECTYPE_SHIFT);
- }
- *l1_tte |= (pg->ns << TTBL_L1TBL_TTE_NS2_SHIFT) &
- TTBL_L1TBL_TTE_NS2_MASK;
- *l1_tte |= (pg->ng << TTBL_L1TBL_TTE_NG_SHIFT) &
- TTBL_L1TBL_TTE_NG_MASK;
- *l1_tte |= (pg->s << TTBL_L1TBL_TTE_S_SHIFT) &
- TTBL_L1TBL_TTE_S_MASK;
- *l1_tte |= (pg->ap << (TTBL_L1TBL_TTE_AP2_SHIFT - 2)) &
- TTBL_L1TBL_TTE_AP2_MASK;
- *l1_tte |= (pg->tex << TTBL_L1TBL_TTE_TEX_SHIFT) &
- TTBL_L1TBL_TTE_TEX_MASK;
- *l1_tte |= (pg->ap << TTBL_L1TBL_TTE_AP_SHIFT) &
- TTBL_L1TBL_TTE_AP_MASK;
- *l1_tte |= (pg->imp << TTBL_L1TBL_TTE_IMP_SHIFT) &
- TTBL_L1TBL_TTE_IMP_MASK;
- *l1_tte |= (pg->xn << TTBL_L1TBL_TTE_XN_SHIFT) &
- TTBL_L1TBL_TTE_XN_MASK;
- *l1_tte |= (pg->c << TTBL_L1TBL_TTE_C_SHIFT) &
- TTBL_L1TBL_TTE_C_MASK;
- *l1_tte |= (pg->b << TTBL_L1TBL_TTE_B_SHIFT) &
- TTBL_L1TBL_TTE_B_MASK;
- *l1_tte |= TTBL_L1TBL_TTE_TYPE_SECTION;
- cpu_mmu_sync_tte(l1_tte);
- l1->tte_cnt++;
- if (pg->sz == TTBL_L1TBL_SUPSECTION_PAGE_SIZE) {
- for (ite = 1; ite < 16; ite++) {
- l1_tte[ite] = l1_tte[0];
- cpu_mmu_sync_tte(&l1_tte[ite]);
- l1->tte_cnt++;
- }
- }
- break;
- case TTBL_L2TBL_LARGE_PAGE_SIZE: /* 64K Large Page */
- case TTBL_L2TBL_SMALL_PAGE_SIZE: /* 4K Small Page */
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2_tte = (u32 *) ((pg->va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (l2) {
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- if (pg->sz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- l2_tte = l2_tte - ((u32)l2_tte % 64) / 4;
- *l2_tte = 0x0;
- *l2_tte |= (pg->pa & TTBL_L2TBL_TTE_BASE16_MASK);
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_LARGE;
- *l2_tte |= (pg->xn << TTBL_L2TBL_TTE_LXN_SHIFT) &
- TTBL_L2TBL_TTE_LXN_MASK;
- *l2_tte |= (pg->tex << TTBL_L2TBL_TTE_LTEX_SHIFT) &
- TTBL_L2TBL_TTE_LTEX_MASK;
- } else {
- *l2_tte = 0x0;
- *l2_tte |= (pg->pa & TTBL_L2TBL_TTE_BASE12_MASK);
- if (pg->xn) {
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_SMALL_XN;
- } else {
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_SMALL_X;
- }
- *l2_tte |= (pg->tex << TTBL_L2TBL_TTE_STEX_SHIFT) &
- TTBL_L2TBL_TTE_STEX_MASK;
- }
- *l2_tte |= (pg->ng << TTBL_L2TBL_TTE_NG_SHIFT) &
- TTBL_L2TBL_TTE_NG_MASK;
- *l2_tte |= (pg->s << TTBL_L2TBL_TTE_S_SHIFT) &
- TTBL_L2TBL_TTE_S_MASK;
- *l2_tte |= (pg->ap << (TTBL_L2TBL_TTE_AP2_SHIFT - 2)) &
- TTBL_L2TBL_TTE_AP2_MASK;
- *l2_tte |= (pg->ap << TTBL_L2TBL_TTE_AP_SHIFT) &
- TTBL_L2TBL_TTE_AP_MASK;
- *l2_tte |= (pg->c << TTBL_L2TBL_TTE_C_SHIFT) &
- TTBL_L2TBL_TTE_C_MASK;
- *l2_tte |= (pg->b << TTBL_L2TBL_TTE_B_SHIFT) &
- TTBL_L2TBL_TTE_B_MASK;
- cpu_mmu_sync_tte(l2_tte);
- l2->tte_cnt++;
- if (pg->sz == TTBL_L2TBL_LARGE_PAGE_SIZE) {
- for (ite = 1; ite < 16; ite++) {
- l2_tte[ite] = l2_tte[0];
- cpu_mmu_sync_tte(&l2_tte[ite]);
- l2->tte_cnt++;
- }
- }
- } else {
- rc = VMM_EFAIL;
- goto mmu_map_return;
- }
- break;
- default:
- break;
- };
-#endif
-
-mmu_map_return:
- return rc;
-}
-
-int cpu_mmu_get_reserved_page(virtual_addr_t va, struct cpu_page *pg)
-{
- int rc;
- irq_flags_t flags;
-
- vmm_spin_lock_irqsave(&mmuctrl.defl1_lock, flags);
- rc = cpu_mmu_get_page(&mmuctrl.defl1, va, pg);
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
-
- return rc;
-}
-
-int cpu_mmu_unmap_reserved_page(struct cpu_page *pg)
-{
- int rc;
- irq_flags_t flags;
- struct cpu_l1tbl *l1;
-
- if (!pg) {
- return VMM_EFAIL;
- }
-
- vmm_spin_lock_irqsave(&mmuctrl.defl1_lock, flags);
- if ((rc = cpu_mmu_unmap_page(&mmuctrl.defl1, pg))) {
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
- return rc;
- }
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
-
- /* Note: It might be possible that the reserved page
- * was mapped on-demand into l1 tables other than
- * default l1 table so, we should try to remove mappings
- * of this page from other l1 tables.
- */
-
- vmm_spin_lock_irqsave(&mmuctrl.l1_alloc_lock, flags);
-
- list_for_each_entry(l1, &mmuctrl.l1tbl_list, head) {
- rc = cpu_mmu_unmap_page(l1, pg);
- }
-
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
-
- return VMM_OK;
-}
-
-int cpu_mmu_map_reserved_page(struct cpu_page *pg)
-{
- int rc;
- irq_flags_t flags;
-
- if (!pg) {
- return VMM_EFAIL;
- }
-
- vmm_spin_lock_irqsave(&mmuctrl.defl1_lock, flags);
- if ((rc = cpu_mmu_map_page(&mmuctrl.defl1, pg))) {
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
- return rc;
- }
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
-
- /* Note: Ideally resereved page mapping should be created
- * in each and every l1 table that exist, but that would
- * be uneccesary and redundant. To avoid this we only
- * create mapping in default l1 table and let other VCPUs
- * fault on this page and load the page on-demand from
- * data abort and prefetch abort handlers.
- */
-
- return VMM_OK;
-}
-
-struct cpu_l1tbl *cpu_mmu_l1tbl_alloc(void)
-{
- u32 i, *nl1_tte, *nl2_tte, *l2_tte;
- irq_flags_t flags;
- struct dlist *le;
- struct cpu_l1tbl *nl1 = NULL;
- struct cpu_l2tbl *l2, *nl2;
- virtual_addr_t l2_tte_va;
-
- vmm_spin_lock_irqsave(&mmuctrl.l1_alloc_lock, flags);
- if (list_empty(&mmuctrl.free_l1tbl_list)) {
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
- return NULL;
- }
- nl1 = list_entry(list_first(&mmuctrl.free_l1tbl_list),
- struct cpu_l1tbl, head);
- if (!nl1) {
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
- return NULL;
- }
- list_del(&nl1->head);
- mmuctrl.l1_alloc_count++;
- nl1->contextid = mmuctrl.l1_next_contextid;
- mmuctrl.l1_next_contextid++;
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
-
- INIT_LIST_HEAD(&nl1->l2tbl_list);
- nl1->tte_cnt = 0;
- nl1->l2tbl_cnt = 0;
-
- vmm_spin_lock_irqsave(&mmuctrl.defl1_lock, flags);
-
- for (i = 0; i < (TTBL_L1TBL_SIZE / 4); i++) {
- ((u32 *)nl1->tbl_va)[i] = ((u32 *)mmuctrl.defl1.tbl_va)[i];
- cpu_mmu_sync_tte(&((u32 *)nl1->tbl_va)[i]);
- }
- nl1->tte_cnt = mmuctrl.defl1.tte_cnt;
-
- list_for_each_entry(l2, &mmuctrl.defl1.l2tbl_list, head) {
- nl1_tte = (u32 *) (nl1->tbl_va +
- ((l2->map_va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- *nl1_tte = 0x0;
- cpu_mmu_sync_tte(nl1_tte);
- nl1->tte_cnt--;
-
- nl2 = cpu_mmu_l2tbl_alloc();
- if (!nl2) {
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
- goto l1tbl_alloc_fail;
- }
-
- for (i = 0; i < (TTBL_L2TBL_SIZE / 4); i++) {
- nl2_tte = &((u32 *)nl2->tbl_va)[i];
- l2_tte = &((u32 *)l2->tbl_va)[i];
- l2_tte_va = l2->map_va + TTBL_L2TBL_SMALL_PAGE_SIZE * i;
-
- /* Don't copy l2 tables enteries for identity mappings */
- if (!vmm_host_vapool_isvalid(l2_tte_va) &&
- (l2_tte_va != CPU_IRQ_LOWVEC_BASE) &&
- (l2_tte_va != CPU_IRQ_HIGHVEC_BASE)) {
- *nl2_tte = 0x0;
- } else {
- *nl2_tte = *l2_tte;
- }
-
- if ((*nl2_tte & TTBL_L2TBL_TTE_TYPE_MASK) != 0x0) {
- nl2->tte_cnt++;
- }
- cpu_mmu_sync_tte(nl2_tte);
- }
-
- if (!nl2->tte_cnt) {
- cpu_mmu_l2tbl_free(nl2);
- continue;
- }
-
- if (cpu_mmu_l2tbl_attach
- (nl1, nl2, l2->imp, l2->domain, l2->map_va, FALSE)) {
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
- goto l1tbl_alloc_fail;
- }
- }
- nl1->l2tbl_cnt = mmuctrl.defl1.l2tbl_cnt;
-
- vmm_spin_unlock_irqrestore(&mmuctrl.defl1_lock, flags);
-
- vmm_spin_lock_irqsave(&mmuctrl.l1_alloc_lock, flags);
- list_add(&nl1->head, &mmuctrl.l1tbl_list);
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
-
- return nl1;
-
-l1tbl_alloc_fail:
- while (!list_empty(&nl1->l2tbl_list)) {
- le = list_first(&nl1->l2tbl_list);
- nl2 = list_entry(le, struct cpu_l2tbl, head);
- cpu_mmu_l2tbl_free(nl2);
- }
-
- vmm_spin_lock_irqsave(&mmuctrl.l1_alloc_lock, flags);
- list_add_tail(&nl1->head, &mmuctrl.free_l1tbl_list);
- mmuctrl.l1_alloc_count--;
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
-
- return NULL;
-}
-
-int cpu_mmu_l1tbl_free(struct cpu_l1tbl *l1)
-{
- irq_flags_t flags;
- struct dlist *le;
- struct cpu_l2tbl *l2;
-
- if (!l1) {
- return VMM_EFAIL;
- }
- if (l1->tbl_pa == mmuctrl.defl1.tbl_pa) {
- return VMM_EFAIL;
- }
-
- while (!list_empty(&l1->l2tbl_list)) {
- le = list_first(&l1->l2tbl_list);
- l2 = list_entry(le, struct cpu_l2tbl, head);
- cpu_mmu_l2tbl_free(l2);
- }
-
- vmm_spin_lock_irqsave(&mmuctrl.l1_alloc_lock, flags);
- list_del(&l1->head);
- list_add_tail(&l1->head, &mmuctrl.free_l1tbl_list);
- mmuctrl.l1_alloc_count--;
- vmm_spin_unlock_irqrestore(&mmuctrl.l1_alloc_lock, flags);
-
- return VMM_OK;
-}
-
-struct cpu_l1tbl *cpu_mmu_l1tbl_default(void)
-{
- return &mmuctrl.defl1;
-}
-
-struct cpu_l1tbl *cpu_mmu_l1tbl_current(void)
-{
- u32 ttbr0;
-
- ttbr0 = read_ttbr0();
-
- return cpu_mmu_l1tbl_find_tbl_pa(ttbr0);
-}
-
-int cpu_mmu_change_dacr(u32 new_dacr)
-{
- u32 old_dacr;
-
- old_dacr = read_dacr();
- isb();
-
- new_dacr &= ~0x3;
- new_dacr |= old_dacr & 0x3;
-
- if (new_dacr != old_dacr) {
- write_dacr(new_dacr);
- isb();
- }
-
- return VMM_OK;
-}
-
-int cpu_mmu_change_ttbr(struct cpu_l1tbl *l1)
-{
- struct cpu_l1tbl *curr_l1;
-
- if (!l1) {
- return VMM_EFAIL;
- }
-
- /* Do nothing if new l1 table is already current l1 table */
- curr_l1 = cpu_mmu_l1tbl_current();
- if (curr_l1 == l1) {
- return VMM_OK;
- }
-
- /* Call low-level MMU switch */
- proc_mmu_switch(l1->tbl_pa, l1->contextid & 0xFF);
-
- return VMM_OK;
-}
-
-int cpu_mmu_sync_ttbr(struct cpu_l1tbl *l1)
-{
- if (!l1) {
- return VMM_EFAIL;
- }
-
-#if defined(CONFIG_ARMV5)
- invalid_tlb();
-#else
- invalid_tlb_asid(l1->contextid & 0xFF);
-#endif
- isb();
-
- return VMM_OK;
-}
-
-int cpu_mmu_sync_ttbr_va(struct cpu_l1tbl *l1, virtual_addr_t va)
-{
- if (!l1) {
- return VMM_EFAIL;
- }
-
- invalid_tlb_mva(va);
- isb();
-
- return VMM_OK;
-}
-
-void arch_cpu_aspace_print_info(struct vmm_chardev *cdev)
-{
- /* Nothing to do here. */
-}
-
-#if defined(CONFIG_ARMV5)
-
-int arch_cpu_aspace_memory_read(virtual_addr_t tmp_va,
- physical_addr_t src,
- void *dst, u32 len, bool cacheable)
-{
- int rc;
- struct cpu_page p;
- struct cpu_l1tbl *l1 = NULL;
-
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- return VMM_EFAIL;
- }
-
- p.pa = src & ~VMM_PAGE_MASK;
- p.va = tmp_va;
- p.sz = VMM_PAGE_SIZE;
- p.imp = 0;
- p.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- p.ap = TTBL_AP_SRW_U;
- p.xn = 1;
- p.tex = 0;
- p.c = (cacheable) ? 1 : 0;
- p.b = (cacheable) ? 1 : 0;
- p.ng = 0;
- p.s = 0;
-
- if ((rc = cpu_mmu_map_page(l1, &p))) {
- return rc;
- }
-
- switch (len) {
- case 1:
- *((u8 *)dst) = *(u8 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- case 2:
- *((u16 *)dst) = *(u16 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- case 4:
- *((u32 *)dst) = *(u32 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- default:
- memcpy(dst, (void *)(tmp_va + (src & VMM_PAGE_MASK)), len);
- break;
- };
-
- if ((rc = cpu_mmu_unmap_page(l1, &p))) {
- return rc;
- }
-
- return VMM_OK;
-}
-
-int arch_cpu_aspace_memory_write(virtual_addr_t tmp_va,
- physical_addr_t dst,
- void *src, u32 len, bool cacheable)
-{
- int rc;
- struct cpu_page p;
- struct cpu_l1tbl *l1 = NULL;
-
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- return VMM_EFAIL;
- }
-
- p.pa = dst & ~VMM_PAGE_MASK;
- p.va = tmp_va;
- p.sz = VMM_PAGE_SIZE;
- p.imp = 0;
- p.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- p.ap = TTBL_AP_SRW_U;
- p.xn = 1;
- p.tex = 0;
- p.c = (cacheable) ? 1 : 0;
- p.b = (cacheable) ? 1 : 0;
- p.ng = 0;
- p.s = 0;
-
- if ((rc = cpu_mmu_map_page(l1, &p))) {
- return rc;
- }
-
- switch (len) {
- case 1:
- *(u8 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u8 *)src);
- break;
- case 2:
- *(u16 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u16 *)src);
- break;
- case 4:
- *(u32 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u32 *)src);
- break;
- default:
- memcpy((void *)(tmp_va + (dst & VMM_PAGE_MASK)), src, len);
- break;
- };
-
- if ((rc = cpu_mmu_unmap_page(l1, &p))) {
- return rc;
- }
-
- return VMM_OK;
-}
-
-int __cpuinit arch_cpu_aspace_memory_rwinit(virtual_addr_t tmp_va)
-{
- /* For ARMv5 we don't have optimized memory read/write
- * hence do nothing here.
- */
- return VMM_OK;
-}
-
-#else
-
-#define PHYS_RW_L2_TTE ((TTBL_L2TBL_TTE_TYPE_SMALL_XN) | \
- ((0x0 << TTBL_L2TBL_TTE_STEX_SHIFT) & \
- TTBL_L2TBL_TTE_STEX_MASK) | \
- ((0x0 << TTBL_L2TBL_TTE_NG_SHIFT) & \
- TTBL_L2TBL_TTE_NG_MASK) | \
- ((0x0 << TTBL_L2TBL_TTE_S_SHIFT) & \
- TTBL_L2TBL_TTE_S_MASK) | \
- ((TTBL_AP_SRW_U << (TTBL_L2TBL_TTE_AP2_SHIFT - 2)) & \
- TTBL_L2TBL_TTE_AP2_MASK) | \
- ((TTBL_AP_SRW_U << TTBL_L2TBL_TTE_AP_SHIFT) & \
- TTBL_L2TBL_TTE_AP_MASK))
-
-#define PHYS_RW_L2_TTE_NOCACHE \
- (PHYS_RW_L2_TTE)
-
-#define PHYS_RW_L2_TTE_CACHE \
- (PHYS_RW_L2_TTE | \
- ((0x1 << TTBL_L2TBL_TTE_C_SHIFT) & \
- TTBL_L2TBL_TTE_C_MASK) | \
- ((0x1 << TTBL_L2TBL_TTE_B_SHIFT) & \
- TTBL_L2TBL_TTE_B_MASK))
-
-int arch_cpu_aspace_memory_read(virtual_addr_t tmp_va,
- physical_addr_t src,
- void *dst, u32 len, bool cacheable)
-{
- u32 cpu = vmm_smp_processor_id();
- u32 *l1_tte, *l2_tte;
- physical_addr_t l2base;
- struct cpu_l1tbl *l1;
- struct cpu_l2tbl *l2;
-
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- return VMM_EFAIL;
- }
-
- l1_tte = (u32 *) (l1->tbl_va + mmuctrl.mem_rw_l1_offset[cpu]);
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (!l2) {
- return VMM_EFAIL;
- }
- l2_tte = (u32 *) (l2->tbl_va + mmuctrl.mem_rw_l2_offset[cpu]);
-
- if (cacheable) {
- *l2_tte = PHYS_RW_L2_TTE_CACHE;
- } else {
- *l2_tte = PHYS_RW_L2_TTE_NOCACHE;
- }
- *l2_tte |= (src & TTBL_L2TBL_TTE_BASE12_MASK);
- clean_dcache_mva((virtual_addr_t)l2_tte);
-
- switch (len) {
- case 1:
- *((u8 *)dst) = *(u8 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- case 2:
- *((u16 *)dst) = *(u16 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- case 4:
- *((u32 *)dst) = *(u32 *)(tmp_va + (src & VMM_PAGE_MASK));
- break;
- default:
- memcpy(dst, (void *)(tmp_va + (src & VMM_PAGE_MASK)), len);
- break;
- };
-
- *l2_tte = 0x0;
- clean_dcache_mva((virtual_addr_t)l2_tte);
- invalid_tlb_mva(tmp_va);
- isb();
-
- return VMM_OK;
-}
-
-int arch_cpu_aspace_memory_write(virtual_addr_t tmp_va,
- physical_addr_t dst,
- void *src, u32 len, bool cacheable)
-{
- u32 cpu = vmm_smp_processor_id();
- u32 *l1_tte, *l2_tte;
- physical_addr_t l2base;
- struct cpu_l1tbl *l1;
- struct cpu_l2tbl *l2;
-
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- return VMM_EFAIL;
- }
-
- l1_tte = (u32 *) (l1->tbl_va + mmuctrl.mem_rw_l1_offset[cpu]);
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (!l2) {
- return VMM_EFAIL;
- }
- l2_tte = (u32 *) (l2->tbl_va + mmuctrl.mem_rw_l2_offset[cpu]);
-
- if (cacheable) {
- *l2_tte = PHYS_RW_L2_TTE_CACHE;
- } else {
- *l2_tte = PHYS_RW_L2_TTE_NOCACHE;
- }
- *l2_tte |= (dst & TTBL_L2TBL_TTE_BASE12_MASK);
- clean_dcache_mva((virtual_addr_t)l2_tte);
-
- switch (len) {
- case 1:
- *(u8 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u8 *)src);
- break;
- case 2:
- *(u16 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u16 *)src);
- break;
- case 4:
- *(u32 *)(tmp_va + (dst & VMM_PAGE_MASK)) = *((u32 *)src);
- break;
- default:
- memcpy((void *)(tmp_va + (dst & VMM_PAGE_MASK)), src, len);
- break;
- };
-
- *l2_tte = 0x0;
- clean_dcache_mva((virtual_addr_t)l2_tte);
- invalid_tlb_mva(tmp_va);
- isb();
-
- return VMM_OK;
-}
-
-int __cpuinit arch_cpu_aspace_memory_rwinit(virtual_addr_t tmp_va)
-{
- int rc;
- u32 l1_tte_type;
- u32 *l1_tte, *l2_tte;
- physical_addr_t l2base;
- struct cpu_l1tbl *l1;
- struct cpu_l2tbl *l2;
- struct cpu_page p;
-
- memset(&p, 0, sizeof(p));
- p.pa = 0;
- p.va = tmp_va;
- p.sz = VMM_PAGE_SIZE;
- p.imp = 0;
- p.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- p.ap = TTBL_AP_S_U;
- p.xn = 1;
- p.tex = 0;
- p.c = 0;
- p.b = 0;
- p.ng = 0;
- p.s = 0;
-
- rc = cpu_mmu_map_reserved_page(&p);
- if (rc) {
- return rc;
- }
-
- l1 = cpu_mmu_l1tbl_current();
- if (!l1) {
- return VMM_EFAIL;
- }
-
- l1_tte = (u32 *) (l1->tbl_va +
- ((tmp_va >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
- if (l1_tte_type != TTBL_L1TBL_TTE_TYPE_FAULT) {
- if (l1_tte_type != TTBL_L1TBL_TTE_TYPE_L2TBL) {
- return VMM_EFAIL;
- }
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- l2 = cpu_mmu_l2tbl_find_tbl_pa(l2base);
- if (!l2) {
- return VMM_ENOTAVAIL;
- }
- l2_tte = (u32 *) ((tmp_va & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *) (l2->tbl_va + ((u32) l2_tte << 2));
- *l2_tte = 0x0;
- mmuctrl.mem_rw_l1_offset[vmm_smp_processor_id()] =
- ((virtual_addr_t)l1_tte) - l1->tbl_va;
- mmuctrl.mem_rw_l2_offset[vmm_smp_processor_id()] =
- ((virtual_addr_t)l2_tte) - l2->tbl_va;
- } else {
- return VMM_ENOTAVAIL;
- }
-
- return VMM_OK;
-}
-
-#endif
-
-u32 arch_cpu_aspace_hugepage_log2size(void)
-{
- return TTBL_L1TBL_SECTION_PAGE_SHIFT;
-}
-
-int arch_cpu_aspace_map(virtual_addr_t page_va,
- virtual_size_t page_sz,
- physical_addr_t page_pa,
- u32 mem_flags)
-{
- struct cpu_page p;
-
- if (page_sz != TTBL_L2TBL_SMALL_PAGE_SIZE &&
- page_sz != TTBL_L1TBL_SECTION_PAGE_SIZE)
- return VMM_EINVALID;
-
- memset(&p, 0, sizeof(p));
-
- /* Initialize the page struct */
- p.pa = page_pa;
- p.va = page_va;
- p.sz = page_sz;
- p.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
-
-#if defined(CONFIG_ARMV5)
- /* For ARMV5 we cannot prevent writing to priviledge mode */
- if (mem_flags & (VMM_MEMORY_READABLE | VMM_MEMORY_WRITEABLE)) {
- p.ap = TTBL_AP_SRW_U;
- } else {
- p.ap = TTBL_AP_S_U;
- }
-#else
- p.imp = 0;
- if (mem_flags & VMM_MEMORY_WRITEABLE) {
- p.ap = TTBL_AP_SRW_U;
- } else if (mem_flags & VMM_MEMORY_READABLE) {
- p.ap = TTBL_AP_SR_U;
- } else {
- p.ap = TTBL_AP_S_U;
- }
- p.xn = (mem_flags & VMM_MEMORY_EXECUTABLE) ? 0 : 1;
- p.tex = 0;
- p.ng = 0;
- p.s = 0;
-#endif
-
- if ((mem_flags & VMM_MEMORY_CACHEABLE) &&
- (mem_flags & VMM_MEMORY_BUFFERABLE)) {
- p.c = 1;
- p.b = 1;
- } else if (mem_flags & VMM_MEMORY_CACHEABLE) {
- p.c = 1;
- p.b = 0;
- } else if (mem_flags & VMM_MEMORY_BUFFERABLE) {
- p.c = 0;
- p.b = 1;
- } else if (mem_flags & VMM_MEMORY_DMA_COHERENT) {
- p.c = 1;
- p.b = 1;
- } else if (mem_flags & VMM_MEMORY_DMA_NONCOHERENT) {
- p.c = 0;
- p.b = 0;
- } else if (mem_flags & VMM_MEMORY_IO_DEVICE) {
- p.c = 0;
- p.b = 0;
- } else {
- p.c = 0;
- p.b = 0;
- }
-
- return cpu_mmu_map_reserved_page(&p);
-}
-
-int arch_cpu_aspace_unmap(virtual_addr_t page_va)
-{
- int rc;
- struct cpu_page p;
-
- rc = cpu_mmu_get_reserved_page(page_va, &p);
- if (rc) {
- return rc;
- }
-
- return cpu_mmu_unmap_reserved_page(&p);
-}
-
-int arch_cpu_aspace_va2pa(virtual_addr_t va, physical_addr_t *pa)
-{
- int rc;
- struct cpu_page p;
-
- if ((rc = cpu_mmu_get_reserved_page(va, &p)) == VMM_OK) {
- *pa = p.pa + (va & (p.sz - 1));
- }
-
- return rc;
-}
-
-virtual_addr_t __init arch_cpu_aspace_vapool_start(void)
-{
- return arch_code_vaddr_start();
-}
-
-virtual_size_t __init arch_cpu_aspace_vapool_estimate_size(
- physical_size_t total_ram)
-{
- return CONFIG_VAPOOL_SIZE_MB << 20;
-}
-
-int __init arch_cpu_aspace_primary_init(physical_addr_t *core_resv_pa,
- virtual_addr_t *core_resv_va,
- virtual_size_t *core_resv_sz,
- physical_addr_t *arch_resv_pa,
- virtual_addr_t *arch_resv_va,
- virtual_size_t *arch_resv_sz)
-{
- int rc = VMM_EFAIL;
- u32 i, j, val;
- virtual_addr_t va, resv_va = *core_resv_va;
- virtual_size_t sz, resv_sz = *core_resv_sz;
- physical_addr_t pa, resv_pa = *core_resv_pa;
- struct cpu_l2tbl *l2;
- struct cpu_page respg;
-
- /* Reset the memory of MMU control structure */
- memset(&mmuctrl, 0, sizeof(mmuctrl));
-
- /* Initialize list heads */
- INIT_SPIN_LOCK(&mmuctrl.defl1_lock);
- INIT_SPIN_LOCK(&mmuctrl.l1_alloc_lock);
- INIT_LIST_HEAD(&mmuctrl.l1tbl_list);
- INIT_LIST_HEAD(&mmuctrl.free_l1tbl_list);
- INIT_SPIN_LOCK(&mmuctrl.l2_alloc_lock);
- INIT_LIST_HEAD(&mmuctrl.free_l2tbl_list);
-
- /* Check & setup core reserved space and update the
- * core_resv_pa, core_resv_va, and core_resv_sz parameters
- * to inform host aspace about correct placement of the
- * core reserved space.
- */
- pa = arch_code_paddr_start();
- va = arch_code_vaddr_start();
- sz = arch_code_size();
- resv_va = va + sz;
- resv_pa = pa + sz;
- if (resv_va & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) {
- resv_va += TTBL_L2TBL_SMALL_PAGE_SIZE -
- (resv_va & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
- }
- if (resv_pa & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) {
- resv_pa += TTBL_L2TBL_SMALL_PAGE_SIZE -
- (resv_pa & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
- }
- if (resv_sz & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) {
- resv_sz += TTBL_L2TBL_SMALL_PAGE_SIZE -
- (resv_sz & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
- }
- *core_resv_pa = resv_pa;
- *core_resv_va = resv_va;
- *core_resv_sz = resv_sz;
-
- /* Allocate arch reserved space and update the *arch_resv_pa,
- * *arch_resv_va, and *arch_resv_sz parameters to inform host
- * aspace about the arch reserved space.
- */
- if ((resv_pa + resv_sz) & (TTBL_L1TBL_SIZE - 1)) {
- resv_sz += TTBL_L1TBL_SIZE -
- ((resv_pa + resv_sz) & (TTBL_L1TBL_SIZE - 1));
- }
- *arch_resv_va = (resv_va + resv_sz);
- *arch_resv_pa = (resv_pa + resv_sz);
- *arch_resv_sz = resv_sz;
- mmuctrl.l1_base_va = resv_va + resv_sz;
- mmuctrl.l1_base_pa = resv_pa + resv_sz;
- resv_sz += TTBL_L1TBL_SIZE * TTBL_MAX_L1TBL_COUNT;
- mmuctrl.l2_base_va = resv_va + resv_sz;
- mmuctrl.l2_base_pa = resv_pa + resv_sz;
- resv_sz += TTBL_L2TBL_SIZE * TTBL_MAX_L2TBL_COUNT;
- if (resv_sz & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) {
- resv_sz += TTBL_L2TBL_SMALL_PAGE_SIZE -
- (resv_sz & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
- }
- *arch_resv_sz = resv_sz - *arch_resv_sz;
- mmuctrl.il2_base_va = (virtual_addr_t)&defl2_ttbl;
- mmuctrl.il2_base_pa = mmuctrl.il2_base_va -
- arch_code_vaddr_start() +
- arch_code_paddr_start();
-
- /* Setup up l1 array */
- memset(mmuctrl.l1_array, 0x0,
- sizeof(struct cpu_l1tbl) * TTBL_MAX_L1TBL_COUNT);
- for (i = 0; i < TTBL_MAX_L1TBL_COUNT; i++) {
- INIT_LIST_HEAD(&mmuctrl.l1_array[i].head);
- mmuctrl.l1_array[i].num = i;
- mmuctrl.l1_array[i].tbl_pa = mmuctrl.l1_base_pa +
- i * TTBL_L1TBL_SIZE;
- mmuctrl.l1_array[i].tbl_va = mmuctrl.l1_base_va +
- i * TTBL_L1TBL_SIZE;
- mmuctrl.l1_array[i].tte_cnt = 0;
- mmuctrl.l1_array[i].l2tbl_cnt = 0;
- INIT_LIST_HEAD(&mmuctrl.l1_array[i].l2tbl_list);
- list_add_tail(&mmuctrl.l1_array[i].head,
- &mmuctrl.free_l1tbl_list);
- }
-
- /* Setup up initial l2 array */
- memset(mmuctrl.il2_array, 0x0,
- sizeof(struct cpu_l2tbl) * TTBL_INITIAL_L2TBL_COUNT);
- for (i = 0; i < TTBL_INITIAL_L2TBL_COUNT; i++) {
- if (defl2_ttbl_used[i]) {
- continue;
- }
- INIT_LIST_HEAD(&mmuctrl.il2_array[i].head);
- mmuctrl.il2_array[i].num = i;
- mmuctrl.il2_array[i].tbl_pa = mmuctrl.il2_base_pa +
- i * TTBL_L2TBL_SIZE;
- mmuctrl.il2_array[i].tbl_va = mmuctrl.il2_base_va +
- i * TTBL_L2TBL_SIZE;
- mmuctrl.il2_array[i].tte_cnt = 0;
- list_add_tail(&mmuctrl.il2_array[i].head,
- &mmuctrl.free_l2tbl_list);
- }
-
- /* Setup up l2 array */
- memset(mmuctrl.l2_array, 0x0,
- sizeof(struct cpu_l2tbl) * TTBL_MAX_L2TBL_COUNT);
- for (i = 0; i < TTBL_MAX_L2TBL_COUNT; i++) {
- INIT_LIST_HEAD(&mmuctrl.l2_array[i].head);
- mmuctrl.l2_array[i].num = i + TTBL_INITIAL_L2TBL_COUNT;
- mmuctrl.l2_array[i].tbl_pa = mmuctrl.l2_base_pa +
- i * TTBL_L2TBL_SIZE;
- mmuctrl.l2_array[i].tbl_va = mmuctrl.l2_base_va +
- i * TTBL_L2TBL_SIZE;
- mmuctrl.l2_array[i].tte_cnt = 0;
- list_add_tail(&mmuctrl.l2_array[i].head,
- &mmuctrl.free_l2tbl_list);
- }
-
- /* Handcraft default (or master) ttbl */
- INIT_LIST_HEAD(&mmuctrl.defl1.l2tbl_list);
- mmuctrl.defl1.num = TTBL_MAX_L1TBL_COUNT;
- mmuctrl.defl1.contextid = mmuctrl.l1_next_contextid;
- mmuctrl.l1_next_contextid++;
- mmuctrl.defl1.tbl_va = (virtual_addr_t)&defl1_ttbl;
- mmuctrl.defl1.tbl_pa = arch_code_paddr_start() +
- ((virtual_addr_t)&defl1_ttbl - arch_code_vaddr_start());
- /* Scan table */
- mmuctrl.defl1.tte_cnt = 0;
- for (i = 0; i < TTBL_L1TBL_SIZE; i += 4) {
- val = *((u32 *)(mmuctrl.defl1.tbl_va + i));
- if ((val & TTBL_L1TBL_TTE_TYPE_MASK) !=
- TTBL_L1TBL_TTE_TYPE_FAULT) {
- mmuctrl.defl1.tte_cnt++;
- }
- }
- mmuctrl.defl1.l2tbl_cnt = 0;
- /* Update MMU control */
- for (i = 0; i < TTBL_INITIAL_L2TBL_COUNT; i++) {
- if (!defl2_ttbl_used[i]) {
- break;
- }
- l2 = &mmuctrl.il2_array[i];
- INIT_LIST_HEAD(&l2->head);
- l2->num = i;
- l2->l1 = &mmuctrl.defl1;
- l2->imp = 0;
- l2->domain = TTBL_L1TBL_TTE_DOM_RESERVED;
- l2->tbl_pa = mmuctrl.il2_base_pa + i * TTBL_L2TBL_SIZE;
- l2->tbl_va = mmuctrl.il2_base_va + i * TTBL_L2TBL_SIZE;
- l2->map_va = defl2_ttbl_mapva[i];
- l2->tte_cnt = 0;
- for (j = 0; j < TTBL_L2TBL_SIZE; j += 4) {
- val = *((u32 *)(l2->tbl_va + j));
- if ((val & TTBL_L2TBL_TTE_TYPE_MASK) !=
- TTBL_L2TBL_TTE_TYPE_FAULT) {
- l2->tte_cnt++;
- }
- }
- list_add_tail(&l2->head,
- &mmuctrl.defl1.l2tbl_list);
- mmuctrl.defl1.l2tbl_cnt++;
- mmuctrl.l2_alloc_count++;
- }
-
- /* Force switch over to default (or master) ttbl */
- proc_mmu_switch(mmuctrl.defl1.tbl_pa, mmuctrl.defl1.contextid & 0xFF);
-
- /* Remove all TLB enteries to start fresh */
- invalid_tlb();
-
- /* Map reserved space (core reserved space + arch reserved space)
- * We have kept our page table pool in reserved area pages
- * as cacheable and write-back. We will clean data cache every
- * time we modify a page table (or translation table) entry.
- */
- pa = resv_pa;
- va = resv_va;
- sz = resv_sz;
- while (sz) {
- memset(&respg, 0, sizeof(respg));
-#if defined(CONFIG_ARMV5)
- respg.pa = pa;
- respg.va = va;
- respg.sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- respg.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- respg.ap = TTBL_AP_SRW_U;
- respg.c = 1;
- respg.b = 1;
-#else
- respg.pa = pa;
- respg.va = va;
- respg.sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- respg.imp = 0;
- respg.dom = TTBL_L1TBL_TTE_DOM_RESERVED;
- respg.ap = TTBL_AP_SRW_U;
- respg.xn = 0;
- respg.tex = 0;
- respg.c = 1;
- respg.b = 1;
- respg.s = 0;
- respg.ng = 0;
-#endif
- if ((rc = cpu_mmu_map_reserved_page(&respg))) {
- goto mmu_init_error;
- }
- sz -= TTBL_L2TBL_SMALL_PAGE_SIZE;
- pa += TTBL_L2TBL_SMALL_PAGE_SIZE;
- va += TTBL_L2TBL_SMALL_PAGE_SIZE;
- }
-
- return VMM_OK;
-
-mmu_init_error:
- return rc;
-}
-
-int __cpuinit arch_cpu_aspace_secondary_init(void)
-{
- /* Force switch over to default (or master) ttbl */
- proc_mmu_switch(mmuctrl.defl1.tbl_pa, mmuctrl.defl1.contextid & 0xFF);
-
- /* Remove all TLB enteries to start fresh */
- invalid_tlb();
-
- return VMM_OK;
-}
diff --git a/arch/arm/cpu/arm32/cpu_mmu_entry.c b/arch/arm/cpu/arm32/cpu_mmu_entry.c
deleted file mode 100644
index 23e1e1aa..00000000
--- a/arch/arm/cpu/arm32/cpu_mmu_entry.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- * Copyright (c) 2014 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_mmu_entry.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief Initial translation table setup at boot time
- */
-
-#include <vmm_types.h>
-#include <arch_io.h>
-#include <libs/libfdt.h>
-#include <generic_devtree.h>
-#include <cpu_defines.h>
-#include <cpu_mmu.h>
-
-struct mmu_entry_ctrl {
- virtual_addr_t l1_base;
- virtual_addr_t l2_base;
- u32 *next_l2;
- u32 l2_count;
- int *l2_used;
- virtual_addr_t *l2_mapva;
-};
-
-extern u8 defl1_ttbl[];
-extern u8 defl2_ttbl[];
-extern int defl2_ttbl_used[];
-extern virtual_addr_t defl2_ttbl_mapva[];
-#ifdef CONFIG_ARCH_GENERIC_DEFTERM_EARLY
-extern u8 defterm_early_base[];
-#endif
-
-void __attribute__ ((section(".entry")))
- __setup_initial_ttbl(struct mmu_entry_ctrl *entry,
- virtual_addr_t map_start, virtual_addr_t map_end,
- virtual_addr_t pa_start, int cacheable, int writable)
-{
- u32 i;
- u32 *l1_tte, *l2_tte;
- u32 l1_tte_type, l2_tte_type;
- virtual_addr_t l2base, page_addr;
-
- /* align start addresses */
- map_start &= ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
- pa_start &= ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
-
- page_addr = map_start;
-
- while (page_addr < map_end) {
-
- /* Setup level1 table */
- l1_tte = (u32 *) (entry->l1_base +
- ((page_addr >> TTBL_L1TBL_TTE_OFFSET_SHIFT) << 2));
- l1_tte_type = *l1_tte & TTBL_L1TBL_TTE_TYPE_MASK;
- if (l1_tte_type == TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL) {
- /* Find level2 table */
- l2base = *l1_tte & TTBL_L1TBL_TTE_BASE10_MASK;
- } else {
- /* Allocate new level2 table */
- if (entry->l2_count == TTBL_INITIAL_L2TBL_COUNT) {
- while (1) ; /* No initial table available */
- }
- for (i = 0; i < (TTBL_L2TBL_SIZE/4); i++) {
- entry->next_l2[i] = 0x0;
- }
- entry->l2_used[entry->l2_count] = 1;
- entry->l2_mapva[entry->l2_count] =
- page_addr & TTBL_L1TBL_TTE_OFFSET_MASK;
- entry->l2_count++;
-
-#if defined(CONFIG_ARMV5)
- *l1_tte = TTBL_L1TBL_TTE_REQ_MASK;
- *l1_tte |= TTBL_L1TBL_TTE_DOM_RESERVED <<
- TTBL_L1TBL_TTE_DOM_SHIFT;
- *l1_tte |= ((virtual_addr_t)entry->next_l2) &
- TTBL_L1TBL_TTE_BASE10_MASK;
- *l1_tte |= TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL;
-#else
- *l1_tte = 0x0;
- *l1_tte |= TTBL_L1TBL_TTE_DOM_RESERVED <<
- TTBL_L1TBL_TTE_DOM_SHIFT;
- *l1_tte |= ((virtual_addr_t)entry->next_l2) &
- TTBL_L1TBL_TTE_BASE10_MASK;
- *l1_tte |= TTBL_L1TBL_TTE_TYPE_L2TBL;
-#endif
-
- l2base = (virtual_addr_t)entry->next_l2;
- entry->next_l2 += (TTBL_L2TBL_SIZE/4);
- }
-
- /* Setup level2 table */
- l2_tte = (u32 *)((page_addr & ~TTBL_L1TBL_TTE_OFFSET_MASK) >>
- TTBL_L2TBL_TTE_OFFSET_SHIFT);
- l2_tte = (u32 *)(l2base + ((u32)l2_tte << 2));
- l2_tte_type = *l2_tte & TTBL_L2TBL_TTE_TYPE_MASK;
- if (l2_tte_type != TTBL_L2TBL_TTE_TYPE_SMALL) {
-#if defined(CONFIG_ARMV5)
- *l2_tte = (((page_addr - map_start) + pa_start) &
- TTBL_L2TBL_TTE_BASE12_MASK);
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_SMALL;
- *l2_tte |=
- (TTBL_AP_SRW_U << TTBL_L2TBL_TTE_V5_AP0_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP0_MASK;
- *l2_tte |=
- (TTBL_AP_SRW_U << TTBL_L2TBL_TTE_V5_AP1_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP1_MASK;
- *l2_tte |=
- (TTBL_AP_SRW_U << TTBL_L2TBL_TTE_V5_AP2_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP2_MASK;
- *l2_tte |=
- (TTBL_AP_SRW_U << TTBL_L2TBL_TTE_V5_AP3_SHIFT) &
- TTBL_L2TBL_TTE_V5_AP3_MASK;
- *l2_tte |=
- (cacheable << TTBL_L2TBL_TTE_C_SHIFT) &
- TTBL_L2TBL_TTE_C_MASK;
- *l2_tte |=
- (cacheable << TTBL_L2TBL_TTE_B_SHIFT) &
- TTBL_L2TBL_TTE_B_MASK;
-#else
- *l2_tte = 0x0;
- *l2_tte |= (((page_addr - map_start) + pa_start) &
- TTBL_L2TBL_TTE_BASE12_MASK);
- /*
- * When JTAG debugging is disable, set writable page to
- * TTBL_L2TBL_TTE_TYPE_SMALL_XN
- */
- *l2_tte |= TTBL_L2TBL_TTE_TYPE_SMALL_X;
- *l2_tte |= (0x0 << TTBL_L2TBL_TTE_STEX_SHIFT) &
- TTBL_L2TBL_TTE_STEX_MASK;
- *l2_tte |= (0x0 << TTBL_L2TBL_TTE_NG_SHIFT) &
- TTBL_L2TBL_TTE_NG_MASK;
- *l2_tte |= (0x0 << TTBL_L2TBL_TTE_S_SHIFT) &
- TTBL_L2TBL_TTE_S_MASK;
- if (writable) {
- *l2_tte |=
- (TTBL_AP_SRW_U << (TTBL_L2TBL_TTE_AP2_SHIFT - 2)) &
- TTBL_L2TBL_TTE_AP2_MASK;
- *l2_tte |= (TTBL_AP_SRW_U << TTBL_L2TBL_TTE_AP_SHIFT) &
- TTBL_L2TBL_TTE_AP_MASK;
- } else {
- *l2_tte |= (TTBL_AP_SR_U << (TTBL_L2TBL_TTE_AP2_SHIFT - 2)) &
- TTBL_L2TBL_TTE_AP2_MASK;
- *l2_tte |= (TTBL_AP_SR_U << TTBL_L2TBL_TTE_AP_SHIFT) &
- TTBL_L2TBL_TTE_AP_MASK;
- }
- *l2_tte |= (cacheable << TTBL_L2TBL_TTE_C_SHIFT) &
- TTBL_L2TBL_TTE_C_MASK;
- *l2_tte |= (cacheable << TTBL_L2TBL_TTE_B_SHIFT) &
- TTBL_L2TBL_TTE_B_MASK;
-#endif
- }
-
- /* Point to next page */
- page_addr += TTBL_L2TBL_SMALL_PAGE_SIZE;
- }
-}
-
-/* Note: This functions must be called with MMU disabled from
- * primary CPU only.
- * Note: This functions cannot refer to any global variable &
- * functions to ensure that it can execute from anywhere.
- */
-#define to_load_pa(va) ({ \
- virtual_addr_t _tva = (va); \
- if (exec_start <= _tva && _tva < exec_end) { \
- _tva = _tva - exec_start + load_start; \
- } \
- _tva; \
- })
-#define to_exec_va(va) ({ \
- virtual_addr_t _tva = (va); \
- if (load_start <= _tva && _tva < load_end) { \
- _tva = _tva - load_start + exec_start; \
- } \
- _tva; \
- })
-
-#define SECTION_START(SECTION) _ ## SECTION ## _start
-#define SECTION_END(SECTION) _ ## SECTION ## _end
-
-#define SECTION_ADDR_START(SECTION) (virtual_addr_t)&SECTION_START(SECTION)
-#define SECTION_ADDR_END(SECTION) (virtual_addr_t)&SECTION_END(SECTION)
-
-#define DECLARE_EXTERN_SECTION(SECTION) \
- extern virtual_addr_t SECTION_START(SECTION); \
- extern virtual_addr_t SECTION_END(SECTION)
-
-DECLARE_EXTERN_SECTION(text);
-DECLARE_EXTERN_SECTION(init_text);
-DECLARE_EXTERN_SECTION(cpuinit);
-DECLARE_EXTERN_SECTION(spinlock);
-DECLARE_EXTERN_SECTION(rodata);
-
-#define SETUP_RO_SECTION(ENTRY, SECTION) \
- __setup_initial_ttbl(&(ENTRY), \
- SECTION_ADDR_START(SECTION), \
- SECTION_ADDR_END(SECTION), \
- to_load_pa(SECTION_ADDR_START(SECTION)), \
- TRUE, \
- FALSE)
-
-virtual_size_t __attribute__ ((section(".entry")))
- _fdt_size(virtual_addr_t dtb_start)
-{
- u32 *src = (u32 *)dtb_start;
-
- if (rev32(src[0]) != FDT_MAGIC) {
- while (1); /* Hang !!! */
- }
-
- return rev32(src[1]);
-}
-
-void __attribute__ ((section(".entry")))
- _setup_initial_ttbl(virtual_addr_t load_start, virtual_addr_t load_end,
- virtual_addr_t exec_start, virtual_addr_t dtb_start)
-{
- u32 i;
- virtual_addr_t exec_end = exec_start + (load_end - load_start);
-#ifdef CONFIG_ARCH_GENERIC_DEFTERM_EARLY
- virtual_addr_t defterm_early_va;
-#endif
- virtual_addr_t *dt_virt =
- (virtual_addr_t *)to_load_pa((virtual_addr_t)&devtree_virt);
- virtual_addr_t *dt_virt_base =
- (virtual_addr_t *)to_load_pa((virtual_addr_t)&devtree_virt_base);
- virtual_size_t *dt_virt_size =
- (virtual_size_t *)to_load_pa((virtual_addr_t)&devtree_virt_size);
- physical_addr_t *dt_phys_base =
- (physical_addr_t *)to_load_pa((virtual_addr_t)&devtree_phys_base);
- struct mmu_entry_ctrl entry = { 0, 0, NULL, 0, NULL };
-
- /* Init ttbl_used, ttbl_mapva, and related stuff */
- entry.l2_used =
- (int *)to_load_pa((virtual_addr_t)&defl2_ttbl_used);
- entry.l2_mapva =
- (virtual_addr_t *)to_load_pa((virtual_addr_t)&defl2_ttbl_mapva);
- for (i = 0; i < TTBL_INITIAL_L2TBL_COUNT; i++) {
- entry.l2_used[i] = 0;
- entry.l2_mapva[i] = 0;
- }
- entry.l1_base = to_load_pa((virtual_addr_t)&defl1_ttbl);
- entry.l2_base = to_load_pa((virtual_addr_t)&defl2_ttbl);
- entry.next_l2 = (u32 *)entry.l2_base;
-
- /* Init l1 ttbl */
- for (i = 0; i < (TTBL_L1TBL_SIZE/4); i++) {
- ((u32 *)entry.l1_base)[i] = 0x0;
- }
-
-#ifdef CONFIG_ARCH_GENERIC_DEFTERM_EARLY
- /* Map UART for early defterm
- * Note: This is for early debug purpose
- */
- defterm_early_va = to_exec_va((virtual_addr_t)&defterm_early_base);
- __setup_initial_ttbl(&entry,
- defterm_early_va,
- defterm_early_va + TTBL_L2TBL_SMALL_PAGE_SIZE,
- (virtual_addr_t)CONFIG_ARCH_GENERIC_DEFTERM_EARLY_BASE_PA,
- FALSE, TRUE);
-#endif
-
- /* Map physical = logical
- * Note: This mapping is using at boot time only
- */
- __setup_initial_ttbl(&entry, load_start, load_end, load_start,
- TRUE, TRUE);
-
- /* Map to logical addresses which are
- * covered by read-only linker sections
- * Note: This mapping is used at runtime
- */
- SETUP_RO_SECTION(entry, text);
- SETUP_RO_SECTION(entry, init_text);
- SETUP_RO_SECTION(entry, cpuinit);
- SETUP_RO_SECTION(entry, spinlock);
- SETUP_RO_SECTION(entry, rodata);
-
- /* Map rest of logical addresses which are
- * not covered by read-only linker sections
- * Note: This mapping is used at runtime
- */
- __setup_initial_ttbl(&entry, exec_start, exec_end, load_start,
- TRUE, TRUE);
-
- /* Compute and save devtree addresses */
- *dt_phys_base = dtb_start & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
- *dt_virt_base = exec_start - _fdt_size(dtb_start);
- *dt_virt_base &= ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
- *dt_virt_size = exec_start - *dt_virt_base;
- *dt_virt = *dt_virt_base + (dtb_start & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1));
-
- /* Map device tree */
- __setup_initial_ttbl(&entry, *dt_virt_base,
- *dt_virt_base + *dt_virt_size, *dt_phys_base,
- TRUE, TRUE);
-}
diff --git a/arch/arm/cpu/arm32/cpu_proc_v5.S b/arch/arm/cpu/arm32/cpu_proc_v5.S
deleted file mode 100644
index a591acbc..00000000
--- a/arch/arm/cpu/arm32/cpu_proc_v5.S
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_proc_v5.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of ARMv5 specific quirky functions
- *
- * Please note that these functions are primarily for ARM926.
- */
-
-#include <cpu_defines.h>
-
-/*
- * Idle the processor (eg, wait for interrupt).
- *
- * IRQs are already disabled.
- */
- .globl proc_do_idle
-proc_do_idle:
- mov r0, #0
- mrc p15, 0, r1, c1, c0, 0 @ Read control register
- mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
- bic r2, r1, #1 << 12
- mrs r3, cpsr @ Disable FIQs while Icache
- orr ip, r3, #CPSR_FIQ_DISABLED @ is disabled
- msr cpsr_c, ip
- mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
- mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
- mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
- msr cpsr_c, r3 @ Restore FIQ state
- mov pc, lr
-
-/*
- * MMU context switch
- *
- * Set the translation table base pointer and context ID
- *
- * It is assumed that:
- * - we are not using split page tables
- *
- * Note: For ARM926, we ignore the context ID
- */
- .globl proc_mmu_switch
-proc_mmu_switch:
- mov ip, #0
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
-#else
-@ && 'Clean & Invalidate whole DCache'
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
- bne 1b
-#endif
- mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, ip, c7, c10, 4 @ drain WB
- mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
- mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
- bx lr
-
-/*
- * Boot-time processor setup
- *
- * Initialise TLB, Caches, and MMU state ready to switch the MMU
- * on. Return in r0 the new CP15 C1 control register setting.
- *
- * Note: We blindly use all registers because this will be
- * called at boot-time when there is not stack
- */
- .globl proc_setup
-proc_setup:
- mov r0, #0
- mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
- mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
-
- mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- mov r0, #4 @ disable write-back on caches explicitly
- mcr p15, 7, r0, c15, c0, 0
-#endif
-
- adr r5, arm926_crval
- ldmia r5, {r5, r6}
- mrc p15, 0, r0, c1, c0 @ get control register v4
- bic r0, r0, r5
- orr r0, r0, r6
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
- orr r0, r0, #0x4000 @ .1.. .... .... ....
-#endif
- mov pc, lr
-
- /*
- * R
- * .RVI ZFRS BLDP WCAM
- * .001 0001 ..11 0101
- *
- */
- .align 2
- .type arm926_crval, #object
-arm926_crval:
- .word 0x00007f3f /* clear */
- .word 0x00001135 /* mmuset */
-
diff --git a/arch/arm/cpu/arm32/cpu_proc_v6.S b/arch/arm/cpu/arm32/cpu_proc_v6.S
deleted file mode 100644
index 1a3a11c4..00000000
--- a/arch/arm/cpu/arm32/cpu_proc_v6.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_proc_v6.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of ARMv6 specific quirky functions
- */
-
-#include <cpu_defines.h>
-
-#define D_CACHE_LINE_SIZE 32
-
-#define TTB_C (1 << 0)
-#define TTB_S (1 << 1)
-#define TTB_IMP (1 << 2)
-#define TTB_RGN_NC (0 << 3)
-#define TTB_RGN_WBWA (1 << 3)
-#define TTB_RGN_WT (2 << 3)
-#define TTB_RGN_WB (3 << 3)
-
-#if 0 /* Note: We don't use cachable page-table walks */
-#define TTB_FLAGS_UP TTB_RGN_WBWA
-#else
-#define TTB_FLAGS_UP 0x0
-#endif
-
-#if 0 /* Note: We don't use cachable page-table walks */
-#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
-#else
-#define TTB_FLAGS_SMP 0x0
-#endif
-
-/*
- * Idle the processor (eg, wait for interrupt).
- *
- * IRQs are already disabled.
- */
- .globl proc_do_idle
-proc_do_idle:
- mov r1, #0
- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
- mov pc, lr
-
-/*
- * MMU context switch
- *
- * Set the translation table base pointer and context ID
- *
- * It is assumed that:
- * - we are not using split page tables
- */
- .globl proc_mmu_switch
-proc_mmu_switch:
- mov r2, #0
-#ifdef CONFIG_SMP
- orr r0, r0, #TTB_FLAGS_SMP
-#else
- orr r0, r0, #TTB_FLAGS_UP
-#endif
- mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
- mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
- mcr p15, 0, r0, c2, c0, 0 @ set TTBR0
-#ifdef CONFIG_PID_IN_CONTEXTIDR
- mrc p15, 0, r2, c13, c0, 1 @ read current context ID
- bic r2, r2, #0xff @ extract the PID
- and r1, r1, #0xff
- orr r1, r1, r2 @ insert into new context ID
-#endif
- mcr p15, 0, r1, c13, c0, 1 @ set context ID
- bx lr
-
-/*
- * Boot-time processor setup
- *
- * Initialise TLB, Caches, and MMU state ready to switch the MMU
- * on. Return in r0 the new CP15 C1 control register setting.
- *
- * We automatically detect if we have a Harvard cache, and use the
- * Harvard cache control instructions insead of the unified cache
- * control instructions.
- *
- * This should be able to cover all ARMv6 cores.
- *
- * It is assumed that:
- * - cache type register is implemented
- *
- * Note: We blindly use all registers because this will be
- * called at boot-time when there is not stack
- */
- .globl proc_setup
-proc_setup:
- mrc p15, 0, r0, c0, c0, 0 @ Read Main ID register
- and r10, r0, #0xff000000 @ ARM?
- teq r10, #0x41000000
- bne arm_proc_setup_skip
- lsl r0, r0, #16
- lsr r0, r0, #20
-
- ldr r10, =0x00000b02 @ ARM11MP primary part number
- teq r0, r10
- bne arm_arm11mp_skip
-#ifdef CONFIG_SMP
- mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
- nop
- orr r0, r0, #0x20
- mcr p15, 0, r0, c1, c0, 1
- nop
-#endif
- b proc_specific_setup_done
-arm_arm11mp_skip:
-arm_proc_setup_skip:
-
-proc_specific_setup_done:
- mov r0, #0
- mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
- mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
- mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
-
- mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
- mcr p15, 0, r0, c2, c0, 2 @ TTB control register
-
- adr r5, v6_crval
- ldmia r5, {r5, r6}
- mrc p15, 0, r0, c1, c0, 0 @ read control register
- bic r0, r0, r5 @ clear bits them
- orr r0, r0, r6 @ set them
-#ifdef CONFIG_ARM_ERRATA_364296
- /*
- * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
- * corruption with hit-under-miss enabled). The conditional code below
- * (setting the undocumented bit 31 in the auxiliary control register
- * and the FI bit in the control register) disables hit-under-miss
- * without putting the processor into full low interrupt latency mode.
- */
- ldr r6, =0x4107b362 @ id for ARM1136 r0p2
- mrc p15, 0, r5, c0, c0, 0 @ get processor id
- teq r5, r6 @ check for the faulty core
- mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
- orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
- mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
- orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
-#endif
- mov pc, lr @ return
-
- /*
- * V X F I D LR
- * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
- * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
- * 0 110 0001 1.00 .111 1101 < we want
- */
- .align 2
- .type v6_crval, #object
-v6_crval:
- .word 0x01e0fb7f /* clear */
- .word 0x00c0187d /* mmuset */
-
-#ifdef CONFIG_SMP
- /*
- * Retrive SMP ID of current processor
- */
- .globl arch_smp_id
-arch_smp_id:
- mrc p15, 0, r0, c13, c0, 4
- bx lr
-
- /*
- * Setup SMP ID of current processor
- */
- .globl proc_setup_smp_id
-proc_setup_smp_id:
- /* Ensure that next SMP ID in r0
- * is less than CONFIG_CPU_COUNT
- */
- ldr r1, =CONFIG_CPU_COUNT
- cmp r0, r1
- blt proc_setup_smp_id_done
- b .
-
-proc_setup_smp_id_done:
- mcr p15, 0, r0, c13, c0, 4
- bx lr
-#endif
diff --git a/arch/arm/cpu/arm32/cpu_proc_v7.S b/arch/arm/cpu/arm32/cpu_proc_v7.S
deleted file mode 100644
index a76c7bcb..00000000
--- a/arch/arm/cpu/arm32/cpu_proc_v7.S
+++ /dev/null
@@ -1,264 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_proc_v7.S
- * @author Anup Patel (an...@brainfault.org)
- * @brief Low-level implementation of ARMv7 specific quirky functions
- */
-
-#include <cpu_defines.h>
-
-#define TTB_S (1 << 1)
-#define TTB_RGN_NC (0 << 3)
-#define TTB_RGN_OC_WBWA (1 << 3)
-#define TTB_RGN_OC_WT (2 << 3)
-#define TTB_RGN_OC_WB (3 << 3)
-#define TTB_NOS (1 << 5)
-#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
-#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
-#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
-#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
-
-#if 0 /* Note: We don't use cachable page-table walks */
-/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
-#else
-#define TTB_FLAGS_UP 0x0
-#endif
-
-#if 0 /* Note: We don't use cachable page-table walks */
-/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#else
-#define TTB_FLAGS_SMP 0x0
-#endif
-
-/*
- * Idle the processor (eg, wait for interrupt).
- *
- * IRQs are already disabled.
- */
- .globl proc_do_idle
-proc_do_idle:
- dsb
- wfi
- mov pc, lr
-
-/*
- * MMU context switch
- *
- * Set the translation table base pointer and context ID
- *
- * It is assumed that:
- * - we are not using split page tables
- */
- .globl proc_mmu_switch
-proc_mmu_switch:
- mov r2, #0
-#ifdef CONFIG_SMP
- orr r0, r0, #TTB_FLAGS_SMP
-#else
- orr r0, r0, #TTB_FLAGS_UP
-#endif
-#ifdef CONFIG_ARM_ERRATA_430973
- mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
-#endif
-#ifdef CONFIG_PID_IN_CONTEXTIDR
- mrc p15, 0, r2, c13, c0, 1 @ read current context ID
- lsr r2, r2, #8 @ extract the PID
- bfi r1, r2, #8, #24 @ insert into new context ID
-#endif
-#ifdef CONFIG_ARM_ERRATA_754322
- dsb
-#endif
- mcr p15, 0, r0, c2, c0, 0 @ set TTBR0
- isb
- mcr p15, 0, r1, c13, c0, 1 @ set context ID
- isb
- bx lr
-
-/*
- * Boot-time processor setup
- *
- * Initialise TLB, Caches, and MMU state ready to switch the MMU
- * on. Return in r0 the new CP15 C1 control register setting.
- *
- * This should be able to cover all ARMv7 cores.
- *
- * It is assumed that:
- * - cache type register is implemented
- *
- * Note: We blindly use all registers because this will be
- * called at boot-time when there is not stack
- */
- .globl proc_setup
-proc_setup:
- mrc p15, 0, r0, c0, c0, 0 @ read main ID register
- and r10, r0, #0xff000000 @ ARM?
- teq r10, #0x41000000
- bne arm_proc_setup_skip
- and r5, r0, #0x00f00000 @ variant
- and r6, r0, #0x0000000f @ revision
- orr r6, r6, r5, lsr #20-4 @ combine variant and revision
- ubfx r0, r0, #4, #12 @ primary part number
-
- /* Cortex-A8 Errata */
- ldr r10, =0x00000c08 @ Cortex-A8 primary part number
- teq r0, r10
- bne arm_cortex_a8_skip
-#ifdef CONFIG_ARM_ERRATA_430973
- teq r5, #0x00100000 @ only present in r1p*
- mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
- orreq r10, r10, #(1 << 6) @ set IBE to 1
- mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
-#endif
-#ifdef CONFIG_ARM_ERRATA_458693
- teq r6, #0x20 @ only present in r2p0
- mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
- orreq r10, r10, #(1 << 5) @ set L1NEON to 1
- orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
- mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
-#endif
-#ifdef CONFIG_ARM_ERRATA_460075
- teq r6, #0x20 @ only present in r2p0
- mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
- tsteq r10, #1 << 22
- orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
- mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
-#endif
- b proc_specific_setup_done
-arm_cortex_a8_skip:
-
- /* Cortex-A9 Errata */
- ldr r10, =0x00000c09 @ Cortex-A9 primary part number
- teq r0, r10
- bne arm_cortex_a9_skip
-#ifdef CONFIG_SMP
- mov r10, #(1 << 0) @ TLB ops broadcasting
- mrc p15, 0, r0, c1, c0, 1
- tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
- orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
- orreq r0, r0, r10 @ Enable CPU-specific SMP bits
- mcreq p15, 0, r0, c1, c0, 1
-#endif
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 @ only present up to r2p2
- mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
- orrle r10, r10, #1 << 4 @ set bit #4
- mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
-#endif
-#ifdef CONFIG_ARM_ERRATA_742231
- teq r6, #0x20 @ present in r2p0
- teqne r6, #0x21 @ present in r2p1
- teqne r6, #0x22 @ present in r2p2
- mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
- orreq r10, r10, #1 << 12 @ set bit #12
- orreq r10, r10, #1 << 22 @ set bit #22
- mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
-#endif
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 @ only present in r2p*
- mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
- orreq r10, r10, #1 << 6 @ set bit #6
- mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
-#endif
-#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
- cmp r6, #0x30 @ present prior to r3p0
- mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
- orrlt r10, r10, #1 << 11 @ set bit #11
- mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
-#endif
- b proc_specific_setup_done
-arm_cortex_a9_skip:
-
- /* Cortex-A15 Errata */
- ldr r10, =0x00000c0f @ Cortex-A15 primary part number
- teq r0, r10
- bne arm_cortex_a15_skip
-#ifdef CONFIG_SMP
- mov r10, #0
- mrc p15, 0, r0, c1, c0, 1
- tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
- orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
- orreq r0, r0, r10 @ Enable CPU-specific SMP bits
- mcreq p15, 0, r0, c1, c0, 1
-#endif
-#ifdef CONFIG_ARM_ERRATA_773022
- cmp r6, #0x4 @ only present up to r0p4
- mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
- orrle r10, r10, #1 << 1 @ disable loop buffer
- mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
-#endif
-arm_cortex_a15_skip:
-
-arm_proc_setup_skip:
-
-proc_specific_setup_done:
- mov r10, #0
- mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
- dsb
-
- adr r5, v7_crval
- ldmia r5, {r5, r6}
-#ifdef CONFIG_SWP_EMULATE
- orr r5, r5, #(1 << 10) @ set SW bit in "clear"
- bic r6, r6, #(1 << 10) @ clear it in "mmuset"
-#endif
- mrc p15, 0, r0, c1, c0, 0 @ read control register
- bic r0, r0, r5 @ clear bits them
- orr r0, r0, r6 @ set them
- mov pc, lr
-
- /* AT
- * TFR EV X F I D LR S
- * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
- * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
- * 0 0 110 0001 1100 .111 1101 < we want
- */
- .align 2
- .type v7_crval, #object
-v7_crval:
- .word 0x0120c302 /* clear */
- .word 0x00c01c7d /* mmuset */
-
-#ifdef CONFIG_SMP
- /*
- * Retrive SMP ID of current processor
- */
- .globl arch_smp_id
-arch_smp_id:
- mrc p15, 0, r0, c13, c0, 4
- bx lr
-
- /*
- * Setup SMP ID of current processor
- */
- .globl proc_setup_smp_id
-proc_setup_smp_id:
- /* Ensure that next SMP ID in r0
- * is less than CONFIG_CPU_COUNT
- */
- ldr r1, =CONFIG_CPU_COUNT
- cmp r0, r1
- blt proc_setup_smp_id_done
- b .
-
-proc_setup_smp_id_done:
- mcr p15, 0, r0, c13, c0, 4
- bx lr
-#endif
diff --git a/arch/arm/cpu/arm32/cpu_stacktrace.c b/arch/arm/cpu/arm32/cpu_stacktrace.c
deleted file mode 100644
index 5ab9f25c..00000000
--- a/arch/arm/cpu/arm32/cpu_stacktrace.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- * Copyright (c) 2012 Sukanto Ghosh.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_stacktrace.c
- * @author Sukanto Ghosh (sukant...@gmail.com)
- * @brief ARM32VE specific function stacktrace.
- *
- * Portions of this file are derived from arch/arm/kernel/stacktrace.c
- * in linux source
- *
- */
-
-#include <vmm_compiler.h>
-#include <vmm_stdio.h>
-#include <vmm_error.h>
-#include <libs/kallsyms.h>
-#include <libs/stacktrace.h>
-
-struct stackframe {
- unsigned long fp;
- unsigned long sp;
- unsigned long lr;
- unsigned long pc;
-};
-
-#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
-/*
- * Unwind the current stack frame and store the new register values in the
- * structure passed as argument. Unwinding is equivalent to a function return,
- * hence the new PC value rather than LR should be used for backtrace.
- *
- * With framepointer enabled, a simple function prologue looks like this:
- * mov ip, sp
- * stmdb sp!, {fp, ip, lr, pc}
- * sub fp, ip, #4
- *
- * A simple function epilogue looks like this:
- * ldm sp, {fp, sp, pc}
- *
- * Note that with framepointer enabled, even the leaf functions have the same
- * prologue and epilogue, therefore we can ignore the LR value in this case.
- */
-int unwind_frame(struct stackframe *frame)
-{
- unsigned long high, low;
- unsigned long fp = frame->fp;
-
- /* only go to a higher address on the stack */
- low = frame->sp;
- high = ALIGN(low, 4096);
-
- /* check current frame pointer is within bounds */
- if (fp < (low + 12) || fp + 4 >= high)
- return VMM_EFAIL;
-
- /* restore the registers from the stack frame */
- frame->fp = *(unsigned long *)(fp - 12);
- frame->sp = *(unsigned long *)(fp - 8);
- frame->pc = *(unsigned long *)(fp - 4);
-
- return 0;
-}
-
-void walk_stackframe(struct stackframe *frame,
- int (*fn)(struct stackframe *, void *), void *data)
-{
- while (1) {
- int ret;
-
- if (fn(frame, data))
- break;
- ret = unwind_frame(frame);
- if (ret < 0)
- break;
- }
-}
-
-struct stack_trace_data {
- struct stack_trace *trace;
- unsigned int skip;
-};
-
-static int save_trace(struct stackframe *frame, void *d)
-{
- struct stack_trace_data *data = d;
- struct stack_trace *trace = data->trace;
- unsigned long addr = frame->pc;
-
- if (data->skip) {
- data->skip--;
- return 0;
- }
-
- trace->entries[trace->nr_entries++] = addr;
-
- return trace->nr_entries >= trace->max_entries;
-}
-
-void arch_save_stacktrace(struct stack_trace *trace)
-{
- struct stack_trace_data data;
- struct stackframe frame;
-
- data.trace = trace;
- data.skip = trace->skip;
-
- register unsigned long current_sp asm ("sp");
-
- frame.fp = (unsigned long)__builtin_frame_address(0);
- frame.sp = current_sp;
- frame.lr = (unsigned long)__builtin_return_address(0);
- frame.pc = (unsigned long)arch_save_stacktrace;
-
- walk_stackframe(&frame, save_trace, &data);
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_coproc.c b/arch/arm/cpu/arm32/cpu_vcpu_coproc.c
deleted file mode 100644
index e525a0cb..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_coproc.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_coproc.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source file for coprocessor access
- */
-
-#include <cpu_defines.h>
-#include <cpu_vcpu_vfp.h>
-#include <cpu_vcpu_cp14.h>
-#include <cpu_vcpu_cp15.h>
-#include <cpu_vcpu_coproc.h>
-
-static bool cpu_vcpu_cpx_ldcstc_accept_nop(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 D, u32 CRd,
- u32 uopt, u32 imm8)
-{
- return TRUE;
-}
-
-static bool cpu_vcpu_cpx_ldcstc_done_nop(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8)
-{
- return TRUE;
-}
-
-static u32 cpu_vcpu_cpx_ldcstc_read_zero(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8)
-{
- return 0;
-}
-
-static void cpu_vcpu_cpx_ldcstc_ignore_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8, u32 data)
-{
-}
-
-static bool cpu_vcpu_cpx_read2_zero(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 CRm,
- u32 *data, u32 *data2)
-{
- *data = 0x0;
- *data2 = 0x0;
-
- return TRUE;
-}
-
-static bool cpu_vcpu_cpx_ignore_write2(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 CRm,
- u32 data, u32 data2)
-{
- return TRUE;
-}
-
-static bool cpu_vcpu_cpx_data_process_nop(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2,
- u32 CRd, u32 CRn, u32 CRm)
-{
- return TRUE;
-}
-
-static struct cpu_vcpu_coproc cp_array[CPU_COPROC_COUNT] =
-{
- {
- .cpnum = 0,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 1,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 2,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 3,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 4,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 5,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 6,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 7,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 8,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 9,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 10,
- .ldcstc_accept = cpu_vcpu_cpx_ldcstc_accept_nop,
- .ldcstc_done = cpu_vcpu_cpx_ldcstc_done_nop,
- .ldcstc_read = cpu_vcpu_cpx_ldcstc_read_zero,
- .ldcstc_write = cpu_vcpu_cpx_ldcstc_ignore_write,
- .write2 = cpu_vcpu_cpx_ignore_write2,
- .read2 = cpu_vcpu_cpx_read2_zero,
- .data_process = cpu_vcpu_cpx_data_process_nop,
- .write = &cpu_vcpu_cp10_write,
- .read = &cpu_vcpu_cp10_read,
- },
- {
- .cpnum = 11,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 12,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 13,
- .ldcstc_accept = NULL,
- .ldcstc_done = NULL,
- .ldcstc_read = NULL,
- .ldcstc_write = NULL,
- .write2 = NULL,
- .read2 = NULL,
- .data_process = NULL,
- .write = NULL,
- .read = NULL,
- },
- {
- .cpnum = 14,
- .ldcstc_accept = cpu_vcpu_cpx_ldcstc_accept_nop,
- .ldcstc_done = cpu_vcpu_cpx_ldcstc_done_nop,
- .ldcstc_read = cpu_vcpu_cpx_ldcstc_read_zero,
- .ldcstc_write = cpu_vcpu_cpx_ldcstc_ignore_write,
- .write2 = cpu_vcpu_cpx_ignore_write2,
- .read2 = cpu_vcpu_cpx_read2_zero,
- .data_process = cpu_vcpu_cpx_data_process_nop,
- .write = &cpu_vcpu_cp14_write,
- .read = &cpu_vcpu_cp14_read,
- },
- {
- .cpnum = 15,
- .ldcstc_accept = cpu_vcpu_cpx_ldcstc_accept_nop,
- .ldcstc_done = cpu_vcpu_cpx_ldcstc_done_nop,
- .ldcstc_read = cpu_vcpu_cpx_ldcstc_read_zero,
- .ldcstc_write = cpu_vcpu_cpx_ldcstc_ignore_write,
- .write2 = cpu_vcpu_cpx_ignore_write2,
- .read2 = cpu_vcpu_cpx_read2_zero,
- .data_process = cpu_vcpu_cpx_data_process_nop,
- .write = &cpu_vcpu_cp15_write,
- .read = &cpu_vcpu_cp15_read,
- },
-};
-
-struct cpu_vcpu_coproc *cpu_vcpu_coproc_get(u32 cpnum)
-{
- if (cpnum < CPU_COPROC_COUNT) {
- return &cp_array[cpnum];
- }
- return NULL;
-}
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_cp14.c b/arch/arm/cpu/arm32/cpu_vcpu_cp14.c
deleted file mode 100644
index 52c3b8ac..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_cp14.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
- * Copyright (c) 2013 Sting Cheng.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_cp14.c
- * @author Sting Cheng (sting...@gmail.com)
- * @author Anup Patel (an...@brainfault.org)
- * @brief Source file for VCPU cp14 (Debug, Trace, and ThumbEE) emulation
- */
-
-#include <vmm_error.h>
-#include <vmm_stdio.h>
-#include <arch_regs.h>
-#include <cpu_inline_asm.h>
-#include <cpu_vcpu_cp14.h>
-
-#include <arm_features.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DPRINTF(msg...) vmm_printf(msg)
-#else
-#define DPRINTF(msg...)
-#endif
-
-bool cpu_vcpu_cp14_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data)
-{
- struct arm_priv_cp14 *cp14 = &arm_priv(vcpu)->cp14;
-
- switch (opc1) {
- case 6: /* ThumbEE registers. */
- if (!arm_feature(vcpu, ARM_FEATURE_THUMB2EE))
- goto bad_reg;
- switch (CRn) {
- case 0: /* TEECR */
- if ((CRm == 0) && (opc2 == 0)) {
- cp14->teecr = read_teecr();
- *data = cp14->teecr;
- } else {
- goto bad_reg;
- }
- DPRINTF("%s: TEECR: vcpu=%s data=0x%08x\n",
- __func__, vcpu->name, *data);
- break;
- case 1: /* TEEHBR */
- if ((CRm == 0) && (opc2 == 0)) {
- cp14->teehbr = read_teehbr();
- *data = cp14->teehbr;
- } else {
- goto bad_reg;
- }
- DPRINTF("%s: TEEHBR: vcpu=%s data=0x%08x\n",
- __func__, vcpu->name, *data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 0: /* Debug registers */
- if ((1 == CRn) && (4 == opc2)) {
- if (1 == CRm) {
- /* DBGOSLSR: No debug support */
- *data = 0;
- break;
- } else {
- /* DBGPRSR, Device Powerdown and Reset Status Register */
- *data = 0;
- break;
- }
- }
- vmm_printf("%s: Debug not supported yet!\n", __func__);
- goto bad_reg;
- case 1: /* Trace registers. */
- vmm_printf("%s: Trace not supported yet!\n", __func__);
- goto bad_reg;
- case 7: /* Jazelle registers. */
- vmm_printf("%s: Jazelle not supported yet!\n", __func__);
- goto bad_reg;
- default:
- goto bad_reg;
- }
-
- return TRUE;
-
-bad_reg:
- vmm_printf("%s: vcpu=%s opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->name, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-bool cpu_vcpu_cp14_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data)
-{
- struct arm_priv_cp14 *cp14 = &arm_priv(vcpu)->cp14;
-
- switch (opc1) {
- case 6: /* ThumbEE registers. */
- if (!arm_feature(vcpu, ARM_FEATURE_THUMB2EE))
- goto bad_reg;
- switch (CRn) {
- case 0: /* TEECR */
- DPRINTF("%s: TEECR: vcpu=%s data=0x%08x\n",
- __func__, vcpu->name, data);
- if ((CRm == 0) && (opc2 == 0)) {
- write_teecr(data);
- cp14->teecr = data;
- } else {
- goto bad_reg;
- }
- break;
- case 1: /* TEEHBR */
- DPRINTF("%s: TEEHBR: vcpu=%s data=0x%08x\n",
- __func__, vcpu->name, data);
- if ((CRm == 0) && (opc2 == 0)) {
- write_teehbr(data);
- cp14->teehbr = data;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- case 0: /* Debug registers */
- if (0 == CRn) {
- if ((0 == opc2) && (7 == CRm)) {
- /* DBGVCR, Vector Catch Register */
- break;
- } else if (7 == opc2) {
- /* DBGBCR, Watchpoint Control Registers */
- /* CRm: C0-15 */
- break;
- } else if (6 == opc2) {
- /* DBGBVR, Watchpoint Value Registers */
- /* CRm: C0-15 */
- break;
- } else if (5 == opc2) {
- /* DBGBCR, Breakpoint Control Registers */
- /* CRm: C0-15 */
- break;
- } else if (4 == opc2) {
- /* DBGBVR, Breakpoint Value Registers */
- /* CRm: C0-15 */
- break;
- } else if ((2 == opc2) && (2 == CRm)) {
- /* DBGDSCR, Debug Status and Control Register */
- break;
- }
- }
- vmm_printf("%s: Debug not supported yet!\n", __func__);
- goto bad_reg;
- case 1: /* Trace registers. */
- vmm_printf("%s: Trace not supported yet!\n", __func__);
- goto bad_reg;
- case 7: /* Jazelle registers. */
- vmm_printf("%s: Jazelle not supported yet!\n", __func__);
- goto bad_reg;
- default:
- goto bad_reg;
- }
-
- return TRUE;
-
-bad_reg:
- vmm_printf("%s: vcpu=%s opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->name, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-void cpu_vcpu_cp14_regs_save(struct vmm_vcpu *vcpu)
-{
- /* All CP14 register access by VCPU always trap hence,
- * we always have updated copy of CP14 registers.
- */
-}
-
-void cpu_vcpu_cp14_regs_restore(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_cp14 *cp14 = &arm_priv(vcpu)->cp14;
-
- /* Do nothing if:
- * 1. Host HW does not have ThumbEE feature
- */
- if (!cpu_supports_thumbee()) {
- return;
- }
-
- /* Restore ThumbEE registers */
- write_teecr(cp14->teecr);
- write_teehbr(cp14->teehbr);
-}
-
-void cpu_vcpu_cp14_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu)
-{
- struct arm_priv_cp14 *cp14 = &arm_priv(vcpu)->cp14;
-
- /* Do nothing if:
- * 1. VCPU does not have ThumbEE feature
- */
- if (!arm_feature(vcpu, ARM_FEATURE_THUMB2EE)) {
- return;
- }
-
- vmm_cprintf(cdev, "CP14 ThumbEE Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x\n",
- "TEECR", cp14->teecr,
- "TEEHBR", cp14->teehbr);
-}
-
-int cpu_vcpu_cp14_init(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_cp14 *cp14 = &arm_priv(vcpu)->cp14;
-
- /* Clear all CP14 registers */
- memset(cp14, 0, sizeof(*cp14));
-
- /* If host HW does not have ThumbEE then clear all
- * ThumbEE feature flag so that VCPU always gets
- * undefined exception when accessing ThumbEE registers.
- */
- if (!cpu_supports_thumbee()) {
- arm_clear_feature(vcpu, ARM_FEATURE_THUMB2EE);
- }
-
- return VMM_OK;
-}
-
-int cpu_vcpu_cp14_deinit(struct vmm_vcpu *vcpu)
-{
- /* For now nothing to do here. */
- return VMM_OK;
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_cp15.c b/arch/arm/cpu/arm32/cpu_vcpu_cp15.c
deleted file mode 100644
index d57ee291..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_cp15.c
+++ /dev/null
@@ -1,2589 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_cp15.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief VCPU CP15 Emulation
- * @details This source file implements CP15 coprocessor for each VCPU.
- *
- * The Translation table walk and CP15 register read/write has been
- * largely adapted from QEMU 0.14.xx targe-arm/helper.c source file
- * which is licensed under GPL.
- */
-
-#include <vmm_error.h>
-#include <vmm_heap.h>
-#include <vmm_stdio.h>
-#include <vmm_scheduler.h>
-#include <vmm_host_vapool.h>
-#include <vmm_guest_aspace.h>
-#include <vmm_vcpu_irq.h>
-#include <arch_barrier.h>
-#include <libs/stringlib.h>
-#include <cpu_mmu.h>
-#include <cpu_cache.h>
-#include <cpu_inline_asm.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_vcpu_cp15.h>
-
-#include <arm_features.h>
-#include <emulate_arm.h>
-#include <emulate_thumb.h>
-
-static u32 __zone_start[] = {
- 0,
- CPU_VCPU_VTLB_ZONE_V_LEN,
- CPU_VCPU_VTLB_ZONE_V_LEN + \
- CPU_VCPU_VTLB_ZONE_HVEC_LEN,
- CPU_VCPU_VTLB_ZONE_V_LEN + \
- CPU_VCPU_VTLB_ZONE_HVEC_LEN + \
- CPU_VCPU_VTLB_ZONE_LVEC_LEN,
- CPU_VCPU_VTLB_ZONE_V_LEN + \
- CPU_VCPU_VTLB_ZONE_HVEC_LEN + \
- CPU_VCPU_VTLB_ZONE_LVEC_LEN + \
- CPU_VCPU_VTLB_ZONE_G_LEN,
-};
-
-static u32 __zone_len[] = {
- CPU_VCPU_VTLB_ZONE_V_LEN,
- CPU_VCPU_VTLB_ZONE_HVEC_LEN,
- CPU_VCPU_VTLB_ZONE_LVEC_LEN,
- CPU_VCPU_VTLB_ZONE_G_LEN,
- CPU_VCPU_VTLB_ZONE_NG_LEN
-};
-
-#define CPU_VCPU_VTLB_ZONE_START(x) __zone_start[(x)]
-#define CPU_VCPU_VTLB_ZONE_LEN(x) __zone_len[(x)]
-
-/* Update Virtual TLB */
-static int cpu_vcpu_cp15_vtlb_update(struct arm_priv_cp15 *cp15,
- struct cpu_page *p,
- u32 domain,
- bool is_virtual)
-{
- int rc;
- u32 entry, victim, zone;
- struct arm_vtlb_entry *e = NULL;
-
- /* Find appropriate zone */
- if (p->ng) {
- zone = CPU_VCPU_VTLB_ZONE_NG;
- } else {
- if (is_virtual) {
- zone = CPU_VCPU_VTLB_ZONE_V;
- } else if ((CPU_IRQ_HIGHVEC_BASE <= p->va) &&
- (p->va < (CPU_IRQ_HIGHVEC_BASE + 0x10000))) {
- zone = CPU_VCPU_VTLB_ZONE_HVEC;
- } else if ((CPU_IRQ_LOWVEC_BASE <= p->va) &&
- (p->va < (CPU_IRQ_LOWVEC_BASE + 0x10000))) {
- zone = CPU_VCPU_VTLB_ZONE_LVEC;
- } else {
- zone = CPU_VCPU_VTLB_ZONE_G;
- }
- }
-
- /* Find out next victim entry from TLB */
- victim = cp15->vtlb.victim[zone];
- entry = victim + CPU_VCPU_VTLB_ZONE_START(zone);
- e = &cp15->vtlb.table[entry];
- if (e->l2) {
- /* Remove valid victim page from L2 Page Table */
- rc = cpu_mmu_unmap_l2tbl_page(e->l2, e->pva, e->psz, TRUE);
- if (rc) {
- return rc;
- }
- e->dom = 0;
- e->l2 = NULL;
- }
-
- /* Save original domain */
- e->dom = domain;
-
- /* Ensure pages for normal vcpu are non-global */
- p->ng = 1;
-
- /* Ensure non-shareable pages for normal vcpu
- * when running on UP host. This will force usage
- * of local monitors in case of UP host.
- */
- if (vmm_num_online_cpus() == 1) {
- p->s = 0;
- }
-
- /* Add victim page to L1 page table */
- if ((rc = cpu_mmu_map_page(cp15->l1, p))) {
- return rc;
- }
-
- /* Save page address and page size */
- e->pva = p->va;
- e->psz = p->sz;
-
- /* Get the L2 table pointer
- * Note: VTLB entry with non-NULL L2 table pointer is valid
- */
- if ((rc = cpu_mmu_get_l2tbl(cp15->l1, p->va, &e->l2))) {
- return rc;
- }
-
- /* Point to next victim of TLB line */
- victim = victim + 1;
- if (CPU_VCPU_VTLB_ZONE_LEN(zone) <= victim) {
- victim = 0;
- }
- cp15->vtlb.victim[zone] = victim;
-
- return VMM_OK;
-}
-
-int cpu_vcpu_cp15_vtlb_flush(struct arm_priv_cp15 *cp15)
-{
- int rc;
- register u32 vtlb, zone;
- register struct arm_vtlb_entry *e;
-
- for (vtlb = 0; vtlb < CPU_VCPU_VTLB_ENTRY_COUNT; vtlb++) {
- if (!cp15->vtlb.table[vtlb].l2) {
- continue;
- }
-
- e = &cp15->vtlb.table[vtlb];
- rc = cpu_mmu_unmap_l2tbl_page(e->l2, e->pva, e->psz, FALSE);
- if (rc) {
- return rc;
- }
- e->dom = 0;
- e->l2 = NULL;
- }
-
- for (zone = 0; zone < CPU_VCPU_VTLB_ZONE_COUNT; zone++) {
- cp15->vtlb.victim[zone] = 0;
- }
-
- return cpu_mmu_sync_ttbr(cp15->l1);
-}
-
-
-int cpu_vcpu_cp15_vtlb_flush_va(struct arm_priv_cp15 *cp15,
- virtual_addr_t va)
-{
- int rc;
- register u32 vtlb;
- register struct arm_vtlb_entry *e;
-
- for (vtlb = 0; vtlb < CPU_VCPU_VTLB_ENTRY_COUNT; vtlb++) {
- e = &cp15->vtlb.table[vtlb];
- if (!e->l2) {
- continue;
- }
-
- if ((e->pva <= va) && (va < (e->pva + e->psz))) {
- rc = cpu_mmu_unmap_l2tbl_page(e->l2,
- e->pva, e->psz, FALSE);
- if (rc) {
- return rc;
- }
- e->dom = 0;
- e->l2 = NULL;
- break;
- }
- }
-
- return cpu_mmu_sync_ttbr_va(cp15->l1, va);
-}
-
-int cpu_vcpu_cp15_vtlb_flush_ng_va(struct arm_priv_cp15 *cp15,
- virtual_addr_t va)
-{
- int rc;
- register u32 vtlb, vtlb_last;
- register struct arm_vtlb_entry *e;
-
- vtlb = CPU_VCPU_VTLB_ZONE_START(CPU_VCPU_VTLB_ZONE_NG);
- vtlb_last = vtlb + CPU_VCPU_VTLB_ZONE_LEN(CPU_VCPU_VTLB_ZONE_NG);
- for (; vtlb < vtlb_last; vtlb++) {
- e = &cp15->vtlb.table[vtlb];
- if (!e->l2) {
- continue;
- }
-
- if ((e->pva <= va) && (va < (e->pva + e->psz))) {
- rc = cpu_mmu_unmap_l2tbl_page(e->l2,
- e->pva, e->psz,
- FALSE);
- if (rc) {
- return rc;
- }
- e->l2 = NULL;
- e->dom = 0;
- break;
- }
- }
-
- return cpu_mmu_sync_ttbr(cp15->l1);
-}
-
-int cpu_vcpu_cp15_vtlb_flush_ng(struct arm_priv_cp15 *cp15)
-{
- int rc;
- register u32 vtlb, vtlb_last;
- register struct arm_vtlb_entry *e;
-
- vtlb = CPU_VCPU_VTLB_ZONE_START(CPU_VCPU_VTLB_ZONE_NG);
- vtlb_last = vtlb + CPU_VCPU_VTLB_ZONE_LEN(CPU_VCPU_VTLB_ZONE_NG);
- for (; vtlb < vtlb_last; vtlb++) {
- e = &cp15->vtlb.table[vtlb];
- if (!e->l2) {
- continue;
- }
-
- rc = cpu_mmu_unmap_l2tbl_page(e->l2,
- e->pva, e->psz,
- FALSE);
- if (rc) {
- return rc;
- }
- e->l2 = NULL;
- e->dom = 0;
- }
-
- return cpu_mmu_sync_ttbr(cp15->l1);
-}
-
-int cpu_vcpu_cp15_vtlb_flush_domain(struct arm_priv_cp15 *cp15,
- u32 dacr_xor_diff)
-{
- int rc;
- register u32 vtlb;
- register struct arm_vtlb_entry *e;
-
- for (vtlb = 0; vtlb < CPU_VCPU_VTLB_ENTRY_COUNT; vtlb++) {
- e = &cp15->vtlb.table[vtlb];
- if (!e->l2) {
- continue;
- }
-
- if ((dacr_xor_diff >> ((e->dom & 0xF) << 1)) & 0x3) {
- rc = cpu_mmu_unmap_l2tbl_page(e->l2,
- e->pva, e->psz, FALSE);
- if (rc) {
- return rc;
- }
- e->dom = 0;
- e->l2 = NULL;
- }
- }
-
- return cpu_mmu_sync_ttbr(cp15->l1);
-}
-
-
-enum cpu_vcpu_cp15_access_permission {
- CP15_ACCESS_DENIED = 0,
- CP15_ACCESS_GRANTED = 1
-};
-
-/* Check section/page access permissions.
- * Returns 1 - permitted, 0 - not-permitted
- */
-static inline enum cpu_vcpu_cp15_access_permission check_ap(
- struct vmm_vcpu *vcpu,
- struct arm_priv_cp15 *cp15,
- int ap, int access_type, int is_user)
-{
- switch (ap) {
- case TTBL_AP_S_U:
- if (access_type == CP15_ACCESS_WRITE) {
- return CP15_ACCESS_DENIED;
- }
-
- switch (cp15->c1_sctlr & (SCTLR_R_MASK | SCTLR_S_MASK)) {
- case SCTLR_S_MASK:
- if (is_user) {
- return CP15_ACCESS_DENIED;
- }
-
- return CP15_ACCESS_GRANTED;
- break;
- case SCTLR_R_MASK:
- return CP15_ACCESS_GRANTED;
- break;
- default:
- return CP15_ACCESS_DENIED;
- break;
- }
- break;
- case TTBL_AP_SRW_U:
- if (is_user) {
- return CP15_ACCESS_DENIED;
- }
-
- return CP15_ACCESS_GRANTED;
- break;
- case TTBL_AP_SRW_UR:
- if (is_user) {
- return (access_type != CP15_ACCESS_WRITE) ?
- CP15_ACCESS_GRANTED : CP15_ACCESS_DENIED;
- }
-
- return CP15_ACCESS_GRANTED;
- break;
- case TTBL_AP_SRW_URW:
- return CP15_ACCESS_GRANTED;
- break;
- case TTBL_AP_SR_U:
- if (is_user) {
- return CP15_ACCESS_DENIED;
- }
-
- return (access_type != CP15_ACCESS_WRITE) ?
- CP15_ACCESS_GRANTED : CP15_ACCESS_DENIED;
- break;
- case TTBL_AP_SR_UR_DEPRECATED:
- return (access_type != CP15_ACCESS_WRITE) ?
- CP15_ACCESS_GRANTED : CP15_ACCESS_DENIED;
- break;
- case TTBL_AP_SR_UR:
- if (!arm_feature(vcpu, ARM_FEATURE_V6K)) {
- return CP15_ACCESS_DENIED;
- }
-
- return (access_type != CP15_ACCESS_WRITE) ?
- CP15_ACCESS_GRANTED : CP15_ACCESS_DENIED;
- break;
- default:
- return CP15_ACCESS_DENIED;
- break;
- };
-
- return CP15_ACCESS_DENIED;
-}
-
-#define get_level1_table_pa(cp15, va) \
- (((va) & (cp15)->c2_mask) ? \
- ((cp15)->c2_ttbr1 & 0xffffc000) : \
- ((cp15)->c2_ttbr0 & (cp15)->c2_base_mask))
-
-static int ttbl_walk_v6(struct vmm_vcpu *vcpu, virtual_addr_t va,
- int access_type, int is_user,
- struct cpu_page *pg, u32 *fs)
-{
- physical_addr_t table;
- int type, domain;
- u32 desc;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- pg->va = va;
-
- /* Pagetable walk. */
- /* Lookup l1 descriptor. */
- table = get_level1_table_pa(cp15, va);
-
- /* compute the L1 descriptor physical location */
- table |= (va >> 18) & 0x3ffc;
-
- /* FIXME: Should this be cacheable memory access ? */
- if (!vmm_guest_memory_read(vcpu->guest, table,
- &desc, sizeof(desc), TRUE)) {
- return VMM_EFAIL;
- }
-
- type = (desc & 3);
- if (type == 0) {
- /* Section translation fault. */
- *fs = 5;
- pg->dom = 0;
- goto do_fault;
- } else if (type == 2 && (desc & (1 << 18))) {
- /* Supersection. */
- pg->dom = 0;
- } else {
- /* Section or page. */
- pg->dom = (desc >> 5) & 0xF;
- }
-
- domain = (cp15->c3_dacr >> (pg->dom << 1)) & 3;
- if (domain == 0 || domain == 2) {
- /* Section / Page domain fault ?? */
- *fs = (type == 2) ? 9 : 11;
- goto do_fault;
- }
-
- if (type == 2) {
- if (desc & (1 << 18)) {
- /* Supersection. */
- pg->pa = (desc & 0xff000000) | (va & 0x00ffffff);
- pg->sz = 0x1000000;
- } else {
- /* Section. */
- pg->pa = (desc & 0xfff00000) | (va & 0x000fffff);
- pg->sz = 0x100000;
- }
- pg->ng = (desc >> 17) & 0x1;
- pg->s = (desc >> 16) & 0x1;
- pg->tex = (desc >> 12) & 0x7;
- pg->ap = ((desc >> 10) & 0x3) | ((desc >> 13) & 0x4);
- pg->xn = (desc >> 4) & 0x1;
- pg->c = (desc >> 3) & 0x1;
- pg->b = (desc >> 2) & 0x1;
- *fs = 13;
- } else {
- /* Lookup l2 entry. */
- table = (desc & 0xfffffc00);
- table |= ((va >> 10) & 0x3fc);
-
- /* FIXME: Should this be cacheable memory access ? */
- if (!vmm_guest_memory_read(vcpu->guest, table,
- &desc, sizeof(desc), TRUE)) {
- return VMM_EFAIL;
- }
-
- switch (desc & 3) {
- case 0: /* Page translation fault. */
- *fs = 7;
- goto do_fault;
- case 1: /* 64k page. */
- pg->pa = (desc & 0xffff0000) | (va & 0xffff);
- pg->sz = 0x10000;
- pg->xn = (desc >> 15) & 0x1;
- pg->tex = (desc >> 12) & 0x7;
- break;
- case 2:
- case 3: /* 4k page. */
- pg->pa = (desc & 0xfffff000) | (va & 0xfff);
- pg->sz = 0x1000;
- pg->tex = (desc >> 6) & 0x7;
- pg->xn = desc & 0x1;
- break;
- default:
- /* Never happens, but compiler isn't
- * smart enough to tell.
- */
- return VMM_EFAIL;
- }
- pg->ng = (desc >> 11) & 0x1;
- pg->s = (desc >> 10) & 0x1;
- pg->ap = ((desc >> 4) & 0x3) | ((desc >> 7) & 0x4);
- pg->c = (desc >> 3) & 0x1;
- pg->b = (desc >> 2) & 0x1;
- *fs = 15;
- }
-
- if (domain == 3) {
- /* Page permission not to be checked so,
- * give full access using access permissions.
- */
- pg->ap = TTBL_AP_SRW_URW;
- pg->xn = 0;
- } else {
- if (pg->xn && access_type == 2)
- goto do_fault;
- /* The simplified model uses AP[0] as an access control bit. */
- if ((cp15->c1_sctlr & (1 << 29))
- && (pg->ap & 1) == 0) {
- /* Access flag fault. */
- *fs = (*fs == 15) ? 6 : 3;
- goto do_fault;
- }
- if (check_ap(vcpu, cp15, pg->ap, access_type, is_user) ==
- CP15_ACCESS_DENIED) {
- /* Access permission fault. */
- goto do_fault;
- }
- }
-
- return VMM_OK;
-
- do_fault:
- return VMM_EFAIL;
-}
-
-static int ttbl_walk_v5(struct vmm_vcpu *vcpu, virtual_addr_t va,
- int access_type, int is_user,
- struct cpu_page *pg, u32 *fs)
-{
- physical_addr_t table;
- int type, domain;
- u32 desc;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- pg->va = va;
-
- /* Pagetable walk. */
- /* Lookup l1 descriptor. */
- table = get_level1_table_pa(cp15, va);
-
- /* compute the L1 descriptor physical location */
- table |= (va >> 18) & 0x3ffc;
-
- /* get it */
- /* FIXME: Should this be cacheable memory access ? */
- if (!vmm_guest_memory_read(vcpu->guest, table,
- &desc, sizeof(desc), TRUE)) {
- goto do_fault;
- }
-
- /* extract type */
- type = (desc & TTBL_L1TBL_TTE_TYPE_MASK);
-
- /* retreive domain info */
- pg->dom = (desc & TTBL_L1TBL_TTE_DOM_MASK) >>
- TTBL_L1TBL_TTE_DOM_SHIFT;
- domain = (cp15->c3_dacr >> (pg->dom << 1)) & 3;
-
- switch (type) {
- case TTBL_L1TBL_TTE_TYPE_SECTION: /* 1Mb section. */
- if (domain == 0 || domain == 2) {
- /* Section domain fault. */
- *fs = DFSR_FS_DOMAIN_FAULT_SECTION;
- goto do_fault;
- break;
- }
-
- /* compute physical address */
- pg->pa = (desc & ~TTBL_L1TBL_SECTION_PAGE_MASK) |
- (va & TTBL_L1TBL_SECTION_PAGE_MASK);
- /* extract access protection */
- pg->ap = (desc & TTBL_L1TBL_TTE_AP_MASK) >>
- TTBL_L1TBL_TTE_AP_SHIFT;
- /* Set Section size */
- pg->sz = TTBL_L1TBL_SECTION_PAGE_SIZE;
- pg->c = (desc & TTBL_L1TBL_TTE_C_MASK) >>
- TTBL_L1TBL_TTE_C_SHIFT;
- pg->b = (desc & TTBL_L1TBL_TTE_B_MASK) >>
- TTBL_L1TBL_TTE_B_SHIFT;
-
- *fs = DFSR_FS_PERM_FAULT_SECTION;
- break;
- case TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL: /* Coarse pagetable. */
- if (domain == 0 || domain == 2) {
- /* Page domain fault. */
- *fs = DFSR_FS_DOMAIN_FAULT_PAGE;
- goto do_fault;
- break;
- }
-
- /* compute L2 table physical address */
- table = desc & 0xfffffc00;
-
- /* compute L2 desc physical address */
- table |= ((va >> 10) & 0x3fc);
-
- /* get it */
- /* FIXME: Should this be cacheable memory access ? */
- if (!vmm_guest_memory_read(vcpu->guest, table,
- &desc, sizeof(desc), TRUE)) {
- goto do_fault;
- }
-
- switch (desc & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE: /* 64k page. */
- pg->pa = (desc & 0xffff0000) | (va & 0xffff);
- pg->ap = (desc >> (4 + ((va >> 13) & 6))) & 3;
- pg->sz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- *fs = DFSR_FS_PERM_FAULT_PAGE;
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL: /* 4k page. */
- pg->pa = (desc & 0xfffff000) | (va & 0xfff);
- pg->ap = (desc >> (4 + ((va >> 13) & 6))) & 3;
- pg->sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- *fs = DFSR_FS_PERM_FAULT_PAGE;
- break;
- case TTBL_L2TBL_TTE_TYPE_FAULT:
- default:
- /* Page translation fault. */
- *fs = DFSR_FS_TRANS_FAULT_PAGE;
- goto do_fault;
- break;
- }
-
- pg->c = (desc & TTBL_L2TBL_TTE_C_MASK) >>
- TTBL_L2TBL_TTE_C_SHIFT;
- pg->b = (desc & TTBL_L2TBL_TTE_B_MASK) >>
- TTBL_L2TBL_TTE_B_SHIFT;
-
- break;
- case TTBL_L1TBL_TTE_TYPE_FINE_L2TBL: /* Fine pagetable. */
- if (domain == 0 || domain == 2) {
- /* Page domain fault. */
- *fs = DFSR_FS_DOMAIN_FAULT_PAGE;
- goto do_fault;
- break;
- }
-
- table = (desc & 0xfffff000);
- table |= ((va >> 8) & 0xffc);
-
- /* FIXME: Should this be cacheable memory access ? */
- if (!vmm_guest_memory_read(vcpu->guest, table,
- &desc, sizeof(desc), TRUE)) {
- goto do_fault;
- }
-
- switch (desc & TTBL_L2TBL_TTE_TYPE_MASK) {
- case TTBL_L2TBL_TTE_TYPE_LARGE: /* 64k page. */
- pg->pa = (desc & 0xffff0000) | (va & 0xffff);
- pg->ap = (desc >> (4 + ((va >> 13) & 6))) & 3;
- pg->sz = TTBL_L2TBL_LARGE_PAGE_SIZE;
- *fs = DFSR_FS_PERM_FAULT_PAGE;
- break;
- case TTBL_L2TBL_TTE_TYPE_SMALL: /* 4k page. */
- pg->pa = (desc & 0xfffff000) | (va & 0xfff);
- pg->ap = (desc >> (4 + ((va >> 13) & 6))) & 3;
- pg->sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- *fs = DFSR_FS_PERM_FAULT_PAGE;
- break;
- case TTBL_L2TBL_TTE_TYPE_TINY: /* 1k page. */
- pg->pa = (desc & 0xfffffc00) | (va & 0x3ff);
- pg->ap = (desc >> 4) & 3;
- pg->sz = TTBL_L2TBL_TINY_PAGE_SIZE;
- *fs = DFSR_FS_PERM_FAULT_PAGE;
- break;
- case TTBL_L2TBL_TTE_TYPE_FAULT: /* Page translation fault. */
- default:
- *fs = DFSR_FS_TRANS_FAULT_PAGE;
- goto do_fault;
- break;
- }
-
- pg->c = (desc & TTBL_L2TBL_TTE_C_MASK) >>
- TTBL_L2TBL_TTE_C_SHIFT;
- pg->b = (desc & TTBL_L2TBL_TTE_B_MASK) >>
- TTBL_L2TBL_TTE_B_SHIFT;
-
- break;
- case TTBL_L1TBL_TTE_TYPE_FAULT:
- default:
- pg->dom = 0;
- /* Section translation fault. */
- *fs = DFSR_FS_TRANS_FAULT_SECTION;
- goto do_fault;
- break;
- }
-
- if (domain == 3) {
- /* Page permission not to be checked so,
- * give full access using access permissions.
- */
- pg->ap = TTBL_AP_SRW_URW;
- } else if (check_ap(vcpu, cp15, pg->ap, access_type, is_user) ==
- CP15_ACCESS_DENIED) {
- /* Access permission fault. */
- goto do_fault;
- }
-
- return VMM_OK;
-
- do_fault:
- return VMM_EFAIL;
-}
-
-u32 cpu_vcpu_cp15_find_page(struct vmm_vcpu *vcpu,
- virtual_addr_t va,
- int access_type,
- bool is_user, struct cpu_page *pg)
-{
- int rc = VMM_OK;
- u32 fs = 0x0;
- virtual_addr_t mva = va;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- /* Fast Context Switch Extension. */
- if (mva < 0x02000000) {
- mva += cp15->c13_fcse;
- }
-
- /* zeroize our page descriptor */
- memset(pg, 0, sizeof(*pg));
-
- /* Get the required page for vcpu */
- if (cp15->c1_sctlr & SCTLR_M_MASK) {
- /* MMU enabled for vcpu */
- if (cp15->c1_sctlr & SCTLR_V6_MASK) {
- rc = ttbl_walk_v6(vcpu, mva, access_type,
- is_user, pg, &fs);
- } else {
- rc = ttbl_walk_v5(vcpu, mva, access_type,
- is_user, pg, &fs);
- }
- if (rc) {
- /* FIXME: should be ORed with (pg->dom & 0xF) */
- return (fs << 4) |
- ((cp15->c3_dacr >> (pg->dom << 1)) & 0x3);
- }
- pg->va = va;
- } else {
- /* MMU disabled for vcpu */
- pg->pa = mva;
- pg->va = va;
- pg->sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- pg->ap = TTBL_AP_SRW_URW;
- pg->c = 1;
- pg->b = 0;
- }
-
- /* Ensure pages for normal vcpu have aligned va & pa */
- pg->pa &= ~(pg->sz - 1);
- pg->va &= ~(pg->sz - 1);
-
- return 0;
-}
-
-int cpu_vcpu_cp15_assert_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info)
-{
- u32 fsr;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- if (!(cp15->c1_sctlr & SCTLR_M_MASK)) {
- cpu_vcpu_halt(vcpu, info->regs);
- return VMM_EFAIL;
- }
-
- if (info->xn) {
- fsr = (info->fs & DFSR_FS_MASK);
- fsr |= ((info->dom << DFSR_DOM_SHIFT) & DFSR_DOM_MASK);
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- fsr |= ((info->fs >> 4) << DFSR_FS4_SHIFT);
- fsr |= ((info->wnr << DFSR_WNR_SHIFT) & DFSR_WNR_MASK);
- }
- cp15->c5_dfsr = fsr;
- cp15->c6_dfar = info->far;
- vmm_vcpu_irq_assert(vcpu, CPU_DATA_ABORT_IRQ, 0x0);
- } else {
- fsr = info->fs & IFSR_FS_MASK;
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- fsr |= ((info->fs >> 4) << IFSR_FS4_SHIFT);
- cp15->c6_ifar = info->far;
- }
- cp15->c5_ifsr = fsr;
- vmm_vcpu_irq_assert(vcpu, CPU_PREFETCH_ABORT_IRQ, 0x0);
- }
-
- return VMM_OK;
-}
-
-int cpu_vcpu_cp15_trans_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info,
- bool force_user)
-{
- u32 orig_domain, tre_index, tre_inner, tre_outer, tre_type;
- u32 ecode, reg_flags;
- bool is_user, is_virtual;
- int rc, access_type;
- struct cpu_page pg;
- physical_size_t availsz;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- /* If VCPU tried to access hypervisor space then
- * halt the VCPU very early.
- */
- if (vmm_host_vapool_isvalid(info->far)) {
- vmm_manager_vcpu_halt(vcpu);
- return VMM_EINVALID;
- }
-
- if (info->xn) {
- if (info->wnr) {
- access_type = CP15_ACCESS_WRITE;
- } else {
- access_type = CP15_ACCESS_READ;
- }
- } else {
- access_type = CP15_ACCESS_EXECUTE;
- }
-
- if (force_user) {
- is_user = TRUE;
- } else {
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- is_user = TRUE;
- } else {
- is_user = FALSE;
- }
- }
-
- if ((ecode = cpu_vcpu_cp15_find_page(vcpu, info->far,
- access_type, is_user, &pg))) {
- info->fs = (ecode >> 4);
- info->dom = (ecode & 0xF);
- return cpu_vcpu_cp15_assert_fault(vcpu, info);
- }
- if (pg.sz > TTBL_L2TBL_SMALL_PAGE_SIZE) {
- pg.sz = TTBL_L2TBL_SMALL_PAGE_SIZE;
- pg.pa = pg.pa + ((info->far & ~(pg.sz - 1)) - pg.va);
- pg.va = info->far & ~(pg.sz - 1);
- }
-
- if ((rc = vmm_guest_physical_map(vcpu->guest,
- pg.pa, pg.sz,
- &pg.pa, &availsz,
- &reg_flags))) {
- vmm_manager_vcpu_halt(vcpu);
- return rc;
- }
- if (availsz < TTBL_L2TBL_SMALL_PAGE_SIZE) {
- return rc;
- }
- orig_domain = pg.dom;
- pg.sz = cpu_mmu_best_page_size(pg.va, pg.pa, availsz);
- switch (pg.ap) {
- case TTBL_AP_S_U:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_USER;
- pg.ap = TTBL_AP_S_U;
- break;
- case TTBL_AP_SRW_U:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_SUPER;
- pg.ap = TTBL_AP_SRW_URW;
- break;
- case TTBL_AP_SRW_UR:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R;
- pg.ap = TTBL_AP_SRW_UR;
- break;
- case TTBL_AP_SRW_URW:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_USER;
- pg.ap = TTBL_AP_SRW_URW;
- break;
-#if !defined(CONFIG_ARMV5)
- case TTBL_AP_SR_U:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_SUPER;
- pg.ap = TTBL_AP_SRW_UR;
- break;
- case TTBL_AP_SR_UR_DEPRECATED:
- case TTBL_AP_SR_UR:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_USER;
- pg.ap = TTBL_AP_SRW_UR;
- break;
-#endif
- default:
- pg.dom = TTBL_L1TBL_TTE_DOM_VCPU_USER;
- pg.ap = TTBL_AP_S_U;
- break;
- };
- is_virtual = FALSE;
- if (reg_flags & VMM_REGION_VIRTUAL) {
- is_virtual = TRUE;
- switch (pg.ap) {
- case TTBL_AP_SRW_U:
- pg.ap = TTBL_AP_S_U;
- break;
- case TTBL_AP_SRW_UR:
-#if !defined(CONFIG_ARMV5)
- pg.ap = TTBL_AP_SR_U;
-#else
- /* FIXME: I am not sure this is right */
- pg.ap = TTBL_AP_SRW_U;
-#endif
- break;
- case TTBL_AP_SRW_URW:
- pg.ap = TTBL_AP_SRW_U;
- break;
- default:
- break;
- }
- } else if (reg_flags & VMM_REGION_READONLY) {
- switch (pg.ap) {
- case TTBL_AP_SRW_URW:
- pg.ap = TTBL_AP_SRW_UR;
- break;
- default:
- break;
- }
- }
-
- if (arm_feature(vcpu, ARM_FEATURE_V6K) &&
- (cp15->c1_sctlr & SCTLR_TRE_MASK)) {
- tre_index = ((pg.tex & 0x1) << 2) |
- ((pg.c & 0x1) << 1) |
- (pg.b & 0x1);
- tre_inner = cp15->c10_nmrr >> (tre_index * 2);
- tre_inner &= 0x3;
- tre_outer = cp15->c10_nmrr >> (tre_index * 2);
- tre_outer = (tre_outer >> 16) & 0x3;
- tre_type = cp15->c10_prrr >> (tre_index * 2);
- tre_type &= 0x3;
- switch (tre_type) {
- case 0: /* Strongly-Ordered Memory */
- pg.c = 0;
- pg.b = 0;
- pg.tex = 0;
- pg.s = 1;
- break;
- case 1: /* Device Memory */
- pg.c = (tre_inner & 0x2) >> 1;
- pg.b = (tre_inner & 0x1);
- pg.tex = 0x4 | tre_outer;
- pg.s = cp15->c10_prrr >> (16 + pg.s);
- break;
- case 2: /* Normal Memory */
- pg.c = (tre_inner & 0x2) >> 1;
- pg.b = (tre_inner & 0x1);
- pg.tex = 0x4 | tre_outer;
- pg.s = cp15->c10_prrr >> (18 + pg.s);
- break;
- case 3:
- default:
- pg.c = 0;
- pg.b = 0;
- pg.tex = 0;
- pg.s = 0;
- break;
- };
- }
-
- if (pg.tex & 0x4) {
- if (reg_flags & VMM_REGION_CACHEABLE) {
- if (!(reg_flags & VMM_REGION_BUFFERABLE)) {
- if ((pg.c == 0 && pg.b == 1) ||
- (pg.c == 1 && pg.b == 1)) {
- pg.c = 1;
- pg.b = 0;
- }
- if (((pg.tex & 0x3) == 0x1) ||
- ((pg.tex & 0x3) == 0x3)) {
- pg.tex = 0x6;
- }
- }
- } else {
- pg.c = 0;
- pg.b = 0;
- pg.tex = 0x4;
- }
- } else {
- pg.c = pg.c && (reg_flags & VMM_REGION_CACHEABLE);
- pg.b = pg.b && (reg_flags & VMM_REGION_BUFFERABLE);
- }
-
- return cpu_vcpu_cp15_vtlb_update(cp15, &pg, orig_domain, is_virtual);
-}
-
-int cpu_vcpu_cp15_access_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info)
-{
- /* If VCPU tried to access hypervisor space then
- * halt the VCPU very early.
- */
- if (vmm_host_vapool_isvalid(info->far)) {
- vmm_manager_vcpu_halt(vcpu);
- return VMM_EINVALID;
- }
-
- /* We don't do anything about access fault */
- /* Assert fault to vcpu */
- return cpu_vcpu_cp15_assert_fault(vcpu, info);
-}
-
-int cpu_vcpu_cp15_domain_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info)
-{
- int rc = VMM_OK;
- struct cpu_page pg;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- /* If VCPU tried to access hypervisor space then
- * halt the VCPU very early.
- */
- if (vmm_host_vapool_isvalid(info->far)) {
- vmm_manager_vcpu_halt(vcpu);
- return VMM_EINVALID;
- }
-
- /* Try to retrieve the faulting page */
- if ((rc = cpu_mmu_get_page(cp15->l1, info->far, &pg))) {
- /* Remove fault address from VTLB */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, info->far);
-
- /* Force TTBL walk If MMU is enabled so that
- * appropriate fault will be generated.
- */
- rc = cpu_vcpu_cp15_trans_fault(vcpu, info, FALSE);
- if (rc) {
- return rc;
- }
-
- /* Try again to retrieve the faulting page */
- rc = cpu_mmu_get_page(cp15->l1, info->far, &pg);
- if (rc == VMM_ENOTAVAIL) {
- return VMM_OK;
- } else if (rc) {
- return rc;
- }
- }
-
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- /* Remove fault address from VTLB */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, info->far);
-
- /* Force TTBL walk If MMU is enabled so that
- * appropriate fault will be generated.
- */
- rc = cpu_vcpu_cp15_trans_fault(vcpu, info, FALSE);
- if (rc) {
- return rc;
- }
- } else {
- cpu_vcpu_halt(vcpu, info->regs);
- rc = VMM_EFAIL;
- }
-
- return rc;
-}
-
-int cpu_vcpu_cp15_perm_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info)
-{
- int rc = VMM_OK;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
- struct cpu_page *pg = &cp15->virtio_page;
-
- /* If VCPU tried to access hypervisor space then
- * halt the VCPU very early.
- */
- if (vmm_host_vapool_isvalid(info->far)) {
- vmm_manager_vcpu_halt(vcpu);
- return VMM_EINVALID;
- }
-
- /* Try to retrieve the faulting page */
- if ((rc = cpu_mmu_get_page(cp15->l1, info->far, pg))) {
- /* Remove fault address from VTLB */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, info->far);
-
- /* Force TTBL walk If MMU is enabled so that
- * appropriate fault will be generated.
- */
- rc = cpu_vcpu_cp15_trans_fault(vcpu, info, FALSE);
- if (rc) {
- return rc;
- }
-
- /* Try again to retrieve the faulting page */
- rc = cpu_mmu_get_page(cp15->l1, info->far, pg);
- if (rc == VMM_ENOTAVAIL) {
- return VMM_OK;
- } else if (rc) {
- return rc;
- }
- }
-
- /* Check if vcpu was trying read/write to virtual space */
- if (info->xn &&
- ((pg->ap == TTBL_AP_SRW_U) || (pg->ap == TTBL_AP_SR_U))) {
- /* Emulate load/store instructions */
- cp15->virtio_active = TRUE;
- if (info->regs->cpsr & CPSR_THUMB_ENABLED) {
- rc = emulate_thumb_inst(vcpu, info->regs,
- *((u32 *)info->regs->pc));
- } else {
- rc = emulate_arm_inst(vcpu, info->regs,
- *((u32 *)info->regs->pc));
- }
- cp15->virtio_active = FALSE;
- return rc;
- }
-
- /* Remove fault address from VTLB */
- return cpu_vcpu_cp15_vtlb_flush_va(cp15, info->far);
-}
-
-bool cpu_vcpu_cp15_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm, u32 *data)
-{
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- switch (CRn) {
- case 0: /* ID codes. */
- switch (opc1) {
- case 0:
- switch (CRm) {
- case 0:
- switch (opc2) {
- case 0: /* Device ID. */
- *data = cp15->c0_midr;
- break;
- case 1: /* Cache Type. */
- *data = cp15->c0_cachetype;
- break;
- case 2: /* TCM status. */
- *data = 0;
- break;
- case 3: /* TLB type register. */
- *data = 0; /* No lockable entries. */
- break;
- case 5: /* MPIDR */
- /* The MPIDR was standardised in v7;
- * prior to this it was implemented
- * only in the 11MPCore.
- *
- * For all other pre-v7 cores
- * it does not exist.
- */
- if (!arm_feature(vcpu, ARM_FEATURE_MPIDR)) {
- goto bad_reg;
- }
- *data = cp15->c0_mpidr;
- break;
- default:
- goto bad_reg;
- }
- break;
- case 1:
- if (!arm_feature(vcpu, ARM_FEATURE_V6))
- goto bad_reg;
- switch (opc2) {
- case 0:
- *data = cp15->c0_pfr0;
- break;
- case 1:
- *data = cp15->c0_pfr1;
- break;
- case 2:
- *data = cp15->c0_dfr0;
- break;
- case 3:
- *data = cp15->c0_afr0;
- break;
- case 4:
- *data = cp15->c0_mmfr0;
- break;
- case 5:
- *data = cp15->c0_mmfr1;
- break;
- case 6:
- *data = cp15->c0_mmfr2;
- break;
- case 7:
- *data = cp15->c0_mmfr3;
- break;
- default:
- *data = 0;
- break;
- };
- break;
- case 2:
- if (!arm_feature(vcpu, ARM_FEATURE_V6))
- goto bad_reg;
- switch (opc2) {
- case 0:
- *data = cp15->c0_isar0;
- break;
- case 1:
- *data = cp15->c0_isar1;
- break;
- case 2:
- *data = cp15->c0_isar2;
- break;
- case 3:
- *data = cp15->c0_isar3;
- break;
- case 4:
- *data = cp15->c0_isar4;
- break;
- case 5:
- *data = cp15->c0_isar5;
- break;
- default:
- *data = 0;
- break;
- };
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- *data = 0;
- break;
- default:
- goto bad_reg;
- }
- break;
- case 1:
- /* These registers aren't documented on arm11 cores.
- * However Linux looks at them anyway.
- */
- if (!arm_feature(vcpu, ARM_FEATURE_V6))
- goto bad_reg;
- if (CRm != 0)
- goto bad_reg;
- if (!arm_feature(vcpu, ARM_FEATURE_V7)) {
- *data = 0;
- break;
- }
- switch (opc2) {
- case 0:
- *data = cp15->c0_ccsid[cp15->c0_cssel];
- break;
- case 1:
- *data = cp15->c0_clid;
- break;
- case 7:
- *data = 0;
- break;
- default:
- goto bad_reg;
- }
- break;
- case 2:
- if (opc2 != 0 || CRm != 0)
- goto bad_reg;
- *data = cp15->c0_cssel;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 1: /* System configuration. */
- switch (opc2) {
- case 0: /* Control register. */
- *data = cp15->c1_sctlr;
- break;
- case 1: /* Auxiliary control register. */
- if (!arm_feature(vcpu, ARM_FEATURE_AUXCR))
- goto bad_reg;
- switch (arm_cpuid(vcpu)) {
- case ARM_CPUID_ARM1026:
- *data = 1;
- break;
- case ARM_CPUID_ARM1136:
- case ARM_CPUID_ARM1136_R2:
- *data = 7;
- break;
- case ARM_CPUID_ARM11MPCORE:
- *data = 1;
- break;
- case ARM_CPUID_CORTEXA8:
- *data = 2;
- break;
- case ARM_CPUID_CORTEXA9:
- *data = 0;
- if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
- *data |= (1 << 6);
- } else {
- *data &= ~(1 << 6);
- }
- break;
- default:
- goto bad_reg;
- }
- break;
- case 2: /* Coprocessor access register. */
- if (!arm_feature(vcpu, ARM_FEATURE_V6))
- goto bad_reg;
- *data = cp15->c1_cpacr;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 2: /* MMU Page table control / MPU cache control. */
- switch (opc2) {
- case 0:
- *data = cp15->c2_ttbr0;
- break;
- case 1:
- *data = cp15->c2_ttbr1;
- break;
- case 2:
- *data = cp15->c2_ttbcr;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 3: /* MMU Domain access control / MPU write buffer control. */
- *data = cp15->c3_dacr;
- break;
- case 4: /* Reserved. */
- goto bad_reg;
- case 5: /* MMU Fault status / MPU access permission. */
- switch (opc2) {
- case 0:
- switch (CRm) {
- case 0:
- *data = cp15->c5_dfsr;
- break;
- case 1:
- *data = cp15->c5_adfsr;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 1:
- switch (CRm) {
- case 0:
- *data = cp15->c5_ifsr;
- break;
- case 1:
- *data = cp15->c5_aifsr;
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- break;
- case 6: /* MMU Fault address. */
- switch (opc2) {
- case 0:
- *data = cp15->c6_dfar;
- break;
- case 1:
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- /* Watchpoint Fault Adrress. */
- *data = 0; /* Not implemented. */
- } else {
- /* Instruction Fault Adrress. */
- /* Arm9 doesn't have an IFAR,
- * but implementing it anyway
- * shouldn't do any harm.
- */
- *data = cp15->c6_ifar;
- }
- break;
- case 2:
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- /* Instruction Fault Adrress. */
- *data = cp15->c6_ifar;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- case 7: /* Cache control. */
- switch (opc2) {
- case 0:
- if (CRm == 4 && opc1 == 0) {
- *data = cp15->c7_par;
- } else {
- /* FIXME: Should only clear Z flag
- * if destination is r15.
- */
- regs->cpsr &= ~CPSR_ZERO_MASK;
- *data = 0;
- }
- break;
- case 3:
- switch (CRm) {
- case 10: /* Test and clean DCache */
- clean_dcache();
- regs->cpsr |= CPSR_ZERO_MASK;
- *data = 0;
- break;
- case 14: /* Test, clean and invalidate DCache */
- clean_dcache();
- regs->cpsr |= CPSR_ZERO_MASK;
- *data = 0;
- break;
- default:
- /* FIXME: Should only clear Z flag
- * if destination is r15.
- */
- regs->cpsr &= ~CPSR_ZERO_MASK;
- *data = 0;
- break;
- }
- break;
- default:
- /* FIXME: Should only clear Z flag
- * if destination is r15.
- */
- regs->cpsr &= ~CPSR_ZERO_MASK;
- *data = 0;
- break;
- }
- break;
- case 8: /* MMU TLB control. */
- goto bad_reg;
- case 9: /* Cache lockdown. */
- switch (opc1) {
- case 0: /* L1 cache. */
- switch (opc2) {
- case 0:
- *data = cp15->c9_data;
- break;
- case 1:
- *data = cp15->c9_insn;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 1: /* L2 cache */
- if (CRm != 0)
- goto bad_reg;
- /* L2 Lockdown and Auxiliary control. */
- *data = 0;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- *data = 0;
- switch (CRm) {
- case 2:
- switch (opc2) {
- case 0:
- *data = cp15->c10_prrr;
- break;
- case 1:
- *data = cp15->c10_nmrr;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- };
- break;
- case 11: /* TCM DMA control. */
- goto bad_reg;
- case 12:
- if (arm_feature(vcpu, ARM_FEATURE_TRUSTZONE)) {
- switch (opc2) {
- case 0: /* VBAR */
- *data = cp15->c12_vbar;
- break;
- default:
- goto bad_reg;
- };
- break;
- }
- goto bad_reg;
- case 13: /* Process ID. */
- switch (opc2) {
- case 0:
- *data = cp15->c13_fcse;
- break;
- case 1:
- *data = cp15->c13_context;
- break;
- case 2:
- /* TPIDRURW */
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- *data = cp15->c13_tls1;
- } else {
- goto bad_reg;
- }
- break;
- case 3:
- /* TPIDRURO */
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- *data = cp15->c13_tls2;
- } else {
- goto bad_reg;
- }
- break;
- case 4:
- /* TPIDRPRW */
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- *data = cp15->c13_tls3;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- case 14: /* Reserved. */
- goto bad_reg;
- case 15: /* Implementation specific. */
- switch (opc1) {
- case 0:
- switch (arm_cpuid(vcpu)) {
- case ARM_CPUID_CORTEXA9:
- /* PCR: Power control register */
- /* Read always zero. */
- *data = 0x0;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 4:
- switch (arm_cpuid(vcpu)) {
- case ARM_CPUID_CORTEXA9:
- /* CBAR: Configuration Base Address Register */
- *data = 0x1e000000;
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- break;
- }
- return TRUE;
-bad_reg:
- vmm_printf("%s: vcpu=%d opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->id, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-bool cpu_vcpu_cp15_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm, u32 data)
-{
- u32 tmp;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- switch (CRn) {
- case 0:
- /* ID codes. */
- if (arm_feature(vcpu, ARM_FEATURE_V7) &&
- (opc1 == 2) && (CRm == 0) && (opc2 == 0)) {
- cp15->c0_cssel = data & 0xf;
- break;
- }
- goto bad_reg;
- case 1: /* System configuration. */
- switch (opc2) {
- case 0:
- /* store old value of sctlr */
- tmp = cp15->c1_sctlr & SCTLR_MMU_MASK;
- if (arm_feature(vcpu, ARM_FEATURE_V7)) {
- cp15->c1_sctlr &= SCTLR_ROBITS_MASK;
- cp15->c1_sctlr |= (data & ~SCTLR_ROBITS_MASK);
- } else if (arm_feature(vcpu, ARM_FEATURE_V6K)) {
- cp15->c1_sctlr &= SCTLR_V6K_ROBITS_MASK;
- cp15->c1_sctlr |= (data & ~SCTLR_V6K_ROBITS_MASK);
- } else if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- cp15->c1_sctlr &= SCTLR_V6_ROBITS_MASK;
- cp15->c1_sctlr |= (data & ~SCTLR_V6_ROBITS_MASK);
- } else {
- cp15->c1_sctlr &= SCTLR_V5_ROBITS_MASK;
- cp15->c1_sctlr |= (data & ~SCTLR_V5_ROBITS_MASK);
- }
-
- /* ??? Lots of these bits are not implemented. */
- if (tmp != (cp15->c1_sctlr & SCTLR_MMU_MASK)) {
- /* For single-core guests flush VTLB only when
- * MMU related bits in SCTLR changes
- */
- cpu_vcpu_cp15_vtlb_flush(cp15);
- }
- break;
- case 1: /* Auxiliary control register. */
- if (!arm_feature(vcpu, ARM_FEATURE_AUXCR))
- goto bad_reg;
- /* Not implemented. */
- break;
- case 2:
- if (!arm_feature(vcpu, ARM_FEATURE_V6))
- goto bad_reg;
- if (cp15->c1_cpacr != data) {
- cp15->c1_cpacr = data;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- case 2: /* MMU Page table control / MPU cache control. */
- switch (opc2) {
- case 0:
- cp15->c2_ttbr0 = data;
- break;
- case 1:
- cp15->c2_ttbr1 = data;
- break;
- case 2:
- data &= 7;
- cp15->c2_ttbcr = data;
- cp15->c2_mask =
- ~(((u32) 0xffffffffu) >> data);
- cp15->c2_base_mask =
- ~((u32) 0x3fffu >> data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 3: /* MMU Domain access control / MPU write buffer control. */
- tmp = cp15->c3_dacr;
- cp15->c3_dacr = data;
-
- if (tmp != data) {
- cpu_vcpu_cp15_vtlb_flush_domain(cp15, tmp ^ data);
- }
- break;
- case 4: /* Reserved. */
- goto bad_reg;
- case 5: /* MMU Fault status / MPU access permission. */
- switch (opc2) {
- case 0:
- switch (CRm) {
- case 0:
- cp15->c5_dfsr = data;
- break;
- case 1:
- cp15->c5_adfsr = data;
- break;
- default:
- goto bad_reg;
- };
- break;
- case 1:
- switch (CRm) {
- case 0:
- cp15->c5_ifsr = data;
- break;
- case 1:
- cp15->c5_aifsr = data;
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- break;
- case 6: /* MMU Fault address / MPU base/size. */
- switch (opc2) {
- case 0:
- cp15->c6_dfar = data;
- break;
- case 1: /* ??? This is WFAR on armv6 */
- case 2:
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- cp15->c6_ifar = data;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- }
- break;
- case 7: /* Cache control. */
- cp15->c15_i_max = 0x000;
- cp15->c15_i_min = 0xff0;
- if (opc1 != 0) {
- goto bad_reg;
- }
- /* Note: Data cache invalidate is a dangerous
- * operation since it is possible that Xvisor had its
- * own updates in data cache which are not written to
- * main memory we might end-up losing those updates
- * which can potentially crash the system.
- */
- switch (CRm) {
- case 0:
- switch (opc2) {
- case 4:
- /* Legacy wait-for-interrupt */
- /* Emulation for ARMv5, ARMv6 */
- vmm_vcpu_irq_wait(vcpu);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 1:
- if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
- /* TODO: Can we treat these as nop ? */
- switch (opc2) {
- case 0:
- /* Invalidate all I-caches to PoU
- * innner-shareable - ICIALLUIS */
- invalidate_icache();
- break;
- case 6:
- /* Invalidate all branch predictors
- * innner-shareable - BPIALLUIS */
- invalidate_bpredictor();
- break;
- default:
- goto bad_reg;
- };
- }
- break;
- case 4:
- /* VA->PA translations. */
- if (arm_feature(vcpu, ARM_FEATURE_VAPA)) {
- if (arm_feature(vcpu, ARM_FEATURE_V7)) {
- cp15->c7_par = data & 0xfffff6ff;
- } else {
- cp15->c7_par = data & 0xfffff1ff;
- }
- }
- break;
- case 5:
- switch (opc2) {
- case 0:
- /* Invalidate all instruction caches to PoU */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- invalidate_icache();
- break;
- case 1:
- /* Invalidate instruction cache line
- * by MVA to PoU
- */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- invalidate_icache_mva(data);
- break;
- case 2:
- /* Invalidate instruction cache line
- * by set/way.
- */
- /* Emulation for ARMv5, ARMv6 */
- invalidate_icache_line(data);
- break;
- case 4:
- /* Instruction synchroization barrier */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- isb();
- break;
- case 6:
- /* Invalidate entire branch predictor array */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- invalidate_bpredictor();
- break;
- case 7:
- /* Invalidate MVA from branch predictor array */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- invalidate_bpredictor_mva(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 6:
- switch (opc2) {
- case 0:
- /* Invalidate data caches */
- /* Emulation for ARMv5, ARMv6 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate data cache.
- */
- clean_invalidate_dcache();
- break;
- case 1:
- /* Invalidate data cache line by MVA to PoC. */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate data cache.
- */
- clean_invalidate_dcache_mva(data);
- break;
- case 2:
- /* Invalidate data cache line by set/way. */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate data cache.
- */
- clean_invalidate_dcache_line(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 7:
- switch (opc2) {
- case 0:
- /* Invalidate unified cache */
- /* Emulation for ARMv5, ARMv6 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate unified cache
- */
- clean_invalidate_idcache();
- break;
- case 1:
- /* Invalidate unified cache line by MVA */
- /* Emulation for ARMv5, ARMv6 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate unified cache
- */
- clean_invalidate_idcache_mva(data);
- break;
- case 2:
- /* Invalidate unified cache line by set/way */
- /* Emulation for ARMv5, ARMv6 */
- /* For safety and correctness upgrade it to
- * Clean and invalidate unified cache
- */
- clean_invalidate_idcache_line(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 8:
- /* VA->PA translations. */
- if (arm_feature(vcpu, ARM_FEATURE_VAPA)) {
- struct cpu_page pg;
- int ret, is_user = opc2 & 2;
- int access_type = opc2 & 1;
- if (opc2 & 4) {
- /* Other states are only available
- * with TrustZone
- */
- goto bad_reg;
- }
- ret = cpu_vcpu_cp15_find_page(vcpu, data,
- access_type, is_user, &pg);
- if (ret == 0) {
- /* We do not set any attribute bits
- * in the PAR
- */
- if (pg.sz == TTBL_L1TBL_SUPSECTION_PAGE_SIZE &&
- arm_feature(vcpu, ARM_FEATURE_V7)) {
- cp15->c7_par =
- (pg.pa & 0xff000000) | 1 << 1;
- } else {
- cp15->c7_par =
- pg.pa & 0xfffff000;
- }
- } else {
- cp15->c7_par =
- (((ret >> 9) & 0x1) << 6) |
- (((ret >> 4) & 0x1F) << 1) | 1;
- }
- }
- break;
- case 10:
- switch (opc2) {
- case 0:
- /* Clean data cache */
- /* Emulation for ARMv6 */
- clean_dcache();
- break;
- case 1:
- /* Clean data cache line by MVA. */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- clean_dcache_mva(data);
- break;
- case 2:
- /* Clean data cache line by set/way. */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- clean_dcache_line(data);
- break;
- case 4:
- /* Data synchroization barrier */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- dsb();
- break;
- case 5:
- /* Data memory barrier */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- dmb();
- break;
- default:
- goto bad_reg;
- };
- break;
- case 11:
- switch (opc2) {
- case 0:
- /* Clean unified cache */
- /* Emulation for ARMv5, ARMv6 */
- clean_idcache();
- break;
- case 1:
- /* Clean unified cache line by MVA. */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- clean_idcache_mva(data);
- break;
- case 2:
- /* Clean unified cache line by set/way. */
- /* Emulation for ARMv5, ARMv6 */
- clean_idcache_line(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 14:
- switch (opc2) {
- case 0:
- /* Clean and invalidate data cache */
- /* Emulation for ARMv6 */
- clean_invalidate_dcache();
- break;
- case 1:
- /* Clean and invalidate
- * data cache line by MVA
- */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- clean_invalidate_dcache_mva(data);
- break;
- case 2:
- /* Clean and invalidate
- * data cache line by set/way
- */
- /* Emulation for ARMv5, ARMv6, ARMv7 */
- clean_invalidate_dcache_line(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- case 15:
- switch (opc2) {
- case 0:
- /* Clean and invalidate unified cache */
- /* Emulation for ARMv6 */
- clean_invalidate_idcache();
- break;
- case 1:
- /* Clean and Invalidate
- * unified cache line by MVA
- */
- /* Emulation for ARMv5, ARMv6 */
- clean_invalidate_idcache_mva(data);
- break;
- case 2:
- /* Clean and Invalidate
- * unified cache line by set/way
- */
- /* Emulation for ARMv5, ARMv6 */
- clean_invalidate_idcache_line(data);
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- break;
- case 8: /* MMU TLB control. */
- switch (opc2) {
- case 0: /* Invalidate all. */
- cpu_vcpu_cp15_vtlb_flush(cp15);
- break;
- case 1: /* Invalidate single TLB entry. */
- cpu_vcpu_cp15_vtlb_flush_ng_va(cp15, data);
- break;
- case 2: /* Invalidate on ASID. */
- cpu_vcpu_cp15_vtlb_flush_ng(cp15);
- break;
- case 3: /* Invalidate single entry on MVA. */
- /* ??? This is like case 1, but ignores ASID. */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, data);
- break;
- default:
- goto bad_reg;
- }
- break;
- case 9:
- switch (CRm) {
- case 0: /* Cache lockdown. */
- switch (opc1) {
- case 0: /* L1 cache. */
- switch (opc2) {
- case 0:
- cp15->c9_data = data;
- break;
- case 1:
- cp15->c9_insn = data;
- break;
- default:
- goto bad_reg;
- }
- break;
- case 1: /* L2 cache. */
- /* Ignore writes to
- * L2 lockdown/auxiliary registers.
- */
- break;
- default:
- goto bad_reg;
- }
- break;
- case 1: /* TCM memory region registers. */
- /* Not implemented. */
- goto bad_reg;
- case 12: /* Performance monitor control */
- /* Performance monitors are implementation
- * defined in v7, but with an ARM recommended
- * set of registers, which we follow (although
- * we don't actually implement any counters)
- */
- if (!arm_feature(vcpu, ARM_FEATURE_V7)) {
- goto bad_reg;
- }
- switch (opc2) {
- case 0: /* performance monitor control register */
- /* only the DP, X, D and E bits are writable */
- cp15->c9_pmcr &= ~0x39;
- cp15->c9_pmcr |= (data & 0x39);
- break;
- case 1: /* Count enable set register */
- data &= (1 << 31);
- cp15->c9_pmcnten |= data;
- break;
- case 2: /* Count enable clear */
- data &= (1 << 31);
- cp15->c9_pmcnten &= ~data;
- break;
- case 3: /* Overflow flag status */
- cp15->c9_pmovsr &= ~data;
- break;
- case 4: /* Software increment */
- /* RAZ/WI since we don't implement
- * the software-count event */
- break;
- case 5: /* Event counter selection register */
- /* Since we don't implement any events,
- * writing to this register is actually
- * UNPREDICTABLE. So we choose to RAZ/WI.
- */
- break;
- default:
- goto bad_reg;
- }
- break;
- case 13: /* Performance counters */
- if (!arm_feature(vcpu, ARM_FEATURE_V7)) {
- goto bad_reg;
- }
- switch (opc2) {
- case 0: /* Cycle count register */
- /* not implemented, so RAZ/WI */
- break;
- case 1: /* Event type select */
- cp15->c9_pmxevtyper =
- data & 0xff;
- break;
- case 2: /* Event count register */
- /* Unimplemented (we have no events), RAZ/WI */
- break;
- default:
- goto bad_reg;
- }
- break;
- case 14: /* Performance monitor control */
- if (!arm_feature(vcpu, ARM_FEATURE_V7)) {
- goto bad_reg;
- }
- switch (opc2) {
- case 0: /* user enable */
- cp15->c9_pmuserenr = data & 1;
- break;
- case 1: /* interrupt enable set */
- /* We have no event counters so only
- * the C bit can be changed
- */
- data &= (1 << 31);
- cp15->c9_pminten |= data;
- break;
- case 2: /* interrupt enable clear */
- data &= (1 << 31);
- cp15->c9_pminten &= ~data;
- break;
- }
- break;
- default:
- goto bad_reg;
- }
- break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- switch (CRm) {
- case 2:
- switch (opc2) {
- case 0:
- cp15->c10_prrr = data;
- break;
- case 1:
- cp15->c10_nmrr = data;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- };
- break;
- case 12:
- if (arm_feature(vcpu, ARM_FEATURE_TRUSTZONE)) {
- switch (opc2) {
- case 0: /* VBAR */
- cp15->c12_vbar = (data & ~0x1f);
- break;
- default:
- goto bad_reg;
- };
- break;
- }
- goto bad_reg;
- case 13: /* Process ID. */
- switch (opc2) {
- case 0:
- /* Unlike real hardware vTLB uses virtual addresses,
- * not modified virtual addresses, so this causes
- * a vTLB flush.
- */
- if (cp15->c13_fcse != data) {
- cpu_vcpu_cp15_vtlb_flush(cp15);
- }
- cp15->c13_fcse = data;
- break;
- case 1:
- /* This changes the ASID,
- * so flush non-global pages from vTLB.
- */
- if (cp15->c13_context != data &&
- !arm_feature(vcpu, ARM_FEATURE_MPU)) {
- cpu_vcpu_cp15_vtlb_flush_ng(cp15);
- }
- cp15->c13_context = data;
- break;
- case 2:
- if (!arm_feature(vcpu, ARM_FEATURE_V6)) {
- goto bad_reg;
- }
- /* TPIDRURW */
- cp15->c13_tls1 = data;
- write_tpidrurw(data);
- break;
- case 3:
- if (!arm_feature(vcpu, ARM_FEATURE_V6)) {
- goto bad_reg;
- }
- /* TPIDRURO */
- cp15->c13_tls2 = data;
- write_tpidruro(data);
- break;
- case 4:
- if (!arm_feature(vcpu, ARM_FEATURE_V6)) {
- goto bad_reg;
- }
- /* TPIDRPRW */
- cp15->c13_tls3 = data;
- break;
- default:
- goto bad_reg;
- }
- break;
- case 14: /* Reserved. */
- goto bad_reg;
- case 15: /* Implementation specific. */
- switch (opc1) {
- case 0:
- switch (arm_cpuid(vcpu)) {
- case ARM_CPUID_CORTEXA9:
- /* Power Control Register */
- /* Ignore writes. */;
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- break;
- }
- return TRUE;
-bad_reg:
- vmm_printf("%s: vcpu=%d opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->id, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-virtual_addr_t cpu_vcpu_cp15_vector_addr(struct vmm_vcpu *vcpu, u32 irq_no)
-{
- virtual_addr_t vaddr;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
- irq_no = irq_no % CPU_IRQ_NR;
-
- if (cp15->c1_sctlr & SCTLR_V_MASK) {
- vaddr = CPU_IRQ_HIGHVEC_BASE;
- } else if (arm_feature(vcpu, ARM_FEATURE_TRUSTZONE)) {
- vaddr = cp15->c12_vbar;
- } else {
- vaddr = CPU_IRQ_LOWVEC_BASE;
- }
-
- if (cp15->ovect_base == vaddr) {
- vaddr = (virtual_addr_t)arm_guest_priv(vcpu->guest)->ovect;
- }
-
- vaddr += 4 * irq_no;
-
- return vaddr;
-}
-
-void cpu_vcpu_cp15_sync_cpsr(struct vmm_vcpu *vcpu)
-{
- struct vmm_vcpu *cvcpu = vmm_scheduler_current_vcpu();
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- cp15->dacr &= ~(0x3 << (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER));
- cp15->dacr &= ~(0x3 << (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R));
-
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- cp15->dacr |= (TTBL_DOM_NOACCESS <<
- (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER));
- cp15->dacr |= (TTBL_DOM_CLIENT <<
- (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R));
- } else {
- cp15->dacr |= (TTBL_DOM_CLIENT <<
- (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER));
- cp15->dacr |= (TTBL_DOM_MANAGER <<
- (2 * TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R));
- }
-
- if (cvcpu->id == vcpu->id) {
- cpu_mmu_change_dacr(cp15->dacr);
- }
-}
-
-void cpu_vcpu_cp15_regs_save(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- cp15->c13_tls1 = read_tpidrurw();
- cp15->c13_tls2 = read_tpidruro();
-}
-
-void cpu_vcpu_cp15_regs_restore(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- cpu_mmu_change_dacr(cp15->dacr);
- cpu_mmu_change_ttbr(cp15->l1);
- write_tpidrurw(cp15->c13_tls1);
- write_tpidruro(cp15->c13_tls2);
- if (cp15->inv_icache) {
- cp15->inv_icache = FALSE;
- invalidate_icache();
- }
-
- /* Ensure pending memory operations are complete */
- dsb();
- isb();
-}
-
-void cpu_vcpu_cp15_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu)
-{
- u32 i;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- vmm_cprintf(cdev, "CP15 Identification Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "MIDR", cp15->c0_midr,
- "MPIDR", cp15->c0_mpidr,
- "CTR", cp15->c0_cachetype);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "PFR0", cp15->c0_pfr0,
- "PFR1", cp15->c0_pfr1,
- "DFR0", cp15->c0_dfr0);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "AFR0", cp15->c0_afr0,
- "MMFR0", cp15->c0_mmfr0,
- "MMFR1", cp15->c0_mmfr1);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "MMFR2", cp15->c0_mmfr2,
- "MMFR3", cp15->c0_mmfr3,
- "ISAR0", cp15->c0_isar0);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "ISAR1", cp15->c0_isar1,
- "ISAR2", cp15->c0_isar2,
- "ISAR3", cp15->c0_isar3);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x",
- "ISAR4", cp15->c0_isar4,
- "ISAR5", cp15->c0_isar5,
- "CSSID00", cp15->c0_ccsid[0]);
- for (i = 1; i < 16; i++) {
- if (i % 3 == 1) {
- vmm_cprintf(cdev, "\n");
- }
- vmm_cprintf(cdev, " %5s%02d=0x%08x",
- "CCSID", i, cp15->c0_ccsid[i]);
- }
- vmm_cprintf(cdev, "\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x\n",
- "CLID", cp15->c0_clid,
- "CSSEL", cp15->c0_cssel);
- vmm_cprintf(cdev, "CP15 Control Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SCTLR", cp15->c1_sctlr,
- "CPACR", cp15->c1_cpacr,
- "VBAR", cp15->c12_vbar);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x\n",
- "FCSEIDR", cp15->c13_fcse,
- "CNTXIDR", cp15->c13_context);
- vmm_cprintf(cdev, "CP15 MMU Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "TTBR0", cp15->c2_ttbr0,
- "TTBR1", cp15->c2_ttbr1,
- "TTBCR", cp15->c2_ttbcr);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "DACR", cp15->c3_dacr,
- "PRRR", cp15->c10_prrr,
- "NMRR", cp15->c10_nmrr);
- vmm_cprintf(cdev, "CP15 Fault Status Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "IFSR", cp15->c5_ifsr,
- "DFSR", cp15->c5_dfsr,
- "AIFSR", cp15->c5_aifsr);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "ADFSR", cp15->c5_adfsr,
- "IFAR", cp15->c6_ifar,
- "DFAR", cp15->c6_dfar);
- vmm_cprintf(cdev, "CP15 Address Translation Registers\n");
- vmm_cprintf(cdev, " %7s=%"PRIADDR" %7s=%"PRIADDR64"\n",
- "PAR", cp15->c7_par,
- "PAR64", cp15->c7_par64);
- vmm_cprintf(cdev, "CP15 Cache Lockdown Registers\n");
- vmm_cprintf(cdev, " %7s=%"PRIADDR" %7s=%"PRIADDR"\n",
- "CILOCK", cp15->c9_insn, /* ??? */
- "CDLOCK", cp15->c9_data); /* ??? */
- vmm_cprintf(cdev, "CP15 Performance Monitor Control Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "PMCR", cp15->c9_pmcr,
- "PMCNTEN", cp15->c9_pmcnten,
- "PMOVSR", cp15->c9_pmovsr);
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "PMXEVTY", cp15->c9_pmxevtyper,
- "PMUSREN", cp15->c9_pmuserenr,
- "PMINTEN", cp15->c9_pminten);
- vmm_cprintf(cdev, "CP15 Thread Local Storage Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "TPIDURW", cp15->c13_tls1,
- "TPIDURO", cp15->c13_tls2,
- "TPIDPRW", cp15->c13_tls3);
-}
-
-int cpu_vcpu_cp15_init(struct vmm_vcpu *vcpu, u32 cpuid)
-{
- int rc = VMM_OK;
-#if defined(CONFIG_ARMV7A)
- u32 i, cache_type, last_level;
-#endif
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- if (!vcpu->reset_count) {
- memset(cp15, 0, sizeof(struct arm_priv_cp15));
- cp15->l1 = cpu_mmu_l1tbl_alloc();
- } else {
- if ((rc = cpu_vcpu_cp15_vtlb_flush(cp15))) {
- return rc;
- }
- }
-
- cp15->dacr = 0x0;
- cp15->dacr |= (TTBL_DOM_CLIENT <<
- (TTBL_L1TBL_TTE_DOM_VCPU_SUPER * 2));
- cp15->dacr |= (TTBL_DOM_MANAGER <<
- (TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R * 2));
- cp15->dacr |= (TTBL_DOM_CLIENT <<
- (TTBL_L1TBL_TTE_DOM_VCPU_USER * 2));
-
- if (read_sctlr() & SCTLR_V_MASK) {
- cp15->ovect_base = CPU_IRQ_HIGHVEC_BASE;
- } else {
- cp15->ovect_base = CPU_IRQ_LOWVEC_BASE;
- }
-
- cp15->virtio_active = FALSE;
- memset(&cp15->virtio_page, 0,
- sizeof(struct cpu_page));
-
- cp15->c0_midr = cpuid;
- cp15->c0_mpidr = vcpu->subid;
- /* We don't support setting cluster ID ([8..11]) so
- * these bits always RAZ.
- */
- if (arm_feature(vcpu, ARM_FEATURE_V7MP)) {
- cp15->c0_mpidr |= (1 << 31);
- }
- cp15->c2_ttbcr = 0x0;
- cp15->c2_ttbr0 = 0x0;
- cp15->c2_ttbr1 = 0x0;
- cp15->c2_mask = 0x0;
- cp15->c2_base_mask = 0xFFFFC000;
- cp15->c9_pmcr = (cpuid & 0xFF000000);
- cp15->c10_prrr = 0x0;
- cp15->c10_nmrr = 0x0;
- cp15->c12_vbar = 0x0;
- /* Reset values of important registers */
- switch (cpuid) {
- case ARM_CPUID_ARM926:
- cp15->c0_cachetype = 0x1dd20d2;
- cp15->c1_sctlr = 0x00090078;
- break;
- case ARM_CPUID_ARM11MPCORE:
- cp15->c0_cachetype = 0x1d192992; /* 32K icache 32K dcache */
- cp15->c0_pfr0 = 0x111;
- cp15->c0_pfr1 = 0x1;
- cp15->c0_dfr0 = 0;
- cp15->c0_afr0 = 0x2;
- cp15->c0_mmfr0 = 0x01100103;
- cp15->c0_mmfr1 = 0x10020302;
- cp15->c0_mmfr2 = 0x01222000;
- cp15->c0_isar0 = 0x00100011;
- cp15->c0_isar1 = 0x12002111;
- cp15->c0_isar2 = 0x11221011;
- cp15->c0_isar3 = 0x01102131;
- cp15->c0_isar4 = 0x141;
- cp15->c1_sctlr = 0x00050070;
- break;
- case ARM_CPUID_CORTEXA8:
- cp15->c0_cachetype = 0x82048004;
- cp15->c0_pfr0 = 0x1031;
- cp15->c0_pfr1 = 0x11;
- cp15->c0_dfr0 = 0x400;
- cp15->c0_afr0 = 0x0;
- cp15->c0_mmfr0 = 0x31100003;
- cp15->c0_mmfr1 = 0x20000000;
- cp15->c0_mmfr2 = 0x01202000;
- cp15->c0_mmfr3 = 0x11;
- cp15->c0_isar0 = 0x00101111;
- cp15->c0_isar1 = 0x12112111;
- cp15->c0_isar2 = 0x21232031;
- cp15->c0_isar3 = 0x11112131;
- cp15->c0_isar4 = 0x00111142;
- cp15->c0_isar5 = 0x0;
- cp15->c0_clid = (1 << 27) | (2 << 24) | 3;
- cp15->c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
- cp15->c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
- cp15->c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- cp15->c1_sctlr = 0x00c50078;
- break;
- case ARM_CPUID_CORTEXA9:
- cp15->c0_cachetype = 0x80038003;
- cp15->c0_pfr0 = 0x1031;
- cp15->c0_pfr1 = 0x11;
- cp15->c0_dfr0 = 0x000;
- cp15->c0_afr0 = 0x0;
- cp15->c0_mmfr0 = 0x00100103;
- cp15->c0_mmfr1 = 0x20000000;
- cp15->c0_mmfr2 = 0x01230000;
- cp15->c0_mmfr3 = 0x00002111;
- cp15->c0_isar0 = 0x00101111;
- cp15->c0_isar1 = 0x13112111;
- cp15->c0_isar2 = 0x21232041;
- cp15->c0_isar3 = 0x11112131;
- cp15->c0_isar4 = 0x00111142;
- cp15->c0_isar5 = 0x0;
- cp15->c0_clid = (1 << 27) | (1 << 24) | 3;
- cp15->c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
- cp15->c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- cp15->c1_sctlr = 0x00c50078;
- break;
- default:
- break;
- }
-
-#if defined(CONFIG_ARMV7A)
- if (arm_feature(vcpu, ARM_FEATURE_V7)) {
- /* Current strategy is to show identification registers same
- * as underlying Host HW so that Guest sees same capabilities
- * as Host HW.
- */
- cp15->c0_pfr0 = read_pfr0();
- cp15->c0_pfr1 = read_pfr1();
- cp15->c0_dfr0 = read_dfr0();
- cp15->c0_afr0 = read_afr0();
- cp15->c0_mmfr0 = read_mmfr0();
- cp15->c0_mmfr1 = read_mmfr1();
- cp15->c0_mmfr2 = read_mmfr2();
- cp15->c0_mmfr3 = read_mmfr3();
- cp15->c0_isar0 = read_isar0();
- cp15->c0_isar1 = read_isar1();
- cp15->c0_isar2 = read_isar2();
- cp15->c0_isar3 = read_isar3();
- cp15->c0_isar4 = read_isar4();
- cp15->c0_isar5 = read_isar5();
-
- /* Cache config register such as CTR, CLIDR, and CCSIDRx
- * should be same as that of underlying host.
- */
- cp15->c0_cachetype = read_ctr();
- cp15->c0_clid = read_clidr();
- last_level = (cp15->c0_clid & CLIDR_LOUU_MASK)
- >> CLIDR_LOUU_SHIFT;
- for (i = 0; i <= last_level; i++) {
- cache_type = cp15->c0_clid >> (i * 3);
- cache_type &= 0x7;
- switch (cache_type) {
- case CLIDR_CTYPE_ICACHE:
- write_csselr((i << 1) | 1);
- cp15->c0_ccsid[(i << 1) | 1] = read_ccsidr();
- break;
- case CLIDR_CTYPE_DCACHE:
- case CLIDR_CTYPE_UNICACHE:
- write_csselr(i << 1);
- cp15->c0_ccsid[i << 1] = read_ccsidr();
- break;
- case CLIDR_CTYPE_SPLITCACHE:
- write_csselr(i << 1);
- cp15->c0_ccsid[i << 1] = read_ccsidr();
- write_csselr((i << 1) | 1);
- cp15->c0_ccsid[(i << 1) | 1] = read_ccsidr();
- break;
- case CLIDR_CTYPE_NOCACHE:
- case CLIDR_CTYPE_RESERVED1:
- case CLIDR_CTYPE_RESERVED2:
- case CLIDR_CTYPE_RESERVED3:
- cp15->c0_ccsid[i << 1] = 0;
- cp15->c0_ccsid[(i << 1) | 1] = 0;
- break;
- };
- }
- }
-#endif
-
- /* Set i-cache invalidate flag for this vcpu.
- * This will clear i-cache, b-predictor cache, and execution pipeline
- * on next context switch for this vcpu.
- * This is done to make sure that the host cpu pickup fresh
- * guest code from host RAM after every vcpu reset.
- */
- cp15->inv_icache = TRUE;
-
- return rc;
-}
-
-int cpu_vcpu_cp15_deinit(struct vmm_vcpu *vcpu)
-{
- int rc;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- if ((rc = cpu_mmu_sync_ttbr(cp15->l1))) {
- return rc;
- }
-
- if ((rc = cpu_mmu_l1tbl_free(cp15->l1))) {
- return rc;
- }
-
- memset(cp15, 0, sizeof(struct arm_priv_cp15));
-
- return VMM_OK;
-}
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_helper.c b/arch/arm/cpu/arm32/cpu_vcpu_helper.c
deleted file mode 100644
index a6946d5c..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_helper.c
+++ /dev/null
@@ -1,1189 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_helper.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source of VCPU helper functions
- */
-
-#include <vmm_error.h>
-#include <vmm_heap.h>
-#include <vmm_stdio.h>
-#include <vmm_host_aspace.h>
-#include <vmm_manager.h>
-#include <libs/stringlib.h>
-#include <libs/mathlib.h>
-#include <cpu_defines.h>
-#include <cpu_inline_asm.h>
-#include <cpu_vcpu_vfp.h>
-#include <cpu_vcpu_cp14.h>
-#include <cpu_vcpu_cp15.h>
-#include <cpu_vcpu_helper.h>
-#include <arm_features.h>
-#include <arch_cache.h>
-
-void cpu_vcpu_halt(struct vmm_vcpu *vcpu, arch_regs_t *regs)
-{
- if (!vcpu || !regs) {
- return;
- }
-
- if (vmm_manager_vcpu_get_state(vcpu) != VMM_VCPU_STATE_HALTED) {
- vmm_printf("\n");
- cpu_vcpu_dump_user_reg(vcpu, regs);
- vmm_manager_vcpu_halt(vcpu);
- }
-}
-
-u32 cpu_vcpu_cpsr_retrieve(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- if (!vcpu || !regs) {
- return 0;
- }
- if (vcpu->is_normal) {
- return (regs->cpsr & CPSR_USERBITS_MASK) |
- (arm_priv(vcpu)->cpsr & ~CPSR_USERBITS_MASK);
- } else {
- return regs->cpsr;
- }
-}
-
-static void cpu_vcpu_banked_regs_save(struct arm_priv *p, arch_regs_t *src)
-{
- switch (p->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_USER:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_usr = src->sp;
- p->lr_usr = src->lr;
- break;
- case CPSR_MODE_SYSTEM:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_usr = src->sp;
- p->lr_usr = src->lr;
- break;
- case CPSR_MODE_ABORT:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_abt = src->sp;
- p->lr_abt = src->lr;
- break;
- case CPSR_MODE_UNDEFINED:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_und = src->sp;
- p->lr_und = src->lr;
- break;
- case CPSR_MODE_MONITOR:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_mon = src->sp;
- p->lr_mon = src->lr;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_svc = src->sp;
- p->lr_svc = src->lr;
- break;
- case CPSR_MODE_IRQ:
- p->gpr_usr[0] = src->gpr[8];
- p->gpr_usr[1] = src->gpr[9];
- p->gpr_usr[2] = src->gpr[10];
- p->gpr_usr[3] = src->gpr[11];
- p->gpr_usr[4] = src->gpr[12];
- p->sp_irq = src->sp;
- p->lr_irq = src->lr;
- break;
- case CPSR_MODE_FIQ:
- p->gpr_fiq[0] = src->gpr[8];
- p->gpr_fiq[1] = src->gpr[9];
- p->gpr_fiq[2] = src->gpr[10];
- p->gpr_fiq[3] = src->gpr[11];
- p->gpr_fiq[4] = src->gpr[12];
- p->sp_fiq = src->sp;
- p->lr_fiq = src->lr;
- break;
- default:
- break;
- };
-}
-
-static void cpu_vcpu_banked_regs_restore(struct arm_priv *p, arch_regs_t *dst)
-{
- switch (p->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_USER:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_usr;
- dst->lr = p->lr_usr;
- break;
- case CPSR_MODE_SYSTEM:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_usr;
- dst->lr = p->lr_usr;
- break;
- case CPSR_MODE_ABORT:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_abt;
- dst->lr = p->lr_abt;
- break;
- case CPSR_MODE_UNDEFINED:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_und;
- dst->lr = p->lr_und;
- break;
- case CPSR_MODE_MONITOR:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_mon;
- dst->lr = p->lr_mon;
- break;
- case CPSR_MODE_SUPERVISOR:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_svc;
- dst->lr = p->lr_svc;
- break;
- case CPSR_MODE_IRQ:
- dst->gpr[8] = p->gpr_usr[0];
- dst->gpr[9] = p->gpr_usr[1];
- dst->gpr[10] = p->gpr_usr[2];
- dst->gpr[11] = p->gpr_usr[3];
- dst->gpr[12] = p->gpr_usr[4];
- dst->sp = p->sp_irq;
- dst->lr = p->lr_irq;
- break;
- case CPSR_MODE_FIQ:
- dst->gpr[8] = p->gpr_fiq[0];
- dst->gpr[9] = p->gpr_fiq[1];
- dst->gpr[10] = p->gpr_fiq[2];
- dst->gpr[11] = p->gpr_fiq[3];
- dst->gpr[12] = p->gpr_fiq[4];
- dst->sp = p->sp_fiq;
- dst->lr = p->lr_fiq;
- break;
- default:
- break;
- };
-}
-
-void cpu_vcpu_cpsr_update(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 new_cpsr,
- u32 new_cpsr_mask)
-{
- bool mode_change;
- struct arm_priv *p;
-
- /* Sanity check */
- if (!vcpu || !vcpu->is_normal || !regs) {
- return;
- }
- p = arm_priv(vcpu);
- new_cpsr &= new_cpsr_mask;
-
- /* Determine if mode is changing */
- mode_change = FALSE;
- if ((new_cpsr_mask & CPSR_MODE_MASK) &&
- ((p->cpsr & CPSR_MODE_MASK) != (new_cpsr & CPSR_MODE_MASK))) {
- mode_change = TRUE;
- /* Save banked registers for old CPSR */
- cpu_vcpu_banked_regs_save(p, regs);
- }
-
- /* Set the new priviledged bits of CPSR */
- p->cpsr &= (~CPSR_PRIVBITS_MASK | ~new_cpsr_mask);
- p->cpsr |= new_cpsr & CPSR_PRIVBITS_MASK & new_cpsr_mask;
-
- /* Set the new user bits of CPSR */
- regs->cpsr &= (~CPSR_USERBITS_MASK | ~new_cpsr_mask);
- regs->cpsr |= new_cpsr & CPSR_USERBITS_MASK & new_cpsr_mask;
-
- /* If mode is changing then */
- if (mode_change) {
- /* Restore values of banked registers for new CPSR */
- cpu_vcpu_banked_regs_restore(p, regs);
- /* Synchronize CP15 state to change in mode */
- cpu_vcpu_cp15_sync_cpsr(vcpu);
- }
-
- return;
-}
-
-u32 cpu_vcpu_spsr_retrieve(struct vmm_vcpu *vcpu)
-{
- struct arm_priv *p = arm_priv(vcpu);
-
- /* Find out correct SPSR */
- switch (p->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_ABORT:
- return p->spsr_abt;
- case CPSR_MODE_UNDEFINED:
- return p->spsr_und;
- case CPSR_MODE_MONITOR:
- return p->spsr_mon;
- case CPSR_MODE_SUPERVISOR:
- return p->spsr_svc;
- case CPSR_MODE_IRQ:
- return p->spsr_irq;
- case CPSR_MODE_FIQ:
- return p->spsr_fiq;
- default:
- break;
- };
-
- return 0;
-}
-
-int cpu_vcpu_spsr_update(struct vmm_vcpu *vcpu,
- u32 new_spsr,
- u32 new_spsr_mask)
-{
- struct arm_priv *p;
-
- /* Sanity check */
- if (!vcpu || !vcpu->is_normal) {
- return VMM_EFAIL;
- }
- p = arm_priv(vcpu);
-
- /* VCPU cannot be in user mode */
- if ((p->cpsr & CPSR_MODE_MASK) == CPSR_MODE_USER) {
- return VMM_EFAIL;
- }
-
- new_spsr &= new_spsr_mask;
-
- /* Update appropriate SPSR */
- switch (p->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_ABORT:
- p->spsr_abt &= ~new_spsr_mask;
- p->spsr_abt |= new_spsr;
- break;
- case CPSR_MODE_UNDEFINED:
- p->spsr_und &= ~new_spsr_mask;
- p->spsr_und |= new_spsr;
- break;
- case CPSR_MODE_MONITOR:
- p->spsr_mon &= ~new_spsr_mask;
- p->spsr_mon |= new_spsr;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->spsr_svc &= ~new_spsr_mask;
- p->spsr_svc |= new_spsr;
- break;
- case CPSR_MODE_IRQ:
- p->spsr_irq &= ~new_spsr_mask;
- p->spsr_irq |= new_spsr;
- break;
- case CPSR_MODE_FIQ:
- p->spsr_fiq &= ~new_spsr_mask;
- p->spsr_fiq |= new_spsr;
- break;
- default:
- break;
- };
-
- /* Return success */
- return VMM_OK;
-}
-
-u32 cpu_vcpu_reg_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 reg_num)
-{
- switch (reg_num) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- return regs->gpr[reg_num];
- break;
- case 13:
- return regs->sp;
- break;
- case 14:
- return regs->lr;
- break;
- case 15:
- return regs->pc;
- break;
- default:
- break;
- };
- return 0x0;
-}
-
-void cpu_vcpu_reg_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 reg_num,
- u32 reg_val)
-{
- struct arm_priv *p = arm_priv(vcpu);
- u32 curmode = p->cpsr & CPSR_MODE_MASK;
-
- switch (reg_num) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- regs->gpr[reg_num] = reg_val;
- break;
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- regs->gpr[reg_num] = reg_val;
- if (curmode == CPSR_MODE_FIQ) {
- p->gpr_fiq[reg_num - 8] = reg_val;
- } else {
- p->gpr_usr[reg_num - 8] = reg_val;
- }
- break;
- case 13:
- regs->sp = reg_val;
- switch (curmode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- p->sp_usr = reg_val;
- break;
- case CPSR_MODE_FIQ:
- p->sp_fiq = reg_val;
- break;
- case CPSR_MODE_IRQ:
- p->sp_irq = reg_val;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->sp_svc = reg_val;
- break;
- case CPSR_MODE_ABORT:
- p->sp_abt = reg_val;
- break;
- case CPSR_MODE_UNDEFINED:
- p->sp_und = reg_val;
- break;
- case CPSR_MODE_MONITOR:
- p->sp_mon = reg_val;
- break;
- default:
- break;
- };
- break;
- case 14:
- regs->lr = reg_val;
- switch (curmode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- p->lr_usr = reg_val;
- break;
- case CPSR_MODE_FIQ:
- p->lr_fiq = reg_val;
- break;
- case CPSR_MODE_IRQ:
- p->lr_irq = reg_val;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->lr_svc = reg_val;
- break;
- case CPSR_MODE_ABORT:
- p->lr_abt = reg_val;
- break;
- case CPSR_MODE_UNDEFINED:
- p->lr_und = reg_val;
- break;
- case CPSR_MODE_MONITOR:
- p->lr_mon = reg_val;
- break;
- default:
- break;
- };
- break;
- case 15:
- regs->pc = reg_val;
- break;
- default:
- break;
- };
-}
-
-u32 cpu_vcpu_regmode_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 mode,
- u32 reg_num)
-{
- struct arm_priv *p = arm_priv(vcpu);
- u32 curmode = p->cpsr & CPSR_MODE_MASK;
-
- if (mode == curmode) {
- return cpu_vcpu_reg_read(vcpu, regs, reg_num);
- } else {
- switch (reg_num) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- return regs->gpr[reg_num];
- break;
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- if (curmode == CPSR_MODE_FIQ) {
- return p->gpr_usr[reg_num - 8];
- } else {
- if (mode == CPSR_MODE_FIQ) {
- return p->gpr_fiq[reg_num - 8];
- } else {
- return regs->gpr[reg_num];
- }
- }
- break;
- case 13:
- switch (mode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- return p->sp_usr;
- break;
- case CPSR_MODE_FIQ:
- return p->sp_fiq;
- break;
- case CPSR_MODE_IRQ:
- return p->sp_irq;
- break;
- case CPSR_MODE_SUPERVISOR:
- return p->sp_svc;
- break;
- case CPSR_MODE_ABORT:
- return p->sp_abt;
- break;
- case CPSR_MODE_UNDEFINED:
- return p->sp_und;
- break;
- case CPSR_MODE_MONITOR:
- return p->sp_mon;
- break;
- default:
- break;
- };
- break;
- case 14:
- switch (mode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- return p->lr_usr;
- break;
- case CPSR_MODE_FIQ:
- return p->lr_fiq;
- break;
- case CPSR_MODE_IRQ:
- return p->lr_irq;
- break;
- case CPSR_MODE_SUPERVISOR:
- return p->lr_svc;
- break;
- case CPSR_MODE_ABORT:
- return p->lr_abt;
- break;
- case CPSR_MODE_UNDEFINED:
- return p->lr_und;
- break;
- case CPSR_MODE_MONITOR:
- return p->lr_mon;
- break;
- default:
- break;
- };
- break;
- case 15:
- return regs->pc;
- break;
- default:
- break;
- };
- }
-
- return 0x0;
-}
-
-void cpu_vcpu_regmode_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 mode,
- u32 reg_num,
- u32 reg_val)
-{
- struct arm_priv *p = arm_priv(vcpu);
- u32 curmode = p->cpsr & CPSR_MODE_MASK;
-
- if (mode == curmode) {
- cpu_vcpu_reg_write(vcpu, regs, reg_num, reg_val);
- } else {
- switch (reg_num) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- regs->gpr[reg_num] = reg_val;
- break;
- case 8:
- case 9:
- case 10:
- case 11:
- case 12:
- if (curmode == CPSR_MODE_FIQ) {
- p->gpr_usr[reg_num - 8] = reg_val;
- } else {
- if (mode == CPSR_MODE_FIQ) {
- p->gpr_fiq[reg_num - 8] = reg_val;
- } else {
- regs->gpr[reg_num] = reg_val;
- }
- }
- break;
- case 13:
- switch (mode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- p->sp_usr = reg_val;
- break;
- case CPSR_MODE_FIQ:
- p->sp_fiq = reg_val;
- break;
- case CPSR_MODE_IRQ:
- p->sp_irq = reg_val;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->sp_svc = reg_val;
- break;
- case CPSR_MODE_ABORT:
- p->sp_abt = reg_val;
- break;
- case CPSR_MODE_UNDEFINED:
- p->sp_und = reg_val;
- break;
- case CPSR_MODE_MONITOR:
- p->sp_mon = reg_val;
- break;
- default:
- break;
- };
- break;
- case 14:
- switch (mode) {
- case CPSR_MODE_USER:
- case CPSR_MODE_SYSTEM:
- p->lr_usr = reg_val;
- break;
- case CPSR_MODE_FIQ:
- p->lr_fiq = reg_val;
- break;
- case CPSR_MODE_IRQ:
- p->lr_irq = reg_val;
- break;
- case CPSR_MODE_SUPERVISOR:
- p->lr_svc = reg_val;
- break;
- case CPSR_MODE_ABORT:
- p->lr_abt = reg_val;
- break;
- case CPSR_MODE_UNDEFINED:
- p->lr_und = reg_val;
- break;
- case CPSR_MODE_MONITOR:
- p->lr_mon = reg_val;
- break;
- default:
- break;
- };
- break;
- case 15:
- regs->pc = reg_val;
- break;
- default:
- break;
- };
- }
-}
-
-int arch_guest_init(struct vmm_guest *guest)
-{
- int rc;
- u32 ovect_flags;
- virtual_addr_t ovect_va;
- struct cpu_page pg;
-
- if (!guest->reset_count) {
- guest->arch_priv = vmm_zalloc(sizeof(struct arm_guest_priv));
- if (!guest->arch_priv) {
- rc = VMM_EFAIL;
- goto fail;
- }
- ovect_flags = 0x0;
- ovect_flags |= VMM_MEMORY_READABLE;
- ovect_flags |= VMM_MEMORY_WRITEABLE;
- ovect_flags |= VMM_MEMORY_CACHEABLE;
- ovect_flags |= VMM_MEMORY_EXECUTABLE;
- ovect_va = vmm_host_alloc_pages(1, ovect_flags);
- if (!ovect_va) {
- rc = VMM_EFAIL;
- goto fail;
- }
- if ((rc = cpu_mmu_get_reserved_page(ovect_va, &pg))) {
- goto fail_freepages;
- }
- if ((rc = cpu_mmu_unmap_reserved_page(&pg))) {
- goto fail_freepages;
- }
-#if defined(CONFIG_ARMV5)
- pg.ap = TTBL_AP_SRW_UR;
-#else
- if (pg.ap == TTBL_AP_SR_U) {
- pg.ap = TTBL_AP_SR_UR;
- } else {
- pg.ap = TTBL_AP_SRW_UR;
- }
-#endif
- if ((rc = cpu_mmu_map_reserved_page(&pg))) {
- goto fail_freepages;
- }
- arm_guest_priv(guest)->ovect = (u32 *)ovect_va;
-
- if (vmm_devtree_read_u32(guest->node,
- "psci_version",
- &arm_guest_priv(guest)->psci_version)) {
- /* By default, assume PSCI v0.1 */
- arm_guest_priv(guest)->psci_version = 1;
- }
- }
-
- return VMM_OK;
-
-fail_freepages:
- if (arm_guest_priv(guest)->ovect) {
- vmm_host_free_pages(
- (virtual_addr_t)arm_guest_priv(guest)->ovect, 1);
- }
-fail:
- return rc;
-}
-
-int arch_guest_deinit(struct vmm_guest *guest)
-{
- int rc;
- if (guest->arch_priv) {
- if (arm_guest_priv(guest)->ovect) {
- rc = vmm_host_free_pages(
- (virtual_addr_t)arm_guest_priv(guest)->ovect, 1);
- if (rc) {
- return rc;
- }
- }
- vmm_free(guest->arch_priv);
- }
- return VMM_OK;
-}
-
-int arch_guest_add_region(struct vmm_guest *guest, struct vmm_region *region)
-{
- return VMM_OK;
-}
-
-int arch_guest_del_region(struct vmm_guest *guest, struct vmm_region *region)
-{
- return VMM_OK;
-}
-
-int arch_vcpu_init(struct vmm_vcpu *vcpu)
-{
- int rc;
- u32 ite, cpuid;
- const char *attr;
-
- /* Initialize User Mode Registers */
- /* For both Orphan & Normal VCPUs */
-
- memset(arm_regs(vcpu), 0, sizeof(arch_regs_t));
- arm_regs(vcpu)->pc = vcpu->start_pc;
-
- /*
- * Stacks must be 64-bits aligned to respect AAPCS:
- * Procedure Call Standard for the ARM Architecture.
- * To do so, AAPCS advises that all SP must be set to
- * a value which is 0 modulo 8.
- * The compiler takes care of the frame size.
- *
- * This is terribly important because it messes runtime
- * with values greater than 32 bits (e.g. 64-bits integers).
- */
- arm_regs(vcpu)->sp_excp = vcpu->stack_va +
- (vcpu->stack_sz - ARCH_CACHE_LINE_SIZE);
- arm_regs(vcpu)->sp_excp = arm_regs(vcpu)->sp_excp & ~0x7;
-
- if (vcpu->is_normal) {
- arm_regs(vcpu)->cpsr = CPSR_ZERO_MASK;
- arm_regs(vcpu)->cpsr |= CPSR_ASYNC_ABORT_DISABLED;
- arm_regs(vcpu)->cpsr |= CPSR_MODE_USER;
- arm_regs(vcpu)->sp = 0;
- } else {
- arm_regs(vcpu)->cpsr = CPSR_ZERO_MASK;
- arm_regs(vcpu)->cpsr |= CPSR_ASYNC_ABORT_DISABLED;
- arm_regs(vcpu)->cpsr |= CPSR_MODE_SUPERVISOR;
- arm_regs(vcpu)->sp = arm_regs(vcpu)->sp_excp;
- }
-
- /* Initialize Supervisor Mode Registers */
- /* For only Normal VCPUs */
-
- if (!vcpu->is_normal) {
- return VMM_OK;
- }
- rc = vmm_devtree_read_string(vcpu->node,
- VMM_DEVTREE_COMPATIBLE_ATTR_NAME, &attr);
- if (rc) {
- goto fail;
- }
- if (strcmp(attr, "armv5te,arm926ej") == 0) {
- cpuid = ARM_CPUID_ARM926;
- } else if (strcmp(attr, "armv6,arm11mp") == 0) {
- cpuid = ARM_CPUID_ARM11MPCORE;
- } else if (strcmp(attr, "armv7a,cortex-a8") == 0) {
- cpuid = ARM_CPUID_CORTEXA8;
- } else if (strcmp(attr, "armv7a,cortex-a9") == 0) {
- cpuid = ARM_CPUID_CORTEXA9;
- } else {
- rc = VMM_EINVALID;
- goto fail;
- }
- if (!vcpu->reset_count) {
- vcpu->arch_priv = vmm_zalloc(sizeof(struct arm_priv));
- arm_priv(vcpu)->cpsr = CPSR_ASYNC_ABORT_DISABLED |
- CPSR_IRQ_DISABLED |
- CPSR_FIQ_DISABLED |
- CPSR_MODE_SUPERVISOR;
- } else {
- for (ite = 0; ite < CPU_FIQ_GPR_COUNT; ite++) {
- arm_priv(vcpu)->gpr_usr[ite] = 0x0;
- arm_priv(vcpu)->gpr_fiq[ite] = 0x0;
- }
- arm_priv(vcpu)->sp_usr = 0x0;
- arm_priv(vcpu)->lr_usr = 0x0;
- arm_priv(vcpu)->sp_svc = 0x0;
- arm_priv(vcpu)->lr_svc = 0x0;
- arm_priv(vcpu)->spsr_svc = 0x0;
- arm_priv(vcpu)->sp_mon = 0x0;
- arm_priv(vcpu)->lr_mon = 0x0;
- arm_priv(vcpu)->spsr_mon = 0x0;
- arm_priv(vcpu)->sp_abt = 0x0;
- arm_priv(vcpu)->lr_abt = 0x0;
- arm_priv(vcpu)->spsr_abt = 0x0;
- arm_priv(vcpu)->sp_und = 0x0;
- arm_priv(vcpu)->lr_und = 0x0;
- arm_priv(vcpu)->spsr_und = 0x0;
- arm_priv(vcpu)->sp_irq = 0x0;
- arm_priv(vcpu)->lr_irq = 0x0;
- arm_priv(vcpu)->spsr_irq = 0x0;
- arm_priv(vcpu)->sp_fiq = 0x0;
- arm_priv(vcpu)->lr_fiq = 0x0;
- arm_priv(vcpu)->spsr_fiq = 0x0;
- cpu_vcpu_cpsr_update(vcpu,
- arm_regs(vcpu),
- (CPSR_ZERO_MASK |
- CPSR_ASYNC_ABORT_DISABLED |
- CPSR_IRQ_DISABLED |
- CPSR_FIQ_DISABLED |
- CPSR_MODE_SUPERVISOR),
- CPSR_ALLBITS_MASK);
- }
- if (!vcpu->reset_count) {
- arm_priv(vcpu)->features = 0;
- switch (cpuid) {
- case ARM_CPUID_ARM926:
- arm_set_feature(vcpu, ARM_FEATURE_V5);
- arm_set_feature(vcpu, ARM_FEATURE_VFP);
- arm_set_feature(vcpu, ARM_FEATURE_DUMMY_C15_REGS);
- arm_set_feature(vcpu, ARM_FEATURE_CACHE_TEST_CLEAN);
- break;
- case ARM_CPUID_ARM11MPCORE:
- arm_set_feature(vcpu, ARM_FEATURE_V6);
- arm_set_feature(vcpu, ARM_FEATURE_V6K);
- arm_set_feature(vcpu, ARM_FEATURE_VFP);
- arm_set_feature(vcpu, ARM_FEATURE_VAPA);
- arm_set_feature(vcpu, ARM_FEATURE_MPIDR);
- arm_set_feature(vcpu, ARM_FEATURE_DUMMY_C15_REGS);
- break;
- case ARM_CPUID_CORTEXA8:
- arm_set_feature(vcpu, ARM_FEATURE_V7);
- arm_set_feature(vcpu, ARM_FEATURE_VFP3);
- arm_set_feature(vcpu, ARM_FEATURE_NEON);
- arm_set_feature(vcpu, ARM_FEATURE_THUMB2EE);
- arm_set_feature(vcpu, ARM_FEATURE_DUMMY_C15_REGS);
- arm_set_feature(vcpu, ARM_FEATURE_TRUSTZONE);
- break;
- case ARM_CPUID_CORTEXA9:
- arm_set_feature(vcpu, ARM_FEATURE_V7);
- arm_set_feature(vcpu, ARM_FEATURE_VFP3);
- arm_set_feature(vcpu, ARM_FEATURE_VFP_FP16);
- arm_set_feature(vcpu, ARM_FEATURE_NEON);
- arm_set_feature(vcpu, ARM_FEATURE_THUMB2EE);
- arm_set_feature(vcpu, ARM_FEATURE_V7MP);
- arm_set_feature(vcpu, ARM_FEATURE_TRUSTZONE);
- break;
- default:
- break;
- };
- /* Some features automatically imply others: */
- if (arm_feature(vcpu, ARM_FEATURE_V7)) {
- arm_set_feature(vcpu, ARM_FEATURE_VAPA);
- arm_set_feature(vcpu, ARM_FEATURE_THUMB2);
- arm_set_feature(vcpu, ARM_FEATURE_MPIDR);
- if (!arm_feature(vcpu, ARM_FEATURE_M)) {
- arm_set_feature(vcpu, ARM_FEATURE_V6K);
- } else {
- arm_set_feature(vcpu, ARM_FEATURE_V6);
- }
- }
- if (arm_feature(vcpu, ARM_FEATURE_V6K)) {
- arm_set_feature(vcpu, ARM_FEATURE_V6);
- arm_set_feature(vcpu, ARM_FEATURE_MVFR);
- }
- if (arm_feature(vcpu, ARM_FEATURE_V6)) {
- arm_set_feature(vcpu, ARM_FEATURE_V5);
- if (!arm_feature(vcpu, ARM_FEATURE_M)) {
- arm_set_feature(vcpu, ARM_FEATURE_AUXCR);
- }
- }
- if (arm_feature(vcpu, ARM_FEATURE_V5)) {
- arm_set_feature(vcpu, ARM_FEATURE_V4T);
- }
- if (arm_feature(vcpu, ARM_FEATURE_M)) {
- arm_set_feature(vcpu, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(vcpu, ARM_FEATURE_ARM_DIV)) {
- arm_set_feature(vcpu, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(vcpu, ARM_FEATURE_VFP4)) {
- arm_set_feature(vcpu, ARM_FEATURE_VFP3);
- }
- if (arm_feature(vcpu, ARM_FEATURE_VFP3)) {
- arm_set_feature(vcpu, ARM_FEATURE_VFP);
- }
- if (arm_feature(vcpu, ARM_FEATURE_LPAE)) {
- arm_set_feature(vcpu, ARM_FEATURE_PXN);
- }
- }
-
- rc = cpu_vcpu_vfp_init(vcpu);
- if (rc) {
- goto fail_vfp_init;
- }
-
- rc = cpu_vcpu_cp14_init(vcpu);
- if (rc) {
- goto fail_cp14_init;
- }
-
- rc = cpu_vcpu_cp15_init(vcpu, cpuid);
- if (rc) {
- goto fail_cp15_init;
- }
-
- return VMM_OK;
-
-fail_cp15_init:
- if (!vcpu->reset_count) {
- cpu_vcpu_cp14_deinit(vcpu);
- }
-fail_cp14_init:
- if (!vcpu->reset_count) {
- cpu_vcpu_vfp_deinit(vcpu);
- }
-fail_vfp_init:
- if (!vcpu->reset_count) {
- vmm_free(vcpu->arch_priv);
- vcpu->arch_priv = NULL;
- }
-fail:
- return rc;
-}
-
-int arch_vcpu_deinit(struct vmm_vcpu *vcpu)
-{
- int rc;
-
- /* For both Orphan & Normal VCPUs */
- memset(arm_regs(vcpu), 0, sizeof(arch_regs_t));
-
- /* For Orphan VCPUs do nothing else */
- if (!vcpu->is_normal) {
- return VMM_OK;
- }
-
- /* Cleanup CP15 */
- if ((rc = cpu_vcpu_cp15_deinit(vcpu))) {
- return rc;
- }
-
- /* Cleanup CP14 */
- if ((rc = cpu_vcpu_cp14_deinit(vcpu))) {
- return rc;
- }
-
- /* Cleanup VFP */
- if ((rc = cpu_vcpu_vfp_deinit(vcpu))) {
- return rc;
- }
-
- /* Free super regs */
- vmm_free(vcpu->arch_priv);
-
- return VMM_OK;
-}
-
-void arch_vcpu_switch(struct vmm_vcpu *tvcpu,
- struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- u32 ite;
- /* Save user registers & banked registers */
- if (tvcpu) {
- arm_regs(tvcpu)->pc = regs->pc;
- arm_regs(tvcpu)->lr = regs->lr;
- arm_regs(tvcpu)->sp = regs->sp;
- for (ite = 0; ite < CPU_GPR_COUNT; ite++) {
- arm_regs(tvcpu)->gpr[ite] = regs->gpr[ite];
- }
- arm_regs(tvcpu)->cpsr = regs->cpsr;
- arm_regs(tvcpu)->sp_excp = regs->sp_excp;
- if (tvcpu->is_normal) {
- cpu_vcpu_banked_regs_save(arm_priv(tvcpu), regs);
- /* Save VFP regs */
- cpu_vcpu_vfp_regs_save(tvcpu);
- /* Save CP14 regs */
- cpu_vcpu_cp14_regs_save(tvcpu);
- /* Save CP15 regs */
- cpu_vcpu_cp15_regs_save(tvcpu);
- }
- }
- /* Restore user registers & banked registers */
- regs->pc = arm_regs(vcpu)->pc;
- regs->lr = arm_regs(vcpu)->lr;
- regs->sp = arm_regs(vcpu)->sp;
- for (ite = 0; ite < CPU_GPR_COUNT; ite++) {
- regs->gpr[ite] = arm_regs(vcpu)->gpr[ite];
- }
- regs->cpsr = arm_regs(vcpu)->cpsr;
- regs->sp_excp = arm_regs(vcpu)->sp_excp;
- if (vcpu->is_normal) {
- /* Restore VFP regs */
- cpu_vcpu_vfp_regs_restore(vcpu);
- /* Restore CP14 regs */
- cpu_vcpu_cp14_regs_restore(vcpu);
- /* Restore CP15 regs */
- cpu_vcpu_cp15_regs_restore(vcpu);
- /* Restore banked registers */
- cpu_vcpu_banked_regs_restore(arm_priv(vcpu), regs);
- } else {
- /* Restore hypervisor TTBL for Orphan VCPUs */
- if (tvcpu) {
- if (tvcpu->is_normal) {
- cpu_mmu_change_ttbr(cpu_mmu_l1tbl_default());
- }
- } else {
- cpu_mmu_change_ttbr(cpu_mmu_l1tbl_default());
- }
- }
- /* Clear exclusive monitor */
- clrex();
-}
-
-void arch_vcpu_post_switch(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- /* Nothing to do here. */
-}
-
-void arch_vcpu_preempt_orphan(void)
-{
- /* Trigger SVC call from supervisor mode. This will cause
- * do_soft_irq() function to call vmm_scheduler_preempt_orphan()
- */
- asm volatile ("svc #0\t\n");
-}
-
-static void __cpu_vcpu_dump_user_reg(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu, arch_regs_t *regs)
-{
- u32 i;
-
- vmm_cprintf(cdev, "Core Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", regs->sp,
- "LR", regs->lr,
- "PC", regs->pc);
- vmm_cprintf(cdev, " %7s=0x%08x\n",
- "CPSR", cpu_vcpu_cpsr_retrieve(vcpu, regs));
- vmm_cprintf(cdev, "General Purpose Registers");
- for (i = 0; i < CPU_GPR_COUNT; i++) {
- if (i % 3 == 0) {
- vmm_cprintf(cdev, "\n");
- }
- vmm_cprintf(cdev, " %5s%02d=0x%08x",
- "R", i, regs->gpr[i]);
- }
- vmm_cprintf(cdev, "\n");
-}
-
-void cpu_vcpu_dump_user_reg(struct vmm_vcpu *vcpu, arch_regs_t *regs)
-{
- __cpu_vcpu_dump_user_reg(NULL, vcpu, regs);
-}
-
-void arch_vcpu_regs_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu)
-{
- u32 i;
-
- /* For both Normal & Orphan VCPUs */
- __cpu_vcpu_dump_user_reg(cdev, vcpu, arm_regs(vcpu));
-
- /* For only Normal VCPUs */
- if (!vcpu->is_normal) {
- return;
- }
-
- /* Print banked registers */
- vmm_cprintf(cdev, "User Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_usr,
- "LR", arm_priv(vcpu)->lr_usr);
- vmm_cprintf(cdev, "Supervisor Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_svc,
- "LR", arm_priv(vcpu)->lr_svc,
- "SPSR", arm_priv(vcpu)->spsr_svc);
- vmm_cprintf(cdev, "Monitor Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_mon,
- "LR", arm_priv(vcpu)->lr_mon,
- "SPSR", arm_priv(vcpu)->spsr_mon);
- vmm_cprintf(cdev, "Abort Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_abt,
- "LR", arm_priv(vcpu)->lr_abt,
- "SPSR", arm_priv(vcpu)->spsr_abt);
- vmm_cprintf(cdev, "Undefined Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_und,
- "LR", arm_priv(vcpu)->lr_und,
- "SPSR", arm_priv(vcpu)->spsr_und);
- vmm_cprintf(cdev, "IRQ Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "SP", arm_priv(vcpu)->sp_irq,
- "LR", arm_priv(vcpu)->lr_irq,
- "SPSR", arm_priv(vcpu)->spsr_irq);
- vmm_cprintf(cdev, "FIQ Mode Registers (Banked)\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x",
- "SP", arm_priv(vcpu)->sp_fiq,
- "LR", arm_priv(vcpu)->lr_fiq,
- "SPSR", arm_priv(vcpu)->spsr_fiq);
- for (i = 0; i < 5; i++) {
- if (i % 3 == 0) {
- vmm_cprintf(cdev, "\n");
- }
- vmm_cprintf(cdev, " %5s%02d=0x%08x",
- "R", (i + 8), arm_priv(vcpu)->gpr_fiq[i]);
- }
- vmm_cprintf(cdev, "\n");
-
- /* Print VFP registers */
- cpu_vcpu_vfp_regs_dump(cdev, vcpu);
-
- /* Print CP14 registers */
- cpu_vcpu_cp14_regs_dump(cdev, vcpu);
-
- /* Print CP15 registers */
- cpu_vcpu_cp15_regs_dump(cdev, vcpu);
-}
-
-void arch_vcpu_stat_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu)
-{
- /* For now no arch specific stats */
-}
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_hypercall_arm.c b/arch/arm/cpu/arm32/cpu_vcpu_hypercall_arm.c
deleted file mode 100644
index f1f2ec9c..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_hypercall_arm.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_emulate_arm.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code to emulate ARM hypercall instructions
- */
-
-#include <vmm_error.h>
-#include <vmm_stdio.h>
-#include <vmm_vcpu_irq.h>
-#include <vmm_scheduler.h>
-#include <arch_cpu.h>
-#include <arch_regs.h>
-#include <cpu_defines.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_vcpu_mem.h>
-#include <cpu_vcpu_hypercall_arm.h>
-#include <emulate_arm.h>
-#include <emulate_psci.h>
-
-/** Emulate 'cps' hypercall */
-static int arm_hypercall_cps(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- register u32 cpsr, mask, imod, mode;
- imod = ARM_INST_BITS(inst,
- ARM_HYPERCALL_CPS_IMOD_END,
- ARM_HYPERCALL_CPS_IMOD_START);
- mode = ARM_INST_BITS(inst,
- ARM_HYPERCALL_CPS_MODE_END,
- ARM_HYPERCALL_CPS_MODE_START);
- cpsr = 0x0;
- mask = 0x0;
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_CPS_M_START)) {
- cpsr |= mode;
- mask |= CPSR_MODE_MASK;
- }
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_CPS_A_START)) {
- if (imod == 0x2) {
- cpsr &= ~CPSR_ASYNC_ABORT_DISABLED;
- } else if (imod == 0x3) {
- cpsr |= CPSR_ASYNC_ABORT_DISABLED;
- }
- mask |= CPSR_ASYNC_ABORT_DISABLED;
- }
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_CPS_I_START)) {
- if (imod == 0x2) {
- cpsr &= ~CPSR_IRQ_DISABLED;
- } else if (imod == 0x3) {
- cpsr |= CPSR_IRQ_DISABLED;
- }
- mask |= CPSR_IRQ_DISABLED;
- }
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_CPS_F_START)) {
- if (imod == 0x2) {
- cpsr &= ~CPSR_FIQ_DISABLED;
- } else if (imod == 0x3) {
- cpsr |= CPSR_FIQ_DISABLED;
- }
- mask |= CPSR_FIQ_DISABLED;
- }
- cpu_vcpu_cpsr_update(vcpu, regs, cpsr, mask);
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'mrs' hypercall */
-static int arm_hypercall_mrs(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- register u32 Rd;
- Rd = ARM_INST_BITS(inst,
- ARM_HYPERCALL_MRS_RD_END,
- ARM_HYPERCALL_MRS_RD_START);
- if (Rd == 15) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_MRS_R_START)) {
- cpu_vcpu_reg_write(vcpu, regs, Rd,
- cpu_vcpu_spsr_retrieve(vcpu));
- } else {
- cpu_vcpu_reg_write(vcpu, regs, Rd,
- cpu_vcpu_cpsr_retrieve(vcpu, regs));
- }
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'msr_i' hypercall */
-static int arm_hypercall_msr_i(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- register u32 mask, imm12, psr;
- mask = ARM_INST_BITS(inst,
- ARM_HYPERCALL_MSR_I_MASK_END,
- ARM_HYPERCALL_MSR_I_MASK_START);
- imm12 = ARM_INST_BITS(inst,
- ARM_HYPERCALL_MSR_I_IMM12_END,
- ARM_HYPERCALL_MSR_I_IMM12_START);
- if (!mask) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- mask |= (mask & 0x8) ? 0xFF000000 : 0x00;
- mask |= (mask & 0x4) ? 0xFF0000 : 0x00;
- mask |= (mask & 0x2) ? 0xFF00 : 0x00;
- mask |= (mask & 0x1) ? 0xFF : 0x00;
- psr = arm_expand_imm(regs, imm12);
- psr &= mask;
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_MSR_I_R_START)) {
- cpu_vcpu_spsr_update(vcpu, psr, mask);
- } else {
- cpu_vcpu_cpsr_update(vcpu, regs, psr, mask);
- }
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'msr_r' hypercall */
-static int arm_hypercall_msr_r(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- register u32 mask, Rn, psr;
- mask = ARM_INST_BITS(inst,
- ARM_HYPERCALL_MSR_R_MASK_END,
- ARM_HYPERCALL_MSR_R_MASK_START);
- Rn = ARM_INST_BITS(inst,
- ARM_HYPERCALL_MSR_R_RN_END,
- ARM_HYPERCALL_MSR_R_RN_START);
- if (!mask || (Rn == 15)) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- mask |= (mask & 0x8) ? 0xFF000000 : 0x00;
- mask |= (mask & 0x4) ? 0xFF0000 : 0x00;
- mask |= (mask & 0x2) ? 0xFF00 : 0x00;
- mask |= (mask & 0x1) ? 0xFF : 0x00;
- psr = cpu_vcpu_reg_read(vcpu, regs, Rn);
- psr &= mask;
- if (ARM_INST_BIT(inst, ARM_HYPERCALL_MSR_R_R_START)) {
- cpu_vcpu_spsr_update(vcpu, psr, mask);
- } else {
- cpu_vcpu_cpsr_update(vcpu, regs, psr, mask);
- }
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'rfe' hypercall */
-static int arm_hypercall_rfe(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 data;
- register int rc;
- register u32 Rn, P, U, W;
- register u32 address;
- Rn = ARM_INST_BITS(inst,
- ARM_HYPERCALL_RFE_RN_END,
- ARM_HYPERCALL_RFE_RN_START);
- if (Rn == 15) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- P = ARM_INST_BIT(inst, ARM_HYPERCALL_RFE_P_START);
- U = ARM_INST_BIT(inst, ARM_HYPERCALL_RFE_U_START);
- W = ARM_INST_BIT(inst, ARM_HYPERCALL_RFE_W_START);
- switch (arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_FIQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_FIQ);
- break;
- case CPSR_MODE_IRQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_IRQ);
- break;
- case CPSR_MODE_SYSTEM: /* fall-through */
- case CPSR_MODE_SUPERVISOR:
- vmm_vcpu_irq_deassert(vcpu, CPU_SOFT_IRQ);
- break;
- case CPSR_MODE_ABORT:
- vmm_vcpu_irq_deassert(vcpu, CPU_PREFETCH_ABORT_IRQ);
- vmm_vcpu_irq_deassert(vcpu, CPU_DATA_ABORT_IRQ);
- break;
- case CPSR_MODE_UNDEFINED:
- vmm_vcpu_irq_deassert(vcpu, CPU_UNDEF_INST_IRQ);
- break;
- default:
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- };
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? address : (address - 8);
- address = (P == U) ? (address + 4) : address;
- data = 0x0;
- if ((rc = cpu_vcpu_mem_read(vcpu, regs, address + 4,
- &data, 4, FALSE))) {
- return rc;
- }
- cpu_vcpu_cpsr_update(vcpu, regs, data, CPSR_ALLBITS_MASK);
- data = 0x0;
- if ((rc = cpu_vcpu_mem_read(vcpu, regs, address,
- &data, 4, FALSE))) {
- return rc;
- }
- regs->pc = data;
- if (W == 1) {
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? (address + 8) : (address - 8);
- cpu_vcpu_reg_write(vcpu, regs, Rn, address);
- }
- return VMM_OK;
-}
-
-/** Emulate 'srs' hypercall */
-static int arm_hypercall_srs(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 data;
- register int rc;
- register u32 P, U, W, mode;
- register u32 cpsr, base, address;
- P = ARM_INST_BIT(inst, ARM_HYPERCALL_SRS_P_START);
- U = ARM_INST_BIT(inst, ARM_HYPERCALL_SRS_U_START);
- W = ARM_INST_BIT(inst, ARM_HYPERCALL_SRS_W_START);
- mode = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SRS_MODE_END,
- ARM_HYPERCALL_SRS_MODE_START);
- cpsr = arm_priv(vcpu)->cpsr & CPSR_MODE_MASK;
- if ((cpsr == CPSR_MODE_USER) ||
- (cpsr == CPSR_MODE_SYSTEM)) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- base = cpu_vcpu_regmode_read(vcpu, regs, mode, 13);
- address = (U == 1) ? base : (base - 8);
- address = (P == U) ? (address + 4) : address;
- data = regs->lr;
- if ((rc = cpu_vcpu_mem_write(vcpu, regs, address,
- &data, 4, FALSE))) {
- return rc;
- }
- address += 4;
- data = cpu_vcpu_spsr_retrieve(vcpu);
- if ((rc = cpu_vcpu_mem_write(vcpu, regs, address,
- &data, 4, FALSE))) {
- return rc;
- }
- if (W == 1) {
- address = (U == 1) ? (base + 8) : (base - 8);
- cpu_vcpu_regmode_write(vcpu, regs, mode, 13, address);
- }
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'wfi' hypercall */
-static int arm_hypercall_wfi(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- /* Wait for irq on this vcpu */
- vmm_vcpu_irq_wait(vcpu);
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'wfe' hypercall */
-static int arm_hypercall_wfe(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- /* give up the cpu */
- vmm_scheduler_yield();
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'yield' hypercall */
-static int arm_hypercall_yield(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- /* give up the cpu */
- vmm_scheduler_yield();
- regs->pc += 4;
- return VMM_OK;
-}
-
-static int arm_hypercall_unused(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- return VMM_EFAIL;
-}
-
-static int (* const wfx_funcs[]) (u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu) =
-{
- arm_hypercall_wfi, /* ARM_HYPERCALL_WFI_SUBID */
- arm_hypercall_wfe, /* ARM_HYPERCALL_WFE_SUBID */
- arm_hypercall_yield, /* ARM_HYPERCALL_YIELD_SUBID */
- arm_hypercall_unused /* not used yet */
-};
-
-/** Emulate 'wfi', 'wfe', 'sev', 'yield' hypercall */
-static int arm_hypercall_wfx(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 subid = ARM_INST_DECODE(inst,
- ARM_INST_HYPERCALL_WFX_MASK,
- ARM_INST_HYPERCALL_WFX_SHIFT);
-
- return wfx_funcs[subid] (inst, regs, vcpu);
-}
-
-/** Emulate 'smc' hypercall */
-static int arm_hypercall_smc(u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- int rc;
-
- /* Treat this as PSCI call and emulate it */
- rc = emulate_psci_call(vcpu, regs, TRUE);
- if (rc) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- } else {
- regs->pc += 4;
- }
-
- return VMM_OK;
-}
-
-/** Emulate 'ldm_ue' hypercall */
-static int arm_hypercall_ldm_ue(u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 ndata[16];
- register int rc;
- register u32 Rn, U, P, W, reg_list;
- register u32 address, i, pos, length;
- Rn = ARM_INST_BITS(inst,
- ARM_HYPERCALL_LDM_UE_RN_END,
- ARM_HYPERCALL_LDM_UE_RN_START);
- P = ((id - ARM_HYPERCALL_LDM_UE_ID0) & 0x4) >> 2;
- U = ((id - ARM_HYPERCALL_LDM_UE_ID0) & 0x2) >> 1;
- W = ((id - ARM_HYPERCALL_LDM_UE_ID0) & 0x1);
- reg_list = ARM_INST_BITS(inst,
- ARM_HYPERCALL_LDM_UE_REGLIST_END,
- ARM_HYPERCALL_LDM_UE_REGLIST_START);
- if (Rn == 15) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- if (reg_list & 0x8000) {
- /* LDM (Exception Return) */
- if ((W == 1) && (reg_list & (0x1 << Rn))) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- switch (arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_FIQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_FIQ);
- break;
- case CPSR_MODE_IRQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_IRQ);
- break;
- case CPSR_MODE_SUPERVISOR:
- vmm_vcpu_irq_deassert(vcpu, CPU_SOFT_IRQ);
- break;
- case CPSR_MODE_ABORT:
- vmm_vcpu_irq_deassert(vcpu, CPU_PREFETCH_ABORT_IRQ);
- vmm_vcpu_irq_deassert(vcpu, CPU_DATA_ABORT_IRQ);
- break;
- case CPSR_MODE_UNDEFINED:
- vmm_vcpu_irq_deassert(vcpu, CPU_UNDEF_INST_IRQ);
- break;
- default:
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- };
- length = 4;
- for (i = 0; i < 15; i++) {
- if (reg_list & (0x1 << i)) {
- length += 4;
- }
- }
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? address : address - length;
- address = (P == U) ? (address + 4) : address;
- if (((address + length - 4) & ~TTBL_MIN_PAGE_MASK) !=
- (address & ~TTBL_MIN_PAGE_MASK)) {
- pos = TTBL_MIN_PAGE_SIZE -
- (address & TTBL_MIN_PAGE_MASK);
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address, &ndata, pos, FALSE))) {
- return rc;
- }
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address + pos, &ndata[pos >> 2],
- length - pos, FALSE))) {
- return rc;
- }
- } else {
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address, &ndata, length, FALSE))) {
- return rc;
- }
- }
- address = address + length - 4;
- pos = 0;
- for (i = 0; i < 15; i++) {
- if (reg_list & (0x1 << i)) {
- cpu_vcpu_reg_write(vcpu, regs,
- i, ndata[pos]);
- pos++;
- }
- }
- if ((W == 1) && !(reg_list & (0x1 << Rn))) {
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? address + length :
- address - length;
- cpu_vcpu_reg_write(vcpu, regs, Rn, address);
- }
- cpu_vcpu_cpsr_update(vcpu, regs,
- cpu_vcpu_spsr_retrieve(vcpu),
- CPSR_ALLBITS_MASK);
- regs->pc = ndata[pos];
- } else {
- /* LDM (User Registers) */
- if ((W == 1) || !reg_list) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- i = arm_priv(vcpu)->cpsr & CPSR_MODE_MASK;
- if ((i == CPSR_MODE_USER) || (i == CPSR_MODE_SYSTEM)) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- length = 0;
- for (i = 0; i < 15; i++) {
- if (reg_list & (0x1 << i)) {
- length += 4;
- }
- }
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? address : address - length;
- address = (P == U) ? (address + 4) : address;
- if (((address + length - 4) & ~TTBL_MIN_PAGE_MASK) !=
- (address & ~TTBL_MIN_PAGE_MASK)) {
- pos = TTBL_MIN_PAGE_SIZE -
- (address & TTBL_MIN_PAGE_MASK);
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address, &ndata, pos, FALSE))) {
- return rc;
- }
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address + pos, &ndata[pos >> 2],
- length - pos, FALSE))) {
- return rc;
- }
- } else {
- if ((rc = cpu_vcpu_mem_read(vcpu, regs,
- address, &ndata, length, FALSE))) {
- return rc;
- }
- }
- pos = 0;
- for (i = 0; i < 15; i++) {
- if (reg_list & (0x1 << i)) {
- cpu_vcpu_regmode_write(vcpu, regs,
- CPSR_MODE_USER,
- i, ndata[pos]);
- pos++;
- }
- }
- regs->pc += 4;
- }
- return VMM_OK;
-}
-
-/** Emulate 'stm_u' hypercall */
-static int arm_hypercall_stm_u(u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 ndata[16];
- register int rc;
- register u32 Rn, P, U, reg_list;
- register u32 i, pos, length, address;
- Rn = ARM_INST_BITS(inst,
- ARM_HYPERCALL_STM_U_RN_END,
- ARM_HYPERCALL_STM_U_RN_START);
- reg_list = ARM_INST_BITS(inst,
- ARM_HYPERCALL_STM_U_REGLIST_END,
- ARM_HYPERCALL_STM_U_REGLIST_START);
- if ((Rn == 15) || !reg_list) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- P = ((id - ARM_HYPERCALL_STM_U_ID0) & 0x2) >> 1;
- U = ((id - ARM_HYPERCALL_STM_U_ID0) & 0x1);
- i = arm_priv(vcpu)->cpsr & CPSR_MODE_MASK;
- if ((i == CPSR_MODE_USER) || (i == CPSR_MODE_SYSTEM)) {
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- }
- length = 0;
- for (i = 0; i < 16; i++) {
- if (reg_list & (0x1 << i)) {
- length += 4;
- }
- }
- address = cpu_vcpu_reg_read(vcpu, regs, Rn);
- address = (U == 1) ? address : address - length;
- address = (P == U) ? address + 4 : address;
- pos = 0;
- for (i = 0; i < 16; i++) {
- if (reg_list & (0x1 << i)) {
- ndata[pos] = cpu_vcpu_regmode_read(vcpu, regs,
- CPSR_MODE_USER, i);
- pos++;
- }
- }
- if (((address + length - 4) & ~TTBL_MIN_PAGE_MASK) !=
- (address & ~TTBL_MIN_PAGE_MASK)) {
- pos = TTBL_MIN_PAGE_SIZE -
- (address & TTBL_MIN_PAGE_MASK);
- if ((rc = cpu_vcpu_mem_write(vcpu, regs,
- address, &ndata, pos, FALSE))) {
- return rc;
- }
- if ((rc = cpu_vcpu_mem_write(vcpu, regs,
- address + pos, &ndata[pos >> 2],
- length - pos, FALSE))) {
- return rc;
- }
- } else {
- if ((rc = cpu_vcpu_mem_write(vcpu, regs,
- address, &ndata, length, FALSE))) {
- return rc;
- }
- }
- regs->pc += 4;
- return VMM_OK;
-}
-
-/** Emulate 'subs_rel' hypercall */
-static int arm_hypercall_subs_rel(u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 shift_t;
- register u32 opcode, Rn, imm, type, Rm;
- register u32 operand2, result;
- opcode = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_OPCODE_END,
- ARM_HYPERCALL_SUBS_REL_OPCODE_START);
- Rn = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_RN_END,
- ARM_HYPERCALL_SUBS_REL_RN_START);
- switch (arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) {
- case CPSR_MODE_FIQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_FIQ);
- break;
- case CPSR_MODE_IRQ:
- vmm_vcpu_irq_deassert(vcpu, CPU_EXTERNAL_IRQ);
- break;
- case CPSR_MODE_SYSTEM: /* fall-through */
- case CPSR_MODE_SUPERVISOR:
- vmm_vcpu_irq_deassert(vcpu, CPU_SOFT_IRQ);
- break;
- case CPSR_MODE_ABORT:
- vmm_vcpu_irq_deassert(vcpu, CPU_PREFETCH_ABORT_IRQ);
- vmm_vcpu_irq_deassert(vcpu, CPU_DATA_ABORT_IRQ);
- break;
- case CPSR_MODE_UNDEFINED:
- vmm_vcpu_irq_deassert(vcpu, CPU_UNDEF_INST_IRQ);
- break;
- default:
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- };
- if (id == ARM_HYPERCALL_SUBS_REL_ID0) {
- /* Register form */
- imm = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_IMM5_END,
- ARM_HYPERCALL_SUBS_REL_IMM5_START);
- type = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_TYPE_END,
- ARM_HYPERCALL_SUBS_REL_TYPE_START);
- Rm = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_RM_END,
- ARM_HYPERCALL_SUBS_REL_RM_START);
- type = arm_decode_imm_shift(type, imm, &shift_t);
- operand2 = cpu_vcpu_reg_read(vcpu, regs, Rm);
- operand2 = arm_shift(operand2, shift_t, type,
- (regs->cpsr & CPSR_CARRY_MASK) >>
- CPSR_CARRY_SHIFT);
- } else {
- /* Immediate value */
- imm = ARM_INST_BITS(inst,
- ARM_HYPERCALL_SUBS_REL_IMM12_END,
- ARM_HYPERCALL_SUBS_REL_IMM12_START);
- operand2 = arm_expand_imm(regs, imm);
- }
- result = cpu_vcpu_reg_read(vcpu, regs, Rn);
- switch (opcode) {
- case 0x0: /* AND */
- result = result & operand2;
- break;
- case 0x1: /* EOR */
- result = result ^ operand2;
- break;
- case 0x2: /* SUB */
- result = arm_add_with_carry(result, ~operand2,
- 1, NULL, NULL);
- break;
- case 0x3: /* RSB */
- result = arm_add_with_carry(~result, operand2,
- 1, NULL, NULL);
- break;
- case 0x4: /* ADD */
- result = arm_add_with_carry(result, operand2,
- 0, NULL, NULL);
- break;
- case 0x5: /* ADC */
- if (regs->cpsr & CPSR_CARRY_MASK) {
- result = arm_add_with_carry(result, operand2,
- 1, NULL, NULL);
- } else {
- result = arm_add_with_carry(result, operand2,
- 0, NULL, NULL);
- }
- break;
- case 0x6: /* SBC */
- if (regs->cpsr & CPSR_CARRY_MASK) {
- result = arm_add_with_carry(result, ~operand2,
- 1, NULL, NULL);
- } else {
- result = arm_add_with_carry(result, ~operand2,
- 0, NULL, NULL);
- }
- break;
- case 0x7: /* RSC */
- if (regs->cpsr & CPSR_CARRY_MASK) {
- result = arm_add_with_carry(~result, operand2,
- 1, NULL, NULL);
- } else {
- result = arm_add_with_carry(~result, operand2,
- 0, NULL, NULL);
- }
- break;
- case 0xC: /* ORR*/
- result = result | operand2;
- break;
- case 0xD: /* MOV */
- result = operand2;
- break;
- case 0xE: /* BIC */
- result = result & ~operand2;
- break;
- case 0xF: /* MVN */
- result = ~operand2;
- break;
- default:
- arm_unpredictable(regs, vcpu, inst, __func__);
- return VMM_EFAIL;
- break;
- };
- cpu_vcpu_cpsr_update(vcpu, regs,
- cpu_vcpu_spsr_retrieve(vcpu),
- CPSR_ALLBITS_MASK);
- regs->pc = result;
- return VMM_OK;
-}
-
-static int (* const cps_and_co_funcs[]) (u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu) =
-{
- arm_hypercall_cps, /* ARM_HYPERCALL_CPS_SUBID */
- arm_hypercall_mrs, /* ARM_HYPERCALL_MRS_SUBID */
- arm_hypercall_msr_i, /* ARM_HYPERCALL_MSR_I_SUBID */
- arm_hypercall_msr_r, /* ARM_HYPERCALL_MSR_R_SUBID */
- arm_hypercall_rfe, /* ARM_HYPERCALL_RFE_SUBID */
- arm_hypercall_srs, /* ARM_HYPERCALL_SRS_SUBID */
- arm_hypercall_wfx, /* ARM_HYPERCALL_WFI_SUBID */
- arm_hypercall_smc /* ARM_HYPERCALL_SMC_SUBID */
-};
-
-static int arm_hypercall_cps_and_co(u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- u32 subid = ARM_INST_DECODE(inst,
- ARM_INST_HYPERCALL_SUBID_MASK,
- ARM_INST_HYPERCALL_SUBID_SHIFT);
-
- return cps_and_co_funcs[subid] (inst, regs, vcpu);
-}
-
-static int arm_hypercall_svc(u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu)
-{
- vmm_vcpu_irq_assert(vcpu, CPU_SOFT_IRQ, 0x0);
- return VMM_OK;
-}
-
-static int (* const hcall_funcs[]) (u32 id, u32 inst,
- arch_regs_t *regs, struct vmm_vcpu *vcpu) =
-{
- arm_hypercall_cps_and_co, /* ARM_HYPERCALL_CPS_ID */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID0 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID1 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID2 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID3 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID4 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID5 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID6 */
- arm_hypercall_ldm_ue, /* ARM_HYPERCALL_LDM_UE_ID7 */
- arm_hypercall_stm_u, /* ARM_HYPERCALL_STM_U_ID0 */
- arm_hypercall_stm_u, /* ARM_HYPERCALL_STM_U_ID1 */
- arm_hypercall_stm_u, /* ARM_HYPERCALL_STM_U_ID2 */
- arm_hypercall_stm_u, /* ARM_HYPERCALL_STM_U_ID3 */
- arm_hypercall_subs_rel, /* ARM_HYPERCALL_SUBS_REL_ID0 */
- arm_hypercall_subs_rel, /* ARM_HYPERCALL_SUBS_REL_ID1 */
- arm_hypercall_svc, /* ARM_HYPERCALL_SVC_ID */
-};
-
-int cpu_vcpu_hypercall_arm(struct vmm_vcpu *vcpu,
- arch_regs_t *regs, u32 inst)
-{
- u32 id = ARM_INST_DECODE(inst,
- ARM_INST_HYPERCALL_ID_MASK,
- ARM_INST_HYPERCALL_ID_SHIFT);
-
- return hcall_funcs[id] (id, inst, regs, vcpu);
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_hypercall_thumb.c b/arch/arm/cpu/arm32/cpu_vcpu_hypercall_thumb.c
deleted file mode 100644
index e26eb000..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_hypercall_thumb.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_emulate_thumb.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code to emulate Thumb instructions
- */
-
-#include <vmm_error.h>
-#include <vmm_vcpu_irq.h>
-#include <vmm_scheduler.h>
-#include <arch_cpu.h>
-#include <arch_regs.h>
-#include <emulate_thumb.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_vcpu_hypercall_thumb.h>
-
-/* FIXME: */
-int cpu_vcpu_hypercall_thumb(struct vmm_vcpu *vcpu, arch_regs_t *regs, u32 inst)
-{
- /* Sanity check */
- if (!vcpu) {
- return VMM_EFAIL;
- }
- if (!vcpu->is_normal) {
- return VMM_EFAIL;
- }
-
- /* Thumb mode emulation not supported so halt the VCPU */
- cpu_vcpu_halt(vcpu, regs);
-
- return VMM_OK;
-}
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_irq.c b/arch/arm/cpu/arm32/cpu_vcpu_irq.c
deleted file mode 100644
index 73d2d986..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_irq.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_irq.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief source code for handling vcpu interrupts
- */
-
-#include <vmm_error.h>
-#include <vmm_vcpu_irq.h>
-#include <arch_cpu.h>
-#include <cpu_vcpu_cp15.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_defines.h>
-#include <arm_features.h>
-
-u32 arch_vcpu_irq_count(struct vmm_vcpu *vcpu)
-{
- return CPU_IRQ_NR;
-}
-
-u32 arch_vcpu_irq_priority(struct vmm_vcpu *vcpu, u32 irq_no)
-{
- u32 ret = 3;
-
- switch (irq_no) {
- case CPU_RESET_IRQ:
- ret = 0;
- break;
- case CPU_UNDEF_INST_IRQ:
- ret = 1;
- break;
- case CPU_SOFT_IRQ:
- ret = 2;
- break;
- case CPU_PREFETCH_ABORT_IRQ:
- ret = 2;
- break;
- case CPU_DATA_ABORT_IRQ:
- ret = 2;
- break;
- case CPU_NOT_USED_IRQ:
- ret = 2;
- break;
- case CPU_EXTERNAL_IRQ:
- ret = 2;
- break;
- case CPU_EXTERNAL_FIQ:
- ret = 2;
- break;
- default:
- break;
- };
- return ret;
-}
-
-int arch_vcpu_irq_assert(struct vmm_vcpu *vcpu, u32 irq_no, u64 reason)
-{
- /* We don't implement this. */
- return VMM_OK;
-}
-
-bool arch_vcpu_irq_can_execute_multiple(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- return FALSE;
-}
-
-int arch_vcpu_irq_execute(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 irq_no, u64 reason)
-{
- u32 old_cpsr, new_cpsr, new_mode, new_flags, lr_off;
- virtual_addr_t new_pc;
-
- old_cpsr = cpu_vcpu_cpsr_retrieve(vcpu, regs);
- new_cpsr = old_cpsr;
- new_flags = 0x0;
-
- switch(irq_no) {
- case CPU_RESET_IRQ:
- new_mode = CPSR_MODE_SUPERVISOR;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- new_flags |= CPSR_FIQ_DISABLED;
- lr_off = 0;
- break;
- case CPU_UNDEF_INST_IRQ:
- new_mode = CPSR_MODE_UNDEFINED;
- new_flags |= CPSR_IRQ_DISABLED;
- lr_off = 4;
- break;
- case CPU_SOFT_IRQ:
- new_mode = CPSR_MODE_SUPERVISOR;
- new_flags |= CPSR_IRQ_DISABLED;
- lr_off = 4;
- break;
- case CPU_PREFETCH_ABORT_IRQ:
- new_mode = CPSR_MODE_ABORT;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- lr_off = 4;
- break;
- case CPU_DATA_ABORT_IRQ:
- new_mode = CPSR_MODE_ABORT;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- lr_off = 8;
- break;
- case CPU_NOT_USED_IRQ:
- new_mode = CPSR_MODE_SUPERVISOR;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- new_flags |= CPSR_FIQ_DISABLED;
- lr_off = 0;
- break;
- case CPU_EXTERNAL_IRQ:
- if (old_cpsr & CPSR_IRQ_DISABLED) {
- return VMM_EFAIL;
- }
- new_mode = CPSR_MODE_IRQ;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- lr_off = 4;
- break;
- case CPU_EXTERNAL_FIQ:
- if (old_cpsr & CPSR_FIQ_DISABLED) {
- return VMM_EFAIL;
- }
- new_mode = CPSR_MODE_FIQ;
- new_flags |= CPSR_ASYNC_ABORT_DISABLED;
- new_flags |= CPSR_IRQ_DISABLED;
- new_flags |= CPSR_FIQ_DISABLED;
- lr_off = 4;
- break;
- default:
- return VMM_EFAIL;
- break;
- };
-
- new_pc = cpu_vcpu_cp15_vector_addr(vcpu, irq_no);
- new_cpsr &= ~CPSR_MODE_MASK;
- new_cpsr |= (new_mode | new_flags);
- new_cpsr &= ~(CPSR_IT1_MASK | CPSR_IT2_MASK);
- if (arm_feature(vcpu, ARM_FEATURE_V4T)) {
- if (arm_priv(vcpu)->cp15.c1_sctlr & (1 << 30)) {
- new_cpsr |= CPSR_THUMB_ENABLED;
- } else {
- new_cpsr &= ~CPSR_THUMB_ENABLED;
- }
- }
- cpu_vcpu_cpsr_update(vcpu, regs, new_cpsr, CPSR_ALLBITS_MASK);
- cpu_vcpu_spsr_update(vcpu, old_cpsr, CPSR_ALLBITS_MASK);
- regs->lr = regs->pc + lr_off;
- regs->pc = new_pc;
-
- return VMM_OK;
-}
-
-int arch_vcpu_irq_clear(struct vmm_vcpu *vcpu, u32 irq_no, u64 reason)
-{
- /* We don't implement this. */
- return VMM_OK;
-}
-
-int arch_vcpu_irq_deassert(struct vmm_vcpu *vcpu, u32 irq_no, u64 reason)
-{
- /* We don't implement this. */
- return VMM_OK;
-}
-
-bool arch_vcpu_irq_pending(struct vmm_vcpu *vcpu)
-{
- return false;
-}
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_mem.c b/arch/arm/cpu/arm32/cpu_vcpu_mem.c
deleted file mode 100644
index 5aa2c925..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_mem.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_mem.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief VCPU CP15 Emulation
- * @details This source file for VCPU memory read/write emulation
- */
-
-#include <vmm_error.h>
-#include <vmm_devemu.h>
-#include <cpu_defines.h>
-#include <cpu_inline_asm.h>
-#include <cpu_vcpu_helper.h>
-#include <cpu_vcpu_cp15.h>
-#include <cpu_vcpu_mem.h>
-
-int cpu_vcpu_mem_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *dst, u32 dst_len,
- bool force_unpriv)
-{
- struct cpu_page pg;
- register int rc = VMM_OK;
- register u32 vind;
- register struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
- register struct cpu_page *pgp;
-
- if ((addr & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) == cp15->ovect_base) {
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) ==
- CPSR_MODE_USER) {
- force_unpriv = TRUE;
- }
- if ((vind = cpu_vcpu_cp15_find_page(vcpu, addr,
- CP15_ACCESS_READ,
- force_unpriv, &pg))) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = (vind >> 4);
- vinfo.dom = (vind & 0xF);
- vinfo.wnr = 0;
- vinfo.xn = 1;
- cpu_vcpu_cp15_assert_fault(vcpu, &vinfo);
- return VMM_EFAIL;
- }
- vind = addr & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
- switch (dst_len) {
- case 4:
- vind = vind >> 2;
- *((u32 *)dst) = arm_guest_priv(vcpu->guest)->ovect[vind];
- break;
- case 2:
- vind = vind >> 1;
- *((u16 *) dst) =
- ((u16 *)arm_guest_priv(vcpu->guest)->ovect)[vind];
- break;
- case 1:
- *((u8 *) dst) =
- ((u8 *)arm_guest_priv(vcpu->guest)->ovect)[vind];
- break;
- default:
- return VMM_EFAIL;
- break;
- };
- } else {
- if (cp15->virtio_active) {
- pgp = &cp15->virtio_page;
- } else {
- pgp = &pg;
- rc = cpu_mmu_get_page(cp15->l1, addr, &pg);
- if (rc == VMM_ENOTAVAIL) {
- if (pgp->va) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = DFSR_FS_TRANS_FAULT_PAGE;
- vinfo.dom = 0;
- vinfo.wnr = 0;
- vinfo.xn = 1;
- rc = cpu_vcpu_cp15_trans_fault(vcpu,
- &vinfo, force_unpriv);
- } else {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = DFSR_FS_TRANS_FAULT_SECTION;
- vinfo.dom = 0;
- vinfo.wnr = 0;
- vinfo.xn = 1;
- rc = cpu_vcpu_cp15_trans_fault(vcpu,
- &vinfo, force_unpriv);
- }
- if (!rc) {
- rc = cpu_mmu_get_page(cp15->l1, addr, pgp);
- }
- }
- if (rc) {
- cpu_vcpu_halt(vcpu, regs);
- return rc;
- }
- }
- switch (pgp->ap) {
-#if !defined(CONFIG_ARMV5)
- case TTBL_AP_SR_U:
-#endif
- case TTBL_AP_SRW_U:
- return vmm_devemu_emulate_read(vcpu,
- (addr - pgp->va) +
- pgp->pa, dst, dst_len,
- VMM_DEVEMU_NATIVE_ENDIAN);
- break;
- case TTBL_AP_SRW_UR:
- case TTBL_AP_SRW_URW:
- switch (dst_len) {
- case 4:
- *((u32 *) dst) = *((u32 *)addr);
- break;
- case 2:
- *((u16 *) dst) = *((u16 *)addr);
- break;
- case 1:
- *((u8 *) dst) = *((u8 *)addr);
- break;
- default:
- if (dst_len < 4) {
- return VMM_EFAIL;
- }
- vind = dst_len >> 2;
- while (vind) {
- ((u32 *) dst)[vind-1] =
- ((u32 *) addr)[vind-1];
- vind--;
- }
- break;
- };
- break;
- default:
- /* Remove fault address from VTLB and restart.
- * Doing this will force us to do TTBL walk If MMU
- * is enabled then appropriate fault will be generated
- */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, addr);
- return VMM_EFAIL;
- break;
- };
- }
- return VMM_OK;
-}
-
-int cpu_vcpu_mem_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *src, u32 src_len,
- bool force_unpriv)
-{
- struct cpu_page pg;
- register int rc = VMM_OK;
- register u32 vind;
- register struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
- register struct cpu_page *pgp;
-
- if ((addr & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) == cp15->ovect_base) {
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) ==
- CPSR_MODE_USER) {
- force_unpriv = TRUE;
- }
- if ((vind = cpu_vcpu_cp15_find_page(vcpu, addr,
- CP15_ACCESS_WRITE,
- force_unpriv, &pg))) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = (vind >> 4);
- vinfo.dom = (vind & 0xF);
- vinfo.wnr = 1;
- vinfo.xn = 1;
- cpu_vcpu_cp15_assert_fault(vcpu, &vinfo);
- return VMM_EFAIL;
- }
- vind = addr & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1);
- switch (src_len) {
- case 4:
- vind = vind >> 2;
- arm_guest_priv(vcpu->guest)->ovect[vind] =
- *((u32 *) src);
- break;
- case 2:
- vind = vind >> 1;
- ((u16 *)arm_guest_priv(vcpu->guest)->ovect)[vind] =
- *((u16 *) src);
- break;
- case 1:
- ((u8 *)arm_guest_priv(vcpu->guest)->ovect)[vind] =
- *((u8 *) src);
- break;
- default:
- return VMM_EFAIL;
- break;
- };
- } else {
- if (cp15->virtio_active) {
- pgp = &cp15->virtio_page;
- } else {
- pgp = &pg;
- rc = cpu_mmu_get_page(cp15->l1, addr, &pg);
- if (rc == VMM_ENOTAVAIL) {
- if (pgp->va) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = DFSR_FS_TRANS_FAULT_PAGE;
- vinfo.dom = 0;
- vinfo.wnr = 1;
- vinfo.xn = 1;
- rc = cpu_vcpu_cp15_trans_fault(vcpu,
- &vinfo, force_unpriv);
- } else {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = DFSR_FS_TRANS_FAULT_SECTION;
- vinfo.dom = 0;
- vinfo.wnr = 1;
- vinfo.xn = 1;
- rc = cpu_vcpu_cp15_trans_fault(vcpu,
- &vinfo, force_unpriv);
- }
- if (!rc) {
- rc = cpu_mmu_get_page(cp15->l1, addr, pgp);
- }
- }
- if (rc) {
- cpu_vcpu_halt(vcpu, regs);
- return rc;
- }
- }
- switch (pgp->ap) {
- case TTBL_AP_SRW_U:
- return vmm_devemu_emulate_write(vcpu,
- (addr - pgp->va) +
- pgp->pa, src, src_len,
- VMM_DEVEMU_NATIVE_ENDIAN);
- break;
- case TTBL_AP_SRW_URW:
- switch (src_len) {
- case 4:
- *((u32 *) addr) = *((u32 *) src);
- break;
- case 2:
- *((u16 *) addr) = *((u16 *) src);
- break;
- case 1:
- *((u8 *) addr) = *((u8 *) src);
- break;
- default:
- if (src_len < 4) {
- return VMM_EFAIL;
- }
- vind = src_len >> 2;
- while (vind) {
- ((u32 *) addr)[vind-1] =
- ((u32 *) src)[vind-1];
- vind--;
- }
- break;
- };
- break;
- default:
- /* Remove fault address from VTLB and restart.
- * Doing this will force us to do TTBL walk If MMU
- * is enabled then appropriate fault will be generated
- */
- cpu_vcpu_cp15_vtlb_flush_va(cp15, addr);
- return VMM_EFAIL;
- break;
- };
- }
- return VMM_OK;
-}
-
-int cpu_vcpu_mem_readex(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *dst, u32 dst_len,
- bool force_unpriv)
-{
- register int ecode;
- struct cpu_page pg;
- u32 vind, data;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- if ((addr & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) == cp15->ovect_base) {
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) ==
- CPSR_MODE_USER) {
- force_unpriv = TRUE;
- }
- if ((ecode = cpu_vcpu_cp15_find_page(vcpu, addr,
- CP15_ACCESS_READ,
- force_unpriv, &pg))) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = (ecode >> 4);
- vinfo.dom = (ecode & 0xF);
- vinfo.wnr = 0;
- vinfo.xn = 1;
- cpu_vcpu_cp15_assert_fault(vcpu, &vinfo);
- return VMM_EFAIL;
- }
- vind = (addr & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1))/4;
- addr = (u32)(&(arm_guest_priv(vcpu->guest)->ovect[vind]));
-
- ldrex(addr, data);
-
- switch (dst_len) {
- case 1:
- *((u8 *)dst) = (u8)data;
- break;
- case 2:
- *((u16 *)dst) = (u16)data;
- break;
- case 4:
- *((u32 *)dst) = data;
- break;
- default:
- return VMM_EFAIL;
- };
- } else {
- /* We do not allow any faulting ldrex on non-ovect region */
- return VMM_EFAIL;
- }
-
- return VMM_OK;
-}
-
-int cpu_vcpu_mem_writeex(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *src, u32 src_len,
- bool force_unpriv)
-{
- register int ecode;
- struct cpu_page pg;
- u32 vind, data;
- struct arm_priv_cp15 *cp15 = &arm_priv(vcpu)->cp15;
-
- if ((addr & ~(TTBL_L2TBL_SMALL_PAGE_SIZE - 1)) == cp15->ovect_base) {
- if ((arm_priv(vcpu)->cpsr & CPSR_MODE_MASK) ==
- CPSR_MODE_USER) {
- force_unpriv = TRUE;
- }
- if ((ecode = cpu_vcpu_cp15_find_page(vcpu, addr,
- CP15_ACCESS_READ,
- force_unpriv, &pg))) {
- struct cpu_vcpu_cp15_fault_info vinfo;
- vinfo.regs = regs;
- vinfo.far = addr;
- vinfo.fs = (ecode >> 4);
- vinfo.dom = (ecode & 0xF);
- vinfo.wnr = 0;
- vinfo.xn = 1;
- cpu_vcpu_cp15_assert_fault(vcpu, &vinfo);
- return VMM_EFAIL;
- }
- vind = (addr & (TTBL_L2TBL_SMALL_PAGE_SIZE - 1))/4;
- addr = (u32)(&(arm_guest_priv(vcpu->guest)->ovect[vind]));
-
- switch (src_len) {
- case 1:
- data = *((u8 *)src);
- break;
- case 2:
- data = *((u16 *)src);
- break;
- case 4:
- data = *((u32 *)src);
- break;
- default:
- return VMM_EFAIL;
- };
-
- strex(addr, data, ecode);
-
- return (ecode == 0) ? VMM_OK : VMM_EFAIL;
- } else {
- /* We do not allow any faulting strex on non-ovect region */
- return VMM_EFAIL;
- }
-
- return VMM_OK;
-}
-
diff --git a/arch/arm/cpu/arm32/cpu_vcpu_vfp.c b/arch/arm/cpu/arm32/cpu_vcpu_vfp.c
deleted file mode 100644
index af78a657..00000000
--- a/arch/arm/cpu/arm32/cpu_vcpu_vfp.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_vfp.c
- * @author Anup Patel (an...@brainfault.org)
- * @brief Source file for VCPU cp10 and cp11 emulation
- */
-
-#include <vmm_error.h>
-#include <vmm_stdio.h>
-#include <arm_features.h>
-#include <cpu_inline_asm.h>
-#include <cpu_vcpu_vfp.h>
-
-bool cpu_vcpu_cp10_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data)
-{
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- switch (opc1) {
- case 7:
- switch (CRn) {
- case 0: /* FPSID */
- if (arm_feature(vcpu, ARM_FEATURE_VFP)) {
- *data = read_fpsid();
- } else {
- goto bad_reg;
- }
- break;
- case 1: /* FPSCR */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- *data = read_fpscr();
- vfp->fpscr = *data;
- } else {
- goto bad_reg;
- }
- break;
- case 6: /* MVFR1 */
- if (arm_feature(vcpu, ARM_FEATURE_MVFR)) {
- *data = read_mvfr1();
- } else {
- goto bad_reg;
- }
- break;
- case 7: /* MVFR0 */
- if (arm_feature(vcpu, ARM_FEATURE_MVFR)) {
- *data = read_mvfr0();
- } else {
- goto bad_reg;
- }
- break;
- case 8: /* FPEXC */
- if (arm_feature(vcpu, ARM_FEATURE_VFP)) {
- *data = read_fpexc();
- vfp->fpexc = *data;
- } else {
- goto bad_reg;
- }
- break;
- case 9: /* FPINST */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- *data = read_fpinst();
- vfp->fpinst = *data;
- } else {
- goto bad_reg;
- }
- break;
- case 10: /* FPINST2 */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- *data = read_fpinst2();
- vfp->fpinst2 = *data;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- return TRUE;
-bad_reg:
- vmm_printf("%s: vcpu=%d opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->id, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-bool cpu_vcpu_cp10_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data)
-{
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- switch (opc1) {
- case 7:
- switch (CRn) {
- case 0: /* FPSID */
- if (arm_feature(vcpu, ARM_FEATURE_VFP)) {
- /* Ignore writes to FPSID */
- } else {
- goto bad_reg;
- }
- break;
- case 1: /* FPSCR */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- write_fpscr(data);
- vfp->fpscr = data;
- } else {
- goto bad_reg;
- }
- break;
- case 6: /* MVFR1 */
- if (arm_feature(vcpu, ARM_FEATURE_MVFR)) {
- /* Ignore writes to MVFR1 */
- } else {
- goto bad_reg;
- }
- break;
- case 7: /* MVFR0 */
- if (arm_feature(vcpu, ARM_FEATURE_MVFR)) {
- /* Ignore writes to MVFR0 */
- } else {
- goto bad_reg;
- }
- break;
- case 8: /* FPEXC */
- if (arm_feature(vcpu, ARM_FEATURE_VFP)) {
- write_fpexc(data);
- vfp->fpexc = data;
- } else {
- goto bad_reg;
- }
- break;
- case 9: /* FPINST */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- write_fpinst(data);
- vfp->fpinst = data;
- } else {
- goto bad_reg;
- }
- break;
- case 10: /* FPINST2 */
- if (arm_feature(vcpu, ARM_FEATURE_VFP) &&
- (vfp->fpexc & FPEXC_EN_MASK)) {
- write_fpinst2(data);
- vfp->fpinst2 = data;
- } else {
- goto bad_reg;
- }
- break;
- default:
- goto bad_reg;
- };
- break;
- default:
- goto bad_reg;
- };
- return TRUE;
-bad_reg:
- vmm_printf("%s: vcpu=%d opc1=%x opc2=%x CRn=%x CRm=%x (invalid)\n",
- __func__, vcpu->id, opc1, opc2, CRn, CRm);
- return FALSE;
-}
-
-void cpu_vcpu_vfp_regs_save(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- /* VFP feature must be available */
- if (!arm_feature(vcpu, ARM_FEATURE_VFP)) {
- return;
- }
-
- /* Save FPEXC */
- vfp->fpexc = read_fpexc();
-
- /* Force enable FPU */
- write_fpexc(vfp->fpexc | FPEXC_EN_MASK);
-
- /* Save FPSCR */
- vfp->fpscr = read_fpscr();
-
- /* Check for sub-architecture */
- if (vfp->fpexc & FPEXC_EX_MASK) {
- /* Save FPINST */
- vfp->fpinst = read_fpinst();
-
- /* Save FPINST2 */
- if (vfp->fpexc & FPEXC_FP2V_MASK) {
- vfp->fpinst2 = read_fpinst2();
- }
-
- /* Disable FPEXC_EX */
- write_fpexc((vfp->fpexc | FPEXC_EN_MASK) & ~FPEXC_EX_MASK);
- }
-
- /* Save {d0-d15} */
- asm volatile("stc p11, cr0, [%0], #32*4"
- : : "r" (vfp->fpregs1));
-
- /* 32x 64 bits registers? */
- if (arm_feature(vcpu, ARM_FEATURE_VFP3)) {
- if ((read_mvfr0() & MVFR0_A_SIMD_MASK) == 2) {
- /* Save {d16-d31} */
- asm volatile("stcl p11, cr0, [%0], #32*4"
- : : "r" (vfp->fpregs2));
- }
- }
-
- /* Leave FPU in disabled state */
- write_fpexc(vfp->fpexc & ~(FPEXC_EN_MASK));
-}
-
-void cpu_vcpu_vfp_regs_restore(struct vmm_vcpu *vcpu)
-{
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- /* VFP feature must be available */
- if (!arm_feature(vcpu, ARM_FEATURE_VFP)) {
- return;
- }
-
- /* Force enable FPU */
- write_fpexc(read_fpexc() | FPEXC_EN_MASK);
-
- /* Restore {d0-d15} */
- asm volatile("ldc p11, cr0, [%0], #32*4"
- : : "r" (vfp->fpregs1));
-
- /* 32x 64 bits registers? */
- if (arm_feature(vcpu, ARM_FEATURE_VFP3)) {
- if ((read_mvfr0() & MVFR0_A_SIMD_MASK) == 2) {
- /* Restore {d16-d31} */
- asm volatile("ldcl p11, cr0, [%0], #32*4"
- : : "r" (vfp->fpregs2));
- }
- }
-
- /* Check for sub-architecture */
- if (vfp->fpexc & FPEXC_EX_MASK) {
- /* Restore FPINST */
- write_fpinst(vfp->fpinst);
-
- /* Restore FPINST2 */
- if (vfp->fpexc & FPEXC_FP2V_MASK) {
- write_fpinst2(vfp->fpinst2);
- }
- }
-
- /* Restore FPSCR */
- write_fpscr(vfp->fpscr);
-
- /* Restore FPEXC */
- write_fpexc(vfp->fpexc);
-}
-
-void cpu_vcpu_vfp_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu)
-{
- u32 i;
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- /* VFP feature must be available */
- if (!arm_feature(vcpu, ARM_FEATURE_VFP)) {
- return;
- }
-
- vmm_cprintf(cdev, "VFP System Registers\n");
- vmm_cprintf(cdev, " %7s=0x%08x %7s=0x%08x %7s=0x%08x\n",
- "FPEXC", vfp->fpexc,
- "FPSCR", vfp->fpscr,
- "FPINST", vfp->fpinst);
- vmm_cprintf(cdev, " %7s=0x%08x\n",
- "FPINST2", vfp->fpinst2);
- vmm_cprintf(cdev, "VFP Data Registers");
- for (i = 0; i < 32; i++) {
- if (i % 2 == 0) {
- vmm_cprintf(cdev, "\n");
- } else {
- vmm_cprintf(cdev, " ");
- }
- if (i < 16) {
- vmm_cprintf(cdev, " %5s%02d=0x%016llx",
- "D", (i), vfp->fpregs1[i]);
- } else {
- vmm_cprintf(cdev, " %5s%02d=0x%016llx",
- "D", (i), vfp->fpregs2[i-16]);
- }
- }
- vmm_cprintf(cdev, "\n");
-}
-
-int cpu_vcpu_vfp_init(struct vmm_vcpu *vcpu)
-{
- u32 vfp_arch;
- struct arm_priv_vfp *vfp = &arm_priv(vcpu)->vfp;
-
- /* If host HW does not have VFP (i.e. software VFP) then
- * clear all VFP feature flags so that VCPU always gets
- * undefined exception when accessing VFP registers.
- */
- if (!cpu_supports_fpu()) {
- goto no_vfp_for_vcpu;
- }
-
- /* VCPU with VFP3 would requie host HW to have VFP3 or higher */
- vfp_arch = (read_fpsid() & FPSID_ARCH_MASK) >> FPSID_ARCH_SHIFT;
- if (arm_feature(vcpu, ARM_FEATURE_VFP3) && (vfp_arch < 2)) {
- goto no_vfp_for_vcpu;
- }
-
- /* Reset VFP control registers */
- vfp->fpexc = 0x0;
- vfp->fpscr = 0x0;
- vfp->fpinst = 0x0;
- vfp->fpinst2 = 0x0;
- memset(&vfp->fpregs1, 0, sizeof(vfp->fpregs1));
- memset(&vfp->fpregs2, 0, sizeof(vfp->fpregs2));
-
- return VMM_OK;
-
-no_vfp_for_vcpu:
- arm_clear_feature(vcpu, ARM_FEATURE_MVFR);
- arm_clear_feature(vcpu, ARM_FEATURE_VFP);
- arm_clear_feature(vcpu, ARM_FEATURE_VFP3);
- arm_clear_feature(vcpu, ARM_FEATURE_VFP4);
- return VMM_OK;
-}
-
-int cpu_vcpu_vfp_deinit(struct vmm_vcpu *vcpu)
-{
- /* For now nothing to do here. */
- return VMM_OK;
-}
-
diff --git a/arch/arm/cpu/arm32/elf2cpatch.py b/arch/arm/cpu/arm32/elf2cpatch.py
deleted file mode 100755
index fa805d1b..00000000
--- a/arch/arm/cpu/arm32/elf2cpatch.py
+++ /dev/null
@@ -1,708 +0,0 @@
-#!/usr/bin/python
-#/**
-# Copyright (c) 2011 Anup Patel.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file elf2cpatch.py
-# @author Anup Patel (an...@brainfault.org)
-# @brief Script to generate cpatch script from guest OS ELF
-# */
-
-# Each sensitive non-priviledged ARM instruction is converted to a hypercall
-# The hypercall in ARM instruction set is SVC <imm24> instruction.
-#
-# We encode sensitive non-priviledged instructions in <imm24> operand of SVC
-# instruction. Each encoded instruction will have its own unique inst_id.
-# the fields of instruction will be encoded as inst_field. The inst_field
-# for each encoded sensitive non-priviledged instruction will be diffrent.
-
-import os
-import sys
-from optparse import OptionParser
-
-usage = "Usage: %prog [options]"
-parser = OptionParser(usage=usage)
-parser.add_option("-f", "--file", dest="filename",
- help="Input ARM ELF32 file", metavar="FILE")
-parser.add_option("-q", "--quiet",
- action="store_false", dest="verbose", default=True,
- help="Don't print status messages to stdout")
-
-(options, add_args) = parser.parse_args()
-
-if not options.filename:
- print("Error: No input ARM ELF32 file")
- sys.exit()
-
-seccmd = os.environ.get("CROSS_COMPILE") + "objdump -h " + options.filename
-dumpcmd = os.environ.get("CROSS_COMPILE") + "objdump -d " + options.filename
-
-# Populate sections to patch
-secs = []
-secs_name = ""
-secs_parse_start = 0
-secs_parse_pos = 0
-p = os.popen(seccmd, "r")
-while 1:
- l = p.readline()
- if not l: break
- l = l.strip(" ");
- l = l.replace("\n","");
- l = l.replace("\t"," ");
- while l.count(" ")>0:
- l = l.replace(" "," ")
- w = l.split(" ");
- if w[0]=="Sections:":
- l = p.readline()
- if not l: break
- secs_parse_start = 1
- continue
- if secs_parse_start==1:
- secs_name = w[1]
- l = p.readline()
- if not l: break
- l = l.strip(" ");
- l = l.replace("\n","");
- l = l.replace("\t"," ");
- w = l.split(" ");
- if ('CODE' in w) and (secs_name.find(".notes") == -1) and (secs_name.find(".info") == -1):
- secs.append(secs_name)
- secs_parse_pos = secs_parse_pos + 1
-
-if len(secs)==0:
- print("Error: Did not find code sections to scan")
- sys.exit()
-
-#print(secs)
-#sys.exit()
-
-# Initialize data structures
-lines = [];
-lsyms = [];
-lsecs = [];
-vlnums = [];
-vsymdec = [];
-addr2lnum = {};
-sym2base = {};
-
-# Populate data structures
-sec = ""
-sec_valid = 0
-lnum = 0
-sym = ""
-base = 0
-p = os.popen(dumpcmd,"r")
-while 1:
- l = p.readline()
- if not l: break
- l = l.strip(" ");
- l = l.replace("\n","");
- l = l.replace("\t"," ");
- while l.count(" ")>0:
- l = l.replace(" "," ")
- w = l.split(" ");
- if len(w)>3 and w[0]=="Disassembly" and w[1]=="of" and w[2]=="section":
- w[3] = w[3].replace(":", "")
- sec = ""
- sec_valid = 0
- if w[3] in secs:
- sec = w[3]
- sec_valid = 1
- elif sec_valid==1:
- if len(w)>2:
- addr = base | int(w[0].replace(":",""), 16)
- lines.append(l)
- lsecs.append(sec)
- lsyms.append(sym)
- addr2lnum[addr] = lnum
- vlnums.append(True)
- vsymdec.append(False)
- lnum += 1
- elif len(w)==2:
- if not(w[1].startswith("<") and w[1].endswith(">:")):
- continue
- base = int(w[0].replace(":",""), 16)
- w[1] = w[1].replace("<","")
- w[1] = w[1].replace(">:","")
- sym = w[1]
- lines.append(l)
- sym2base[sym] = base
- lsecs.append(sec)
- lsyms.append(sym)
- vlnums.append(False)
- vsymdec.append(True)
- lnum += 1
-
-# CPS
-# Syntax:
-# cpsie <iflags> {,#mode}
-# cpsid <iflags> {,#mode}
-# cps #<mode>
-# Fields:
-# imod = bits[19:18]
-# M = bits[17:17]
-# A = bits[8:8]
-# I = bits[7:7]
-# F = bits[6:6]
-# mode = bits[4:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 0
-# inst_fields[16:15] = imod
-# inst_fields[14:14] = M
-# inst_fields[13:13] = A
-# inst_fields[12:12] = I
-# inst_fields[11:11] = F
-# inst_fields[10:6] = mode
-def convert_cps_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 0
- cond = 0xe
- imod = (hx >> 18) & 0x3
- M = (hx >> 17) & 0x1
- A = (hx >> 8) & 0x1
- I = (hx >> 7) & 0x1
- F = (hx >> 6) & 0x1
- mode = hx & 0x1F
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (imod << 15)
- rethx = rethx | (M << 14)
- rethx = rethx | (A << 13)
- rethx = rethx | (I << 12)
- rethx = rethx | (F << 11)
- rethx = rethx | (mode << 6)
- return rethx
-
-# MRS
-# Syntax:
-# mrs<c> <Rd>, <spec_reg>
-# Fields:
-# cond = bits[31:28]
-# R = bits[22:22]
-# Rd = bits[15:12]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 1
-# inst_fields[16:13] = Rd
-# inst_fields[12:12] = R
-def convert_mrs_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 1
- cond = (hx >> 28) & 0xF
- R = (hx >> 22) & 0x1
- Rd = (hx >> 12) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (Rd << 13)
- rethx = rethx | (R << 12)
- return rethx
-
-# MSR (immediate)
-# Syntax:
-# msr<c> <spec_reg>, #<const>
-# Fields:
-# cond = bits[31:28]
-# R = bits[22:22]
-# mask = bits[19:16]
-# imm12 = bits[11:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 2
-# inst_fields[16:13] = mask
-# inst_fields[12:1] = imm12
-# inst_fields[0:0] = R
-def convert_msr_i_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 2
- cond = (hx >> 28) & 0xF
- R = (hx >> 22) & 0x1
- mask = (hx >> 16) & 0xF
- imm12 = (hx >> 0) & 0xFFF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (mask << 13)
- rethx = rethx | (imm12 << 1)
- rethx = rethx | (R << 0)
- return rethx
-
-# MSR (register)
-# Syntax:
-# msr<c> <spec_reg>, <Rn>
-# Fields:
-# cond = bits[31:28]
-# R = bits[22:22]
-# mask = bits[19:16]
-# Rn = bits[3:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 3
-# inst_fields[16:13] = mask
-# inst_fields[12:9] = Rn
-# inst_fields[8:8] = R
-def convert_msr_r_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 3
- cond = (hx >> 28) & 0xF
- R = (hx >> 22) & 0x1
- mask = (hx >> 16) & 0xF
- Rn = (hx >> 0) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (mask << 13)
- rethx = rethx | (Rn << 9)
- rethx = rethx | (R << 8)
- return rethx
-
-# RFE
-# Syntax:
-# rfe<amode><c> <Rn>{!}
-# Fields:
-# P = bits[24:24]
-# U = bits[23:23]
-# W = bits[21:21]
-# Rn = bits[19:16]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 4
-# inst_fields[16:16] = P
-# inst_fields[15:15] = U
-# inst_fields[14:14] = W
-# inst_fields[13:10] = Rn
-def convert_rfe_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 4
- cond = 0xE
- P = (hx >> 24) & 0x1
- U = (hx >> 23) & 0x1
- W = (hx >> 21) & 0x1
- Rn = (hx >> 16) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (P << 16)
- rethx = rethx | (U << 15)
- rethx = rethx | (W << 14)
- rethx = rethx | (Rn << 10)
- return rethx
-
-# SVC
-# Syntax:
-# svc{cond} #imm
-# Fields:
-# cond = bits[31:28]
-# imm = bits[23:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xF
-# inst_id[23:20] = 0xF
-# inst_imm[19:0] = imm[19:0]
-def convert_svc_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 15
- cond = (hx >> 28) & 0xF
- imm = hx & 0xFFFFF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | imm
- return rethx
-
-# SRS
-# Syntax:
-# srs{amode}<c> sp{!}, #mode
-# Fields:
-# P = bits[24:24]
-# U = bits[23:23]
-# W = bits[21:21]
-# mode = bits[4:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 5
-# inst_fields[16:16] = P
-# inst_fields[15:15] = U
-# inst_fields[14:14] = W
-# inst_fields[13:9] = mode
-def convert_srs_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 5
- cond = 0xE
- P = (hx >> 24) & 0x1
- U = (hx >> 23) & 0x1
- W = (hx >> 21) & 0x1
- mode = hx & 0x1F
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (P << 16)
- rethx = rethx | (U << 15)
- rethx = rethx | (W << 14)
- rethx = rethx | (mode << 9)
- return rethx
-
-# WFI
-# Syntax:
-# wfi<c>
-# Fields:
-# cond = bits[31:28]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 6
-# inst_ev[16:15] = 0
-def convert_wfi_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 6
- inst_ev = 0
- cond = (hx >> 28) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (inst_ev << 15)
- return rethx
-
-# WFE
-# Syntax:
-# wfe<c>
-# Fields:
-# cond = bits[31:28]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 6
-# inst_ev[16:15] = 1
-def convert_wfe_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 6
- inst_ev = 1
- cond = (hx >> 28) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (inst_ev << 15)
- return rethx
-
-# YIELD
-# Syntax:
-# yield<c>
-# Fields:
-# cond = bits[31:28]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 6
-# inst_ev[16:15] = 2
-def convert_yield_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 6
- inst_ev = 2
- cond = (hx >> 28) & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (inst_ev << 15)
- return rethx
-
-# SEV
-# Syntax:
-# sev<c>
-# Just an unconditionnal NOP
-def convert_sev_inst(hxstr):
- rethx = 0xe1a00000
- return rethx
-
-# SMC
-# Syntax:
-# smc<c><q> {#}<imm4>
-# Fields:
-# cond = bits[31:28]
-# imm4 = bits[3:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 0
-# inst_subid[19:17] = 7
-# inst_fields[16:13] = imm4
-def convert_smc_inst(hxstr):
- hx = int(hxstr, 16)
- inst_id = 0
- inst_subid = 7
- cond = (hx >> 28) & 0xF
- imm4 = hx & 0xF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (inst_subid << 17)
- rethx = rethx | (imm4 << 13)
- return rethx
-
-# LDM (exception return or user register)
-# Syntax:
-# ldm<amode><c> <Rn>{!}, <registers_with_or_without_pc>^
-# Fields:
-# cond = bits[31:28]
-# P = bits[24:24]
-# U = bits[23:23]
-# W = bits[21:21]
-# Rn = bits[19:16]
-# reg_list = bits[15:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 1 (if P==0 && U==0 && W==0)
-# inst_id[23:20] = 2 (if P==0 && U==0 && W==1)
-# inst_id[23:20] = 3 (if P==0 && U==1 && W==0)
-# inst_id[23:20] = 4 (if P==0 && U==1 && W==1)
-# inst_id[23:20] = 5 (if P==1 && U==0 && W==0)
-# inst_id[23:20] = 6 (if P==1 && U==0 && W==1)
-# inst_id[23:20] = 7 (if P==1 && U==1 && W==0)
-# inst_id[23:20] = 8 (if P==1 && U==1 && W==1)
-# inst_fields[19:16] = Rn
-# inst_fields[15:0] = reg_list
-def convert_ldm_ue_inst(hxstr):
- hx = int(hxstr, 16)
- cond = (hx >> 28) & 0xF
- P = (hx >> 24) & 0x1
- U = (hx >> 23) & 0x1
- W = (hx >> 21) & 0x1
- Rn = (hx >> 16) & 0xF
- inst_id = 1 + P * 4 + U * 2 + W
- reg_list = (hx >> 0) & 0xFFFF
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (Rn << 16)
- rethx = rethx | (reg_list << 0)
- return rethx
-
-# STM (user registers)
-# Syntax:
-# stm<amode><c> <Rn>, <registers>^
-# Fields:
-# cond = bits[31:28]
-# P = bits[24:24]
-# U = bits[23:23]
-# Rn = bits[19:16]
-# reg_list = bits[15:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 9 (if P==0 && U==0)
-# inst_id[23:20] = 10 (if P==0 && U==1)
-# inst_id[23:20] = 11 (if P==1 && U==0)
-# inst_id[23:20] = 12 (if P==1 && U==1)
-# inst_fields[19:16] = Rn
-# inst_fields[15:0] = reg_list
-def convert_stm_u_inst(hxstr):
- hx = int(hxstr, 16)
- cond = (hx >> 28) & 0xF
- P = (hx >> 24) & 0x1
- U = (hx >> 23) & 0x1
- Rn = (hx >> 16) & 0xF
- reg_list = (hx >> 0) & 0x7FFF
- inst_id = 9 + (P * 2) + U
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (Rn << 16)
- rethx = rethx | (reg_list << 0)
- return rethx
-
-# SUBS PC, LR and related instructions
-# Syntax:
-# subs<c> pc, lr, #<const>
-# <opc1>s<c> pc, <Rn>, #<const>
-# <opc1>S<c> pc, <Rn>, <Rm> {,<shift>}
-# <opc2>s<c> pc, #<const>
-# <opc2>S<c> pc, <Rm> {,<shift>}
-# Fields:
-# cond = bits[31:28]
-# opcode = bits[24:21]
-# Rn = bits[19:16]
-# imm12 = bits[11:0]
-# imm5 = bits[11:7]
-# type = bits[6:5]
-# Rm = bits[3:0]
-# Hypercall Fields:
-# inst_cond[31:28] = cond
-# inst_op[27:24] = 0xf
-# inst_id[23:20] = 13 (if bits[25:25]==0)
-# inst_id[23:20] = 14 (if bits[25:25]==1)
-# inst_fields[19:16] = opcode
-# inst_fields[15:12] = Rn
-# inst_fields[11:0] = imm12
-# inst_fields[11:7] = imm5
-# inst_fields[6:5] = type
-# inst_fields[3:0] = Rm
-def convert_subs_rel_inst(hxstr):
- hx = int(hxstr, 16)
- cond = (hx >> 28) & 0xF
- opcode = (hx >> 21) & 0xF
- Rn = (hx >> 16) & 0xF
- imm12 = (hx >> 0) & 0xFFF
- imm5 = (hx >> 7) & 0x1F
- typ = (hx >> 5) & 0x3
- Rm = (hx >> 0) & 0xF
- inst_id = 13 + ((hx >> 25) & 0x1)
- rethx = 0x0F000000
- rethx = rethx | (cond << 28)
- rethx = rethx | (inst_id << 20)
- rethx = rethx | (opcode << 16)
- rethx = rethx | (Rn << 12)
- if (inst_id==14):
- rethx = rethx | (imm12 << 0)
- else:
- rethx = rethx | (imm5 << 7)
- rethx = rethx | (typ << 5)
- rethx = rethx | (Rm << 0)
- return rethx
-
-psec = ""
-for ln, l in enumerate(lines):
- if vlnums[ln]:
- sec = lsecs[ln];
- if sec!=psec:
- print("section," + sec)
- psec = sec
- w = l.split(" ")
- if len(w)<3:
- continue
- w[0] = w[0].replace(":", "")
- addr = int(w[0], 16)
- if (len(w)>1):
- if (w[1]=="Address"):
- continue
- if (len(w)==3):
- if (w[2].startswith("wfi")):
- print("\t#", w[2])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_wfi_inst(w[1])))
- elif (w[2].startswith("wfe")):
- print("\t#", w[2])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_wfe_inst(w[1])))
- elif (w[2].startswith("sev")):
- print("\t#", w[2])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_sev_inst(w[1])))
- elif (w[2].startswith("yield")):
- print("\t#", w[2])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_yield_inst(w[1])))
- elif (len(w)==4):
- if (w[2]=="cps" or w[2]=="cpsie" or w[2]=="cpsid"):
- print("\t#", w[2], w[3])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_cps_inst(w[1])))
- elif (w[2].startswith("svc")):
- print("\t#", w[2], w[3])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_svc_inst(w[1])))
- elif (w[2]=="rfeda" or
- w[2]=="rfedb" or
- w[2]=="rfeia" or
- w[2]=="rfeib" or
- w[2]=="rfe"):
- print("\t#", w[2], w[3])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_rfe_inst(w[1])) )
- elif (w[2].startswith("smc")):
- print("\t#", w[2], w[3])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_smc_inst(w[1])) )
- elif len(w)>=5:
- if (w[2]=="mrs"):
- print("\t#", w[2], w[3], w[4])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_mrs_inst(w[1])))
- elif (w[2]=="msr"):
- print("\t#", w[2], w[3], w[4])
- # Check bit[25] to findout
- # whether instruction is immediate or literal
- if int(w[1], 16) & 0x02000000:
- print("\twrite32,0x%x,0x%08x" % (addr, convert_msr_i_inst(w[1])))
- else:
- print("\twrite32,0x%x,0x%08x" % (addr, convert_msr_r_inst(w[1])))
- elif (w[2]=="srsda" or
- w[2]=="srsdb" or
- w[2]=="srsia" or
- w[2]=="srsib" or
- w[2]=="srs"):
- print("\t#", w[2], w[3], w[4])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_srs_inst(w[1])))
- elif ((w[2]=="ldmda" or
- w[2]=="ldmdb" or
- w[2]=="ldmia" or
- w[2]=="ldmib" or
- w[2]=="ldm") and
- w[4].startswith("{") and
- w[len(w)-1].endswith("}^")):
- print("\t#", w[2], w[3], w[4])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_ldm_ue_inst(w[1])))
- elif ((w[2]=="stmda" or
- w[2]=="stmdb" or
- w[2]=="stmia" or
- w[2]=="stmib" or
- w[2]=="stm") and
- w[4].startswith("{") and
- w[len(w)-1].endswith("}^")):
- print("\t#", w[2], w[3], w[4])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_stm_u_inst(w[1])))
- elif (((int(w[1], 16) & 0x0C10F000) == 0x0010F000) and
- (w[2]=="ands" or
- w[2]=="eors" or
- w[2]=="subs" or
- w[2]=="rsbs" or
- w[2]=="adds" or
- w[2]=="adcs" or
- w[2]=="sbcs" or
- w[2]=="rscs" or
- w[2]=="orrs" or
- w[2]=="movs" or
- w[2]=="bics" or
- w[2]=="mvns")):
- print("\t#", w[2], w[3], w[4])
- print("\twrite32,0x%x,0x%08x" % (addr, convert_subs_rel_inst(w[1])))
-
diff --git a/arch/arm/cpu/arm32/include/arch_barrier.h b/arch/arm/cpu/arm32/include/arch_barrier.h
deleted file mode 100644
index 5a33a8a8..00000000
--- a/arch/arm/cpu/arm32/include/arch_barrier.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_barrier.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief architecure specific memory barriers
- */
-#ifndef __ARCH_BARRIER_H__
-#define __ARCH_BARRIER_H__
-
-#if defined(CONFIG_ARMV5)
-
-#define isb() asm volatile ("" : : : "memory")
-#define dsb() asm volatile ("mcr p15, 0, %0, c7, c10, 4" \
- : : "r" (0) : "memory")
-#define dmb() asm volatile ("" : : : "memory")
-
-#define sev()
-#define wfe()
-#define wfi()
-
-#elif defined(CONFIG_ARMV6)
-
-#define isb() asm volatile ("mcr p15, 0, %0, c7, c5, 4" \
- : : "r" (0) : "memory")
-#define dsb() asm volatile ("mcr p15, 0, %0, c7, c10, 4" \
- : : "r" (0) : "memory")
-#define dmb() asm volatile ("mcr p15, 0, %0, c7, c10, 5" \
- : : "r" (0) : "memory")
-
-#define sev() asm volatile ("sev" : : : "memory")
-#define wfe() asm volatile ("wfe" : : : "memory")
-#define wfi() asm volatile ("wfi" : : : "memory")
-
-#else /* CONFIG_ARMV7 */
-
-#define isb() asm volatile ("isb" : : : "memory")
-#define dsb() asm volatile ("dsb" : : : "memory")
-#define dmb() asm volatile ("dmb" : : : "memory")
-
-#define sev() asm volatile ("sev" : : : "memory")
-#define wfe() asm volatile ("wfe" : : : "memory")
-#define wfi() asm volatile ("wfi" : : : "memory")
-
-#endif
-
-/* Read & Write Memory barrier */
-#define arch_mb() dsb()
-
-/* Read Memory barrier */
-#define arch_rmb() dsb()
-
-/* Write Memory barrier */
-#define arch_wmb() dsb()
-
-/* SMP Read & Write Memory barrier */
-#define arch_smp_mb() dmb()
-
-/* SMP Read Memory barrier */
-#define arch_smp_rmb() dmb()
-
-/* SMP Write Memory barrier */
-#define arch_smp_wmb() dmb()
-
-/* CPU relax for busy loop */
-#if defined(CONFIG_ARMV6) || defined(CONFIG_ARM_ERRATA_754327)
-#define arch_cpu_relax() arch_smp_mb()
-#else
-#define arch_cpu_relax() asm volatile ("" : : : "memory")
-#endif
-
-#endif /* __ARCH_BARRIER_H__ */
diff --git a/arch/arm/cpu/arm32/include/arch_cache.h b/arch/arm/cpu/arm32/include/arch_cache.h
deleted file mode 100644
index db8d762e..00000000
--- a/arch/arm/cpu/arm32/include/arch_cache.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_cache.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief arch specific cache operation
- */
-#ifndef _ARCH_CACHE_H__
-#define _ARCH_CACHE_H__
-
-#include <cpu_cache.h>
-
-#define ARCH_CACHE_LINE_SIZE 32
-#define ARCH_CACHE_LINE_SHIFT 5
-
-/* Prototype:
- * void arch_flush_cache_all(void)
- */
-#define ARCH_HAS_FLUSH_CACHE_ALL
-#define arch_flush_cache_all() do { \
- clean_invalidate_dcache(); \
- } while (0)
-
-/* Prototype:
- * void arch_flush_cache_range(virtual_addr_t start, virtual_addr_t end)
- */
-#define ARCH_HAS_FLUSH_CACHE_RANGE
-#define arch_flush_cache_range(start, end) do { \
- clean_invalidate_dcache_mva_range((start),(end)); \
- } while (0)
-
-/* Prototype:
- * void arch_flush_dcache_range(virtual_addr_t start, virtual_addr_t end)
- */
-#define ARCH_HAS_FLUSH_DCACHE_RANGE
-#define arch_flush_dcache_range(start, end) do { \
- clean_invalidate_dcache_mva_range((start),(end)); \
- } while (0)
-
-/* Prototype:
- * void arch_inv_cache_range(virtual_addr_t start, virtual_addr_t end)
- */
-#define ARCH_HAS_INV_DCACHE_RANGE
-#define arch_inv_dcache_range(start, end) do { \
- invalidate_dcache_mva_range((start),(end)); \
- } while (0)
-
-/* Prototype:
- * void arch_clean_cache_range(virtual_addr_t start, virtual_addr_t end)
- */
-#define ARCH_HAS_CLEAN_DCACHE_RANGE
-#define arch_clean_dcache_range(start, end) do { \
- clean_dcache_mva_range((start),(end)); \
- } while (0)
-
-/* Prefetching support.
- * Prototype:
- * void arch_prefetch(const void *ptr)
- */
-#if (defined(CONFIG_ARMV5) || \
- defined(CONFIG_ARMV6) || \
- defined(CONFIG_ARMV6K) || \
- defined(CONFIG_ARMV7A))
-
-#define ARCH_HAS_PREFETCH
-static inline void arch_prefetch(const void *ptr)
-{
- __asm__ __volatile__(
- "pld\t%a0"
- :: "p" (ptr));
-}
-
-#endif /* CONFIG_ARMV5 || CONFIG_ARMV6 || CONFIG_ARMV6K || CONFIG_ARMV7A */
-
-#endif /* _ARCH_CACHE_H__ */
diff --git a/arch/arm/cpu/arm32/include/arch_config.h b/arch/arm/cpu/arm32/include/arch_config.h
deleted file mode 100644
index 7417c0e0..00000000
--- a/arch/arm/cpu/arm32/include/arch_config.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_config.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief config file for specifying arch specific optional features
- *
- */
-#ifndef _ARCH_CONFIG_H__
-#define _ARCH_CONFIG_H__
-
-#define ARCH_HAS_MEMORY_READWRITE
-
-#define ARCH_HAS_MEMCPY
-#define ARCH_HAS_MEMSET
-
-#endif /* _ARCH_CONFIG_H__ */
diff --git a/arch/arm/cpu/arm32/include/arch_cpu_irq.h b/arch/arm/cpu/arm32/include/arch_cpu_irq.h
deleted file mode 100644
index 512682ae..00000000
--- a/arch/arm/cpu/arm32/include/arch_cpu_irq.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_cpu_irq.h
- * @author Anup Patel (an...@brainfault.org)
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief interface for controlling CPU IRQs
- */
-#ifndef _ARCH_CPU_IRQ_H__
-#define _ARCH_CPU_IRQ_H__
-
-#include <vmm_types.h>
-#include <cpu_defines.h>
-#include <cpu_proc.h>
-
-/** Setup IRQ for CPU */
-int arch_cpu_irq_setup(void);
-
-/** Enable IRQ
- * Prototype: void arch_cpu_irq_enable(void);
- */
-#if defined(CONFIG_ARMV5)
-#define arch_cpu_irq_enable() do { \
- unsigned long _tf; \
- asm volatile( \
- "mrs %0, cpsr\n" \
- "bic %0, %0, #128\n" \
- "msr cpsr_c, %0" \
- : "=r" (_tf) : : "memory", "cc"); \
- } while (0)
-#else
-#define arch_cpu_irq_enable() do { \
- asm volatile ("cpsie i"); \
- } while (0)
-#endif
-
-/** Disable IRQ
- * Prototype: void arch_cpu_irq_disable(void);
- */
-#if defined(CONFIG_ARMV5)
-#define arch_cpu_irq_disable() do { \
- unsigned long _tf; \
- asm volatile( \
- "mrs %0, cpsr\n" \
- "orr %0, %0, #128\n" \
- "msr cpsr_c, %0" \
- : "=r" (_tf) : : "memory", "cc"); \
- } while (0)
-#else
-#define arch_cpu_irq_disable() do { \
- asm volatile ("cpsid i"); \
- } while (0)
-#endif
-
-/** Check whether IRQs are disabled
- * Prototype: bool arch_cpu_irq_disabled(void);
- */
-#define arch_cpu_irq_disabled() ({ unsigned long _tf; \
- asm volatile ( \
- "mrs %0, cpsr\n\t" \
- :"=r" (_tf) : : "memory", "cc"); \
- (_tf & CPSR_IRQ_DISABLED) ? TRUE : FALSE; \
- })
-
-/** Save IRQ flags and disable IRQ
- * Prototype: void arch_cpu_irq_save(irq_flags_t flags);
- */
-#if defined(CONFIG_ARMV5)
-#define arch_cpu_irq_save(flags) do { unsigned long _tt; \
- asm volatile( \
- "mrs %0, cpsr\n" \
- "orr %1, %0, #128\n" \
- "msr cpsr_c, %1" \
- : "=r" ((flags)), "=r" (_tt) \
- : : "memory", "cc"); \
- } while (0)
-#else
-#define arch_cpu_irq_save(flags) do { \
- asm volatile ( \
- "mrs %0, cpsr\n\t" \
- "cpsid i\n\t" \
- :"=r" ((flags)) : : "memory", "cc"); \
- } while (0)
-#endif
-
-/** Restore IRQ flags
- * Prototype: void arch_cpu_irq_restore(irq_flags_t flags);
- */
-#define arch_cpu_irq_restore(flags) do { \
- asm volatile ( \
- "msr cpsr_c, %0" \
- : : "r" ((flags)) : "memory", "cc"); \
- } while (0)
-
-/** Wait for IRQ
- * Prototype: void arch_cpu_wait_for_irq(void);
- */
-#define arch_cpu_wait_for_irq() do { \
- irq_flags_t _ifl; \
- arch_cpu_irq_save(_ifl); \
- proc_do_idle(); \
- arch_cpu_irq_restore(_ifl); \
- } while (0)
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_delay.h b/arch/arm/cpu/arm32/include/arch_delay.h
deleted file mode 100644
index fb7868ec..00000000
--- a/arch/arm/cpu/arm32/include/arch_delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_delay.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief arch specific delay routines
- */
-#ifndef _ARCH_DELAY_H__
-#define _ARCH_DELAY_H__
-
-#include <vmm_types.h>
-
-/** Low-level delay loop */
-void arch_delay_loop(unsigned long count);
-
-/** Estimated cycles for given loop count
- * Note: This can be processor specific
- */
-unsigned long arch_delay_loop_cycles(unsigned long count);
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_elf.h b/arch/arm/cpu/arm32/include/arch_elf.h
deleted file mode 100644
index 41c1d34e..00000000
--- a/arch/arm/cpu/arm32/include/arch_elf.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_elf.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief arch specific ELF routines
- */
-#ifndef _ARCH_ELF_H__
-#define _ARCH_ELF_H__
-
-#include <vmm_types.h>
-
-/* ARM elf specific declarations */
-
-#define EF_ARM_EABI_MASK 0xff000000
-#define EF_ARM_EABI_UNKNOWN 0x00000000
-#define EF_ARM_EABI_VER1 0x01000000
-#define EF_ARM_EABI_VER2 0x02000000
-#define EF_ARM_EABI_VER3 0x03000000
-#define EF_ARM_EABI_VER4 0x04000000
-#define EF_ARM_EABI_VER5 0x05000000
-
-#define EF_ARM_BE8 0x00800000 /* ABI 4,5 */
-#define EF_ARM_LE8 0x00400000 /* ABI 4,5 */
-#define EF_ARM_MAVERICK_FLOAT 0x00000800 /* ABI 0 */
-#define EF_ARM_VFP_FLOAT 0x00000400 /* ABI 0 */
-#define EF_ARM_SOFT_FLOAT 0x00000200 /* ABI 0 */
-#define EF_ARM_OLD_ABI 0x00000100 /* ABI 0 */
-#define EF_ARM_NEW_ABI 0x00000080 /* ABI 0 */
-#define EF_ARM_ALIGN8 0x00000040 /* ABI 0 */
-#define EF_ARM_PIC 0x00000020 /* ABI 0 */
-#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ABI 2 */
-#define EF_ARM_APCS_FLOAT 0x00000010 /* ABI 0, floats in fp regs */
-#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ABI 2 */
-#define EF_ARM_APCS_26 0x00000008 /* ABI 0 */
-#define EF_ARM_SYMSARESORTED 0x00000004 /* ABI 1,2 */
-#define EF_ARM_INTERWORK 0x00000004 /* ABI 0 */
-#define EF_ARM_HASENTRY 0x00000002 /* All */
-#define EF_ARM_RELEXEC 0x00000001 /* All */
-
-#define R_ARM_NONE 0
-#define R_ARM_PC24 1
-#define R_ARM_ABS32 2
-#define R_ARM_CALL 28
-#define R_ARM_JUMP24 29
-#define R_ARM_V4BX 40
-#define R_ARM_PREL31 42
-#define R_ARM_MOVW_ABS_NC 43
-#define R_ARM_MOVT_ABS 44
-
-#define R_ARM_THM_CALL 10
-#define R_ARM_THM_JUMP24 30
-#define R_ARM_THM_MOVW_ABS_NC 47
-#define R_ARM_THM_MOVT_ABS 48
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#ifdef __ARMEB__
-#define ELF_DATA ELFDATA2MSB
-#else
-#define ELF_DATA ELFDATA2LSB
-#endif
-#define ELF_ARCH EM_ARM
-
-struct elf32_hdr;
-struct elf32_shdr;
-
-int arch_elf_check_hdr(const struct elf32_hdr *x);
-
-int arch_elf_apply_relocate(struct elf32_shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relindex,
- struct vmm_module *mod);
-
-int arch_elf_apply_relocate_add(struct elf32_shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct vmm_module *mod);
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_io.h b/arch/arm/cpu/arm32/include/arch_io.h
deleted file mode 100644
index 7325e063..00000000
--- a/arch/arm/cpu/arm32/include/arch_io.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_io.h
- * @author Anup Patel (an...@brainfault.org)
- * @author Jim Huang (js...@0xlab.org)
- * @brief header file for CPU I/O or Memory read/write functions
- */
-#ifndef _ARCH_IO_H__
-#define _ARCH_IO_H__
-
-#include <vmm_types.h>
-#include <arch_barrier.h>
-#include <cpu_inline_asm.h>
-
-#define __raw_write8(a,v) (*(volatile u8 *)(a) = (v))
-#define __raw_write16(a,v) (*(volatile u16 *)(a) = (v))
-#define __raw_write32(a,v) (*(volatile u32 *)(a) = (v))
-#define __raw_write64(a,v) (*(volatile u64 *)(a) = (v))
-
-#define __raw_read8(a) (*(volatile u8 *)(a))
-#define __raw_read16(a) (*(volatile u16 *)(a))
-#define __raw_read32(a) (*(volatile u32 *)(a))
-#define __raw_read64(a) (*(volatile u64 *)(a))
-
-#define __iormb() arch_rmb()
-#define __iowmb() arch_wmb()
-
-/*
- * Endianness primitives
- * ------------------------
- */
-#define arch_cpu_to_le16(v) (v)
-
-#define arch_le16_to_cpu(v) (v)
-
-#define arch_cpu_to_be16(v) rev16(v)
-
-#define arch_be16_to_cpu(v) rev16(v)
-
-#define arch_cpu_to_le32(v) (v)
-
-#define arch_le32_to_cpu(v) (v)
-
-#define arch_cpu_to_be32(v) rev32(v)
-
-#define arch_be32_to_cpu(v) rev32(v)
-
-#define arch_cpu_to_le64(v) (v)
-
-#define arch_le64_to_cpu(v) (v)
-
-#define arch_cpu_to_be64(v) rev64(v)
-
-#define arch_be64_to_cpu(v) rev64(v)
-
-#define __io(p) ((void *)p)
-
-/*
- * IO port access primitives
- * -------------------------
- *
- * The ARM doesn't have special IO access instructions; all IO is memory
- * mapped. Note that these are defined to perform little endian accesses
- * only. For ARM, IO port read/write operations translate to a read/write
- * operation to memory address. All IO port read/write operations are
- * assumed to be little-endian.
- */
-#define arch_outb(v, p) {__iowmb(); __raw_write8(__io(p), v); }
-#define arch_outw(v, p) {__iowmb(); __raw_write16(__io(p), v); }
-#define arch_outl(v, p) {__iowmb(); __raw_write32(__io(p), v); }
-#define arch_inb(p) ({u8 v = __raw_read8(__io(p)); __iormb(); v; })
-#define arch_inw(p) ({u16 v = __raw_read16(__io(p)); __iormb(); v; })
-#define arch_inl(p) ({u32 v = __raw_read32(__io(p)); __iormb(); v; })
-
-#define arch_outb_p(v, p) arch_outb((v), (p))
-#define arch_outw_p(v, p) arch_outw((v), (p))
-#define arch_outl_p(v, p) arch_outl((v), (p))
-#define arch_inb_p(p) arch_inb((p))
-#define arch_inw_p(p) arch_inw((p))
-#define arch_inl_p(p) arch_inl((p))
-
-static inline void arch_insb(unsigned long p, void *b, int c)
-{
- if (c) {
- u8 *buf = b;
- do {
- u8 x = arch_inb(p);
- *buf++ = x;
- } while (--c);
- }
-}
-
-static inline void arch_insw(unsigned long p, void *b, int c)
-{
- if (c) {
- u16 *buf = b;
- do {
- u16 x = arch_inw(p);
- *buf++ = x;
- } while (--c);
- }
-}
-
-static inline void arch_insl(unsigned long p, void *b, int c)
-{
- if (c) {
- u32 *buf = b;
- do {
- u32 x = arch_inl(p);
- *buf++ = x;
- } while (--c);
- }
-}
-
-static inline void arch_outsb(unsigned long p, const void *b, int c)
-{
- if (c) {
- const u8 *buf = b;
- do {
- arch_outb(*buf++, p);
- } while (--c);
- }
-}
-
-static inline void arch_outsw(unsigned long p, const void *b, int c)
-{
- if (c) {
- const u16 *buf = b;
- do {
- arch_outw(*buf++, p);
- } while (--c);
- }
-}
-
-static inline void arch_outsl(unsigned long p, const void *b, int c)
-{
- if (c) {
- const u32 *buf = b;
- do {
- arch_outl(*buf++, p);
- } while (--c);
- }
-}
-
-/*
- * Memory access primitives
- * ------------------------
- */
-#define arch_in_8(a) ({u8 v = __raw_read8(a); __iormb(); v; })
-#define arch_out_8(a, v) {__iowmb(); __raw_write8(a, v); }
-#define arch_in_le16(a) ({u16 v = __raw_read16(a); __iormb(); v; })
-#define arch_out_le16(a, v) ({__raw_write16(a, v); __iowmb(); })
-#define arch_in_be16(a) ({u16 v = __raw_read16(a); __iormb(); rev16(v); })
-#define arch_out_be16(a, v) {__iowmb(); __raw_write16(a, (rev16(v))); }
-#define arch_in_le32(a) ({u32 v = __raw_read32(a); __iormb(); v; })
-#define arch_out_le32(a, v) {__iowmb(); __raw_write32(a, v); }
-#define arch_in_be32(a) ({u32 v = __raw_read32(a); __iormb(); rev32(v); })
-#define arch_out_be32(a, v) {__iowmb(); __raw_write32(a, rev32(v)); }
-#define arch_in_le64(a) ({u64 v = __raw_read64(a); __iormb(); v; })
-#define arch_out_le64(a, v) {__iowmb(); __raw_write64(a, v); }
-#define arch_in_be64(a) ({u64 v = __raw_read64(a); __iormb(); rev64(v); })
-#define arch_out_be64(a, v) {__iowmb(); __raw_write64(a, rev64(v)); }
-
-#define arch_in_8_relax(a) ({u8 v = __raw_read8(a); v; })
-#define arch_out_8_relax(a, v) { __raw_write8(a, v); }
-#define arch_in_le16_relax(a) ({u16 v = __raw_read16(a); v; })
-#define arch_out_le16_relax(a, v) ({ __raw_write16(a, v); })
-#define arch_in_be16_relax(a) ({u16 v = __raw_read16(a); rev16(v); })
-#define arch_out_be16_relax(a, v) { __raw_write16(a, (rev16(v))); }
-#define arch_in_le32_relax(a) ({u32 v = __raw_read32(a); v; })
-#define arch_out_le32_relax(a, v) {__iowmb(); __raw_write32(a, v); }
-#define arch_in_be32_relax(a) ({u32 v = __raw_read32(a); rev32(v); })
-#define arch_out_be32_relax(a, v) { __raw_write32(a, rev32(v)); }
-#define arch_in_le64_relax(a) ({u64 v = __raw_read64(a); v; })
-#define arch_out_le64_relax(a, v) { __raw_write64(a, v); }
-#define arch_in_be64_relax(a) ({u64 v = __raw_read64(a); rev64(v); })
-#define arch_out_be64_relax(a, v) { __raw_write64(a, rev64(v)); }
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_regs.h b/arch/arm/cpu/arm32/include/arch_regs.h
deleted file mode 100644
index 9d488856..00000000
--- a/arch/arm/cpu/arm32/include/arch_regs.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_regs.h
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @author Anup Patel (an...@brainfault.org)
- * @brief common header file for CPU registers
- */
-#ifndef _ARCH_REGS_H__
-#define _ARCH_REGS_H__
-
-#include <vmm_types.h>
-#include <vmm_compiler.h>
-#include <cpu_defines.h>
-#include <cpu_mmu.h>
-
-struct arch_regs {
- u32 sp_excp; /* Stack Pointer for Exceptions */
- u32 cpsr; /* CPSR */
- u32 gpr[CPU_GPR_COUNT]; /* R0 - R12 */
- u32 sp; /* Stack Pointer */
- u32 lr; /* Link Register */
- u32 pc; /* Program Counter */
-} __packed;
-
-typedef struct arch_regs arch_regs_t;
-
-struct arm_priv_vfp {
- /* Control Registers */
- u32 fpexc;
- u32 fpscr;
- u32 fpinst;
- u32 fpinst2;
- /* General Purpose Registers */
- u64 fpregs1[16]; /* {d0-d15} 64bit floating point registers.*/
- u64 fpregs2[16]; /* {d16-d31} 64bit floating point registers.*/
-} __packed;
-
-struct arm_priv_cp14 {
- /* ThumbEE Registers */
- u32 teecr;
- u32 teehbr;
-} __packed;
-
-struct arm_vtlb_entry {
- u32 dom;
- virtual_addr_t pva;
- virtual_size_t psz;
- struct cpu_l2tbl *l2;
-} __packed;
-
-struct arm_vtlb {
- struct arm_vtlb_entry table[CPU_VCPU_VTLB_ENTRY_COUNT];
- u32 victim[CPU_VCPU_VTLB_ZONE_COUNT];
-} __packed;
-
-struct arm_priv_cp15 {
- /* Shadow L1 */
- struct cpu_l1tbl *l1;
- /* Shadow DACR */
- u32 dacr;
- /* Virtual TLB */
- struct arm_vtlb vtlb;
- /* Overlapping vector page base */
- u32 ovect_base;
- /* Virtual IO */
- bool virtio_active;
- struct cpu_page virtio_page;
- /* Invalidate i-cache */
- bool inv_icache;
- /* Coprocessor Registers */
- u32 c0_midr;
- u32 c0_mpidr;
- u32 c0_cachetype;
- u32 c0_pfr0;
- u32 c0_pfr1;
- u32 c0_dfr0;
- u32 c0_afr0;
- u32 c0_mmfr0;
- u32 c0_mmfr1;
- u32 c0_mmfr2;
- u32 c0_mmfr3;
- u32 c0_isar0;
- u32 c0_isar1;
- u32 c0_isar2;
- u32 c0_isar3;
- u32 c0_isar4;
- u32 c0_isar5;
- u32 c0_ccsid[16]; /* Cache size. */
- u32 c0_clid; /* Cache level. */
- u32 c0_cssel; /* Cache size selection. */
- u32 c1_sctlr; /* System control register. */
- u32 c1_cpacr; /* Coprocessor access register. */
- u32 c2_ttbr0; /* MMU translation table base 0. */
- u32 c2_ttbr1; /* MMU translation table base 1. */
- u32 c2_ttbcr; /* MMU translation table base control. */
- u32 c2_mask; /* MMU translation table base selection mask. */
- u32 c2_base_mask; /* MMU translation table base 0 mask. */
- u32 c3_dacr; /* MMU domain access control register */
- u32 c5_ifsr; /* Fault status registers. */
- u32 c5_dfsr; /* Fault status registers. */
- u32 c5_aifsr; /* Auxillary fault status registers. */
- u32 c5_adfsr; /* Auxillary fault status registers. */
- u32 c6_ifar; /* Fault address registers. */
- u32 c6_dfar; /* Fault address registers. */
- u32 c7_par; /* Translation result. */
- u64 c7_par64; /* Translation result. (To be used in future) */
- u32 c9_insn; /* Cache lockdown registers. */
- u32 c9_data;
- u32 c9_pmcr; /* performance monitor control register */
- u32 c9_pmcnten; /* perf monitor counter enables */
- u32 c9_pmovsr; /* perf monitor overflow status */
- u32 c9_pmxevtyper; /* perf monitor event type */
- u32 c9_pmuserenr; /* perf monitor user enable */
- u32 c9_pminten; /* perf monitor interrupt enables */
- u32 c12_vbar; /* non-secure vector base addr */
- u32 c10_prrr;
- u32 c10_nmrr;
- u32 c13_fcse; /* FCSE PID. */
- u32 c13_context; /* Context ID. */
- u32 c13_tls1; /* User RW Thread register. */
- u32 c13_tls2; /* User RO Thread register. */
- u32 c13_tls3; /* Privileged Thread register. */
- u32 c15_i_max; /* Maximum D-cache dirty line index. */
- u32 c15_i_min; /* Minimum D-cache dirty line index. */
-} __packed;
-
-struct arm_priv {
- /* Priviledged CPSR */
- u32 cpsr;
- /* Banked Registers */
- u32 gpr_usr[CPU_FIQ_GPR_COUNT]; /* User Mode */
- u32 sp_usr;
- u32 lr_usr;
- u32 sp_svc; /* Supervisor Mode */
- u32 lr_svc;
- u32 spsr_svc;
- u32 sp_mon; /* Monitor Mode */
- u32 lr_mon;
- u32 spsr_mon;
- u32 sp_abt; /* Abort Mode */
- u32 lr_abt;
- u32 spsr_abt;
- u32 sp_und; /* Undefined Mode */
- u32 lr_und;
- u32 spsr_und;
- u32 sp_irq; /* IRQ Mode */
- u32 lr_irq;
- u32 spsr_irq;
- u32 gpr_fiq[CPU_FIQ_GPR_COUNT]; /* FIQ Mode */
- u32 sp_fiq;
- u32 lr_fiq;
- u32 spsr_fiq;
- /* Internal CPU feature flags. */
- u64 features;
- /* VFP context (cp10 & cp11 coprocessors) */
- struct arm_priv_vfp vfp;
- /* Debug, Trace, and ThumbEE (cp14 coprocessor) */
- struct arm_priv_cp14 cp14;
- /* System control (cp15 coprocessor) */
- struct arm_priv_cp15 cp15;
-};
-
-struct arm_guest_priv {
- /* Overlapping vector page */
- u32 *ovect;
- /* PSCI version
- * Bits[31:16] = Major number
- * Bits[15:0] = Minor number
- */
- u32 psci_version;
-};
-
-#define arm_regs(vcpu) (&((vcpu)->regs))
-#define arm_priv(vcpu) ((struct arm_priv *)((vcpu)->arch_priv))
-#define arm_guest_priv(guest) ((struct arm_guest_priv *)((guest)->arch_priv))
-
-#define arm_cpuid(vcpu) (arm_priv(vcpu)->cp15.c0_midr)
-#define arm_set_feature(vcpu, feat) \
- (arm_priv(vcpu)->features |= (0x1ULL << (feat)))
-#define arm_clear_feature(vcpu, feat) \
- (arm_priv(vcpu)->features &= ~(0x1ULL << (feat)))
-#define arm_feature(vcpu, feat) (arm_priv(vcpu)->features & (0x1ULL << (feat)))
-
-/**
- * Instruction emulation support macros
- */
-#define arm_pc(regs) ((regs)->pc)
-#define arm_cpsr(regs) ((regs)->cpsr)
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_sections.h b/arch/arm/cpu/arm32/include/arch_sections.h
deleted file mode 100644
index 4f1ed0af..00000000
--- a/arch/arm/cpu/arm32/include/arch_sections.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_sections.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief interface for accessing VMM sections
- */
-#ifndef _ARCH_SECTIONS_H__
-#define _ARCH_SECTIONS_H__
-
-#include <vmm_types.h>
-
-/** Overall code */
-virtual_addr_t arch_code_vaddr_start(void);
-physical_addr_t arch_code_paddr_start(void);
-virtual_size_t arch_code_size(void);
-
-/** Module table */
-extern u8 _modtbl_start;
-extern u8 _modtbl_end;
-static inline virtual_addr_t arch_modtbl_vaddr(void)
-{
- return (virtual_addr_t) &_modtbl_start;
-}
-static inline virtual_size_t arch_modtbl_size(void)
-{
- return (virtual_size_t) (&_modtbl_end - &_modtbl_start);
-}
-
-/** PerCPU section */
-extern u8 _percpu_start;
-extern u8 _percpu_end;
-static inline virtual_addr_t arch_percpu_vaddr(void)
-{
- return (virtual_addr_t) &_percpu_start;
-}
-static inline virtual_size_t arch_percpu_size(void)
-{
- return (virtual_size_t) (&_percpu_end - &_percpu_start);
-}
-
-/** Init section */
-extern u8 _init_start;
-extern u8 _init_end;
-static inline virtual_addr_t arch_init_vaddr(void)
-{
- return (virtual_addr_t) &_init_start;
-}
-static inline virtual_size_t arch_init_size(void)
-{
- return (virtual_size_t) (&_init_end - &_init_start);
-}
-
-/** Device tree nodeid table */
-extern u8 _nidtbl_start;
-extern u8 _nidtbl_end;
-static inline virtual_addr_t arch_nidtbl_vaddr(void)
-{
- return (virtual_addr_t) &_nidtbl_start;
-}
-static inline virtual_size_t arch_nidtbl_size(void)
-{
- return (virtual_size_t) (&_nidtbl_end - &_nidtbl_start);
-}
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/arch_types.h b/arch/arm/cpu/arm32/include/arch_types.h
deleted file mode 100644
index 95ddb919..00000000
--- a/arch/arm/cpu/arm32/include/arch_types.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file arch_types.h
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @brief common header file for typedefs
- */
-#ifndef _ARCH_TYPES_H__
-#define _ARCH_TYPES_H__
-
-/** cpu specific types */
-typedef unsigned int irq_flags_t;
-typedef unsigned int virtual_addr_t;
-typedef unsigned int virtual_size_t;
-typedef unsigned int physical_addr_t;
-typedef unsigned int physical_size_t;
-
-#define __ARCH_PRIADDR_PREFIX ""
-#define __ARCH_PRIADDR_DIGITS "8"
-#define __ARCH_PRISIZE_PREFIX ""
-#define __ARCH_PRIPADDR_PREFIX ""
-#define __ARCH_PRIPADDR_DIGITS "8"
-#define __ARCH_PRIPSIZE_PREFIX ""
-#define __ARCH_PRI64_PREFIX "ll"
-
-typedef struct {
- volatile long counter;
-} atomic_t;
-
-typedef struct {
- volatile long long counter;
-} atomic64_t;
-
-typedef struct {
- volatile long lock;
-} arch_spinlock_t;
-
-#define ARCH_ATOMIC_INIT(_lptr, val) \
- (_lptr)->counter = (val)
-
-#define ARCH_ATOMIC_INITIALIZER(val) \
- { .counter = (val), }
-
-#define ARCH_ATOMIC64_INIT(_lptr, val) \
- (_lptr)->counter = (val)
-
-#define ARCH_ATOMIC64_INITIALIZER(val) \
- { .counter = (val), }
-
-#define __ARCH_SPIN_UNLOCKED 0xffffffff
-
-/* FIXME: Need memory barrier for this. */
-#define ARCH_SPIN_LOCK_INIT(_lptr) \
- (_lptr)->lock = __ARCH_SPIN_UNLOCKED
-
-#define ARCH_SPIN_LOCK_INITIALIZER \
- { .lock = __ARCH_SPIN_UNLOCKED, }
-
-typedef struct {
- volatile long lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCKED 0x80000000
-#define __ARCH_RW_UNLOCKED 0
-
-/* FIXME: Need memory barrier for this. */
-#define ARCH_RW_LOCK_INIT(_lptr) \
- (_lptr)->lock = __ARCH_RW_UNLOCKED
-
-#define ARCH_RW_LOCK_INITIALIZER \
- { .lock = __ARCH_RW_UNLOCKED, }
-
-#define ARCH_BITS_PER_LONG 32
-#define ARCH_BITS_PER_LONG_LONG 64
-
-#endif /* _ARCH_TYPES_H__ */
diff --git a/arch/arm/cpu/arm32/include/cpu_cache.h b/arch/arm/cpu/arm32/include/cpu_cache.h
deleted file mode 100644
index 1b2da297..00000000
--- a/arch/arm/cpu/arm32/include/cpu_cache.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_cache.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief cache interface of a ARM processor
- */
-#ifndef __CPU_CACHE_H__
-#define __CPU_CACHE_H__
-
-#include <vmm_types.h>
-
-/** Invalidate all instruction caches */
-void invalidate_icache(void);
-
-/** Invalidate instruction cache line by MVA to PoU */
-void invalidate_icache_mva(virtual_addr_t mva);
-
-/** Invalidate instruction cache line by set/way */
-void invalidate_icache_line(u32 line);
-
-/** Invalidate entire branch predictor array */
-void invalidate_bpredictor(void);
-
-/** Invalidate MVA from branch predictor array */
-void invalidate_bpredictor_mva(virtual_addr_t mva);
-
-/** Invalidate data caches */
-void invalidate_dcache(void);
-
-/** Invalidate data cache line by MVA */
-void invalidate_dcache_mva(virtual_addr_t mva);
-
-/** Invalidate data cache lines by MVA range */
-void invalidate_dcache_mva_range(virtual_addr_t start, virtual_addr_t end);
-
-/** Invalidate data cache line by set/way */
-void invalidate_dcache_line(u32 line);
-
-/** Invalidate unified (instruction or data) cache */
-void invalidate_idcache(void);
-
-/** Invalidate unified cache line by MVA */
-void invalidate_idcache_mva(virtual_addr_t mva);
-
-/** Invalidate unified cache line by set/way */
-void invalidate_idcache_line(u32 line);
-
-/** Clean data cache */
-void clean_dcache(void);
-
-/** Clean data cache line by MVA */
-void clean_dcache_mva(virtual_addr_t mva);
-
-/** Clean data cache line by MVA range */
-void clean_dcache_mva_range(virtual_addr_t start, virtual_addr_t end);
-
-/** Clean data cache line by set/way */
-void clean_dcache_line(u32 line);
-
-/** Clean unified (instruction or data) cache */
-void clean_idcache(void);
-
-/** Clean unified cache line by MVA */
-void clean_idcache_mva(virtual_addr_t mva);
-
-/** Clean unified cache line by set/way */
-void clean_idcache_line(u32 line);
-
-/** Clean and invalidate data cache */
-void clean_invalidate_dcache(void);
-
-/** Clean and invalidate data cache line by MVA */
-void clean_invalidate_dcache_mva(virtual_addr_t mva);
-
-/** Clean and invalidate data cache lines by MVA range */
-void clean_invalidate_dcache_mva_range(virtual_addr_t start, virtual_addr_t end);
-
-/** Clean and invalidate data cache line by set/way */
-void clean_invalidate_dcache_line(u32 line);
-
-/** Clean and invalidate unified (instruction or data) cache */
-void clean_invalidate_idcache(void);
-
-/** Clean and invalidate unified cache line by MVA */
-void clean_invalidate_idcache_mva(virtual_addr_t mva);
-
-/** Clean and invalidate unified cache line by set/way */
-void clean_invalidate_idcache_line(u32 line);
-
-#endif /* __CPU_CACHE_H__ */
diff --git a/arch/arm/cpu/arm32/include/cpu_defines.h b/arch/arm/cpu/arm32/include/cpu_defines.h
deleted file mode 100644
index 43f6e15a..00000000
--- a/arch/arm/cpu/arm32/include/cpu_defines.h
+++ /dev/null
@@ -1,584 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_defines.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief common macros & defines for shared by all C & Assembly code
- */
-#ifndef __CPU_DEFINES_H__
-#define __CPU_DEFINES_H__
-
-/* Maximum allowed VTLB entries */
-#define CPU_VCPU_VTLB_ZONE_V 0
-#define CPU_VCPU_VTLB_ZONE_V_LEN 16
-#define CPU_VCPU_VTLB_ZONE_HVEC 1
-#define CPU_VCPU_VTLB_ZONE_HVEC_LEN 16
-#define CPU_VCPU_VTLB_ZONE_LVEC 2
-#define CPU_VCPU_VTLB_ZONE_LVEC_LEN 16
-#define CPU_VCPU_VTLB_ZONE_G 3
-#define CPU_VCPU_VTLB_ZONE_G_LEN 256
-#define CPU_VCPU_VTLB_ZONE_NG 4
-#define CPU_VCPU_VTLB_ZONE_NG_LEN 128
-#define CPU_VCPU_VTLB_ZONE_COUNT 5
-#define CPU_VCPU_VTLB_ENTRY_COUNT \
- (CPU_VCPU_VTLB_ZONE_V_LEN + \
- CPU_VCPU_VTLB_ZONE_HVEC_LEN + \
- CPU_VCPU_VTLB_ZONE_LVEC_LEN + \
- CPU_VCPU_VTLB_ZONE_G_LEN + \
- CPU_VCPU_VTLB_ZONE_NG_LEN)
-
-/* Coprocessor related macros & defines */
-#define CPU_COPROC_COUNT 16
-
-/* GPR related macros & defines */
-#define CPU_GPR_COUNT 13
-#define CPU_FIQ_GPR_COUNT 5
-
-/* Interrupt or Exception related macros & defines */
-#define CPU_IRQ_NR 8
-#define CPU_IRQ_LOWVEC_BASE 0x00000000
-#define CPU_IRQ_HIGHVEC_BASE 0xFFFF0000
-#define CPU_RESET_IRQ 0
-#define CPU_UNDEF_INST_IRQ 1
-#define CPU_SOFT_IRQ 2
-#define CPU_PREFETCH_ABORT_IRQ 3
-#define CPU_DATA_ABORT_IRQ 4
-#define CPU_NOT_USED_IRQ 5
-#define CPU_EXTERNAL_IRQ 6
-#define CPU_EXTERNAL_FIQ 7
-
-/* CPSR related macros & defines */
-#define CPSR_MODE_MASK 0x0000001f
-#define CPSR_MODE_USER 0x00000010
-#define CPSR_MODE_FIQ 0x00000011
-#define CPSR_MODE_IRQ 0x00000012
-#define CPSR_MODE_SUPERVISOR 0x00000013
-#define CPSR_MODE_MONITOR 0x00000016
-#define CPSR_MODE_ABORT 0x00000017
-#define CPSR_MODE_UNDEFINED 0x0000001b
-#define CPSR_MODE_SYSTEM 0x0000001f
-#define CPSR_THUMB_ENABLED (1 << 5)
-#define CPSR_FIQ_DISABLED (1 << 6)
-#define CPSR_IRQ_DISABLED (1 << 7)
-#define CPSR_ASYNC_ABORT_DISABLED (1 << 8)
-#define CPSR_BE_ENABLED (1 << 9)
-#define CPSR_IT2_MASK 0x0000FC00
-#define CPSR_IT2_SHIFT 10
-#define CPSR_GE_MASK 0x000F0000
-#define CPSR_GE_SHIFT 16
-#define CPSR_JAZZLE_ENABLED (1 << 24)
-#define CPSR_IT1_MASK 0x06000000
-#define CPSR_IT1_SHIFT 25
-#define CPSR_CUMMULATE_MASK (1 << 27)
-#define CPSR_CUMMULATE_SHIFT 27
-#define CPSR_OVERFLOW_MASK (1 << 28)
-#define CPSR_OVERFLOW_SHIFT 28
-#define CPSR_CARRY_MASK (1 << 29)
-#define CPSR_CARRY_SHIFT 29
-#define CPSR_ZERO_MASK (1 << 30)
-#define CPSR_ZERO_SHIFT 30
-#define CPSR_NEGATIVE_MASK (1 << 31)
-#define CPSR_NEGATIVE_SHIFT 31
-
-#define CPSR_NZCV_MASK (CPSR_NEGATIVE_MASK |\
- CPSR_ZERO_MASK |\
- CPSR_CARRY_MASK |\
- CPSR_OVERFLOW_MASK)
-#define CPSR_IT_MASK (CPSR_IT2_MASK |\
- CPSR_IT1_MASK)
-#define CPSR_USERBITS_MASK (CPSR_NZCV_MASK |\
- CPSR_CUMMULATE_MASK |\
- CPSR_GE_MASK |\
- CPSR_IT_MASK |\
- CPSR_THUMB_ENABLED)
-#define CPSR_PRIVBITS_MASK (~CPSR_USERBITS_MASK)
-#define CPSR_ALLBITS_MASK 0xFFFFFFFF
-
-/* VFP system registers. */
-#define VFP_FPSID 0
-#define VFP_FPSCR 1
-#define VFP_MVFR1 6
-#define VFP_MVFR0 7
-#define VFP_FPEXC 8
-#define VFP_FPINST 9
-#define VFP_FPINST2 10
-
-/* iwMMXt coprocessor control registers. */
-#define IWMMXT_wCID 0
-#define IWMMXT_wCon 1
-#define IWMMXT_wCSSF 2
-#define IWMMXT_wCASF 3
-#define IWMMXT_wCGR0 8
-#define IWMMXT_wCGR1 9
-#define IWMMXT_wCGR2 10
-#define IWMMXT_wCGR3 11
-
-/* SCTLR related macros & defines */
-#define SCTLR_TE_MASK 0x40000000
-#define SCTLR_AFE_MASK 0x20000000
-#define SCTLR_TRE_MASK 0x10000000
-#define SCTLR_NFI_MASK 0x08000000
-#define SCTLR_EE_MASK 0x02000000
-#define SCTLR_VE_MASK 0x01000000
-#define SCTLR_V6_MASK 0x00800000
-#define SCTLR_U_MASK 0x00400000
-#define SCTLR_FI_MASK 0x00200000
-#define SCTLR_HA_MASK 0x00020000
-#define SCTLR_RR_MASK 0x00004000
-#define SCTLR_L4_MASK 0x00004000
-#define SCTLR_V_MASK 0x00002000
-#define SCTLR_I_MASK 0x00001000
-#define SCTLR_Z_MASK 0x00000800
-#define SCTLR_SW_MASK 0x00000400
-#define SCTLR_R_MASK 0x00000200
-#define SCTLR_S_MASK 0x00000100
-#define SCTLR_B_MASK 0x00000080
-#define SCTLR_C_MASK 0x00000004
-#define SCTLR_A_MASK 0x00000002
-#define SCTLR_M_MASK 0x00000001
-#define SCTLR_ROBITS_MASK 0x849D8378
-#define SCTLR_V6_ROBITS_MASK 0xB01F0470
-#define SCTLR_V6K_ROBITS_MASK 0x801D0470
-#define SCTLR_V5_ROBITS_MASK 0xFFFF0C78
-#define SCTLR_MMU_MASK (SCTLR_M_MASK | \
- SCTLR_TRE_MASK | \
- SCTLR_AFE_MASK | \
- SCTLR_U_MASK)
-
-/* MPIDR related macros & defines */
-#define MPIDR_SMP_BITMASK (0x3 << 30)
-#define MPIDR_SMP_VALUE (0x2 << 30)
-#define MPIDR_MT_BITMASK (0x1 << 24)
-#define MPIDR_HWID_BITMASK 0xFFFFFF
-#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
-#define MPIDR_LEVEL_BITS_SHIFT 3
-#define MPIDR_LEVEL_BITS \
- (1 << MPIDR_LEVEL_BITS_SHIFT)
-#define MPIDR_LEVEL_MASK \
- ((1 << MPIDR_LEVEL_BITS) - 1)
-#define MPIDR_LEVEL_SHIFT(level) \
- (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
-#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
- ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
-
-/* CPACR related macros & define */
-#define CPACR_ASEDIS_MASK 0x80000000
-#define CPACR_ASEDIS_SHIFT 31
-#define CPACR_D32DIS_MASK 0x40000000
-#define CPACR_D32DIS_SHIFT 30
-#define CPACR_TRCDIS_MASK 0x10000000
-#define CPACR_TRCDIS_SHIFT 28
-#define CPACR_CP_MASK(n) (0x3 << ((n)*2))
-#define CPACR_CP_SHIFT(n) ((n)*2)
-
-/* CTR related macros & defines */
-#define CTR_FORMAT_MASK 0xE0000000
-#define CTR_FORMAT_SHIFT 29
-#define CTR_FORMAT_V6 0x0
-#define CTR_FORMAT_V7 0x4
-#define CTR_CWG_MASK 0x0F000000
-#define CTR_CWG_SHIFT 24
-#define CTR_ERG_MASK 0x00F00000
-#define CTR_ERG_SHIFT 20
-#define CTR_DMINLINE_MASK 0x000F0000
-#define CTR_DMINLINE_SHIFT 20
-#define CTR_L1IP_MASK 0x0000C000
-#define CTR_L1IP_SHIFT 14
-#define CTR_IMINLINE_MASK 0x0000000F
-#define CTR_IMINLINE_SHIFT 0
-#define CTR_V6_CTYPE_MASK 0x1E000000
-#define CTR_V6_CTYPE_SHIFT 25
-#define CTR_V6_S_MASK 0x01000000
-#define CTR_V6_S_SHIFT 24
-#define CTR_V6_DSIZE_MASK 0x00FFF000
-#define CTR_V6_DSIZE_SHIFT 12
-#define CTR_V6_ISIZE_MASK 0x00000FFF
-#define CTR_V6_ISIZE_SHIFT 0
-
-/* CLIDR related macros & defines */
-#define CLIDR_LOUU_MASK 0x38000000
-#define CLIDR_LOUU_SHIFT 27
-#define CLIDR_LOC_MASK 0x07000000
-#define CLIDR_LOC_SHIFT 24
-#define CLIDR_LOUIS_MASK 0x00E00000
-#define CLIDR_LOUIS_SHIFT 21
-#define CLIDR_CTYPE7_MASK 0x001C0000
-#define CLIDR_CTYPE7_SHIFT 18
-#define CLIDR_CTYPE6_MASK 0x00038000
-#define CLIDR_CTYPE6_SHIFT 15
-#define CLIDR_CTYPE5_MASK 0x00007000
-#define CLIDR_CTYPE5_SHIFT 12
-#define CLIDR_CTYPE4_MASK 0x00000E00
-#define CLIDR_CTYPE4_SHIFT 9
-#define CLIDR_CTYPE3_MASK 0x000001C0
-#define CLIDR_CTYPE3_SHIFT 6
-#define CLIDR_CTYPE2_MASK 0x00000038
-#define CLIDR_CTYPE2_SHIFT 3
-#define CLIDR_CTYPE1_MASK 0x00000007
-#define CLIDR_CTYPE1_SHIFT 0
-#define CLIDR_CTYPE_NOCACHE 0x0
-#define CLIDR_CTYPE_ICACHE 0x1
-#define CLIDR_CTYPE_DCACHE 0x2
-#define CLIDR_CTYPE_SPLITCACHE 0x3
-#define CLIDR_CTYPE_UNICACHE 0x4
-#define CLIDR_CTYPE_RESERVED1 0x5
-#define CLIDR_CTYPE_RESERVED2 0x6
-#define CLIDR_CTYPE_RESERVED3 0x7
-
-/* CSSELR related macros & defines */
-#define CSSELR_LEVEL_MASK 0x0000000E
-#define CSSELR_LEVEL_SHIFT 1
-#define CSSELR_IND_MASK 0x00000001
-#define CSSELR_IND_SHIFT 0
-
-/* CSSIDR related macros & defines */
-#define CCSIDR_WT_MASK 0x80000000
-#define CCSIDR_WT_SHIFT 31
-#define CCSIDR_WB_MASK 0x40000000
-#define CCSIDR_WB_SHIFT 30
-#define CCSIDR_RA_MASK 0x20000000
-#define CCSIDR_RA_SHIFT 29
-#define CCSIDR_WA_MASK 0x10000000
-#define CCSIDR_WA_SHIFT 28
-#define CCSIDR_NUMSETS_MASK 0x0FFFE000
-#define CCSIDR_NUMSETS_SHIFT 13
-#define CCSIDR_ASSOC_MASK 0x00001FF8
-#define CCSIDR_ASSOC_SHIFT 3
-#define CCSIDR_LINESZ_MASK 0x00000007
-#define CCSIDR_LINESZ_SHIFT 0
-
-/* Translation table related macros & defines */
-#define TTBL_MIN_SIZE 0x1000
-#define TTBL_MIN_PAGE_SIZE TTBL_MIN_SIZE
-#define TTBL_MIN_PAGE_MASK (TTBL_MIN_PAGE_SIZE - 1)
-#define TTBL_MIN_PAGE_SHIFT 12
-#define TTBL_MAX_SIZE 0x4000
-#define TTBL_MAX_PAGE_SIZE 0x1000000
-#define TTBL_MAX_PAGE_MASK (TTBL_MAX_PAGE_SIZE - 1)
-#define TTBL_MAX_PAGE_SHIFT 24
-#define TTBL_AP_S_U 0x0
-#define TTBL_AP_SRW_U 0x1
-#define TTBL_AP_SRW_UR 0x2
-#define TTBL_AP_SRW_URW 0x3
-#define TTBL_AP_SR_U 0x5
-#define TTBL_AP_SR_UR_DEPRECATED 0x6
-#define TTBL_AP_SR_UR 0x7
-#define TTBL_DOM_MANAGER 0x3
-#define TTBL_DOM_RESERVED 0x2
-#define TTBL_DOM_CLIENT 0x1
-#define TTBL_DOM_NOACCESS 0x0
-#define TTBL_L1TBL_SIZE 0x4000
-#define TTBL_L1TBL_MASK (TTBL_L1TBL_SIZE - 1)
-#define TTBL_L1TBL_SIZE_SHIFT 14
-#define TTBL_L1TBL_SECTION_PAGE_SHIFT 20
-#define TTBL_L1TBL_SECTION_PAGE_SIZE (1 << TTBL_L1TBL_SECTION_PAGE_SHIFT)
-#define TTBL_L1TBL_SECTION_PAGE_MASK (TTBL_L1TBL_SECTION_PAGE_SIZE - 1)
-#define TTBL_L1TBL_SUPSECTION_PAGE_SIZE 0x1000000
-#define TTBL_L1TBL_SUPSECTION_PAGE_MASK (TTBL_L1TBL_SUPSECTION_PAGE_SIZE - 1)
-#define TTBL_L1TBL_TTE_OFFSET_MASK 0xFFF00000
-#define TTBL_L1TBL_TTE_OFFSET_SHIFT 20
-#define TTBL_L1TBL_TTE_BASE24_MASK 0xFF000000
-#define TTBL_L1TBL_TTE_BASE24_SHIFT 24
-#define TTBL_L1TBL_TTE_BASE20_MASK 0xFFF00000
-#define TTBL_L1TBL_TTE_BASE20_SHIFT 20
-#define TTBL_L1TBL_TTE_BASE10_MASK 0xFFFFFC00
-#define TTBL_L1TBL_TTE_BASE10_SHIFT 10
-#define TTBL_L1TBL_TTE_NS2_MASK 0x00080000
-#define TTBL_L1TBL_TTE_NS2_SHIFT 19
-#define TTBL_L1TBL_TTE_SECTYPE_MASK 0x00040000
-#define TTBL_L1TBL_TTE_SECTYPE_SHIFT 18
-#define TTBL_L1TBL_TTE_NG_MASK 0x00020000
-#define TTBL_L1TBL_TTE_NG_SHIFT 17
-#define TTBL_L1TBL_TTE_S_MASK 0x00010000
-#define TTBL_L1TBL_TTE_S_SHIFT 16
-#define TTBL_L1TBL_TTE_AP2_MASK 0x00008000
-#define TTBL_L1TBL_TTE_AP2_SHIFT 15
-#define TTBL_L1TBL_TTE_TEX_MASK 0x00007000
-#define TTBL_L1TBL_TTE_TEX_SHIFT 12
-#define TTBL_L1TBL_TTE_AP_MASK 0x00000C00
-#define TTBL_L1TBL_TTE_AP_SHIFT 10
-#define TTBL_L1TBL_TTE_IMP_MASK 0x00000200
-#define TTBL_L1TBL_TTE_IMP_SHIFT 9
-#define TTBL_L1TBL_TTE_DOM_MASK 0x000001E0
-#define TTBL_L1TBL_TTE_DOM_SHIFT 5
-#define TTBL_L1TBL_TTE_DOM_RESERVED 0x0
-#define TTBL_L1TBL_TTE_DOM_VCPU_SUPER 0x1
-#define TTBL_L1TBL_TTE_DOM_VCPU_SUPER_RW_USER_R 0x2
-#define TTBL_L1TBL_TTE_DOM_VCPU_USER 0x3
-#define TTBL_L1TBL_TTE_XN_SHIFT 4
-#define TTBL_L1TBL_TTE_XN_MASK (1 << TTBL_L1TBL_TTE_XN_SHIFT)
-#define TTBL_L1TBL_TTE_REQ_SHIFT 4
-#define TTBL_L1TBL_TTE_REQ_MASK (1 << TTBL_L1TBL_TTE_REQ_SHIFT)
-#define TTBL_L1TBL_TTE_NS1_SHIFT 3
-#define TTBL_L1TBL_TTE_NS1_MASK (1 << TTBL_L1TBL_TTE_NS1_SHIFT)
-#define TTBL_L1TBL_TTE_C_SHIFT 3
-#define TTBL_L1TBL_TTE_C_MASK (1 << TTBL_L1TBL_TTE_C_SHIFT)
-#define TTBL_L1TBL_TTE_B_SHIFT 2
-#define TTBL_L1TBL_TTE_B_MASK (1 << TTBL_L1TBL_TTE_B_SHIFT)
-#define TTBL_L1TBL_TTE_TYPE_MASK 0x00000003
-#define TTBL_L1TBL_TTE_TYPE_SHIFT 0
-#define TTBL_L1TBL_TTE_TYPE_FAULT 0x0
-#define TTBL_L1TBL_TTE_TYPE_L2TBL 0x1
-#define TTBL_L1TBL_TTE_TYPE_COARSE_L2TBL TTBL_L1TBL_TTE_TYPE_L2TBL
-#define TTBL_L1TBL_TTE_TYPE_SECTION 0x2
-#define TTBL_L1TBL_TTE_TYPE_RESERVED 0x3
-#define TTBL_L1TBL_TTE_TYPE_FINE_L2TBL TTBL_L1TBL_TTE_TYPE_RESERVED
-#define TTBL_L2TBL_SIZE 0x400
-#define TTBL_L2TBL_SIZE_SHIFT 10
-#define TTBL_L2TBL_LARGE_PAGE_SIZE 0x10000
-#define TTBL_L2TBL_SMALL_PAGE_SIZE 0x1000
-#define TTBL_L2TBL_TINY_PAGE_SIZE 0x400
-#define TTBL_L2TBL_TTE_OFFSET_MASK 0x000FF000
-#define TTBL_L2TBL_TTE_OFFSET_SHIFT 12
-#define TTBL_L2TBL_TTE_BASE16_MASK 0xFFFF0000
-#define TTBL_L2TBL_TTE_BASE16_SHIFT 16
-#define TTBL_L2TBL_TTE_LXN_MASK 0x00008000
-#define TTBL_L2TBL_TTE_LXN_SHIFT 15
-#define TTBL_L2TBL_TTE_BASE12_MASK 0xFFFFF000
-#define TTBL_L2TBL_TTE_BASE12_SHIFT 12
-#define TTBL_L2TBL_TTE_LTEX_MASK 0x00007000
-#define TTBL_L2TBL_TTE_LTEX_SHIFT 12
-#define TTBL_L2TBL_TTE_NG_MASK 0x00000800
-#define TTBL_L2TBL_TTE_NG_SHIFT 11
-#define TTBL_L2TBL_TTE_S_MASK 0x00000400
-#define TTBL_L2TBL_TTE_S_SHIFT 10
-#define TTBL_L2TBL_TTE_AP2_MASK 0x00000200
-#define TTBL_L2TBL_TTE_AP2_SHIFT 9
-#define TTBL_L2TBL_TTE_STEX_MASK 0x000001C0
-#define TTBL_L2TBL_TTE_STEX_SHIFT 6
-#define TTBL_L2TBL_TTE_AP_SHIFT 4
-#define TTBL_L2TBL_TTE_AP_MASK (3 << TTBL_L2TBL_TTE_AP_SHIFT)
-#define TTBL_L2TBL_TTE_V5_AP0_SHIFT 4
-#define TTBL_L2TBL_TTE_V5_AP0_MASK (3 << TTBL_L2TBL_TTE_V5_AP0_SHIFT)
-#define TTBL_L2TBL_TTE_V5_AP1_SHIFT 6
-#define TTBL_L2TBL_TTE_V5_AP1_MASK (3 << TTBL_L2TBL_TTE_V5_AP1_SHIFT)
-#define TTBL_L2TBL_TTE_V5_AP2_SHIFT 8
-#define TTBL_L2TBL_TTE_V5_AP2_MASK (3 << TTBL_L2TBL_TTE_V5_AP2_SHIFT)
-#define TTBL_L2TBL_TTE_V5_AP3_SHIFT 10
-#define TTBL_L2TBL_TTE_V5_AP3_MASK (3 << TTBL_L2TBL_TTE_V5_AP3_SHIFT)
-#define TTBL_L2TBL_TTE_C_MASK 0x00000008
-#define TTBL_L2TBL_TTE_C_SHIFT 3
-#define TTBL_L2TBL_TTE_B_MASK 0x00000004
-#define TTBL_L2TBL_TTE_B_SHIFT 2
-#define TTBL_L2TBL_TTE_SXN_MASK 0x00000001
-#define TTBL_L2TBL_TTE_SXN_SHIFT 0
-#define TTBL_L2TBL_TTE_TYPE_MASK 0x00000003
-#define TTBL_L2TBL_TTE_TYPE_SHIFT 0
-#define TTBL_L2TBL_TTE_TYPE_FAULT 0x0
-#define TTBL_L2TBL_TTE_TYPE_LARGE 0x1
-#define TTBL_L2TBL_TTE_TYPE_SMALL_X 0x2
-#define TTBL_L2TBL_TTE_TYPE_SMALL 0x2
-#define TTBL_L2TBL_TTE_TYPE_SMALL_XN 0x3
-#define TTBL_L2TBL_TTE_TYPE_TINY 0x3
-#define TTBL_INITIAL_L2TBL_COUNT 8
-#define TTBL_INITIAL_L2TBL_SIZE (TTBL_INITIAL_L2TBL_COUNT * TTBL_L2TBL_SIZE)
-
-/* TTBR0 related macros & defines */
-#define TTBR0_IGRN0_MASK 0x00000040
-#define TTBR0_IRGN0_SHIFT 6
-#define TTBR0_NOS_MASK 0x00000020
-#define TTBR0_RGN_MASK 0x00000018
-#define TTBR0_RGN_SHIFT 3
-#define TTBR0_IMP_MASK 0x00000004
-#define TTBR0_S_MASK 0x00000002
-#define TTBR0_C_MASK 0x00000001
-#define TTBR0_IGRN1_MASK 0x00000001
-
-/* TTBR1 related macros & defines */
-#define TTBR1_IGRN0_MASK 0x00000040
-#define TTBR1_IRGN0_SHIFT 6
-#define TTBR1_NOS_MASK 0x00000020
-#define TTBR1_RGN_MASK 0x00000018
-#define TTBR1_RGN_SHIFT 3
-#define TTBR1_IMP_MASK 0x00000004
-#define TTBR1_S_MASK 0x00000002
-#define TTBR1_C_MASK 0x00000001
-#define TTBR1_IGRN1_MASK 0x00000001
-
-/* TTBCR related macros & defines */
-#define TTBCR_PD1_MASK 0x00000020
-#define TTBCR_PD2_MASK 0x00000010
-#define TTBCR_N_MASK 0x00000007
-
-/* IFSR related macros & defines */
-#define IFSR_EXT_MASK 0x00001000
-#define IFSR_EXT_SHIFT 12
-#define IFSR_FS4_MASK 0x00000400
-#define IFSR_FS4_SHIFT 10
-#define IFSR_FS_MASK 0x0000000F
-#define IFSR_FS_SHIFT 0
-#define IFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_1 12
-#define IFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_2 14
-#define IFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_1 28
-#define IFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_2 30
-#define IFSR_FS_TRANS_FAULT_SECTION 5
-#define IFSR_FS_TRANS_FAULT_PAGE 7
-#define IFSR_FS_ACCESS_FAULT_SECTION 3
-#define IFSR_FS_ACCESS_FAULT_PAGE 6
-#define IFSR_FS_DOMAIN_FAULT_SECTION 9
-#define IFSR_FS_DOMAIN_FAULT_PAGE 11
-#define IFSR_FS_PERM_FAULT_SECTION 13
-#define IFSR_FS_PERM_FAULT_PAGE 15
-#define IFSR_FS_DEBUG_EVENT 2
-#define IFSR_FS_SYNC_EXT_ABORT 8
-#define IFSR_FS_IMP_VALID_LOCKDOWN 20
-#define IFSR_FS_IMP_VALID_COPROC_ABORT 26
-#define IFSR_FS_MEM_ACCESS_SYNC_PARITY_ERROR 25
-
-/* DFSR related macros & defines */
-#define DFSR_EXT_MASK 0x00001000
-#define DFSR_EXT_SHIFT 12
-#define DFSR_WNR_MASK 0x00000800
-#define DFSR_WNR_SHIFT 11
-#define DFSR_FS4_MASK 0x00000400
-#define DFSR_FS4_SHIFT 10
-#define DFSR_DOM_MASK 0x000000F0
-#define DFSR_DOM_SHIFT 4
-#define DFSR_FS_MASK 0x0000000F
-#define DFSR_FS_SHIFT 0
-#define DFSR_FS_ALIGN_FAULT 1
-#define DFSR_FS_ICACHE_MAINT_FAULT 4
-#define DFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_1 12
-#define DFSR_FS_TTBL_WALK_SYNC_EXT_ABORT_2 14
-#define DFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_1 28
-#define DFSR_FS_TTBL_WALK_SYNC_PARITY_ERROR_2 30
-#define DFSR_FS_TRANS_FAULT_SECTION 5
-#define DFSR_FS_TRANS_FAULT_PAGE 7
-#define DFSR_FS_ACCESS_FAULT_SECTION 3
-#define DFSR_FS_ACCESS_FAULT_PAGE 6
-#define DFSR_FS_DOMAIN_FAULT_SECTION 9
-#define DFSR_FS_DOMAIN_FAULT_PAGE 11
-#define DFSR_FS_PERM_FAULT_SECTION 13
-#define DFSR_FS_PERM_FAULT_PAGE 15
-#define DFSR_FS_DEBUG_EVENT 2
-#define DFSR_FS_SYNC_EXT_ABORT 8
-#define DFSR_FS_IMP_VALID_LOCKDOWN 20
-#define DFSR_FS_IMP_VALID_COPROC_ABORT 26
-#define DFSR_FS_MEM_ACCESS_SYNC_PARITY_ERROR 25
-#define DFSR_FS_ASYNC_EXT_ABORT 22
-#define DFSR_FS_MEM_ACCESS_ASYNC_PARITY_ERROR 24
-
-/* PAR */
-#define PAR_PA_MASK 0xFFFFF000
-#define PAR_PA_SHIFT 12
-#define PAR_LPAE_MASK 0x00000800
-#define PAR_LPAE_SHIFT 11
-#define PAR_NOS_MASK 0x00000400
-#define PAR_NOS_SHIFT 10
-#define PAR_NS_MASK 0x00000200
-#define PAR_NS_SHIFT 9
-#define PAR_SH_MASK 0x00000080
-#define PAR_SH_SHIFT 7
-#define PAR_INNER_MASK 0x00000070
-#define PAR_INNER_SHIFT 4
-#define PAR_OUTER_MASK 0x0000000C
-#define PAR_OUTEr_SHIFT 2
-#define PAR_SS_MASK 0x00000002
-#define PAR_SS_SHIFT 1
-#define PAR_F_MASK 0x00000001
-#define PAR_F_SHIFT 0
-
-/* PAR64 */
-#define PAR64_ATTR_MASK 0xFF00000000000000ULL
-#define PAR64_ATTR_SHIFT 56
-#define PAR64_PA_MASK 0x000000FFFFFFF000ULL
-#define PAR64_PA_SHIFT 12
-#define PAR64_LPAE_MASK 0x0000000000000800ULL
-#define PAR64_LPAE_SHIFT 11
-#define PAR64_NS_MASK 0x0000000000000200ULL
-#define PAR64_NS_SHIFT 9
-#define PAR64_SH_MASK 0x0000000000000180ULL
-#define PAR64_SH_SHIFT 7
-#define PAR64_F_MASK 0x0000000000000001ULL
-#define PAR64_F_SHIFT 0
-
-/* MIDR */
-#define MIDR_IMPLEMENTER_MASK 0xFF000000
-#define MIDR_IMPLEMENTER_SHIFT 24
-#define MIDR_VARIANT_MASK 0x00F00000
-#define MIDR_VARIANT_SHIFT 20
-#define MIDR_ARCHITECTURE_MASK 0x000F0000
-#define MIDR_ARCHITECTURE_SHIFT 16
-#define MIDR_PARTNUM_MASK 0x0000FFF0
-#define MIDR_PARTNUM_SHIFT 4
-#define MIDR_REVISON_MASK 0x0000000F
-#define MIDR_REVISON_SHIFT 0
-
-/* FPEXC */
-#define FPEXC_EX_MASK (1u << 31)
-#define FPEXC_EX_SHIFT 31
-#define FPEXC_EN_MASK (1u << 30)
-#define FPEXC_EN_SHIFT 30
-#define FPEXC_FP2V_MASK (1u << 28)
-#define FPEXC_FP2V_SHIFT 28
-
-/* FPSID */
-#define FPSID_IMPLEMENTER_MASK (0xff << 24)
-#define FPSID_IMPLEMENTER_SHIFT (24)
-#define FPSID_SW_MASK (0x1 << 23)
-#define FPSID_SW_SHIFT (23)
-#define FPSID_ARCH_MASK (0x7f << 16)
-#define FPSID_ARCH_SHIFT (16)
-#define FPSID_PART_MASK (0xff << 8)
-#define FPSID_PART_SHIFT (8)
-#define FPSID_VARIANT_MASK (0xf << 4)
-#define FPSID_VARIANT_SHIFT (4)
-#define FPSID_REV_MASK (0xf << 0)
-#define FPSID_REV_SHIFT (0)
-
-/* MVFR0 */
-#define MVFR0_VFP_ROUND_MODES_MASK (0xf << 28)
-#define MVFR0_VFP_ROUND_MODES_SHIFT 28
-#define MVFR0_SHORT_VECTORS_MASK (0xf << 24)
-#define MVFR0_SHORT_VECTORS_SHIFT 24
-#define MVFR0_SQUARE_ROOT_MASK (0xf << 20)
-#define MVFR0_SQUARE_ROOT_SHIFT 20
-#define MVFR0_DIVIDE_MASK (0xf << 16)
-#define MVFR0_DIVIDE_SHIFT 16
-#define MVFR0_VFP_EXEC_TRAP_MASK (0xf << 12)
-#define MVFR0_VFP_EXEC_TRAP_SHIFT 12
-#define MVFR0_DOUBLE_PREC_MASK (0xf << 8)
-#define MVFR0_DOUBLE_PREC_SHIFT 8
-#define MVFR0_SINGLE_PREC_MASK (0xf << 4)
-#define MVFR0_SINGLE_PREC_SHIFT 4
-#define MVFR0_A_SIMD_MASK (0xf << 0)
-#define MVFR0_A_SIMD_SHIFT 0
-
-/* ID_PFR0 */
-#define ID_PFR0_STATE3_MASK 0x0000f000
-#define ID_PFR0_STATE3_SHIFT 12
-#define ID_PFR0_STATE2_MASK 0x00000f00
-#define ID_PFR0_STATE2_SHIFT 8
-#define ID_PFR0_STATE1_MASK 0x000000f0
-#define ID_PFR0_STATE1_SHIFT 4
-#define ID_PFR0_STATE0_MASK 0x00000000
-#define ID_PFR0_STATE0_SHIFT 0
-
-/* ID_PFR1 */
-#define ID_PFR1_GEN_TIMER_MASK 0x000f0000
-#define ID_PFR1_GEN_TIMER_SHIFT 16
-#define ID_PFR1_VIRTEX_MASK 0x0000f000
-#define ID_PFR1_VIRTEX_SHIFT 12
-#define ID_PFR1_M_PROFILE_MASK 0x00000f00
-#define ID_PFR1_M_PROFILE_SHIFT 8
-#define ID_PFR1_SECUREX_MASK 0x000000f0
-#define ID_PFR1_SECUREX_SHIFT 4
-#define ID_PFR1_PRG_MODEL_MASK 0x0000000f
-#define ID_PFR1_PRG_MODEL_SHIFT 0
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/cpu_emulate_psci.h b/arch/arm/cpu/arm32/include/cpu_emulate_psci.h
deleted file mode 100644
index da38bec6..00000000
--- a/arch/arm/cpu/arm32/include/cpu_emulate_psci.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_emulate_psci.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief CPU specific functions for PSCI Emulation
- */
-
-#ifndef __CPU_EMULATE_PSCI_H__
-#define __CPU_EMULATE_PSCI_H__
-
-#include <vmm_types.h>
-#include <cpu_defines.h>
-#include <cpu_vcpu_helper.h>
-
-static inline u32 emulate_psci_version(struct vmm_vcpu *vcpu)
-{
- return arm_guest_priv(vcpu->guest)->psci_version;
-}
-
-static inline bool emulate_psci_is_32bit(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- return TRUE;
-}
-
-static inline void emulate_psci_set_thumb(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- regs->cpsr |= CPSR_THUMB_ENABLED;
-}
-
-static inline bool emulate_psci_is_be(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- return (regs->cpsr & CPSR_BE_ENABLED) ? TRUE : FALSE;
-}
-
-static inline void emulate_psci_set_be(struct vmm_vcpu *vcpu,
- arch_regs_t *regs)
-{
- regs->cpsr |= CPSR_BE_ENABLED;
-}
-
-static inline unsigned long emulate_psci_get_reg(struct vmm_vcpu *vcpu,
- arch_regs_t *regs, u32 reg)
-{
- return (unsigned long)cpu_vcpu_reg_read(vcpu, regs, reg);
-}
-
-static inline void emulate_psci_set_reg(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 reg, unsigned long val)
-{
- cpu_vcpu_reg_write(vcpu, regs, reg, (u32)val);
-}
-
-static inline void emulate_psci_set_pc(struct vmm_vcpu *vcpu,
- arch_regs_t *regs, unsigned long val)
-{
- regs->pc = (u32)val;
-}
-
-static inline unsigned long emulate_psci_get_mpidr(struct vmm_vcpu *vcpu)
-{
- return arm_priv(vcpu)->cp15.c0_mpidr;
-}
-
-#endif /* __CPU_EMULATE_PSCI_H__ */
diff --git a/arch/arm/cpu/arm32/include/cpu_inline_asm.h b/arch/arm/cpu/arm32/include/cpu_inline_asm.h
deleted file mode 100644
index 87126834..00000000
--- a/arch/arm/cpu/arm32/include/cpu_inline_asm.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_inline_asm.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief Frequently required inline assembly macros
- */
-#ifndef __CPU_INLINE_ASM_H__
-#define __CPU_INLINE_ASM_H__
-
-#include <vmm_types.h>
-#include <cpu_defines.h>
-
-#if defined(CONFIG_ARMV5)
-
-static inline u64 rev64(u64 v)
-{
- return ((v & 0x00000000000000FFULL) << 56) |
- ((v & 0x000000000000FF00ULL) << 40) |
- ((v & 0x0000000000FF0000ULL) << 24) |
- ((v & 0x00000000FF000000ULL) << 8) |
- ((v & 0x000000FF00000000ULL) >> 8) |
- ((v & 0x0000FF0000000000ULL) >> 24) |
- ((v & 0x00FF000000000000ULL) >> 40) |
- ((v & 0xFF00000000000000ULL) >> 56);
-}
-
-static inline u32 rev32(u32 v)
-{
- return ((v & 0x000000FF) << 24) |
- ((v & 0x0000FF00) << 8) |
- ((v & 0x00FF0000) >> 8) |
- ((v & 0xFF000000) >> 24);
-}
-
-static inline u16 rev16(u16 v)
-{
- return ((v & 0x00FF) << 8) |
- ((v & 0xFF00) >> 8);
-}
-
-#else
-
-#define rev32(val) ({ u32 rval; asm volatile(\
- " rev %0, %1\n\t" : "=r" (rval) : \
- "r" (val) : "memory", "cc"); rval;})
-
-#define rev64(val) ({ u32 d1, d2; \
- d1 = (u32)((u64)val >> 32); d2 = (u32)val; \
- d1 = rev32(d1); d2 = rev32(d2); \
- (((u64)d2 << 32) | ((u64)d1));})
-
-#define rev16(val) ({ u16 rval; asm volatile(\
- " rev16 %0, %1\n\t" : "=r" (rval) : \
- "r" (val) : "memory", "cc"); rval;})
-
-#endif
-
-#if defined(CONFIG_ARMV5)
-
-/* FIXME: */
-#define ldrex(addr, data) asm volatile("ldr %0, [%1]\n\t" \
- : "=r"(data) : "r"(addr))
-
-/* FIXME: */
-#define strex(addr, data, res) asm volatile("str %0, [%1]\n\t" \
- : : "r"(data), "r"(addr))
-
-/* FIXME: */
-#define clrex()
-
-#elif defined(CONFIG_ARMV6)
-
-#define ldrex(addr, data) asm volatile("ldrex %0, [%1]\n\t" \
- : "=r"(data) : "r"(addr))
-
-#define strex(addr, data, res) asm volatile("strex %0, %1, [%2]\n\t" \
- : "=&r"(res) : "r"(data), "r"(addr))
-
-#define clrex()
-
-#else
-
-#define ldrex(addr, data) asm volatile("ldrex %0, [%1]\n\t" \
- : "=r"(data) : "r"(addr))
-
-#define strex(addr, data, res) asm volatile("strex %0, %1, [%2]\n\t" \
- : "=&r"(res) : "r"(data), "r"(addr))
-
-#define clrex() asm volatile("clrex\n\t")
-
-#endif
-
-/* General CP14 Register Read/Write */
-
-#define read_teecr() ({ u32 rval; asm volatile(\
- " mrc p14, 6, %0, c0, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_teecr(val) asm volatile(\
- " mcr p14, 6, %0, c0, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_teehbr() ({ u32 rval; asm volatile(\
- " mrc p14, 6, %0, c1, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_teehbr(val) asm volatile(\
- " mcr p14, 6, %0, c1, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-/* General CP15 Register Read/Write */
-
-#define read_midr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_ctr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_mpidr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c0, 5\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_ccsidr() ({ u32 rval; asm volatile(\
- " mrc p15, 1, %0, c0, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_clidr() ({ u32 rval; asm volatile(\
- " mrc p15, 1, %0, c0, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_csselr() ({ u32 rval; asm volatile(\
- " mrc p15, 2, %0, c0, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_csselr(val) asm volatile(\
- " mcr p15, 2, %0, c0, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_pfr0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_pfr1() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_dfr0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_afr0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 3\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_mmfr0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 4\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_mmfr1() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 5\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_mmfr2() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 6\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_mmfr3() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c1, 7\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar1() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar2() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar3() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 3\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar4() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 4\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_isar5() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c0, c2, 5\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define read_sctlr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c1, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_sctlr(val) asm volatile(\
- " mcr p15, 0, %0, c1, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_actlr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c1, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_actlr(val) asm volatile(\
- " mcr p15, 0, %0, c1, c0, 1\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#ifndef CONFIG_ARMV5
-
-#define read_cpacr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c1, c0, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_cpacr(val) asm volatile(\
- " mcr p15, 0, %0, c1, c0, 2\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#else
-
-#define read_cpacr() 0
-
-#define write_cpacr(val)
-
-#endif
-
-#define read_dacr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c3, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_dacr(val) asm volatile(\
- " mcr p15, 0, %0, c3, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_ttbr0() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c2, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_ttbr0(val) asm volatile(\
- " mcr p15, 0, %0, c2, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_ttbr1() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c2, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_ttbr1(val) asm volatile(\
- " mcr p15, 0, %0, c2, c0, 1\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#ifndef CONFIG_ARMV5
-
-#define read_vbar() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c12, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_vbar(val) asm volatile(\
- " mcr p15, 0, %0, c12, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#else
-
-#define read_vbar() 0
-#define write_vbar(val)
-
-#endif /* CONFIG_ARMV7A */
-
-#define read_ttbcr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c2, c0, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_ttbcr(val) asm volatile(\
- " mcr p15, 0, %0, c2, c0, 2\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#if defined(CONFIG_ARMV5)
-/*
- * On ARM V5, we don't know if a data abort was triggered by a read or
- * write operation. We need to read the instruction that triggered the
- * abort and determine its type.
- */
-extern unsigned int **_abort_inst;
-
-static inline u32 read_dfsr(void)
-{
- u32 rval, inst;
-
- asm volatile(" mrc p15, 0, %0, c5, c0, 0" : "=r" (rval) : : "memory", "cc");
-
- inst = **_abort_inst;
-
- /*
- * all STM/STR/LDM/LDR instructions have bit 20 to indicate
- * if it is a read or write operation. We test this bit
- * to set or clear bit 11 on the DFSR result.
- * SWP instruction is reading and writing to memory. So we
- * assume write. SWP has 0 on bit 20 (like STM or STR).
- */
- if (inst & (1 << 20)) {
- /* LDM or LDR type instruction */
- rval &= ~(1 << 11);
- } else {
- /* STM or STR type instruction */
- /* SWP instruction is writing to memory */
- rval |= (1 << 11);
- }
-
- return rval;
-}
-#else // CONFIG_ARMV5
-#define read_dfsr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c5, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-#endif // CONFIG_ARMV5
-
-#define write_dfsr(val) asm volatile(\
- " mcr p15, 0, %0, c5, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_ifsr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c5, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_ifsr(val) asm volatile(\
- " mcr p15, 0, %0, c5, c0, 1\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_dfar() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c6, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_dfar(val) asm volatile(\
- " mcr p15, 0, %0, c6, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#if defined(CONFIG_ARMV5)
-
-extern unsigned int *_ifar;
-
-/*
- * On ARM V5, there is no IFAR register. Therefore we need to emulate this
- * function
- */
-#define read_ifar() (*_ifar)
-/* There is no need to write IFAR */
-#else
-#define read_ifar() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c6, c0, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_ifar(val) asm volatile(\
- " mcr p15, 0, %0, c6, c0, 2\n\t" \
- :: "r" ((val)) : "memory", "cc")
-#endif
-
-#define invalid_i_tlb() ({ u32 rval=0; asm volatile(\
- " mcr p15, 0, %0, c8, c5, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define invalid_i_tlb_mva(va) asm volatile(\
- " mcr p15, 0, %0, c8, c5, 1\n\t" \
- :: "r" ((va)) : "memory", "cc")
-
-#define invalid_d_tlb() ({ u32 rval=0; asm volatile(\
- " mcr p15, 0, %0, c8, c6, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define invalid_d_tlb_mva(va) asm volatile(\
- " mcr p15, 0, %0, c8, c6, 1\n\t" \
- :: "r" ((va)) : "memory", "cc")
-
-#define invalid_tlb() ({ u32 rval=0; asm volatile(\
- " mcr p15, 0, %0, c8, c7, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define invalid_tlb_mva(va) asm volatile(\
- " mcr p15, 0, %0, c8, c7, 1\n\t" \
- :: "r" ((va)) : "memory", "cc")
-
-#if !defined(CONFIG_ARMV5)
-
-#define invalid_tlb_asid(asid) asm volatile(\
- " mcr p15, 0, %0, c8, c7, 2\n\t" \
- :: "r" ((asid)) : "memory", "cc")
-
-#endif
-
-#define read_contextidr() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c13, c0, 1\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_contextidr(val) asm volatile(\
- " mcr p15, 0, %0, c13, c0, 1\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#if defined(CONFIG_ARMV5)
-
-#define read_tpidrurw() 0x0
-
-#define write_tpidrurw(val)
-
-#define read_tpidruro() 0x0
-
-#define write_tpidruro(val)
-
-#define read_tpidrprw() 0x0
-
-#define write_tpidrprw(val)
-
-#else
-
-#define read_tpidrurw() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c13, c0, 2\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_tpidrurw(val) asm volatile(\
- " mcr p15, 0, %0, c13, c0, 2\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_tpidruro() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c13, c0, 3\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_tpidruro(val) asm volatile(\
- " mcr p15, 0, %0, c13, c0, 3\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_tpidrprw() ({ u32 rval; asm volatile(\
- " mrc p15, 0, %0, c13, c0, 4\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_tpidrprw(val) asm volatile(\
- " mcr p15, 0, %0, c13, c0, 4\n\t" \
- :: "r" ((val)) : "memory", "cc")
-#endif
-
-/* VFP Control Register Read/Write */
-#define read_fpexc() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c8, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_fpexc(val) asm volatile(\
- " mcr p10, 7, %0, c8, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_fpscr() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c1, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_fpscr(val) asm volatile(\
- " mcr p10, 7, %0, c1, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_fpsid() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c0, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_fpsid(val) asm volatile(\
- " mcr p10, 7, %0, c0, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_fpinst() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c9, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_fpinst(val) asm volatile(\
- " mcr p10, 7, %0, c9, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_fpinst2() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c10, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_fpinst2(val) asm volatile(\
- " mcr p10, 7, %0, c10, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_mvfr0() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c7, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_mvfr0(val) asm volatile(\
- " mcr p10, 7, %0, c7, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-#define read_mvfr1() ({ u32 rval; asm volatile(\
- " mrc p10, 7, %0, c6, c0, 0\n\t" \
- : "=r" (rval) : : "memory", "cc"); rval;})
-
-#define write_mvfr1(val) asm volatile(\
- " mcr p10, 7, %0, c6, c0, 0\n\t" \
- :: "r" ((val)) : "memory", "cc")
-
-/* CPU feature checking macros */
-
-#ifndef CONFIG_ARMV5
-
-#define cpu_supports_thumbee() (((read_pfr0() & ID_PFR0_STATE3_MASK) \
- >> ID_PFR0_STATE3_SHIFT) == 0x1)
-
-#define cpu_supports_securex() (read_pfr1() & ID_PFR1_SECUREX_MASK)
-
-#else
-
-#define cpu_supports_thumbee() 0
-
-#define cpu_supports_securex() 0
-
-#endif
-
-#ifdef CONFIG_ARMV5
-#define cpu_supports_fpu() 0
-#else
-#define cpu_supports_fpu() (!(read_fpsid() & FPSID_SW_MASK))
-#endif
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/cpu_mmu.h b/arch/arm/cpu/arm32/include/cpu_mmu.h
deleted file mode 100644
index 00816d6f..00000000
--- a/arch/arm/cpu/arm32/include/cpu_mmu.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_mmu.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief memory management unit interface of a ARM processor
- */
-#ifndef _CPU_MMU_H__
-#define _CPU_MMU_H__
-
-#include <vmm_types.h>
-#include <libs/list.h>
-
-/* Generic CPU page having superset of page
- * attributes required by all ARM family
- * processors such as ARMv5, ARMv6, and ARMv7
- */
-struct cpu_page {
- virtual_addr_t va;
- physical_addr_t pa;
- virtual_size_t sz;
- u32 ns:1;
- u32 ng:1;
- u32 s:1;
- u32 tex:3;
- u32 ap:3;
- u32 imp:1;
- u32 dom:4;
- u32 xn:1;
- u32 c:1;
- u32 b:1;
- u32 pad:15;
-};
-
-/* Generic L2-table representation */
-struct cpu_l2tbl {
- struct dlist head;
- u32 num;
- struct cpu_l1tbl *l1;
- u32 imp;
- u32 domain;
- physical_addr_t tbl_pa;
- virtual_addr_t tbl_va;
- virtual_addr_t map_va;
- u32 tte_cnt;
-};
-
-/* Generic L1-table representation */
-struct cpu_l1tbl {
- struct dlist head;
- u32 num;
- u32 contextid;
- physical_addr_t tbl_pa;
- virtual_addr_t tbl_va;
- u32 tte_cnt;
- u32 l2tbl_cnt;
- struct dlist l2tbl_list;
-};
-
-/** Estimate good page size */
-u32 cpu_mmu_best_page_size(virtual_addr_t va, physical_addr_t pa, u32 availsz);
-
-/** Get page from a given virtual address */
-int cpu_mmu_get_page(struct cpu_l1tbl *l1,
- virtual_addr_t va,
- struct cpu_page *pg);
-
-/** Get L2 table from a given virtual address */
-int cpu_mmu_get_l2tbl(struct cpu_l1tbl *l1,
- virtual_addr_t va, struct cpu_l2tbl **l2);
-
-/** Unmap a page from given L1 table */
-int cpu_mmu_unmap_page(struct cpu_l1tbl *l1, struct cpu_page *pg);
-
-/** Unmap a page from given L2 table */
-int cpu_mmu_unmap_l2tbl_page(struct cpu_l2tbl *l2,
- virtual_addr_t pgva, virtual_size_t pgsz,
- bool invalidate_tlb);
-
-/** Map a page under a given L1 table */
-int cpu_mmu_map_page(struct cpu_l1tbl *l1, struct cpu_page *pg);
-
-/** Get reserved page from a given virtual address */
-int cpu_mmu_get_reserved_page(virtual_addr_t va, struct cpu_page *pg);
-
-/** Unmap a reserved page */
-int cpu_mmu_unmap_reserved_page(struct cpu_page *pg);
-
-/** Map a reserved page */
-int cpu_mmu_map_reserved_page(struct cpu_page *pg);
-
-/** Allocate a L1 table */
-struct cpu_l1tbl *cpu_mmu_l1tbl_alloc(void);
-
-/** Free a L1 table */
-int cpu_mmu_l1tbl_free(struct cpu_l1tbl *l1);
-
-/** Current L1 table */
-struct cpu_l1tbl *cpu_mmu_l1tbl_default(void);
-
-/** Current L1 table */
-struct cpu_l1tbl *cpu_mmu_l1tbl_current(void);
-
-/** Change domain access control register */
-int cpu_mmu_change_dacr(u32 new_dacr);
-
-/** Change translation table base register */
-int cpu_mmu_change_ttbr(struct cpu_l1tbl *l1);
-
-/** Sync translation table changes */
-int cpu_mmu_sync_ttbr(struct cpu_l1tbl *l1);
-
-/** Sync translation table changes */
-int cpu_mmu_sync_ttbr_va(struct cpu_l1tbl *l1, virtual_addr_t va);
-
-#endif /** _CPU_MMU_H */
diff --git a/arch/arm/cpu/arm32/include/cpu_proc.h b/arch/arm/cpu/arm32/include/cpu_proc.h
deleted file mode 100644
index 06baa3c4..00000000
--- a/arch/arm/cpu/arm32/include/cpu_proc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_proc.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief Interface of processor specific quirky functions
- */
-#ifndef __CPU_PROC_H__
-#define __CPU_PROC_H__
-
-#include <vmm_types.h>
-
-/** Idle the processor (eg, wait for interrupt). */
-void proc_do_idle(void);
-
-/** MMU context switch
- * @param ttbr physical address of translation table
- * @param contexidr new value to be set for CONTEX ID register
- */
-void proc_mmu_switch(u32 ttbr, u32 contexidr);
-
-/** Boot-time processor setup function
- * @return value to be set in system control register
- */
-u32 proc_setup(void);
-
-#endif /* __CPU_PROC_H__ */
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_coproc.h b/arch/arm/cpu/arm32/include/cpu_vcpu_coproc.h
deleted file mode 100644
index 37abc708..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_coproc.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_coproc.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief header file for coprocessor access
- */
-#ifndef _CPU_VCPU_COPROC_H__
-#define _CPU_VCPU_COPROC_H__
-
-#include <vmm_types.h>
-#include <vmm_manager.h>
-
-typedef bool (*cpu_coproc_ldcstc_accept)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 D, u32 CRd,
- u32 uopt, u32 imm8);
-
-typedef bool (*cpu_coproc_ldcstc_done)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8);
-
-typedef u32 (*cpu_coproc_ldcstc_read)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8);
-
-typedef void (*cpu_coproc_ldcstc_write)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 index, u32 D, u32 CRd,
- u32 uopt, u32 imm8, u32 data);
-
-typedef bool (*cpu_coproc_read2)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 CRm,
- u32 *data, u32 *data2);
-
-typedef bool (*cpu_coproc_write2)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 CRm,
- u32 data, u32 data2);
-
-typedef bool (*cpu_coproc_data_process)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2,
- u32 CRd, u32 CRn, u32 CRm);
-
-typedef bool (*cpu_coproc_read)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data);
-
-typedef bool (*cpu_coproc_write)(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data);
-
-struct cpu_vcpu_coproc {
- u32 cpnum;
- cpu_coproc_ldcstc_accept ldcstc_accept;
- cpu_coproc_ldcstc_done ldcstc_done;
- cpu_coproc_ldcstc_read ldcstc_read;
- cpu_coproc_ldcstc_write ldcstc_write;
- cpu_coproc_read2 read2;
- cpu_coproc_write2 write2;
- cpu_coproc_data_process data_process;
- cpu_coproc_read read;
- cpu_coproc_write write;
-};
-
-/** Retrive a coprocessor with given number */
-struct cpu_vcpu_coproc *cpu_vcpu_coproc_get(u32 cpnum);
-
-#endif /* _CPU_VCPU_COPROC_H */
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_cp14.h b/arch/arm/cpu/arm32/include/cpu_vcpu_cp14.h
deleted file mode 100644
index 9d98e944..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_cp14.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * Copyright (c) 2011-2013 Sting Cheng.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_cp14.h
- * @author Sting Cheng (sting...@gmail.com)
- * @author Anup Patel (an...@brainfault.org)
- * @brief Header file for VCPU cp14 (Debug, Trace, and ThumbEE) emulation
- */
-#ifndef _CPU_VCPU_CP14_H__
-#define _CPU_VCPU_CP14_H__
-
-#include <vmm_types.h>
-#include <vmm_chardev.h>
-#include <vmm_manager.h>
-
-/** Read one registers from CP14 */
-bool cpu_vcpu_cp14_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data);
-
-/** Write one registers to CP14 */
-bool cpu_vcpu_cp14_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data);
-
-/** Save CP14 registers for given VCPU */
-void cpu_vcpu_cp14_regs_save(struct vmm_vcpu *vcpu);
-
-/** Restore CP14 registers for given VCPU */
-void cpu_vcpu_cp14_regs_restore(struct vmm_vcpu *vcpu);
-
-/** Print CP14 registers for given VCPU */
-void cpu_vcpu_cp14_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu);
-
-/** Initialize CP14 context for given VCPU */
-int cpu_vcpu_cp14_init(struct vmm_vcpu *vcpu);
-
-/** DeInitialize CP14 context for given VCPU */
-int cpu_vcpu_cp14_deinit(struct vmm_vcpu *vcpu);
-
-#endif /* _CPU_VCPU_CP14_H__ */
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_cp15.h b/arch/arm/cpu/arm32/include/cpu_vcpu_cp15.h
deleted file mode 100644
index 3787c8ed..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_cp15.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_cp15.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief Header File for VCPU cp15 emulation
- */
-#ifndef _CPU_VCPU_CP15_H__
-#define _CPU_VCPU_CP15_H__
-
-#include <vmm_types.h>
-#include <vmm_chardev.h>
-#include <vmm_manager.h>
-
-/** Flush entire VTLB for a VCPU */
-int cpu_vcpu_cp15_vtlb_flush(struct arm_priv_cp15 *cp15);
-
-/** Flush given virtual address from VTLB for a VCPU */
-int cpu_vcpu_cp15_vtlb_flush_va(struct arm_priv_cp15 *cp15,
- virtual_addr_t va);
-
-/** Flush non-global pages from VTLB for a VCPU */
-int cpu_vcpu_cp15_vtlb_flush_ng(struct arm_priv_cp15 *cp15);
-
-/** Flush pages whos domain permissions have changed from VTLB for a VCPU */
-int cpu_vcpu_cp15_vtlb_flush_domain(struct arm_priv_cp15 *cp15,
- u32 dacr_xor_diff);
-
-enum cpu_vcpu_cp15_access_types {
- CP15_ACCESS_READ = 0,
- CP15_ACCESS_WRITE = 1,
- CP15_ACCESS_EXECUTE = 2
-};
-
-/** Fill up the cpu_page object for given virtual address */
-u32 cpu_vcpu_cp15_find_page(struct vmm_vcpu *vcpu,
- virtual_addr_t va,
- int access_type,
- bool is_user, struct cpu_page *pg);
-
-struct cpu_vcpu_cp15_fault_info {
- arch_regs_t *regs;
- u32 far;
- u32 fs;
- u32 dom;
- u32 wnr;
- u32 xn;
-};
-
-/** Assert the appropriate abort/fault to vcpu */
-int cpu_vcpu_cp15_assert_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info);
-
-/** Handle translation fault for a VCPU */
-int cpu_vcpu_cp15_trans_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info,
- bool force_user);
-
-/** Handle access fault for a VCPU */
-int cpu_vcpu_cp15_access_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info);
-
-/** Handle domain fault for a VCPU */
-int cpu_vcpu_cp15_domain_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info);
-
-/** Handle permission fault for a VCPU */
-int cpu_vcpu_cp15_perm_fault(struct vmm_vcpu *vcpu,
- struct cpu_vcpu_cp15_fault_info *info);
-
-/** Read one registers from CP15 */
-bool cpu_vcpu_cp15_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data);
-
-/** Write one registers to CP15 */
-bool cpu_vcpu_cp15_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data);
-
-/* Read from memory using VCPU CP15 */
-virtual_addr_t cpu_vcpu_cp15_vector_addr(struct vmm_vcpu *vcpu,
- u32 irq_no);
-
-/* Syncronize VCPU CP15 with change in VCPU mode */
-void cpu_vcpu_cp15_sync_cpsr(struct vmm_vcpu *vcpu);
-
-/** Save CP15 registers for given VCPU */
-void cpu_vcpu_cp15_regs_save(struct vmm_vcpu *vcpu);
-
-/** Restore CP15 registers for given VCPU */
-void cpu_vcpu_cp15_regs_restore(struct vmm_vcpu *vcpu);
-
-/** Print CP15 registers for given VCPU */
-void cpu_vcpu_cp15_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu);
-
-/** Initialize CP15 subsystem for a VCPU */
-int cpu_vcpu_cp15_init(struct vmm_vcpu *vcpu, u32 cpuid);
-
-/** DeInitialize CP15 subsystem for a VCPU */
-int cpu_vcpu_cp15_deinit(struct vmm_vcpu *vcpu);
-
-#endif /* _CPU_VCPU_CP15_H */
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_helper.h b/arch/arm/cpu/arm32/include/cpu_vcpu_helper.h
deleted file mode 100644
index 4f60f56b..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_helper.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_helper.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief header of VCPU helper functions
- */
-#ifndef _CPU_VCPU_HELPER_H__
-#define _CPU_VCPU_HELPER_H__
-
-#include <vmm_types.h>
-#include <vmm_manager.h>
-
-/* Function to halt VCPU */
-void cpu_vcpu_halt(struct vmm_vcpu * vcpu, arch_regs_t * regs);
-
-/* Function to retrieve CPSR of a VCPU */
-u32 cpu_vcpu_cpsr_retrieve(struct vmm_vcpu * vcpu,
- arch_regs_t * regs);
-
-/* Function to update CPSR of a VCPU */
-void cpu_vcpu_cpsr_update(struct vmm_vcpu * vcpu,
- arch_regs_t * regs,
- u32 new_cpsr,
- u32 new_cpsr_mask);
-
-/* Function to retrieve SPSR of a VCPU */
-u32 cpu_vcpu_spsr_retrieve(struct vmm_vcpu * vcpu);
-
-/* Function to update SPSR of a VCPU */
-int cpu_vcpu_spsr_update(struct vmm_vcpu * vcpu,
- u32 new_spsr,
- u32 new_spsr_update);
-
-/* Function to read a VCPU register of current mode */
-u32 cpu_vcpu_reg_read(struct vmm_vcpu * vcpu,
- arch_regs_t * regs,
- u32 reg_num);
-
-/* Function to write a VCPU register of current mode */
-void cpu_vcpu_reg_write(struct vmm_vcpu * vcpu,
- arch_regs_t * regs,
- u32 reg_num,
- u32 reg_val);
-
-/* Function to read a VCPU register of given mode */
-u32 cpu_vcpu_regmode_read(struct vmm_vcpu * vcpu,
- arch_regs_t * regs,
- u32 mode,
- u32 reg_num);
-
-/* Function to write a VCPU register of given mode */
-void cpu_vcpu_regmode_write(struct vmm_vcpu * vcpu,
- arch_regs_t * regs,
- u32 mode,
- u32 reg_num,
- u32 reg_val);
-
-/* Function to dump user registers */
-void cpu_vcpu_dump_user_reg(struct vmm_vcpu * vcpu, arch_regs_t * regs);
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_arm.h b/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_arm.h
deleted file mode 100644
index c9b65edd..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_arm.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_hypercall_arm.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief header file to emulate ARM hypercall instructions
- */
-#ifndef _CPU_VCPU_HYPERCALL_ARM_H__
-#define _CPU_VCPU_HYPERCALL_ARM_H__
-
-#include <vmm_types.h>
-
-#define ARM_HYPERCALL_CPS_ID 0
-#define ARM_HYPERCALL_CPS_SUBID 0
-#define ARM_HYPERCALL_CPS_IMOD_END 16
-#define ARM_HYPERCALL_CPS_IMOD_START 15
-#define ARM_HYPERCALL_CPS_M_END 14
-#define ARM_HYPERCALL_CPS_M_START 14
-#define ARM_HYPERCALL_CPS_A_END 13
-#define ARM_HYPERCALL_CPS_A_START 13
-#define ARM_HYPERCALL_CPS_I_END 12
-#define ARM_HYPERCALL_CPS_I_START 12
-#define ARM_HYPERCALL_CPS_F_END 11
-#define ARM_HYPERCALL_CPS_F_START 11
-#define ARM_HYPERCALL_CPS_MODE_END 10
-#define ARM_HYPERCALL_CPS_MODE_START 6
-
-#define ARM_HYPERCALL_MRS_ID 0
-#define ARM_HYPERCALL_MRS_SUBID 1
-#define ARM_HYPERCALL_MRS_RD_END 16
-#define ARM_HYPERCALL_MRS_RD_START 13
-#define ARM_HYPERCALL_MRS_R_END 12
-#define ARM_HYPERCALL_MRS_R_START 12
-
-#define ARM_HYPERCALL_MSR_I_ID 0
-#define ARM_HYPERCALL_MSR_I_SUBID 2
-#define ARM_HYPERCALL_MSR_I_MASK_END 16
-#define ARM_HYPERCALL_MSR_I_MASK_START 13
-#define ARM_HYPERCALL_MSR_I_IMM12_END 12
-#define ARM_HYPERCALL_MSR_I_IMM12_START 1
-#define ARM_HYPERCALL_MSR_I_R_END 0
-#define ARM_HYPERCALL_MSR_I_R_START 0
-
-#define ARM_HYPERCALL_MSR_R_ID 0
-#define ARM_HYPERCALL_MSR_R_SUBID 3
-#define ARM_HYPERCALL_MSR_R_MASK_END 16
-#define ARM_HYPERCALL_MSR_R_MASK_START 13
-#define ARM_HYPERCALL_MSR_R_RN_END 12
-#define ARM_HYPERCALL_MSR_R_RN_START 9
-#define ARM_HYPERCALL_MSR_R_R_END 8
-#define ARM_HYPERCALL_MSR_R_R_START 8
-
-#define ARM_HYPERCALL_RFE_ID 0
-#define ARM_HYPERCALL_RFE_SUBID 4
-#define ARM_HYPERCALL_RFE_P_END 16
-#define ARM_HYPERCALL_RFE_P_START 16
-#define ARM_HYPERCALL_RFE_U_END 15
-#define ARM_HYPERCALL_RFE_U_START 15
-#define ARM_HYPERCALL_RFE_W_END 14
-#define ARM_HYPERCALL_RFE_W_START 14
-#define ARM_HYPERCALL_RFE_RN_END 13
-#define ARM_HYPERCALL_RFE_RN_START 10
-
-#define ARM_HYPERCALL_SRS_ID 0
-#define ARM_HYPERCALL_SRS_SUBID 5
-#define ARM_HYPERCALL_SRS_P_END 16
-#define ARM_HYPERCALL_SRS_P_START 16
-#define ARM_HYPERCALL_SRS_U_END 15
-#define ARM_HYPERCALL_SRS_U_START 15
-#define ARM_HYPERCALL_SRS_W_END 14
-#define ARM_HYPERCALL_SRS_W_START 14
-#define ARM_HYPERCALL_SRS_MODE_END 13
-#define ARM_HYPERCALL_SRS_MODE_START 9
-
-#define ARM_HYPERCALL_WFI_ID 0
-#define ARM_HYPERCALL_WFI_SUBID 6
-
-#define ARM_HYPERCALL_SMC_ID 0
-#define ARM_HYPERCALL_SMC_SUBID 7
-#define ARM_HYPERCALL_SMC_IMM4_END 16
-#define ARM_HYPERCALL_SMC_IMM4_START 13
-
-#define ARM_HYPERCALL_LDM_UE_ID0 1
-#define ARM_HYPERCALL_LDM_UE_ID1 2
-#define ARM_HYPERCALL_LDM_UE_ID2 3
-#define ARM_HYPERCALL_LDM_UE_ID3 4
-#define ARM_HYPERCALL_LDM_UE_ID4 5
-#define ARM_HYPERCALL_LDM_UE_ID5 6
-#define ARM_HYPERCALL_LDM_UE_ID6 7
-#define ARM_HYPERCALL_LDM_UE_ID7 8
-#define ARM_HYPERCALL_LDM_UE_RN_END 19
-#define ARM_HYPERCALL_LDM_UE_RN_START 16
-#define ARM_HYPERCALL_LDM_UE_REGLIST_END 15
-#define ARM_HYPERCALL_LDM_UE_REGLIST_START 0
-
-#define ARM_HYPERCALL_STM_U_ID0 9
-#define ARM_HYPERCALL_STM_U_ID1 10
-#define ARM_HYPERCALL_STM_U_ID2 11
-#define ARM_HYPERCALL_STM_U_ID3 12
-#define ARM_HYPERCALL_STM_U_RN_END 19
-#define ARM_HYPERCALL_STM_U_RN_START 16
-#define ARM_HYPERCALL_STM_U_REGLIST_END 15
-#define ARM_HYPERCALL_STM_U_REGLIST_START 0
-
-#define ARM_HYPERCALL_SUBS_REL_ID0 13
-#define ARM_HYPERCALL_SUBS_REL_ID1 14
-#define ARM_HYPERCALL_SUBS_REL_OPCODE_END 19
-#define ARM_HYPERCALL_SUBS_REL_OPCODE_START 16
-#define ARM_HYPERCALL_SUBS_REL_RN_END 15
-#define ARM_HYPERCALL_SUBS_REL_RN_START 12
-#define ARM_HYPERCALL_SUBS_REL_IMM12_END 11
-#define ARM_HYPERCALL_SUBS_REL_IMM12_START 0
-#define ARM_HYPERCALL_SUBS_REL_IMM5_END 11
-#define ARM_HYPERCALL_SUBS_REL_IMM5_START 7
-#define ARM_HYPERCALL_SUBS_REL_TYPE_END 6
-#define ARM_HYPERCALL_SUBS_REL_TYPE_START 5
-#define ARM_HYPERCALL_SUBS_REL_RM_END 3
-#define ARM_HYPERCALL_SUBS_REL_RM_START 0
-
-#define ARM_HYPERCALL_SVC_ID 15
-
-#define ARM_INST_HYPERCALL_ID_MASK 0x00F00000
-#define ARM_INST_HYPERCALL_ID_SHIFT 20
-#define ARM_INST_HYPERCALL_SUBID_MASK 0x000E0000
-#define ARM_INST_HYPERCALL_SUBID_SHIFT 17
-#define ARM_INST_HYPERCALL_WFX_MASK 0x00018000
-#define ARM_INST_HYPERCALL_WFX_SHIFT 15
-
-/** Emulate ARM hypercall instruction */
-int cpu_vcpu_hypercall_arm(struct vmm_vcpu *vcpu, arch_regs_t *regs, u32 inst);
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_thumb.h b/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_thumb.h
deleted file mode 100644
index 80891e8c..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_hypercall_thumb.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_hypercall_thumb.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief header file to emulate Thumb hypercall instructions
- */
-#ifndef _CPU_VCPU_HYPERCALL_THUMB_H__
-#define _CPU_VCPU_HYPERCALL_THUMB_H__
-
-#include <vmm_types.h>
-
-/** FIXME: Emulate Thumb hypercall instruction */
-int cpu_vcpu_hypercall_thumb(struct vmm_vcpu *vcpu, arch_regs_t *regs, u32 inst);
-
-#endif
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_mem.h b/arch/arm/cpu/arm32/include/cpu_vcpu_mem.h
deleted file mode 100644
index 8f6dacbc..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_mem.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_mem.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief Header File for VCPU memory read/write emulation
- */
-#ifndef _CPU_VCPU_MEM_H__
-#define _CPU_VCPU_MEM_H__
-
-#include <vmm_types.h>
-#include <vmm_manager.h>
-
-/** Read from memory for VCPU */
-int cpu_vcpu_mem_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *dst, u32 dst_len,
- bool force_unpriv);
-
-/** Write to memory for VCPU */
-int cpu_vcpu_mem_write(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *src, u32 src_len,
- bool force_unpriv);
-
-/** Read-Exclusive from memory for VCPU */
-int cpu_vcpu_mem_readex(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *dst, u32 dst_len,
- bool force_unpriv);
-
-/** Write-Exclusive to memory for VCPU */
-int cpu_vcpu_mem_writeex(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- virtual_addr_t addr,
- void *src, u32 src_len,
- bool force_unpriv);
-
-#endif /* _CPU_VCPU_MEM_H */
diff --git a/arch/arm/cpu/arm32/include/cpu_vcpu_vfp.h b/arch/arm/cpu/arm32/include/cpu_vcpu_vfp.h
deleted file mode 100644
index 51f2282b..00000000
--- a/arch/arm/cpu/arm32/include/cpu_vcpu_vfp.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file cpu_vcpu_vfp.h
- * @author Anup Patel (an...@brainfault.org)
- * @brief Header file for VCPU cp10 and cp11 emulation
- */
-#ifndef _CPU_VCPU_VFP_H__
-#define _CPU_VCPU_VFP_H__
-
-#include <vmm_types.h>
-#include <vmm_chardev.h>
-#include <vmm_manager.h>
-
-/** Read one registers from CP10 */
-bool cpu_vcpu_cp10_read(struct vmm_vcpu *vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 *data);
-
-/** Write one registers to CP10 */
-bool cpu_vcpu_cp10_write(struct vmm_vcpu * vcpu,
- arch_regs_t *regs,
- u32 opc1, u32 opc2, u32 CRn, u32 CRm,
- u32 data);
-
-/** Save VFP registers for given VCPU */
-void cpu_vcpu_vfp_regs_save(struct vmm_vcpu *vcpu);
-
-/** Restore VFP registers for given VCPU */
-void cpu_vcpu_vfp_regs_restore(struct vmm_vcpu *vcpu);
-
-/** Print VFP registers for given VCPU */
-void cpu_vcpu_vfp_regs_dump(struct vmm_chardev *cdev,
- struct vmm_vcpu *vcpu);
-
-/** Initialize VFP subsystem for a VCPU */
-int cpu_vcpu_vfp_init(struct vmm_vcpu *vcpu);
-
-/** DeInitialize VFP subsystem for a VCPU */
-int cpu_vcpu_vfp_deinit(struct vmm_vcpu *vcpu);
-
-#endif /* _CPU_VCPU_VFP_H */
diff --git a/arch/arm/cpu/arm32/linker.ld b/arch/arm/cpu/arm32/linker.ld
deleted file mode 100755
index df97d6a6..00000000
--- a/arch/arm/cpu/arm32/linker.ld
+++ /dev/null
@@ -1,208 +0,0 @@
-/**
- * Copyright (c) 2011 Pranav Sawargaonkar.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file linker.ld
- * @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
- * @brief CPU specific linker script
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH("arm")
-ENTRY(_start)
-
-SECTIONS
-{
- . = CPU_TEXT_START;
-
- . = ALIGN(0x1000); /* Need this to create proper pages */
-
- PROVIDE(_code_start = .);
-
- /* Beginning of the code section */
-
- .text :
- {
- PROVIDE(_text_start = .);
- *(.entry)
- *(.text)
- . = ALIGN(8);
- PROVIDE(_text_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .init :
- {
- PROVIDE(_init_start = .);
-
- PROVIDE(_init_text_start = .);
-
- *(.init.text)
- . = ALIGN(8);
-
- PROVIDE(__setup_start = .);
- *(.setup.init);
- PROVIDE(__setup_end = .);
-
- . = ALIGN(0x1000);
-
- PROVIDE(_init_text_end = .);
-
- PROVIDE(_initdata_start = .);
- *(.init.data)
- . = ALIGN(8);
- PROVIDE(_initdata_end = .);
-
- PROVIDE(_initconst_start = .);
- *(.init.rodata)
- . = ALIGN(8);
- PROVIDE(_initconst_end = .);
-
- PROVIDE(_init_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .cpuinit :
- {
- PROVIDE(_cpuinit_start = .);
- *(.cpuinit.*)
- . = ALIGN(8);
- PROVIDE(_cpuinit_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .spinlock :
- {
- PROVIDE(_spinlock_start = .);
- *(.spinlock.*)
- . = ALIGN(8);
- PROVIDE(_spinlock_end = .);
- }
-
- /* End of the code sections */
-
- /* Beginning of the read-only data sections */
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .rodata :
- {
- PROVIDE(_rodata_start = .);
- *(.symtbl)
- *(.rodata .rodata.*)
- . = ALIGN(8);
- PROVIDE(_rodata_end = .);
- }
-
- /* End of the read-only data sections */
-
- /* Beginning of the read-write data sections */
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .percpu :
- {
- PROVIDE(_percpu_start = .);
- *(.percpu)
- . = ALIGN(8);
- PROVIDE(_percpu_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .data :
- {
- PROVIDE(_data_start = .);
- *(.data)
- *(.readmostly.data)
- *(*.data)
-
- PROVIDE(_modtbl_start = .);
- *(.modtbl)
- . = ALIGN(8);
- PROVIDE(_modtbl_end = .);
-
- PROVIDE(_nidtbl_start = .);
- *(.nidtbl)
- . = ALIGN(8);
- PROVIDE(_nidtbl_end = .);
-
- PROVIDE(_data_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .bss :
- {
- PROVIDE(_bss_start = .);
- *(.bss)
- *(COMMON)
- . = ALIGN(8);
- PROVIDE(_bss_end = .);
- }
-
- . = ALIGN(0x1000); /* Ensure next section is page aligned */
-
- .svc_stack :
- {
- PROVIDE(_svc_stack_start = .);
- . = . + (CONFIG_IRQ_STACK_SIZE * CONFIG_CPU_COUNT);
- . = ALIGN(8);
- PROVIDE(_svc_stack_end = .);
- }
-
- .abt_stack :
- {
- PROVIDE(_abt_stack_start = .);
- . = . + (0x100 * CONFIG_CPU_COUNT);
- . = ALIGN(8);
- PROVIDE(_abt_stack_end = .);
- }
-
- .und_stack :
- {
- PROVIDE(_und_stack_start = .);
- . = . + (0x100 * CONFIG_CPU_COUNT);
- . = ALIGN(8);
- PROVIDE(_und_stack_end = .);
- }
-
- .irq_stack :
- {
- PROVIDE(_irq_stack_start = .);
- . = . + (0x100 * CONFIG_CPU_COUNT);
- . = ALIGN(8);
- PROVIDE(_irq_stack_end = .);
- }
-
- .fiq_stack :
- {
- PROVIDE(_fiq_stack_start = .);
- . = . + (0x100 * CONFIG_CPU_COUNT);
- . = ALIGN(8);
- PROVIDE(_fiq_stack_end = .);
- }
-
- /* End of the read-write data sections */
-
- . = ALIGN(0x1000); /* Need this to create proper pages */
-
- PROVIDE(_code_end = .);
-}
diff --git a/arch/arm/cpu/arm32/objects.mk b/arch/arm/cpu/arm32/objects.mk
deleted file mode 100644
index 421579ec..00000000
--- a/arch/arm/cpu/arm32/objects.mk
+++ /dev/null
@@ -1,80 +0,0 @@
-#/**
-# Copyright (c) 2011 Pranav Sawargaonkar.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
-# @author Anup Patel (an...@brainfault.org)
-# @brief list of ARM32 cpu objects.
-# */
-
-# This selects which instruction set is used.
-# Note that GCC does not numerically define an architecture version
-# macro, but instead defines a whole series of macros which makes
-# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_ARMV7A) += -D__ARM_ARCH_VERSION__=7 -mno-thumb-interwork -march=armv7-a
-ifdef CONFIG_ARMV6K
-arch-$(CONFIG_ARMV6) += -D__ARM_ARCH_VERSION__=6 -mno-thumb-interwork -march=armv6k
-else
-arch-$(CONFIG_ARMV6) += -D__ARM_ARCH_VERSION__=6 -mno-thumb-interwork -march=armv6
-endif
-arch-$(CONFIG_ARMV5) += -D__ARM_ARCH_VERSION__=5 -mno-thumb-interwork -march=armv5te
-
-# Target processor specific tunning options
-tune-y =
-
-# Need -Uarm for gcc < 3.x
-cpu-cppflags+=-DCPU_TEXT_START=0xFF000000
-cpu-cflags += -msoft-float -marm -Uarm $(arch-y) $(tune-y)
-cpu-cflags += -fno-strict-aliasing -O2
-ifeq ($(CONFIG_ARM32_STACKTRACE), y)
-cpu-cflags += -fno-omit-frame-pointer -mapcs -mno-sched-prolog
-endif
-cpu-asflags += -marm $(arch-y) $(tune-y)
-cpu-ldflags += -msoft-float
-
-cpu-objs-y += cpu_entry.o
-cpu-objs-y += cpu_mmu_entry.o
-cpu-objs-y += cpu_mmu.o
-cpu-objs-y += cpu_atomic.o
-cpu-objs-y += cpu_atomic64.o
-
-cpu-objs-$(CONFIG_ARMV5)+= cpu_proc_v5.o
-cpu-objs-$(CONFIG_ARMV6)+= cpu_proc_v6.o
-cpu-objs-$(CONFIG_ARMV7A)+= cpu_proc_v7.o
-
-cpu-objs-$(CONFIG_ARMV5)+= cpu_cache_v5.o
-cpu-objs-$(CONFIG_ARMV6)+= cpu_cache_v6.o
-cpu-objs-$(CONFIG_ARMV7A)+= cpu_cache_v7.o
-
-cpu-objs-y+= cpu_init.o
-cpu-objs-y+= cpu_delay.o
-cpu-objs-y+= cpu_memcpy.o
-cpu-objs-y+= cpu_memset.o
-cpu-objs-$(CONFIG_MODULES)+= cpu_elf.o
-cpu-objs-$(CONFIG_ARM32_STACKTRACE)+= cpu_stacktrace.o
-cpu-objs-y+= cpu_interrupts.o
-cpu-objs-y+= cpu_vcpu_helper.o
-cpu-objs-y+= cpu_vcpu_coproc.o
-cpu-objs-y+= cpu_vcpu_vfp.o
-cpu-objs-y+= cpu_vcpu_cp14.o
-cpu-objs-y+= cpu_vcpu_cp15.o
-cpu-objs-y+= cpu_vcpu_mem.o
-cpu-objs-y+= cpu_vcpu_irq.o
-cpu-objs-y+= cpu_vcpu_hypercall_arm.o
-cpu-objs-y+= cpu_vcpu_hypercall_thumb.o
-
diff --git a/arch/arm/cpu/arm32/openconf.cfg b/arch/arm/cpu/arm32/openconf.cfg
deleted file mode 100644
index f3190411..00000000
--- a/arch/arm/cpu/arm32/openconf.cfg
+++ /dev/null
@@ -1,205 +0,0 @@
-#/**
-# Copyright (c) 2011 Pranav Sawargaonkar.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file openconf.cfg
-# @author Pranav Sawargaonkar (pranav.sa...@gmail.com)
-# @brief Config file for ARM
-#*/
-
-config CONFIG_CPU
- string
- default "arm32"
-
-config CONFIG_CPU_LE
- bool
- default y
-
-config CONFIG_CPU_BE
- bool
- default n
-
-config CONFIG_32BIT
- bool
- default y
-
-config CONFIG_64BIT
- bool
- default n
-
-config CONFIG_ARM32_STACKTRACE
- bool "Enable Stack Tracing"
- default y
- help
- This option forces ARM compiler to use frame pointer for
- all functions hence making stack tracing possible.
-
- Enabling this option forces compiler to add additional
- instructions to setup stack frame in function prolog of
- all functions.
-
- Disabling this option makes hypervisor slightly faster but
- disable stack trace information printed by hypervisor.
-
- By default, this options is always enabled. You can disable
- this option in-case you want slightly faster and slight
- smaller hypervisor
-
-config CONFIG_ARM32_HIGHVEC
- bool "Enable High Exception Vectors"
- default n
- help
- This sets 0xFFF00000 as exception vector base.
- By default it is 0x00000000
-
-config CONFIG_CPU_DCACHE_WRITETHROUGH
- bool "Force write through D-cache"
- depends on CONFIG_CPU_ARM926T
- default n
- help
- Say Y here to use the data cache in writethrough mode. Unless you
- specifically require this or are unsure, say N.
-
-config CONFIG_CPU_CACHE_ROUND_ROBIN
- bool "Round robin I and D cache replacement algorithm"
- depends on CONFIG_CPU_ARM926T
- help
- Say Y here to use the predictable round-robin cache replacement
- policy. Unless you specifically require this or are unsure, say N.
-
-config CONFIG_ARM_ERRATA_364296
- bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
- depends on CONFIG_ARMV6 && !CONFIG_SMP
- help
- This options enables the workaround for the 364296 ARM1136
- r0p2 erratum (possible cache data corruption with
- hit-under-miss enabled). It sets the undocumented bit 31 in
- the auxiliary control register and the FI bit in the control
- register, thus disabling hit-under-miss without putting the
- processor into full low interrupt latency mode. ARM11MPCore
- is not affected.
-
-config CONFIG_ARM_ERRATA_411920
- bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
- depends on CONFIG_ARMV6 || CONFIG_ARMV6K
- help
- Invalidation of the Instruction Cache operation can
- fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
- It does not affect the MPCore. This option enables the ARM Ltd.
- recommended workaround.
-
-config CONFIG_ARM_ERRATA_430973
- bool "ARM errata: Stale prediction on replaced interworking branch"
- depends on CONFIG_ARMV7A
- help
- This option enables the workaround for the 430973 Cortex-A8
- (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
- interworking branch is replaced with another code sequence at the
- same virtual address, whether due to self-modifying code or virtual
- to physical address re-mapping, Cortex-A8 does not recover from the
- stale interworking branch prediction. This results in Cortex-A8
- executing the new code sequence in the incorrect ARM or Thumb state.
- The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
- and also flushes the branch target cache at every context switch.
- Note that setting specific bits in the ACTLR register may not be
- available in non-secure mode.
-
-config CONFIG_ARM_ERRATA_458693
- bool "ARM errata: Processor deadlock when a false hazard is created"
- depends on CONFIG_ARMV7A
- help
- This option enables the workaround for the 458693 Cortex-A8 (r2p0)
- erratum. For very specific sequences of memory operations, it is
- possible for a hazard condition intended for a cache line to instead
- be incorrectly associated with a different cache line. This false
- hazard might then cause a processor deadlock. The workaround enables
- the L1 caching of the NEON accesses and disables the PLD instruction
- in the ACTLR register. Note that setting specific bits in the ACTLR
- register may not be available in non-secure mode.
-
-config CONFIG_ARM_ERRATA_460075
- bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
- depends on CONFIG_ARMV7A
- help
- This option enables the workaround for the 460075 Cortex-A8 (r2p0)
- erratum. Any asynchronous access to the L2 cache may encounter a
- situation in which recent store transactions to the L2 cache are lost
- and overwritten with stale memory contents from external memory. The
- workaround disables the write-allocate mode for the L2 cache via the
- ACTLR register. Note that setting specific bits in the ACTLR register
- may not be available in non-secure mode.
-
-config CONFIG_ARM_ERRATA_742230
- bool "ARM errata: DMB operation may be faulty"
- depends on CONFIG_ARMV7A && CONFIG_SMP
- help
- This option enables the workaround for the 742230 Cortex-A9
- (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
- between two write operations may not ensure the correct visibility
- ordering of the two writes. This workaround sets a specific bit in
- the diagnostic register of the Cortex-A9 which causes the DMB
- instruction to behave as a DSB, ensuring the correct behaviour of
- the two writes.
-
-config CONFIG_ARM_ERRATA_742231
- bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
- depends on CONFIG_ARMV7A && CONFIG_SMP
- help
- This option enables the workaround for the 742231 Cortex-A9
- (r2p0..r2p2) erratum. Under certain conditions, specific to the
- Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
- accessing some data located in the same cache line, may get corrupted
- data due to bad handling of the address hazard when the line gets
- replaced from one of the CPUs at the same time as another CPU is
- accessing it. This workaround sets specific bits in the diagnostic
- register of the Cortex-A9 which reduces the linefill issuing
- capabilities of the processor.
-
-config CONFIG_ARM_ERRATA_743622
- bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
- depends on CONFIG_ARMV7A && CONFIG_SMP
- help
- This option enables the workaround for the 743622 Cortex-A9
- (r2p*) erratum. Under very rare conditions, a faulty
- optimisation in the Cortex-A9 Store Buffer may lead to data
- corruption. This workaround sets a specific bit in the diagnostic
- register of the Cortex-A9 which disables the Store Buffer
- optimisation, preventing the defect from occurring. This has no
- visible impact on the overall performance or power consumption of the
- processor.
-
-config CONFIG_ARM_ERRATA_751472
- bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
- depends on CONFIG_ARMV7A
- help
- This option enables the workaround for the 751472 Cortex-A9 (prior
- to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
- completion of a following broadcasted operation if the second
- operation is received by a CPU before the ICIALLUIS has completed,
- potentially leading to corrupted entries in the cache or TLB.
-
-config CONFIG_ARM_ERRATA_754322
- bool "ARM errata: possible faulty MMU translations following an ASID switch"
- depends on CONFIG_ARMV7A
- help
- This option enables the workaround for the 754322 Cortex-A9 (r2p*,
- r3p*) erratum. A speculative memory access may cause a page table walk
- which starts prior to an ASID switch but completes afterwards. This
- can populate the micro-TLB with a stale entry which may be hit with
- the new ASID. This workaround places two dsb instructions in the mm
- switching code so that no page table walks can cross the ASID switch.
-
diff --git a/arch/arm/cpu/openconf.cfg b/arch/arm/cpu/openconf.cfg
index 9fd8a82d..6509c84c 100644
--- a/arch/arm/cpu/openconf.cfg
+++ b/arch/arm/cpu/openconf.cfg
@@ -23,45 +23,10 @@

choice
prompt "Target CPU"
- default CONFIG_CPU_CORTEX_A8
+ default CONFIG_CPU_GENERIC_V8
help
Select the target ARM Processor

- config CONFIG_CPU_ARM926T
- bool "arm926t"
- select CONFIG_ARMV5
- help
- Select this if you are using ARM926T.
-
- config CONFIG_CPU_ARM11
- bool "arm11"
- select CONFIG_ARMV6
- help
- Select this if you are using ARM1136J(F)-S, ARM1156T2(F)-S or ARM1176JZ(F)-S.
-
- config CONFIG_CPU_ARM11MP
- bool "arm11mp"
- select CONFIG_SMP
- select CONFIG_ARMV6
- select CONFIG_ARMV6K
- select CONFIG_ARM_LOCKS
- help
- Select this if you are using ARM11 MPcore.
-
- config CONFIG_CPU_CORTEX_A8
- bool "cortex-a8"
- select CONFIG_ARMV7A
- help
- Select this if you are using Cortex-A8
-
- config CONFIG_CPU_CORTEX_A9
- bool "cortex-a9"
- select CONFIG_SMP
- select CONFIG_ARMV7A
- select CONFIG_ARM_LOCKS
- help
- Select this if you are using Cortex-A9
-
config CONFIG_CPU_CORTEX_A7
bool "cortex-a7"
select CONFIG_SMP
@@ -84,28 +49,6 @@ choice
Select this if you are using Cortex-A15 (with virtualization
extension)

- config CONFIG_CPU_GENERIC_V5
- bool "generic-v5"
- select CONFIG_ARMV5
- select CONFIG_ARM_LOCKS if CONFIG_SMP
- help
- Select this if you are using Generic ARMv5 CPU
-
- config CONFIG_CPU_GENERIC_V6
- bool "generic-v6"
- select CONFIG_ARMV6
- select CONFIG_ARMV6K
- select CONFIG_ARM_LOCKS if CONFIG_SMP
- help
- Select this if you are using Generic ARMv6 or ARMv6k CPU
-
- config CONFIG_CPU_GENERIC_V7
- bool "generic-v7"
- select CONFIG_ARMV7A
- select CONFIG_ARM_LOCKS if CONFIG_SMP
- help
- Select this if you are using Generic ARMv7 CPU
-
config CONFIG_CPU_GENERIC_V7_VE
bool "generic-v7-ve"
select CONFIG_ARMV7A_VE
@@ -126,30 +69,6 @@ choice

endchoice

-config CONFIG_ARMV5
- bool
- select CONFIG_ARM
- select CONFIG_ARM32
- default n
-
-config CONFIG_ARMV6
- bool
- select CONFIG_ARM
- select CONFIG_ARM32
- default n
-
-config CONFIG_ARMV6K
- bool
- select CONFIG_ARM
- select CONFIG_ARM32
- default n
-
-config CONFIG_ARMV7A
- bool
- select CONFIG_ARM
- select CONFIG_ARM32
- default n
-
config CONFIG_ARMV7A_VE
bool
select CONFIG_ARM
@@ -166,11 +85,6 @@ config CONFIG_ARM
bool
default n

-config CONFIG_ARM32
- bool
- select CONFIG_CPATCH
- default n
-
config CONFIG_ARM32VE
bool
default n
@@ -246,12 +160,6 @@ config CONFIG_HOST_IRQ_COUNT

source "arch/arm/cpu/common/openconf.cfg"

-if CONFIG_ARM32
-
-source "arch/arm/cpu/arm32/openconf.cfg"
-
-endif
-
if CONFIG_ARM32VE

source "arch/arm/cpu/arm32ve/openconf.cfg"
diff --git a/arch/arm/dts/allwinner/objects.mk b/arch/arm/dts/allwinner/objects.mk
index 34c9f017..8c6b993b 100644
--- a/arch/arm/dts/allwinner/objects.mk
+++ b/arch/arm/dts/allwinner/objects.mk
@@ -23,5 +23,3 @@
# */

arch-dtbs-$(CONFIG_ARMV7A_VE)+=allwinner/sun7i-a20-cubieboard2.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=allwinner/sun4i-a10-cubieboard.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=allwinner/sun4i-a10-hackberry.dtb
diff --git a/arch/arm/dts/allwinner/sun4i-a10-cubieboard.dts b/arch/arm/dts/allwinner/sun4i-a10-cubieboard.dts
deleted file mode 100644
index b258c908..00000000
--- a/arch/arm/dts/allwinner/sun4i-a10-cubieboard.dts
+++ /dev/null
@@ -1,58 +0,0 @@
-
-/dts-v1/;
-
-/include/ "./sun4i-a10.dtsi"
-
-/ {
- model = "Cubietech Cubieboard";
- compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
-
- chosen {
- console = &uart0;
- bootargs = "earlyprintk console=ttyS0,115200";
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- soc@1c00000 {
- mdio@1c0b080 {
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
- emac: ethernet@1c0b000 {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
- phy = <&phy1>;
- status = "okay";
- };
-
- pinctrl@01c20800 {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <1>;
- allwinner,pull = <0>;
- };
- };
-
- uart0: serial@1c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
-
- mmc0: mmc@1c0f000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/allwinner/sun4i-a10-hackberry.dts b/arch/arm/dts/allwinner/sun4i-a10-hackberry.dts
deleted file mode 100644
index 5665af2b..00000000
--- a/arch/arm/dts/allwinner/sun4i-a10-hackberry.dts
+++ /dev/null
@@ -1,61 +0,0 @@
-
-/dts-v1/;
-
-/include/ "./sun4i-a10.dtsi"
-
-/ {
- model = "Miniand Hackberry";
- compatible = "miniand,hackberry", "allwinner,sun4i-a10";
-
- chosen {
- console = &uart0;
- bootargs = "earlyprintk console=ttyS0,115200";
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- soc@1c00000 {
- emac: ethernet@1c0b000 {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
- phy = <&phy0>;
- status = "okay";
- };
-
- mdio@1c0b080 {
- status = "okay";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
- pio: pinctrl@1c20800 {
- pinctrl-names = "default";
- pinctrl-0 = <&hackberry_hogs>;
-
- hackberry_hogs: hogs@0 {
- allwinner,pins = "PH19";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
- };
-
- uart0: serial@1c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
-
- mmc0: mmc@1c0f000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/allwinner/sun4i-a10.dtsi b/arch/arm/dts/allwinner/sun4i-a10.dtsi
deleted file mode 100644
index 076ac1b9..00000000
--- a/arch/arm/dts/allwinner/sun4i-a10.dtsi
+++ /dev/null
@@ -1,469 +0,0 @@
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "allwinner,sun4i";
- interrupt-parent = <&intc>;
-
- chosen { };
-
- aliases {
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A8";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x40000000 0x20000000>; /* 512 MB */
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
- * yet implemented. It should be dropped when the driver
- * is complete.
- */
- dummy: dummy {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- osc24M: clk@1c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- pll1: clk@1c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll4: clk@1c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll5: clk@1c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll5-clk";
- reg = <0x01c20020 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- pll6: clk@1c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- /* dummy is 200M */
- cpu: cpu@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
- clock-output-names = "cpu";
- };
-
- axi: axi@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- axi_gates: clk@1c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
- clocks = <&axi>;
- clock-output-names = "axi_dram";
- };
-
- ahb: ahb@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
- clock-output-names = "ahb";
- };
-
- ahb_gates: clk@1c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
- };
-
- apb0: apb0@1c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk@1c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
- };
-
- apb1_mux: apb1_mux@1c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@1c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
- clock-output-names = "apb1";
- };
-
- apb1_gates: clk@1c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
- };
-
- nand_clk: clk@1c20080 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20080 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "nand";
- };
-
- ms_clk: clk@1c20084 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20084 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ms";
- };
-
- mmc0_clk: clk@1c20088 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0";
- };
-
- mmc1_clk: clk@1c2008c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1";
- };
-
- mmc2_clk: clk@1c20090 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2";
- };
-
- mmc3_clk: clk@1c20094 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3";
- };
-
- ts_clk: clk@1c20098 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20098 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ts";
- };
-
- ss_clk: clk@1c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@1c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@1c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@1c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi2";
- };
-
- pata_clk: clk@1c200ac {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200ac 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "pata";
- };
-
- ir0_clk: clk@1c200b0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-
- ir1_clk: clk@1c200b4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir1";
- };
-
- usb_clk: clk@1c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&pll6 1>;
- clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
- };
-
- spi3_clk: clk@1c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200d4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi3";
- };
- };
-
- soc@1c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mdio@1c0b080 {
- compatible = "allwinner,sun4i-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- emac: ethernet@1c0b000 {
- compatible = "allwinner,sun4i-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <1 23>;
- clocks = <&ahb_gates 17>;
- status = "disabled";
- };
-
- intc: interrupt-controller@1c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pio: pinctrl@1c20800 {
- compatible = "allwinner,sun4i-a10-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <0 28>;
- clocks = <&apb0_gates 5>;
- gpio-controller;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #gpio-cells = <3>;
-
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PB22", "PB23";
- allwinner,function = "uart0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- uart0_pins_b: uart0@1 {
- allwinner,pins = "PF2", "PF4";
- allwinner,function = "uart0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- uart1_pins_a: uart1@0 {
- allwinner,pins = "PA10", "PA11";
- allwinner,function = "uart1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "i2c0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PB18", "PB19";
- allwinner,function = "i2c1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PB20", "PB21";
- allwinner,function = "i2c2";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- emac_pins_a: emac0@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
- "PA3", "PA4", "PA5", "PA6",
- "PA7", "PA8", "PA9", "PA10",
- "PA11", "PA12", "PA13", "PA14",
- "PA15", "PA16";
- allwinner,function = "emac";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
- };
-
- timer@1c20c00 {
- compatible = "allwinner,sun4i-timer";
- reg = <0x01c20c00 0x90>;
- timer_num = <1>; /* Timer1 */
- interrupts = <0 23>;
- clocks = <&osc24M>;
- };
-
- reboot@1c20c90 {
- compatible = "allwinner,sun4i-reboot";
- reg = <0x01c20c90 0x10>;
- };
-
- uart0: serial@1c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <0 1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
- status = "disabled";
- /* Only for Xvisor */
- clock-frequency = <24000000>;
- };
-
- uart1: serial@1c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <0 2>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
- status = "disabled";
- /* Only for Xvisor */
- clock-frequency = <24000000>;
- };
-
- mmc0: mmc@1c0f000 {
- compatible = "allwinner,sun4i-a10-mmc";
- reg = <0x01C0F000 0x1000 /* registers */
- 0x01C20088 0x1000 /* mclkbase */
- 0x01C20060 0x1000 /* hclkbase */
- 0x01C20020 0x1000 /* pll5cfg */
- 0X01C20800 0x1000>; /* gpiobase */
- clocks = <&ahb_gates 8>, <&mmc0_clk>;
- clock-names = "ahb", "mod";
- interrupts = <1 0>;
- bus-width = <4>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dts
deleted file mode 100644
index d193cf0e..00000000
--- a/arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dts
+++ /dev/null
@@ -1,198 +0,0 @@
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- compatible = "arm,realview";
- model = "realview-eb-mpcore";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "ARM11MPCore";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@1 {
- device_type = "cpu";
- model = "ARM11MPCore";
- reg = <1>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@2 {
- device_type = "cpu";
- model = "ARM11MPCore";
- reg = <2>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@3 {
- device_type = "cpu";
- model = "ARM11MPCore";
- reg = <3>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
- nbridge {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- clcd@10020000 {
- compatible = "arm,pl111";
- reg = <0x10020000 0x1000>;
- use_dma = <1>;
- };
-
- eth@4e000000 {
- compatible = "smc91x";
- reg = <0x4E000000 0x1000>;
- smsc,irq-active-high;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sbridge {
- #address-cells = <1>;
- #size-cells = <1>;
-
- scu { /* Snoop Control Unit */
- compatible = "arm,arm11mp-scu";
- reg = <0x10100000 0x100>;
- };
-
- gic: gic { /* Generic Interrupt Controller */
- compatible = "arm,realview-gic";
- reg = <0x10101000 0x1000>,
- <0x10100100 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- twd-timer { /* Local Timer */
- compatible = "arm,arm11mp-twd-timer";
- reg = <0x10100600 0x100 /* Local timer registers */
- 0x1000005C 0x4>; /* Reference counter address */
- ref-counter-freq = <24000000>; /* Reference counter frequency */
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- sysreg { /* System Registers */
- compatible = "arm,realview-sysreg";
- reg = <0x10000000 0x1000>;
- };
-
- reboot {
- compatible = "arm,realview-reboot";
- };
-
- sysctl: sysctl0 { /* System Controller */
- compatible = "arm,sp810";
- reg = <0x10001000 0x1000>;
- clocks = <&refclk32khz>, <&refclk1mhz>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- };
-
- mmci0 { /* Multimedia Card Interface */
- compatible = "arm,pl180";
- reg = <0x10005000 0x1000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- kmi0 { /* Keyboard */
- compatible = "ambakmi";
- reg = <0x10006000 0x1000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- kmi1 { /* Mouse */
- compatible = "ambakmi";
- reg = <0x10007000 0x1000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- SERIAL0: uart0 {
- compatible = "arm,pl011";
- reg = <0x10009000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- timer01 {
- compatible = "arm,sp804";
- reg = <0x10011000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysctl 0>, <&sysctl 1>;
- clock-names = "timclken1", "timclken2";
- };
-
- timer23 {
- compatible = "arm,sp804";
- reg = <0x10012000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysctl 2>, <&sysctl 3>;
- clock-names = "timclken1", "timclken2";
- };
-
- RTC0: rtc0 {
- compatible = "arm,pl031";
- reg = <0x10017000 0x1000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-
- refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "refclk1mhz";
- };
-
- refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "refclk32khz";
- };
-};
diff --git a/arch/arm/dts/arm/arm-realview-pba8.dts b/arch/arm/dts/arm/arm-realview-pba8.dts
deleted file mode 100644
index 2b2f1afa..00000000
--- a/arch/arm/dts/arm/arm-realview-pba8.dts
+++ /dev/null
@@ -1,155 +0,0 @@
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- compatible = "arm,realview";
- model = "realview-pb-a8";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A8";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x70000000 0x10000000>; /* 256 MB */
- };
-
- nbridge {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- clcd@10020000 {
- compatible = "arm,pl111";
- reg = <0x10020000 0x1000>;
- use_dma = <1>;
- };
-
- eth@4e000000 {
- compatible = "smc911x";
- reg = <0x4E000000 0x1000>;
- smsc,irq-active-high;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sbridge {
- #address-cells = <1>;
- #size-cells = <1>;
-
- gic: gic { /* Generic Interrupt Controller */
- compatible = "arm,realview-gic";
- reg = <0x1E001000 0x1000>,
- <0x1E000000 0x1000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- sysreg { /* System Registers */
- compatible = "arm,realview-sysreg";
- reg = <0x10000000 0x1000>;
- };
-
- reboot {
- compatible = "arm,realview-reboot";
- };
-
- sysctl: sysctl0 { /* System Controller */
- compatible = "arm,sp810";
- reg = <0x10001000 0x1000>;
- clocks = <&refclk32khz>, <&refclk1mhz>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- };
-
- mmci0 { /* Multimedia Card Interface */
- compatible = "arm,pl180";
- reg = <0x10005000 0x1000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- kmi0 { /* Keyboard */
- compatible = "ambakmi";
- reg = <0x10006000 0x1000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- kmi1 { /* Mouse */
- compatible = "ambakmi";
- reg = <0x10007000 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- SERIAL0: uart0 {
- compatible = "arm,pl011";
- reg = <0x10009000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- timer01 {
- compatible = "arm,sp804";
- reg = <0x10011000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysctl 0>, <&sysctl 1>;
- clock-names = "timclken1", "timclken2";
- };
-
- timer23 {
- compatible = "arm,sp804";
- reg = <0x10012000 0x1000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysctl 2>, <&sysctl 3>;
- clock-names = "timclken1", "timclken2";
- };
-
- RTC0: rtc0 {
- compatible = "arm,pl031";
- reg = <0x10017000 0x1000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-
- refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "refclk1mhz";
- };
-
- refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "refclk32khz";
- };
-};
diff --git a/arch/arm/dts/arm/objects.mk b/arch/arm/dts/arm/objects.mk
index e096a63e..0a7cd6a1 100644
--- a/arch/arm/dts/arm/objects.mk
+++ b/arch/arm/dts/arm/objects.mk
@@ -24,8 +24,3 @@
arch-dtbs-$(CONFIG_ARMV8)+=arm/foundation-v8-gicv2.dtb
arch-dtbs-$(CONFIG_ARMV8)+=arm/foundation-v8-gicv3.dtb
arch-dtbs-$(CONFIG_ARMV7A_VE)+=arm/vexpress-v2p-ca15-tc1.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=arm/arm-realview-pba8.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=arm/vexpress-v2p-ca9.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=arm/vexpress-v2p-ca15-tc1-nove.dtb
-arch-dtbs-$(CONFIG_ARMV6)+=arm/arm-realview-eb-11mp-ctrevb.dtb
-arch-dtbs-$(CONFIG_ARMV5)+=arm/versatile-pb.dtb
diff --git a/arch/arm/dts/arm/versatile-pb.dts b/arch/arm/dts/arm/versatile-pb.dts
deleted file mode 100644
index ea221150..00000000
--- a/arch/arm/dts/arm/versatile-pb.dts
+++ /dev/null
@@ -1,168 +0,0 @@
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,versatile";
- model = "versatile-pb";
- interrupt-parent = <&vic>;
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "ARM926ej";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
- motherboard {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "arm,amba-bus";
-
- vic: vic { /* Vectored Interrupt Controller */
- compatible = "arm,versatile-vic";
- reg = <0x10140000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- sic: sic { /* Secondary Interrupt Controller */
- compatible = "arm,versatile-sic";
- reg = <0x10003000 0x1000>;
- irq_start = <32>;
- clear-mask = <0xFFFFFFFF>; /* By default mask all interrupts */
- valid-mask = <0x000003FF>; /* Interrupts 0 to 8 routed via VIC irq 31 */
- picen-mask = <0xFFD00000>; /* Interrupts 21 to 31 routed directly to VIC */
- interrupts = <31>; /* Cascaded to vic */
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- sysreg { /* System Registers */
- compatible = "arm,versatile-sysreg";
- reg = <0x10000000 0x1000>;
- };
-
- eth0 {
- compatible = "smc91x";
- reg = <0x10010000 0x1000>;
- interrupts = <25>;
- };
-
- clcd {
- compatible = "arm,pl110,versatile";
- reg = <0x10120000 0x1000>;
- interrupts = <16>;
- use_dma = <1>;
- };
-
- sysctl: sysctl0 { /* System Controller */
- compatible = "arm,sp810";
- reg = <0x101E0000 0x1000>;
- clocks = <&refclk32khz>, <&refclk1mhz>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- };
-
- timer01 {
- compatible = "arm,sp804";
- reg = <0x101E2000 0x1000>;
- interrupts = <4>;
- clocks = <&sysctl 0>, <&sysctl 1>;
- clock-names = "timclken1", "timclken2";
- };
-
- timer23 {
- compatible = "arm,sp804";
- reg = <0x101E3000 0x1000>;
- interrupts = <5>;
- clocks = <&sysctl 2>, <&sysctl 3>;
- clock-names = "timclken1", "timclken2";
- };
-
- SERIAL0: uart0 {
- compatible = "arm,pl011";
- reg = <0x101F1000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <12>;
- };
-
- RTC0: rtc0 {
- compatible = "arm,pl031";
- reg = <0x101E8000 0x1000>;
- clock-frequency = <1>;
- interrupts = <10>;
- };
-
- kmi0 { /* Keyboard */
- compatible = "ambakmi";
- reg = <0x10006000 0x1000>;
- interrupts = <3>;
- interrupt-parent = <&sic>;
- clocks = <&refclk24mhz>;
- clock-names = "KMIREFCLK";
- };
-
- kmi1 { /* Mouse */
- compatible = "ambakmi";
- reg = <0x10007000 0x1000>;
- interrupts = <4>;
- interrupt-parent = <&sic>;
- clocks = <&refclk24mhz>;
- clock-names = "KMIREFCLK";
- };
- };
- };
-
- refclk24mhz: refclk24mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "refclk24mhz";
- };
-
- refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "refclk1mhz";
- };
-
- refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "refclk32khz";
- };
-};
diff --git a/arch/arm/dts/arm/vexpress-v2p-ca15-tc1-nove.dts b/arch/arm/dts/arm/vexpress-v2p-ca15-tc1-nove.dts
deleted file mode 100644
index adca70fd..00000000
--- a/arch/arm/dts/arm/vexpress-v2p-ca15-tc1-nove.dts
+++ /dev/null
@@ -1,322 +0,0 @@
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- compatible = "arm,vexpress";
- model = "vexpress-a15-nove";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen {
- initrd-start = <0x0 0x81000000>;
- initrd-end = <0x0 0x83000000>;
- console = &SERIAL0;
- rtcdev = &RTC0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- enable-method = "spin-table";
- cpu-clear-addr = <0x1C010034>;
- cpu-release-addr = <0x1C010030>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- enable-method = "spin-table";
- cpu-clear-addr = <0x1C010034>;
- cpu-release-addr = <0x1C010030>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB */
- };
-
- gic: gic { /* Generic Interrupt Controller */
- compatible = "arm,cortex-a9-gic";
- reg = <0x0 0x2C001000 0x0 0x1000>, /* GIC Dist */
- <0x0 0x2C002000 0x0 0x1000>; /* GIC CPU */
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- dcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- /* CPU PLL reference clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- freq-range = <50000000 60000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk0";
- };
-
- osc@4 {
- /* Multiplexed AXI master clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 4>;
- freq-range = <20000000 40000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk4";
- };
-
- oscclk5: osc@5 {
- /* HDLCD PLL reference clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 5>;
- freq-range = <23750000 165000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk5";
- };
-
- smbclk: osc@6 {
- /* SMB clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 6>;
- freq-range = <20000000 50000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk6";
- };
-
- oscclk7: osc@7 {
- /* SYS PLL reference clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 7>;
- freq-range = <20000000 60000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk7";
- };
-
- osc@8 {
- /* DDR2 PLL reference clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 8>;
- freq-range = <40000000 40000000>;
- #clock-cells = <0>;
- clock-output-names = "oscclk8";
- };
- };
-
- smb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- motherboard {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- eth@1a000000 {
- compatible = "smc91x";
- reg = <0x1A000000 0x1000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- iofpga {
- #address-cells = <1>;
- #size-cells = <1>;
-
- v2m_sysreg: sysreg@1c010000 { /* System Registers */
- compatible = "arm,vexpress-sysreg";
- reg = <0x1C010000 0x1000>;
- };
-
- v2m_sysctl: sysctl@1c020000 { /* System Controller */
- compatible = "arm,sp810";
- reg = <0x1C020000 0x1000>;
- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- };
-
- mmci@1c050000 { /* Multimedia Card Interface */
- compatible = "arm,pl180";
- reg = <0x1C050000 0x1000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "mclk", "apb_pclk";
- };
-
- kmi@1c060000 { /* Keyboard */
- compatible = "ambakmi";
- reg = <0x1C060000 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- kmi@1c070000 { /* Mouse */
- compatible = "ambakmi";
- reg = <0x1C070000 0x1000>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- SERIAL0: v2m_serial0: uart@1c090000 {
- compatible = "arm,pl011";
- reg = <0x1C090000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_oscclk2>, <&smbclk>;
- clock-names = "uartclk", "apb_pclk";
- };
-
- v2m_timer01: timer@1c110000 {
- compatible = "arm,sp804";
- reg = <0x1C110000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_sysctl 0>, <&v2m_refclk32khz>, <&smbclk>;
- clock-names = "timclken1", "timclken2", "apb_pclk";
- };
-
- v2m_timer23: timer@1c120000 {
- compatible = "arm,sp804";
- reg = <0x1C120000 0x1000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_sysctl 2>, <&v2m_refclk32khz>, <&smbclk>;
- clock-names = "timclken1", "timclken2", "apb_pclk";
- };
-
- RTC0: rtc@1c170000 {
- compatible = "arm,pl031";
- reg = <0x1C170000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&smbclk>;
- clock-names = "apb_pclk";
- };
-
- clcd@1c1f0000 {
- compatible = "arm,pl111";
- reg = <0x1C1F0000 0x1000>;
- clocks = <&v2m_oscclk1>, <&smbclk>;
- clock-names = "clcdclk", "apb_pclk";
- use_dma = <0>;
- framebuffer = <0x18000000 0x00180000>;
- };
- };
-
- v2m_clk24mhz: clk24mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "v2m:clk24mhz";
- };
-
- v2m_refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "v2m:refclk1mhz";
- };
-
- v2m_refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "v2m:refclk32khz";
- };
-
- mcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- /* MCC static memory clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- freq-range = <25000000 60000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk0";
- };
-
- v2m_oscclk1: osc@1 {
- /* CLCD clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 1>;
- freq-range = <23750000 63500000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk1";
- };
-
- v2m_oscclk2: osc@2 {
- /* IO FPGA peripheral clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 2>;
- freq-range = <24000000 24000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk2";
- };
-
- volt@0 {
- /* Logic level voltage */
- compatible = "arm,vexpress-volt";
- arm,vexpress-sysreg,func = <2 0>;
- regulator-name = "VIO";
- regulator-always-on;
- label = "VIO";
- };
-
- temp@0 {
- /* MCC internal operating temperature */
- compatible = "arm,vexpress-temp";
- arm,vexpress-sysreg,func = <4 0>;
- label = "MCC";
- };
-
- reset@0 {
- compatible = "arm,vexpress-reset";
- arm,vexpress-sysreg,func = <5 0>;
- };
-
- muxfpga@0 {
- compatible = "arm,vexpress-muxfpga";
- arm,vexpress-sysreg,func = <7 0>;
- };
-
- shutdown@0 {
- compatible = "arm,vexpress-shutdown";
- arm,vexpress-sysreg,func = <8 0>;
- };
-
- reboot@0 {
- compatible = "arm,vexpress-reboot";
- arm,vexpress-sysreg,func = <9 0>;
- };
-
- dvimode@0 {
- compatible = "arm,vexpress-dvimode";
- arm,vexpress-sysreg,func = <11 0>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/arm/vexpress-v2p-ca9.dts b/arch/arm/dts/arm/vexpress-v2p-ca9.dts
deleted file mode 100644
index b36fa2eb..00000000
--- a/arch/arm/dts/arm/vexpress-v2p-ca9.dts
+++ /dev/null
@@ -1,323 +0,0 @@
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- compatible = "arm,vexpress";
- model = "vexpress-a9";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- enable-method = "smp-scu";
- cpu-clear-addr = <0x10000034>;
- cpu-release-addr = <0x10000030>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x60000000 0x10000000>; /* 256 MB */
- };
-
- scu { /* Snoop Control Unit */
- compatible = "arm,cortex-a9-scu";
- reg = <0x1E000000 0x1000>;
- };
-
- gic: gic { /* Generic Interrupt Controller */
- compatible = "arm,cortex-a9-gic";
- reg = <0x1E001000 0x1000>,
- <0x1E000100 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- twd-timer { /* Local Timer */
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x1E000600 0x100 /* Local timer registers */
- 0x1000005C 0x4>; /* Reference counter address */
- ref-counter-freq = <24000000>; /* Reference counter frequency */
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- dcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- /* ACLK clock to the AXI master port on the test chip */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- freq-range = <30000000 50000000>;
- #clock-cells = <0>;
- clock-output-names = "extsaxiclk";
- };
-
- oscclk1: osc@1 {
- /* Reference clock for the CLCD */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 1>;
- freq-range = <10000000 80000000>;
- #clock-cells = <0>;
- clock-output-names = "clcdclk";
- };
-
- smbclk: oscclk2: osc@2 {
- /* Reference clock for the test chip internal PLLs */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 2>;
- freq-range = <33000000 100000000>;
- #clock-cells = <0>;
- clock-output-names = "tcrefclk";
- };
- };
-
- smb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- motherboard {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- eth@4e000000 {
- compatible = "smc911x";
- reg = <0x4E000000 0x1000>;
- smsc,irq-active-high;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- iofpga {
- #address-cells = <1>;
- #size-cells = <1>;
-
- v2m_sysreg: sysreg@10000000 { /* System Registers */
- compatible = "arm,vexpress-sysreg";
- reg = <0x10000000 0x1000>;
- };
-
- v2m_sysctl: sysctl@10001000 { /* System Controller */
- compatible = "arm,sp810";
- reg = <0x10001000 0x1000>;
- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
- clock-names = "refclk", "timclk", "apb_pclk";
- #clock-cells = <1>;
- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
- };
-
- mmci@10005000 { /* Multimedia Card Interface */
- compatible = "arm,pl180";
- reg = <0x10005000 0x1000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "mclk", "apb_pclk";
- };
-
- kmi@10006000 { /* Keyboard */
- compatible = "arm,pl050";
- reg = <0x10006000 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- kmi@10007000 { /* Mouse */
- compatible = "arm,pl050";
- reg = <0x10007000 0x1000>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_clk24mhz>, <&smbclk>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- SERIAL0: v2m_serial0: uart@10009000 {
- compatible = "arm,pl011";
- reg = <0x10009000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_oscclk2>, <&smbclk>;
- clock-names = "uartclk", "apb_pclk";
- };
-
- v2m_timer01: timer@10011000 {
- compatible = "arm,sp804";
- reg = <0x10011000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
- clock-names = "timclken1", "timclken2", "apb_pclk";
- };
-
- v2m_timer23: timer@10012000 {
- compatible = "arm,sp804";
- reg = <0x10012000 0x1000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
- clock-names = "timclken1", "timclken2", "apb_pclk";
- };
-
- RTC0: v2m_rtc0: rtc@10017000 {
- compatible = "arm,pl031";
- reg = <0x10017000 0x1000>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- clcd@10020000 {
- compatible = "arm,pl111";
- reg = <0x10020000 0x1000>;
- clocks = <&v2m_oscclk1>, <&smbclk>;
- clock-names = "clcdclk", "apb_pclk";
- use_dma = <0>;
- framebuffer = <0x4C000000 0x00180000>;
- };
- };
-
- v2m_clk24mhz: clk24mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "v2m:clk24mhz";
- };
-
- v2m_refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "v2m:refclk1mhz";
- };
-
- v2m_refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "v2m:refclk32khz";
- };
-
- mcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- osc@0 {
- /* MCC static memory clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- freq-range = <25000000 60000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk0";
- };
-
- v2m_oscclk1: osc@1 {
- /* CLCD clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 1>;
- freq-range = <23750000 63500000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk1";
- };
-
- v2m_oscclk2: osc@2 {
- /* IO FPGA peripheral clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 2>;
- freq-range = <24000000 24000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk2";
- };
-
- volt@0 {
- /* Logic level voltage */
- compatible = "arm,vexpress-volt";
- arm,vexpress-sysreg,func = <2 0>;
- regulator-name = "VIO";
- regulator-always-on;
- label = "VIO";
- };
-
- temp@0 {
- /* MCC internal operating temperature */
- compatible = "arm,vexpress-temp";
- arm,vexpress-sysreg,func = <4 0>;
- label = "MCC";
- };
-
- reset@0 {
- compatible = "arm,vexpress-reset";
- arm,vexpress-sysreg,func = <5 0>;
- };
-
- muxfpga@0 {
- compatible = "arm,vexpress-muxfpga";
- arm,vexpress-sysreg,func = <7 0>;
- };
-
- shutdown@0 {
- compatible = "arm,vexpress-shutdown";
- arm,vexpress-sysreg,func = <8 0>;
- };
-
- reboot@0 {
- compatible = "arm,vexpress-reboot";
- arm,vexpress-sysreg,func = <9 0>;
- };
-
- dvimode@0 {
- compatible = "arm,vexpress-dvimode";
- arm,vexpress-sysreg,func = <11 0>;
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/broadcom/bcm2835-rpi-b.dts b/arch/arm/dts/broadcom/bcm2835-rpi-b.dts
deleted file mode 100644
index e82d7ba7..00000000
--- a/arch/arm/dts/broadcom/bcm2835-rpi-b.dts
+++ /dev/null
@@ -1,43 +0,0 @@
-
-/dts-v1/;
-
-/include/ "bcm2835.dtsi"
-
-/ {
- compatible = "raspberrypi,model-b", "brcm,bcm2835";
- model = "Raspberry Pi Model B";
-
- chosen {
- console = &SERIAL0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
-
-&soc {
- firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware";
- mboxes = <&mailbox>;
- };
-};
-
-&i2c0 {
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <100000>;
-};
-
-&sdhci {
- status = "okay";
- bus-width = <4>;
-};
diff --git a/arch/arm/dts/broadcom/bcm2835.dtsi b/arch/arm/dts/broadcom/bcm2835.dtsi
deleted file mode 100644
index a46a238f..00000000
--- a/arch/arm/dts/broadcom/bcm2835.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "brcm,bcm2835";
- model = "BCM2835";
- interrupt-parent = <&intc>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "ARM1176JZ(F)-S";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; /* 512 MB */
- };
-
- soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- timer@20003000 {
- compatible = "brcm,bcm2835-system-timer";
- reg = <0x20003000 0x1000>;
- clock-frequency = <1000000>;
- interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
- };
-
- intc: intc@2000b200 {
- compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x2000b200 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- mailbox: mailbox@2000b880 {
- compatible = "brcm,bcm2835-mbox";
- reg = <0x2000b880 0x40>;
- interrupts = <0 1>;
- #mbox-cells = <0>;
- };
-
- poweroff@20100000 {
- compatible = "brcm,bcm2835-poweroff";
- reg = <0x20100000 0x28>;
- };
-
- gpio: gpio@20200000 {
- compatible = "brcm,bcm2835-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20200000 0xb4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <2 17>,
- <2 18>,
- <2 19>,
- <2 20>;
- };
-
- SERIAL0: uart@20201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011";
- reg = <0x20201000 0x1000>;
- interrupts = <2 25>;
- };
-
- i2c0: i2c@20205000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x20205000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clk_i2c>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdhci: sdhci@20300000 {
- compatible = "brcm,bcm2835-sdhci";
- reg = <0x20300000 0x1000>;
- interrupts = <2 30>;
- clocks = <&clk_mmc>;
- status = "disabled";
- };
-
- i2c1: i2c@20804000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x20804000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clk_i2c>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- usb: usb@20980000 {
- compatible = "brcm,bcm2835-usb";
- reg = <0x20980000 0x10000>;
- interrupts = <1 9>;
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk_mmc: mmc {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- clk_i2c: i2c {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
-
- clk_spi: spi {
- compatible = "fixed-clock";
- reg = <2>;
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
- };
-};
diff --git a/arch/arm/dts/broadcom/objects.mk b/arch/arm/dts/broadcom/objects.mk
index d71b32e0..157d23c4 100644
--- a/arch/arm/dts/broadcom/objects.mk
+++ b/arch/arm/dts/broadcom/objects.mk
@@ -21,7 +21,6 @@
# @brief list of Broadcom DTBs.
# */

-arch-dtbs-$(CONFIG_ARMV6)+=broadcom/bcm2835-rpi-b.dtb
arch-dtbs-$(CONFIG_ARMV7A_VE)+=broadcom/bcm2836-rpi-2-b.dtb
arch-dtbs-$(CONFIG_ARMV8)+=broadcom/bcm2837-rpi-3-b.dtb
arch-dtbs-$(CONFIG_ARMV8)+=broadcom/bcm2838-rpi-4-b.dtb
diff --git a/arch/arm/dts/freescale/imx25-pdk.dts b/arch/arm/dts/freescale/imx25-pdk.dts
deleted file mode 100644
index b0ea95c9..00000000
--- a/arch/arm/dts/freescale/imx25-pdk.dts
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 2015 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx25-pdk.dtsi
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief i.MX25 PDK DTS file
- */
-
-/dts-v1/;
-
-#include "imx25-pinfunc.h"
-#include "imx25.dtsi"
-
-/ {
- model = "Freescale i.MX25 Product Development Kit";
- compatible = "fsl,imx25-pdk", "fsl,imx25";
-
- chosen {
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- chosen {
- console = &uart1;
- };
-
- memory {
- /* NOTE: By default Qemu will only proivde 128 MB
- * unless specified by "-m" option. You will have to
- * run Qemu with "-m 512M" to get the all memory
- */
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512 MB */
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_fec_3v3: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "fec-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 3 0>;
- enable-active-high;
- };
-
- reg_2p5v: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "2P5V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- };
-
- reg_3p3v: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_can_3v3: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "can-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio4 6 0>;
- };
- };
-};
-
-&fec {
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-supply = <&reg_fec_3v3>;
- phy-reset-gpios = <&gpio4 8 0>;
- status = "okay";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- codec: sgtl5000@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&clks 129>;
- VDDA-supply = <&reg_2p5v>;
- VDDIO-supply = <&reg_3p3v>;
- };
-};
-
-&iomuxc {
- imx25-pdk {
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
- MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
- MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
- MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
- MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
- MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
- MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
- MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
- MX25_PAD_A17__GPIO_2_3 0x80000000
- MX25_PAD_D12__GPIO_4_8 0x80000000
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
- MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX25_PAD_UART1_RTS__UART1_RTS 0xe0
- MX25_PAD_UART1_CTS__UART1_CTS 0xe0
- MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
- MX25_PAD_UART1_RXD__UART1_RXD 0xc0
- >;
- };
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- fsl,uart-has-rtscts;
- status = "okay";
-};
diff --git a/arch/arm/dts/freescale/imx25-pinfunc.h b/arch/arm/dts/freescale/imx25-pinfunc.h
deleted file mode 100644
index f826a0bd..00000000
--- a/arch/arm/dts/freescale/imx25-pinfunc.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright (C) 2015 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx25-pinfunc.h
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief PIN PAD definition for i.MX25
- *
- * Adapted from Linux Kernel 4.2.0 arch/arm/boot/dts/imx25-pinfunc.h
- *
- * Copyright 2013 Eukréa Electromatique <de...@eukrea.com>
- * Based on imx35-pinfunc.h in the same directory Which is:
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX25_PINFUNC_H
-#define __DTS_IMX25_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
-
-#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
-#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
-
-#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
-#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
-#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
-
-#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
-#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
-#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
-#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
-
-#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
-#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
-#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
-#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
-
-#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
-#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
-#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
-#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
-
-#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
-#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
-#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
-#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
-
-#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
-#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
-#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
-#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
-
-#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
-#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
-#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
-#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
-
-#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
-#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
-#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
-#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
-
-#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
-#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
-#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
-#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
-
-#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
-#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
-#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
-#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
-#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
-
-#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
-#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
-#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
-#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
-
-#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
-#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
-#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
-#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
-
-#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
-#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000
-#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000
-
-#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000
-#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000
-#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000
-
-#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000
-#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000
-#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000
-
-#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000
-#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000
-#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000
-
-#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
-#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000
-
-#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
-#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
-#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000
-
-#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000
-#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
-#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
-#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
-
-#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
-#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
-#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
-#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
-
-#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
-#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
-
-#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
-#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
-#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
-
-#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
-#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
-#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
-
-#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
-#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
-
-#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000
-#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000
-#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000
-
-#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000
-#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000
-
-#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
-#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
-#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
-#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
-
-#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
-#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
-#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
-#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
-
-#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
-#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
-#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
-#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
-
-#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
-#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
-#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
-
-#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
-#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
-#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
-
-#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
-#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
-#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000
-
-#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
-#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
-#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000
-
-#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
-#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
-#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000
-
-#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
-#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000
-
-#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
-#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000
-
-#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
-#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000
-
-#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
-#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000
-
-#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
-#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000
-
-#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
-#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000
-
-#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
-#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000
-
-#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
-#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000
-
-#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000
-#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000
-#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000
-
-#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000
-#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000
-#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000
-
-#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000
-#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000
-
-#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000
-#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000
-
-#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000
-#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000
-
-#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000
-#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000
-
-#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000
-#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000
-
-#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000
-#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
-
-#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
-#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
-#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
-
-#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
-#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
-#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
-
-#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
-#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
-
-#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
-#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
-#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
-
-#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
-#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
-#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
-
-#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
-#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
-#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
-
-#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
-#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
-#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
-
-#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
-#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
-#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
-
-#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
-#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000
-
-#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000
-#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000
-
-#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000
-#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
-
-#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
-#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
-#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
-
-#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
-#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000
-#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
-#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
-
-#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000
-#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000
-#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
-
-#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
-#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
-#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
-#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
-
-#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
-#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
-#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
-#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
-#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
-
-#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
-#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
-#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
-#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
-#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
-
-#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
-#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
-#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
-#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
-#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
-
-#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
-#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
-#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
-#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
-
-#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001
-#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
-
-#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
-#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
-#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
-#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
-
-#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
-#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
-#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
-#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
-
-#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
-#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
-#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
-
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
-#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
-
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
-#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
-
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
-
-#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
-#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000
-
-#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000
-#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001
-#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
-
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
-
-#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
-#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
-
-#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
-#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
-
-#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
-#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
-#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000
-#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
-
-#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
-#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
-#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
-
-#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
-#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
-
-#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
-#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
-
-#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
-#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
-#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
-#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
-
-#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
-#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
-#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
-#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001
-#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
-#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
-#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001
-#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
-#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001
-#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000
-#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
-#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
-
-#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
-#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
-#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
-#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
-#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
-
-#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000
-#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001
-#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000
-#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001
-#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
-/*
- * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
- * 01/2011) this is CAN1_TX but that's wrong.
- */
-#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
-/*
- * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
- * 01/2011) this is CAN1_RX but that's wrong.
- */
-#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
-
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000
-
-#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000
-#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000
-#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000
-
-#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
-#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
-
-#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
-#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
-#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
-
-#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
-#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
-#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
-
-#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
-#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
-#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
-#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
-#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
-
-#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
-#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
-#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
-
-#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
-#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
-#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
-#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
-#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
-
-#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
-#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
-#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
-#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
-
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
-
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
-
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
-
-#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
-#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
-#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
-
-#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
-#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000
-
-#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
-#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
-
-#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
-#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
-
-#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/dts/freescale/imx25.dtsi b/arch/arm/dts/freescale/imx25.dtsi
deleted file mode 100644
index 6a2f070e..00000000
--- a/arch/arm/dts/freescale/imx25.dtsi
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright (C) 2015 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx25.dtsi
- * @author Jean-Christophe Dubois (j...@tribudubois.net)
- * @brief i.MX25 SOC DTSI file
- */
-
-/ {
- model = "imx25";
- interrupt-parent = <&avic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
-
- aliases {
- ethernet0 = &fec;
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- spi0 = &spi1;
- spi1 = &spi2;
- spi2 = &spi3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "ARM926";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-
- avic: avic@68000000 {
- compatible = "freescale,avic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x68000000 0x1000>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc {
- compatible = "fsl,imx-osc", "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&avic>;
- ranges;
-
- aips@43f00000 {
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x43f00000 0x100000>;
- ranges;
-
- i2c1: i2c@43f80000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
- reg = <0x43f80000 0x4000>;
- clocks = <&clks 48>;
- clock-names = "";
- interrupts = <3>;
- status = "disabled";
- };
-
- i2c3: i2c@43f84000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
- reg = <0x43f84000 0x4000>;
- clocks = <&clks 48>;
- clock-names = "";
- interrupts = <10>;
- status = "disabled";
- };
-
- uart1: serial@43f90000 {
- compatible = "freescale,imx-uart";
- reg = <0x43f90000 0x4000>;
- interrupts = <45>;
- clocks = <&clks 120>, <&clks 57>;
- clock-names = "ipg", "per";
- clock-frequency = <3000000>;
- status = "disabled";
- };
-
- uart2: serial@43f94000 {
- compatible = "freescale,imx-uart";
- reg = <0x43f94000 0x4000>;
- interrupts = <32>;
- clocks = <&clks 121>, <&clks 57>;
- clock-names = "ipg", "per";
- clock-frequency = <3000000>;
- status = "disabled";
- };
-
- i2c2: i2c@43f98000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
- reg = <0x43f98000 0x4000>;
- clocks = <&clks 48>;
- clock-names = "";
- interrupts = <4>;
- status = "disabled";
- };
-
- spi1: spi@43fa4000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-ecspi", "fsl,imx51-ecspi";
- reg = <0x43fa4000 0x4000>;
- interrupts = <14>;
- clocks = <&clks 78>, <&clks 78>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- iomuxc: iomuxc@43fac000 {
- compatible = "fsl,imx25-iomuxc";
- reg = <0x43fac000 0x4000>;
- };
- };
-
- spba@50000000 {
- compatible = "fsl,spba-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x50000000 0x40000>;
- ranges;
-
- spi3: spi@50004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-ecspi", "fsl,imx51-ecspi";
- reg = <0x50004000 0x4000>;
- interrupts = <0>;
- clocks = <&clks 80>, <&clks 80>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart4: serial@50008000 {
- compatible = "freescale,imx-uart";
- reg = <0x50008000 0x4000>;
- interrupts = <5>;
- clocks = <&clks 121>, <&clks 57>;
- clock-names = "ipg", "per";
- clock-frequency = <3000000>;
- status = "disabled";
- };
-
- uart3: serial@5000c000 {
- compatible = "freescale,imx-uart";
- reg = <0x5000c000 0x4000>;
- interrupts = <18>;
- clocks = <&clks 122>, <&clks 57>;
- clock-names = "ipg", "per";
- clock-frequency = <3000000>;
- status = "disabled";
- };
-
- spi2: spi@50010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx25-ecspi", "fsl,imx51-ecspi";
- reg = <0x50010000 0x4000>;
- interrupts = <13>;
- clocks = <&clks 79>, <&clks 79>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart5: serial@5002c000 {
- compatible = "freescale,imx-uart";
- reg = <0x5002c000 0x4000>;
- interrupts = <40>;
- clocks = <&clks 124>, <&clks 57>;
- clock-names = "ipg", "per";
- clock-frequency = <3000000>;
- status = "disabled";
- };
-
- fec: ethernet@50038000 {
- compatible = "fsl,imx25-fec";
- reg = <0x50038000 0x4000>;
- interrupts = <57>;
- clocks = <&clks 88>, <&clks 65>;
- clock-names = "ipg", "ahb";
- status = "disabled";
- };
- };
-
- aips@53f00000 { /* AIPS2 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x53f00000 0x100000>;
- ranges;
-
- clks: ccm@53f80000 {
- compatible = "fsl,imx25-ccm";
- reg = <0x53f80000 0x4000>;
- interrupts = <31>;
- #clock-cells = <1>;
- };
-
- gpt4: timer@53f84000 {
- compatible = "freescale,gpt-timer";
- reg = <0x53f84000 0x4000>;
- clocks = <&clks 95>, <&clks 47>;
- clock-names = "ipg", "per";
- clock-frequency = <1000000>;
- timer_num = <5>;
- interrupts = <1>;
- };
-
- gpt3: timer@53f88000 {
- compatible = "freescale,gpt-timer";
- reg = <0x53f88000 0x4000>;
- clocks = <&clks 94>, <&clks 47>;
- clock-names = "ipg", "per";
- clock-frequency = <1000000>;
- timer_num = <4>;
- interrupts = <29>;
- };
-
- gpt2: timer@53f8c000 {
- compatible = "freescale,gpt-timer";
- reg = <0x53f8c000 0x4000>;
- clocks = <&clks 93>, <&clks 47>;
- clock-names = "ipg", "per";
- clock-frequency = <1000000>;
- timer_num = <3>;
- interrupts = <53>;
- };
-
- gpt1: timer@53f90000 {
- compatible = "freescale,gpt-timer";
- reg = <0x53f90000 0x4000>;
- clocks = <&clks 93>, <&clks 47>;
- clock-names = "ipg", "per";
- clock-frequency = <1000000>;
- timer_num = <2>;
- interrupts = <54>;
- };
-
- epit1: timer@53f94000 {
- compatible = "freescale,epit-timer";
- reg = <0x53f94000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <0>;
- interrupts = <28>;
- };
-
- epit2: timer@53f98000 {
- compatible = "freescale,epit-timer";
- reg = <0x53f98000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <1>;
- interrupts = <27>;
- };
-
- gpio4: gpio@53f9c000 {
- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
- reg = <0x53f9c000 0x4000>;
- interrupts = <23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@53fa4000 {
- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
- reg = <0x53fa4000 0x4000>;
- interrupts = <16>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@53fcc000 {
- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
- reg = <0x53fcc000 0x4000>;
- interrupts = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@53fd0000 {
- compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
- reg = <0x53fd0000 0x4000>;
- interrupts = <51>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/freescale/imx31-kzm.dts b/arch/arm/dts/freescale/imx31-kzm.dts
deleted file mode 100644
index 3babc7dc..00000000
--- a/arch/arm/dts/freescale/imx31-kzm.dts
+++ /dev/null
@@ -1,26 +0,0 @@
-
-/dts-v1/;
-
-/include/ "imx31.dtsi"
-
-/ {
- model = "kzm";
-
- chosen {
- console = &SERIAL1;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-};
-
diff --git a/arch/arm/dts/freescale/imx31.dtsi b/arch/arm/dts/freescale/imx31.dtsi
deleted file mode 100644
index 5263a79e..00000000
--- a/arch/arm/dts/freescale/imx31.dtsi
+++ /dev/null
@@ -1,98 +0,0 @@
-
-/ {
- model = "imx31";
- interrupt-parent = <&avic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "ARM1136JF-S";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- epit@53f94000 {
- compatible = "freescale,epit-timer";
- reg = <0x53f94000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <0>;
- interrupts = <28>;
- };
-
- epit@53f98000 {
- compatible = "freescale,epit-timer";
- reg = <0x53f98000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <1>;
- interrupts = <27>;
- };
-
- gpt@53f90000 {
- compatible = "freescale,gpt-timer";
- reg = <0x53f90000 0x4000>;
- clock-frequency = <1000000>;
- timer_num = <2>;
- interrupts = <29>;
- };
-
- avic: avic@68000000 {
- compatible = "freescale,avic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x68000000 0x1000>;
- };
-
- SERIAL1: uart@43f90000 {
- compatible = "freescale,imx-uart";
- reg = <0x43f90000 0x4000>;
- clock-frequency = <3000000>;
- interrupts = <45>;
- };
-
- SERIAL2: uart@43f94000 {
- compatible = "freescale,imx-uart";
- reg = <0x43f94000 0x4000>;
- clock-frequency = <3000000>;
- interrupts = <32>;
- };
-
- SERIAL4: uart@43fb0000 {
- compatible = "freescale,imx-uart";
- reg = <0x43fb0000 0x4000>;
- clock-frequency = <3000000>;
- interrupts = <46>;
- };
-
- SERIAL5: uart@43fb4000 {
- compatible = "freescale,imx-uart";
- reg = <0x43fb4000 0x4000>;
- clock-frequency = <3000000>;
- interrupts = <47>;
- };
-
- eth@b6000000 {
- compatible = "smc911x";
- reg = <0xb6000000 0x1000>;
- interrupts = <52>;
- smsc,irq-active-high;
- };
- };
-};
diff --git a/arch/arm/dts/freescale/imx6dl-sabrelite.dts b/arch/arm/dts/freescale/imx6dl-sabrelite.dts
deleted file mode 100644
index 0d1f66fa..00000000
--- a/arch/arm/dts/freescale/imx6dl-sabrelite.dts
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file imx6dl-sabrelite.dts
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Sabrelite-specific device tree definitions.
- */
-
-/dts-v1/;
-
-#include "./imx6q.dtsi"
-
-/ {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- model = "Freescale i.MX6 Quad SABRE Lite Board";
- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
-
- memory {
- device_type = "memory";
- reg = <0x10000000 0x40000000>; /* 1 GB */
- };
-
- chosen {
- console = &SERIAL2;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
-
-&SERIAL1 {
- status = "okay";
-};
-
-&SERIAL2 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio3 {
- status = "okay";
-};
-
-&gpio7 {
- status = "okay";
-};
-
-&ecspi1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fsl,spi-num-chipselects = <1>;
- cs-gpios = <&gpio3 19 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
- status = "okay";
-
- flash: m25p80@0 {
- compatible = "sst25vf016b";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
- cd-gpios = <&gpio7 0 0>;
- wp-gpios = <&gpio7 1 0>;
- /* vmmc-supply = <&reg_3p3v>; */
- status = "okay";
-};
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
- status = "okay";
-};
-
-&ldb {
- ipu_id = <0>;
- disp_id = <0>;
- ext_ref = <1>;
- mode = "sin0";
- sec_ipu_id = <1>;
- sec_disp_id = <1>;
- status = "okay";
-};
-
-&hdmi_core {
- status = "okay";
- ipu_id = <1>;
- disp_id = <0>;
-};
-
-&hdmi_video {
- status = "okay";
- fsl,phy_reg_vlev = <0x0294>;
- fsl,phy_reg_cksymtx = <0x800d>;
-};
-
-&mxcfb1 {
- status = "okay";
- interface_pix_fmt = "RGB666";
- default_bpp = <16>;
- mode_str = "LDB-XGA";
-};
-
-&mxcfb2 {
- status = "okay";
- interface_pix_fmt = "RGB24";
- default_bpp = <16>;
- mode_str = "";
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1>;
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_2>;
- hdmi: edid@50 {
- compatible = "fsl,imx6-hdmi-i2c";
- reg = <0x50>;
- };
-};
-
-&i2c3 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_3>;
-
- touchscreen: egalax_ts@4 {
- compatible = "eeti,egalax_ts";
- reg = <0x04>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
-};
-
-&fec {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_4>;
- phy-mode = "rgmii";
- //phy-reset-gpios = <&gpio1 27 0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- #address-cells = <0>;
- #size-cells = <1>;
- phy_int {
- reg = <0x6>;
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_1>;
-
- imx6q-nitrogen6x {
- pinctrl_hog_1: hoggrp-1 {
- fsl,pins = <
- /* Power Button */
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
- /* Menu Button */
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
- /* Home Button */
- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
- /* Back Button */
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- /* Volume Up Button */
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
- /* Volume Down Button */
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 /* ethernet phy reset */
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* Spare */
- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* uSDHC4 CD */
- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* Spare */
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* Spare */
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */
- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */
- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */
- MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* ov5642 mclk */
- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 /* ov5642 Power Down */
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* ov5642 Reset */
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 /* wl12xx_wl_irq */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 /* wl12xx_bt_en */
- /*MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0*/ /* TiWi slow clock */
- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* ISL1208 interrupt */
-
- >;
- };
- };
-
-};
diff --git a/arch/arm/dts/freescale/imx6q-pinfunc.h b/arch/arm/dts/freescale/imx6q-pinfunc.h
deleted file mode 100644
index 0d1e5385..00000000
--- a/arch/arm/dts/freescale/imx6q-pinfunc.h
+++ /dev/null
@@ -1,1048 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * File taken from Linux Kernel 3.13.6.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX6Q_PINFUNC_H
-#define __DTS_IMX6Q_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
-#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
-#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
-#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
-#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
-#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
-#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
-#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
-#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
-#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
-#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
-#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
-#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
-#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
-#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
-#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
-#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
-#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
-#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
-#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
-#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
-#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
-#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
-#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
-#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
-#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
-#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
-#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
-#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
-#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
-#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
-#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
-#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
-#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
-#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
-#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
-#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
-#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
-#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
-#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
-#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
-#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
-#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
-#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
-#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
-#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
-#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
-#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
-#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
-#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
-#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
-#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
-#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
-#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
-#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
-#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
-#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
-#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
-#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
-#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
-#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
-#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
-#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
-#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
-#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
-#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
-#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
-#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0
-#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
-#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
-#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
-#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
-#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
-#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
-#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
-#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
-#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
-#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
-#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
-#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
-#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
-#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
-#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
-#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
-#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
-#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
-#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
-#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
-#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
-#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
-#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
-#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
-#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
-#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
-#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
-#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
-#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
-#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
-#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
-#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
-#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
-#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
-#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
-#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
-#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
-#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
-#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
-#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
-#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
-#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
-#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
-#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
-#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
-#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
-#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
-#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
-#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
-#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
-#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
-#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
-#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
-#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
-#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
-#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
-#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
-#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
-#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
-#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
-#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
-#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
-#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
-#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
-#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
-#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
-#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
-#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
-#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
-#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
-#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
-#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
-#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
-#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
-#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100
-#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
-#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
-#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
-#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
-#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
-#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
-#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
-#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
-#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
-#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
-#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
-#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
-#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
-#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
-#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
-#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
-#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
-#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
-#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
-#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
-#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
-#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
-#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
-#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
-#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
-#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
-#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
-#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
-#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
-#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
-#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
-#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
-#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
-#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
-#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
-#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
-#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
-#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
-#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
-#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
-#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
-#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
-#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
-#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
-#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
-#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
-#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
-#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
-#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
-#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
-#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
-#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
-#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
-#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
-#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
-#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
-#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
-#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
-#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
-#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
-#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
-#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
-#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
-#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
-#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
-#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
-#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
-#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
-#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
-#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
-#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
-#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
-#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
-#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
-#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
-#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
-#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
-#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
-#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
-#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
-#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
-#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
-#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
-#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
-#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
-#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
-#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
-#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
-#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
-#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
-#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
-#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
-#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
-#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
-#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
-#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
-#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
-#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
-#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
-#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
-#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
-#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
-#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
-#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
-#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
-#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
-#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
-#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
-#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
-#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
-#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
-#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
-#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
-#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
-#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
-#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
-#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
-#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
-#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
-#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
-#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
-#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
-#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
-#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
-#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
-#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
-#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
-#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
-#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
-#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
-#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
-#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
-#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
-#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
-#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
-#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
-#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
-#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
-#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
-#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
-#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
-#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
-#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
-#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
-#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
-#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
-#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
-#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
-#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
-#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
-#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
-#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
-#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
-#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
-#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
-#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
-#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
-#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
-#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
-#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
-#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
-#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
-#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
-#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
-#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
-#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
-#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
-#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
-#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
-#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
-#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
-#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
-#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
-#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
-#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
-#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
-#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
-#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
-#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
-#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
-#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
-#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
-#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
-#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
-#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
-#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
-#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
-#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
-#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
-#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
-#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
-#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
-#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
-#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
-#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
-#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
-#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
-#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
-#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
-#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
-#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
-#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
-#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
-#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
-#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
-#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
-#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
-#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
-#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
-#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
-#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
-#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
-
-#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/dts/freescale/imx6q.dtsi b/arch/arm/dts/freescale/imx6q.dtsi
deleted file mode 100644
index a9570ca4..00000000
--- a/arch/arm/dts/freescale/imx6q.dtsi
+++ /dev/null
@@ -1,929 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * Originally from Jean-Christophe Dubois, and modified by
- * Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * to split device tree files between i.MX6-specific and Sabrelite-specific
- * definitions, and add the Anatop definition.
- * Inspired by the Linux Kernel 3.13.6 i.MX6 device tree file.
- */
-
-#include "imx6q-pinfunc.h"
-#include <imx6qdl-clock.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/memreserve/ 0x10000000 0x00001000;
-
-/ {
- compatible = "freescale,imx6";
- model = "imx6q";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- gpio5 = &gpio6;
- gpio6 = &gpio7;
- ipu0 = &ipu1;
- ipu1 = &ipu2;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- spi0 = &ecspi1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- enable-method = "smp-imx";
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- enable-method = "smp-imx";
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <2>;
- enable-method = "smp-imx";
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <3>;
- enable-method = "smp-imx";
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ckil {
- compatible = "imx-ckil", "fixed-clock";
- clock-frequency = <32768>;
- };
-
- ckih1 {
- compatible = "imx-ckih1", "fixed-clock";
- clock-frequency = <0>;
- };
-
- osc {
- compatible = "imx-osc", "fixed-clock";
- clock-frequency = <24000000>;
- };
- };
-
- scu { /* Snoop Control Unit */
- compatible = "arm,cortex-a9-scu";
- reg = <0x00a00000 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- intc: gic { /* Generic Interrupt Controller */
- compatible = "arm,cortex-a9-gic";
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- twd-timer { /* Local Timer */
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x00a00600 0x20>; /* Local timer registers */
- ref-counter-freq = <24000000>; /* Reference counter frequency */
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_EDGE_RISING)>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- ocram: sram@904000 {
- compatible = "mmio-sram";
- reg = <0x00904000 0x3C000>;
- clocks = <&clks IMX6QDL_CLK_OCRAM>;
- };
-
- aips-bus@2000000 { /* AIPS1 */
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x02000000 0x100000>;
- ranges;
-
- gpio1: gpio@209c000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x0209c000 0x4000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio2: gpio@20a0000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020a0000 0x4000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio3: gpio@20a4000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020a4000 0x4000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio4: gpio@20a8000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020a8000 0x4000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio5: gpio@20ac000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020ac000 0x4000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio6: gpio@20b0000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020b0000 0x4000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- gpio7: gpio@20b4000 {
- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020b4000 0x4000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- anatop: anatop@20c8000 {
- compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
- reg = <0x020c8000 0x1000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpc@20dc000 {
- compatible = "fsl,imx6q-gpc";
- reg = <0x020dc000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&intc>;
- //pu-supply = <&reg_pu>;
- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
- <&clks IMX6QDL_CLK_GPU3D_SHADER>,
- <&clks IMX6QDL_CLK_GPU2D_CORE>,
- <&clks IMX6QDL_CLK_GPU2D_AXI>,
- <&clks IMX6QDL_CLK_OPENVG_AXI>,
- <&clks IMX6QDL_CLK_VPU_AXI>;
- #power-domain-cells = <1>;
- };
-
- clks: ccm@20c4000 {
- compatible = "fsl,imx6q-ccm";
- reg = <0x020c4000 0x4000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- #clock-cells = <1>;
- };
-
- src: src@20d8000 {
- compatible = "fsl,imx6q-src", "fsl,imx51-src";
- reg = <0x020d8000 0x4000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- #reset-cells = <1>;
- };
-
- vdoa@21e4000 {
- compatible = "fsl,imx6q-vdoa";
- reg = <0x021e4000 0x4000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_VDOA>;
- iram = <&ocram>;
- };
-
- iomuxc: iomuxc@20e0000 {
- compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
- reg = <0x020e0000 0x4000>;
-
- enet {
- pinctrl_enet_1: enetgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- >;
- };
-
- pinctrl_enet_2: enetgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- >;
- };
-
- pinctrl_enet_3: enetgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- >;
- };
-
- pinctrl_enet_4: enetgrp-4 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- >;
- };
- };
-
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- >;
- };
- };
-
- usdhc1 {
- pinctrl_usdhc1_1: usdhc1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
- MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
- MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
- MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc1_2: usdhc1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- >;
- };
- };
-
- usdhc2 {
- pinctrl_usdhc2_1: usdhc2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2_2: usdhc2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
- };
-
- usdhc3 {
- pinctrl_usdhc3_1: usdhc3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
- >;
- };
-
- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
- >;
- };
-
- pinctrl_usdhc3_2: usdhc3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
- };
-
- usdhc4 {
- pinctrl_usdhc4_1: usdhc4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc4_2: usdhc4grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
- >;
- };
- };
-
- i2c1 {
- pinctrl_i2c1_1: i2c1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c1_2: i2c1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
- >;
- };
- };
-
- i2c2 {
- pinctrl_i2c2_1: i2c2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2_2: i2c2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2_3: i2c2grp-3 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
- };
-
- i2c3 {
- pinctrl_i2c3_1: i2c3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_2: i2c3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_3: i2c3grp-3 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_4: i2c3grp-4 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
- };
-
- pwm4 {
- pinctrl_pwm4: pwm4grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
- >;
- };
- };
- };
-
- ldb: ldb@20e0000 {
- compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
- reg = <0x020e0000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_LDB_DI0>,
- <&clks IMX6QDL_CLK_LDB_DI1>,
- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>,
- <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
- <&clks IMX6QDL_CLK_LVDS1_SEL>,
- <&clks IMX6QDL_CLK_LVDS2_SEL>,
- <&clks IMX6QDL_CLK_LVDS1_GATE>,
- <&clks IMX6QDL_CLK_LVDS2_GATE>;
- clock-names = "ldb_di0", "ldb_di1",
- "ipu1_di0_sel", "ipu1_di1_sel",
- "ipu2_di0_sel", "ipu2_di1_sel",
- "di0_div_3_5", "di1_div_3_5",
- "di0_div_7", "di1_div_7",
- "di0_div_sel", "di1_div_sel";
- status = "disabled";
- };
-
- spba-bus@2000000 {
- #address-cells = <1>;
- #size-cells = <1>;
-
- ecspi1: ecspi@2008000 {
- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
- reg = <0x02008000 0x4000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_ECSPI1>,
- <&clks IMX6QDL_CLK_ECSPI1>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi2: ecspi@200c000 {
- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
- reg = <0x0200c000 0x4000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_ECSPI2>,
- <&clks IMX6QDL_CLK_ECSPI2>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi3: ecspi@2010000 {
- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
- reg = <0x02010000 0x4000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_ECSPI3>,
- <&clks IMX6QDL_CLK_ECSPI3>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi4: ecspi@2014000 {
- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
- reg = <0x02014000 0x4000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_ECSPI4>,
- <&clks IMX6QDL_CLK_ECSPI4>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi5: ecspi@2018000 {
- compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
- reg = <0x02018000 0x4000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6Q_CLK_ECSPI5>,
- <&clks IMX6Q_CLK_ECSPI5>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- pwm4: pwm@208c000 {
- #pwm-cells = <2>;
- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
- reg = <0x0208c000 0x4000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_IPG>,
- <&clks IMX6QDL_CLK_PWM4>;
- clock-names = "ipg", "per";
- };
- };
-
- fec: ethernet@2188000 {
- compatible = "fsl,imx6q-fec";
- reg = <0x02188000 0x4000>;
- /* interrupts-extended = */
- /* <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, */
- /* <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; */
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp";
- status = "disabled";
- };
-
- usdhc1: usdhc@2190000 {
- compatible = "fsl,imx6q-usdhc";
- reg = <0x02190000 0x4000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_USDHC1>,
- <&clks IMX6QDL_CLK_USDHC1>,
- <&clks IMX6QDL_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc2: usdhc@2194000 {
- compatible = "fsl,imx6q-usdhc";
- reg = <0x02194000 0x4000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_USDHC2>,
- <&clks IMX6QDL_CLK_USDHC2>,
- <&clks IMX6QDL_CLK_USDHC2>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc3: usdhc@2198000 {
- compatible = "fsl,imx6q-usdhc";
- reg = <0x02198000 0x4000>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_USDHC3>,
- <&clks IMX6QDL_CLK_USDHC3>,
- <&clks IMX6QDL_CLK_USDHC3>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc4: usdhc@219c000 {
- compatible = "fsl,imx6q-usdhc";
- reg = <0x0219c000 0x4000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_USDHC4>,
- <&clks IMX6QDL_CLK_USDHC4>,
- <&clks IMX6QDL_CLK_USDHC4>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- i2c1: i2c@21a0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
- reg = <0x021a0000 0x4000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_I2C1>;
- status = "disabled";
- };
-
- i2c2: i2c@21a4000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
- reg = <0x021a4000 0x4000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_I2C2>;
- status = "disabled";
- };
-
- i2c3: i2c@21a8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
- reg = <0x021a8000 0x4000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_I2C3>;
- status = "disabled";
- };
-
- SERIAL1: uart@2020000 {
- compatible = "freescale,imx-uart";
- reg = <0x02020000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_UART_IPG>,
- <&clks IMX6QDL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- clock-frequency = <80000000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- SERIAL2: uart@21e8000 {
- compatible = "freescale,imx-uart";
- reg = <0x021e8000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_UART_IPG>,
- <&clks IMX6QDL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- clock-frequency = <80000000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- SERIAL3: uart@21ec000 {
- compatible = "freescale,imx-uart";
- reg = <0x021ec000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_UART_IPG>,
- <&clks IMX6QDL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- clock-frequency = <80000000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- SERIAL4: uart@21f0000 {
- compatible = "freescale,imx-uart";
- reg = <0x021f0000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_UART_IPG>,
- <&clks IMX6QDL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- clock-frequency = <80000000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- SERIAL5: uart@21f4000 {
- compatible = "freescale,imx-uart";
- reg = <0x021f4000 0x4000>;
- clocks = <&clks IMX6QDL_CLK_UART_IPG>,
- <&clks IMX6QDL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- clock-frequency = <80000000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- epit@20d0000 {
- compatible = "freescale,epit-timer";
- reg = <0x020d0000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <0>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- epit@20d4000 {
- compatible = "freescale,epit-timer";
- reg = <0x020d4000 0x4000>;
- clock-frequency = <38999040>;
- timer_num = <1>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpt@2098000 {
- compatible = "freescale,gpt-timer";
- reg = <0x02098000 0x4000>;
- clock-frequency = <32000>;
- timer_num = <2>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- ipu1: ipu@2400000 {
- compatible = "fsl,imx6q-ipu";
- reg = <0x02400000 0x400000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_IPU1>,
- <&clks IMX6QDL_CLK_IPU1_DI0>,
- <&clks IMX6QDL_CLK_IPU1_DI1>,
- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI0>,
- <&clks IMX6QDL_CLK_LDB_DI1>;
- clock-names = "bus", "di0", "di1",
- "di0_sel", "di1_sel",
- "ldb_di0", "ldb_di1";
- resets = <&src 2>;
- bypass_reset = <0>;
- };
-
- ipu2: ipu@2800000 {
- compatible = "fsl,imx6q-ipu";
- reg = <0x02800000 0x400000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_IPU2>,
- <&clks IMX6QDL_CLK_IPU2_DI0>,
- <&clks IMX6QDL_CLK_IPU2_DI1>,
- <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI0>,
- <&clks IMX6QDL_CLK_LDB_DI1>;
- clock-names = "bus", "di0", "di1",
- "di0_sel", "di1_sel",
- "ldb_di0", "ldb_di1";
- resets = <&src 4>;
- bypass_reset = <0>;
- };
-
- hdmi_core: hdmi_core@120000 {
- compatible = "fsl,imx6q-hdmi-core";
- reg = <0x00120000 0x9000>;
- clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
- <&clks IMX6QDL_CLK_HDMI_ISFR>;
- clock-names = "hdmi_iahb", "hdmi_isfr";
- status = "disabled";
- };
- hdmi_video: hdmi_video@20e0000 {
- compatible = "fsl,imx6q-hdmi-video";
- reg = <0x020e0000 0x1000>;
- interrupts = <0 115 0x04>;
- clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
- <&clks IMX6QDL_CLK_HDMI_ISFR>;
- clock-names = "hdmi_iahb", "hdmi_isfr";
- status = "disabled";
- };
-
- mxcfb1: fb@0 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- mxcfb2: fb@1 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "hdmi";
- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-
- backlight_lvds {
- compatible = "pwm-backlight";
- pwms = <&pwm4 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
- /* power-supply = <&reg_3p3v>; */
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/freescale/objects.mk b/arch/arm/dts/freescale/objects.mk
deleted file mode 100644
index 5b65b631..00000000
--- a/arch/arm/dts/freescale/objects.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-#/**
-# Copyright (c) 2014 Jean-Christophe Dubois.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Jean-Christophe Dubois (j...@tribudubois.net)
-# @author Anup Patel (an...@brainfault.org)
-# @brief list of freescale DTBs.
-# */
-
-arch-dtbs-$(CONFIG_ARMV7A)+=freescale/imx6dl-sabrelite.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=freescale/sabrelite/one_guest_sabrelite.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=freescale/sabrelite/two_guest_sabrelite.dtb
-arch-dtbs-$(CONFIG_ARMV6)+=freescale/imx31-kzm.dtb
-arch-dtbs-$(CONFIG_ARMV5)+=freescale/imx25-pdk.dtb
diff --git a/arch/arm/dts/freescale/sabrelite/one_guest_sabrelite.dts b/arch/arm/dts/freescale/sabrelite/one_guest_sabrelite.dts
deleted file mode 100644
index c4343b66..00000000
--- a/arch/arm/dts/freescale/sabrelite/one_guest_sabrelite.dts
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * Originally from Jean-Christophe Dubois, and modified by
- * Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * to split device tree files between i.MX6-specific and Sabrelite-specific
- * definitions.
- */
-
-/dts-v1/;
-
-#include "sabrelite.dtsi"
-
-/ {
- chosen {
- console = &SERIAL2;
- bootcmd =
- "backlight brightness backlight_lvds 6",
- "fb logo fb0",
-
- /* Mount SD device */
- "vfs mount mmc0p0 / 2",
-
- /* Load guest0 device tree from file */
- "vfs fdt_load /guests guest0 /images/arm32/sabrelite.dtb mem0,physical_size,physsize,0x30000000 net0,switch,string,br0",
-
- /* Create guest0 */
- "guest create guest0",
-
- /* Load guest0 images */
- "vfs guest_load_list guest0 /images/arm32/sabrelite/nor_flash.list",
-
- /* Print banner */
- "vfs cat /system/banner.txt",
-
- /* Umount the SD/MMC card */
- "vfs umount /";
- };
-};
diff --git a/arch/arm/dts/freescale/sabrelite/sabrelite.dtsi b/arch/arm/dts/freescale/sabrelite/sabrelite.dtsi
deleted file mode 100644
index 8f2b0c5a..00000000
--- a/arch/arm/dts/freescale/sabrelite/sabrelite.dtsi
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * @file sabrelite.dtsi
- * @author Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * @brief Sabrelite-specific device tree definitions.
- */
-
-#include "../imx6q.dtsi"
-
-/ {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- model = "Freescale i.MX6 Quad SABRE Lite Board";
- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
-
- memory {
- device_type = "memory";
- reg = <0x10000000 0x40000000>; /* 1 GB */
- };
-};
-
-&SERIAL1 {
- status = "okay";
-};
-
-&SERIAL2 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio3 {
- status = "okay";
-};
-
-&gpio7 {
- status = "okay";
-};
-
-&ecspi1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fsl,spi-num-chipselects = <1>;
- cs-gpios = <&gpio3 19 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1_1>;
- status = "okay";
-
- flash: m25p80@0 {
- compatible = "sst25vf016b";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
- cd-gpios = <&gpio7 0 0>;
- wp-gpios = <&gpio7 1 0>;
- /* vmmc-supply = <&reg_3p3v>; */
- status = "okay";
-};
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4>;
- status = "okay";
-};
-
-&ldb {
- ipu_id = <0>;
- disp_id = <0>;
- ext_ref = <1>;
- mode = "sin0";
- sec_ipu_id = <1>;
- sec_disp_id = <1>;
- status = "okay";
-};
-
-&hdmi_core {
- status = "okay";
- ipu_id = <1>;
- disp_id = <0>;
-};
-
-&hdmi_video {
- status = "okay";
- fsl,phy_reg_vlev = <0x0294>;
- fsl,phy_reg_cksymtx = <0x800d>;
-};
-
-&mxcfb1 {
- status = "okay";
- interface_pix_fmt = "RGB666";
- default_bpp = <16>;
- mode_str = "LDB-XGA";
-};
-
-&mxcfb2 {
- status = "okay";
- interface_pix_fmt = "RGB24";
- default_bpp = <16>;
- mode_str = "";
-};
-
-&i2c1 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_1>;
-};
-
-&i2c2 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_2>;
- hdmi: edid@50 {
- compatible = "fsl,imx6-hdmi-i2c";
- reg = <0x50>;
- };
-};
-
-&i2c3 {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_3>;
-
- touchscreen: egalax_ts@4 {
- compatible = "eeti,egalax_ts";
- reg = <0x04>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
- wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
-};
-
-&fec {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_4>;
- phy-mode = "rgmii";
- //phy-reset-gpios = <&gpio1 27 0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- #address-cells = <0>;
- #size-cells = <1>;
- phy_int {
- reg = <0x6>;
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_1>;
-
- imx6q-nitrogen6x {
- pinctrl_hog_1: hoggrp-1 {
- fsl,pins = <
- /* Power Button */
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
- /* Menu Button */
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
- /* Home Button */
- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
- /* Back Button */
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- /* Volume Up Button */
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
- /* Volume Down Button */
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 /* ethernet phy reset */
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* Spare */
- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* uSDHC4 CD */
- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* Spare */
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* Spare */
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */
- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */
- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */
- MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* ov5642 mclk */
- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 /* ov5642 Power Down */
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* ov5642 Reset */
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 /* wl12xx_wl_irq */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 /* wl12xx_bt_en */
- /*MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0*/ /* TiWi slow clock */
- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* ISL1208 interrupt */
-
- >;
- };
- };
-
-};
diff --git a/arch/arm/dts/freescale/sabrelite/two_guest_sabrelite.dts b/arch/arm/dts/freescale/sabrelite/two_guest_sabrelite.dts
deleted file mode 100644
index 87f74844..00000000
--- a/arch/arm/dts/freescale/sabrelite/two_guest_sabrelite.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2014 Institut de Recherche Technologique SystemX and OpenWide.
- * Originally from Jean-Christophe Dubois, and modified by
- * Jimmy Durand Wesolowski (jimmy.duran...@openwide.fr)
- * to split device tree files between i.MX6-specific and Sabrelite-specific
- * definitions.
- */
-
-/dts-v1/;
-
-#include "sabrelite.dtsi"
-
-/ {
- chosen {
- console = &SERIAL2;
- bootcmd =
- "backlight brightness backlight_lvds 6",
- "fb logo fb0",
-
- /* Mount SD device */
- "vfs mount mmc0p0 / 2",
-
- /* Load guest0 device tree from file */
- "vfs fdt_load /guests guest0 /images/arm32/sabrelite.dtb mem0,physical_size,physsize,0x06000000 net0,switch,string,br0",
- /* Create guest0 */
- "guest create guest0",
- /* Load guest0 images */
- "vfs guest_load_list guest0 /images/arm32/sabrelite/nor_flash.list",
-
- /* Load guest1 device tree from file */
- "vfs fdt_load /guests guest1 /images/arm32/sabrelite.dtb mem0,physical_size,physsize,0x06000000 net0,switch,string,br0",
- /* Create guest1 */
- "guest create guest1",
- /* Load guest1 images */
- "vfs guest_load_list guest1 /images/arm32/sabrelite/nor_flash.list",
-
- /* Print banner */
- "vfs cat /system/banner.txt",
-
- /* Umount the SD/MMC card */
- "vfs umount /",
-
- /* Kick the guests */
- "guest kick guest0",
- "guest kick guest1";
- };
-};
diff --git a/arch/arm/dts/samsung/exynos4210-nuri.dts b/arch/arm/dts/samsung/exynos4210-nuri.dts
deleted file mode 100644
index 1f97bc7e..00000000
--- a/arch/arm/dts/samsung/exynos4210-nuri.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-
-/dts-v1/;
-
-#include "./exynos4210.dtsi"
-
-/ {
- model = "nuri";
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x40000000 0x10000000>; /* 256 MB */
- };
-
- chosen {
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
-
diff --git a/arch/arm/dts/samsung/exynos4210-smdkc210.dts b/arch/arm/dts/samsung/exynos4210-smdkc210.dts
deleted file mode 100644
index df9ff579..00000000
--- a/arch/arm/dts/samsung/exynos4210-smdkc210.dts
+++ /dev/null
@@ -1,37 +0,0 @@
-
-/dts-v1/;
-
-#include "./exynos4210.dtsi"
-
-/ {
- model = "smdkc210";
-
- chosen {
- console = &SERIAL0;
- rtcdev = &RTC0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x40000000 0x10000000>; /* 256 MB */
- };
-
- chosen {
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-
- sfrregion {
- eth@5000000 {
- compatible = "smc911x";
- reg = <0x05000000 0x1000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- };
- };
-};
diff --git a/arch/arm/dts/samsung/exynos4210.dtsi b/arch/arm/dts/samsung/exynos4210.dtsi
deleted file mode 100644
index ca95a5ae..00000000
--- a/arch/arm/dts/samsung/exynos4210.dtsi
+++ /dev/null
@@ -1,119 +0,0 @@
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "exynos4210";
- compatible = "samsung,exynos4";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
-
- cpu@1 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <1>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
- };
-
- scu { /* Snoop Control Unit */
- compatible = "arm,cortex-a9-scu";
- reg = <0x10500000 0x1000>;
- };
-
- pmu { /* Performance Monitorig Unit */
- compatible = "arm,a9mpcore-priv";
- reg = <0x10020000 0x10000>;
- };
-
- gic: gic {
- compatible = "arm,cortex-a9-gic";
- reg = <0x10490000 0x1000>,
- <0x10480000 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- mct {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>,
- <GIC_SPI 42 IRQ_TYPE_NONE>,
- <GIC_SPI 48 IRQ_TYPE_NONE>;
- };
-
- sfrregion {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- RTC0: s3c-rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_NONE>,
- <GIC_SPI 45 IRQ_TYPE_NONE>;
- };
-
- SERIAL0: uart@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- clock-frequency = <100000000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
- };
-
- SERIAL1: uart@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- clock-frequency = <100000000>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- };
-
- SERIAL2: uart@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- clock-frequency = <100000000>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_NONE>;
- };
-
- SERIAL3: uart@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- clock-frequency = <100000000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_NONE>;
- };
-
- SERIAL4: uart@13840000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13840000 0x100>;
- clock-frequency = <100000000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_NONE>;
- };
-
- timer@139d0000 {
- compatible = "samsung,exynos4210-PWMtimer";
- reg = <0x139d0000 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>,
- <GIC_SPI 38 IRQ_TYPE_NONE>,
- <GIC_SPI 39 IRQ_TYPE_NONE>,
- <GIC_SPI 40 IRQ_TYPE_NONE>,
- <GIC_SPI 41 IRQ_TYPE_NONE>;
- };
- };
-};
diff --git a/arch/arm/dts/samsung/exynos4212.dtsi b/arch/arm/dts/samsung/exynos4212.dtsi
deleted file mode 100644
index a45b6b19..00000000
--- a/arch/arm/dts/samsung/exynos4212.dtsi
+++ /dev/null
@@ -1,113 +0,0 @@
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "exynos4212";
- compatible = "samsung,exynos4";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
-
- cpu@1 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
- };
-
- scu { /* Snoop Control Unit */
- compatible = "arm,cortex-a9-scu";
- reg = <0x10500000 0x1000>;
- };
-
- pmu { /* Performance Monitorig Unit */
- compatible = "arm,a9mpcore-priv";
- reg = <0x10020000 0x10000>;
- };
-
- gic: gic {
- compatible = "arm,cortex-a9-gic";
- reg = <0x10490000 0x1000>,
- <0x10480000 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- mct {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>,
- <GIC_SPI 42 IRQ_TYPE_NONE>;
- };
-
- sfrregion {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- RTC0: s3c-rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_NONE>,
- <GIC_SPI 45 IRQ_TYPE_NONE>;
- };
-
- SERIAL0: exynos4210-uart@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
- };
-
- SERIAL1: exynos4210-uart@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- };
-
- SERIAL2: exynos4210-uart@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_NONE>;
- };
-
- SERIAL3: exynos4210-uart@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_NONE>;
- };
-
- SERIAL4: exynos4210-uart@13840000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13840000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_NONE>;
- };
-
- timer@139d0000 {
- compatible = "samsung,exynos4210-PWMtimer";
- reg = <0x139d0000 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>,
- <GIC_SPI 38 IRQ_TYPE_NONE>,
- <GIC_SPI 39 IRQ_TYPE_NONE>,
- <GIC_SPI 40 IRQ_TYPE_NONE>,
- <GIC_SPI 41 IRQ_TYPE_NONE>;
- };
- };
-};
diff --git a/arch/arm/dts/samsung/exynos4412-odroidx.dts b/arch/arm/dts/samsung/exynos4412-odroidx.dts
deleted file mode 100644
index 9e99c74e..00000000
--- a/arch/arm/dts/samsung/exynos4412-odroidx.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-
-/dts-v1/;
-
-#include "./exynos4412.dtsi"
-
-/ {
- model = "odroidx";
-
- chosen {
- console = &SERIAL1;
- rtcdev = &RTC0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x40000000 0x40000000>; /* 1 GB */
- };
-
- chosen {
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
-
diff --git a/arch/arm/dts/samsung/exynos4412.dtsi b/arch/arm/dts/samsung/exynos4412.dtsi
deleted file mode 100644
index 8516d3f6..00000000
--- a/arch/arm/dts/samsung/exynos4412.dtsi
+++ /dev/null
@@ -1,129 +0,0 @@
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "exynos4412";
- compatible = "samsung,exynos4";
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <0>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
-
- cpu@1 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <1>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
-
- cpu@2 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <2>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
-
- cpu@3 {
- device_type = "cpu";
- model = "Cortex-A9";
- reg = <3>;
- enable-method = "smp-scu";
- cpu-release-addr = <0x10020814>;
- };
- };
-
- scu { /* Snoop Control Unit */
- compatible = "arm,cortex-a9-scu";
- reg = <0x10500000 0x1000>;
- };
-
- pmu { /* Performance Monitorig Unit */
- compatible = "arm,a9mpcore-priv";
- reg = <0x10020000 0x10000>;
- };
-
- gic: gic {
- compatible = "arm,cortex-a9-gic";
- reg = <0x10490000 0x1000>,
- <0x10480000 0x100>;
- #interrupt-cells = <3>;
- interrupt-controller;
- };
-
- mct {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x1000>;
- clock-frequency = <24000000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>,
- <GIC_SPI 42 IRQ_TYPE_NONE>;
- };
-
- sfrregion {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- RTC0: s3c-rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_NONE>,
- <GIC_SPI 45 IRQ_TYPE_NONE>;
- };
-
- SERIAL0: exynos4210-uart@13800000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13800000 0x100>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
- };
-
- SERIAL1: exynos4210-uart@13810000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13810000 0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
- };
-
- SERIAL2: exynos4210-uart@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_NONE>;
- };
-
- SERIAL3: exynos4210-uart@13830000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13830000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_NONE>;
- };
-
- SERIAL4: exynos4210-uart@13840000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13840000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_NONE>;
- };
-
- timer@139d0000 {
- compatible = "samsung,exynos4210-PWMtimer";
- reg = <0x139d0000 0x1000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>,
- <GIC_SPI 38 IRQ_TYPE_NONE>,
- <GIC_SPI 39 IRQ_TYPE_NONE>,
- <GIC_SPI 40 IRQ_TYPE_NONE>,
- <GIC_SPI 41 IRQ_TYPE_NONE>;
- };
- };
-};
diff --git a/arch/arm/dts/samsung/objects.mk b/arch/arm/dts/samsung/objects.mk
deleted file mode 100644
index 25d4d902..00000000
--- a/arch/arm/dts/samsung/objects.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#/**
-# Copyright (c) 2015 Anup Patel.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Anup Patel (an...@brainfault.org)
-# @brief list of Samsung DTBs.
-# */
-
-arch-dtbs-$(CONFIG_ARMV7A)+=samsung/exynos4210-nuri.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=samsung/exynos4412-odroidx.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=samsung/exynos4210-smdkc210.dtb
diff --git a/arch/arm/dts/ti/objects.mk b/arch/arm/dts/ti/objects.mk
deleted file mode 100644
index 69a521f1..00000000
--- a/arch/arm/dts/ti/objects.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#/**
-# Copyright (c) 2015 Anup Patel.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# @file objects.mk
-# @author Anup Patel (an...@brainfault.org)
-# @brief list of TI DTBs.
-# */
-
-arch-dtbs-$(CONFIG_ARMV7A)+=ti/omap3-beagle.dtb
-arch-dtbs-$(CONFIG_ARMV7A)+=ti/omap3-beagle-xm.dtb
diff --git a/arch/arm/dts/ti/omap3-beagle-xm.dts b/arch/arm/dts/ti/omap3-beagle-xm.dts
deleted file mode 100644
index 21014599..00000000
--- a/arch/arm/dts/ti/omap3-beagle-xm.dts
+++ /dev/null
@@ -1,26 +0,0 @@
-
-/dts-v1/;
-
-/include/ "./omap3.dtsi"
-
-/ {
- model = "BeagleBoard-xM";
- compatible = "ti,omap3";
-
- memory {
- device_type = "memory";
- reg = <0x88000000 0x10000000>; /* 256 MB */
- };
-
- chosen {
- console = &SERIAL0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
diff --git a/arch/arm/dts/ti/omap3-beagle.dts b/arch/arm/dts/ti/omap3-beagle.dts
deleted file mode 100644
index 2e530c2d..00000000
--- a/arch/arm/dts/ti/omap3-beagle.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/dts-v1/;
-
-/include/ "./omap3.dtsi"
-
-/ {
- model = "BeagleBoard";
- compatible = "ti,omap3";
-
- chosen {
- console = &SERIAL0;
- bootcmd = /* Mount initrd device */
- "vfs mount initrd /",
-
- /* Run boot script */
- "vfs run /boot.xscript",
-
- /* Print banner */
- "vfs cat /system/banner.txt";
- };
-};
diff --git a/arch/arm/dts/ti/omap3.dtsi b/arch/arm/dts/ti/omap3.dtsi
deleted file mode 100644
index cdd42f5d..00000000
--- a/arch/arm/dts/ti/omap3.dtsi
+++ /dev/null
@@ -1,76 +0,0 @@
-
-/ {
- model = "OMAP3xxx";
- compatible = "ti,omap3430", "ti,omap3";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen { };
- aliases { };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "Cortex-A8";
- reg = <0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-
- /*
- * XXX: Use a flat representation of the OMAP3 interconnect.
- * The real OMAP interconnect network is quite complex.
- * Since that will not bring real advantage to represent that in DT for
- * the moment, just use a fake OCP bus entry to represent the whole bus
- * hierarchy.
- */
- ocp {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-
- counter32k: counter@48320000 {
- compatible = "ti,omap-counter32k";
- reg = <0x48320000 0x20>;
- ti,hwmods = "counter_32k";
- };
-
- intc: interrupt-controller@48200000 {
- compatible = "ti,omap3-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x48200000 0x1000>;
- };
-
- timer1: timer@48318000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48318000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- };
-
- timer2: timer@49032000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49032000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
- };
-
- SERIAL0: uart@49020000 {
- compatible = "st16654";
- reg = <0x49020000 0x1000>;
- clock-frequency = <48000000>;
- reg-shift = <2>;
- interrupts = <74>;
- };
- };
-};
--
2.25.1

[Anup Patel]

We have tested busybox-1.32.0 and linux-5.4.68 on ARM and RISC-V so
let's make it default in various build scripts.

Signed-off-by: Anup Patel <an...@brainfault.org>
---

tests/common/scripts/build-arm-images.sh | 6 +++---
tests/common/scripts/build-images.sh | 4 ++--
tests/common/scripts/build-riscv-images.sh | 24 +++++++---------------
3 files changed, 12 insertions(+), 22 deletions(-)

diff --git a/tests/common/scripts/build-arm-images.sh b/tests/common/scripts/build-arm-images.sh
index 4efe1550..9d0dfa9b 100755
--- a/tests/common/scripts/build-arm-images.sh
+++ b/tests/common/scripts/build-arm-images.sh
@@ -42,8 +42,8 @@ BUILD_XVISOR_ONLY="no"
BUILD_XVISOR_OUTPUT_PATH=`pwd`/build/xvisor
BUILD_TARBALL_PATH=`pwd`/tarball
BUILD_GUEST_OUTPUT_PATH=`pwd`/build/guest
-BUILD_LINUX_VERSION="5.4.6"
-BUILD_BUSYBOX_VERSION="1.31.1"
+BUILD_LINUX_VERSION="5.4.68"
+BUILD_BUSYBOX_VERSION="1.32.0"
BUILD_PRINT_CONFIG_ONLY="no"

# Derived options
@@ -155,7 +155,7 @@ v8)
fi
if [ "${BUILD_GUEST_TYPE}" != "virt-v8" ]; then
BUILD_LINUX_ARCH="arm"
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabi-
+ BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
fi
;;
diff --git a/tests/common/scripts/build-images.sh b/tests/common/scripts/build-images.sh
index 10adb51b..7f74074e 100755
--- a/tests/common/scripts/build-images.sh
+++ b/tests/common/scripts/build-images.sh
@@ -22,8 +22,8 @@ BUILD_OUTPUT_PATH=`pwd`/build
BUILD_INSTALL_PATH=`pwd`/install
BUILD_XVISOR_SOURCE_PATH=`pwd`
BUILD_TARBALL_PATH=`pwd`/tarball
-BUILD_LINUX_VERSION="5.4.6"
-BUILD_BUSYBOX_VERSION="1.31.1"
+BUILD_LINUX_VERSION="5.4.68"
+BUILD_BUSYBOX_VERSION="1.32.0"

while getopts "d:hj:l:i:o:p:" o; do
case "${o}" in
diff --git a/tests/common/scripts/build-riscv-images.sh b/tests/common/scripts/build-riscv-images.sh
index 5131eea4..000494ae 100755
--- a/tests/common/scripts/build-riscv-images.sh
+++ b/tests/common/scripts/build-riscv-images.sh
@@ -41,8 +41,8 @@ BUILD_XVISOR_ONLY="no"
BUILD_XVISOR_OUTPUT_PATH=`pwd`/build/xvisor
BUILD_TARBALL_PATH=`pwd`/tarball
BUILD_GUEST_OUTPUT_PATH=`pwd`/build/guest
-BUILD_LINUX_VERSION="5.4.6"
-BUILD_BUSYBOX_VERSION="1.31.1"
+BUILD_LINUX_VERSION="5.4.68"
+BUILD_BUSYBOX_VERSION="1.32.0"
BUILD_PRINT_CONFIG_ONLY="no"

# Derived options
@@ -138,29 +138,19 @@ fi

case "${BUILD_RISCV_XLEN}" in
32b)
- BUILD_XVISOR_ARCH="riscv"
- BUILD_XVISOR_CROSS_COMPILE_PREFERRED=riscv32-unknown-linux-gnu-
- BUILD_LINUX_ARCH="riscv"
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=riscv32-unknown-linux-gnu-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=riscv32-unknown-linux-gnu-
;;
64b)
- BUILD_XVISOR_ARCH="riscv"
- BUILD_XVISOR_CROSS_COMPILE_PREFERRED=riscv64-linux-
- BUILD_LINUX_ARCH="riscv"
- if [ "${BUILD_GUEST_TYPE}" == "virt32" ]; then
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=riscv32-unknown-linux-gnu-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=riscv32-unknown-linux-gnu-
- else
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=riscv64-linux-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=riscv64-linux-
- fi
;;
*)
echo "Invalid RISC-V XLEN"
usage
;;
esac
+BUILD_XVISOR_ARCH="riscv"
+BUILD_XVISOR_CROSS_COMPILE_PREFERRED=riscv64-unknown-linux-gnu-
+BUILD_LINUX_ARCH="riscv"
+BUILD_LINUX_CROSS_COMPILE_PREFERRED=riscv64-unknown-linux-gnu-
+BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=riscv64-unknown-linux-gnu-

if [ -z "${BUILD_XVISOR_CROSS_COMPILE}" ]; then
BUILD_XVISOR_CROSS_COMPILE=${BUILD_XVISOR_CROSS_COMPILE_PREFERRED}
--
2.25.1

[Anup Patel]

We remove the guest types meant for ARM32 without virtualization port
because this port has been removed.

Signed-off-by: Anup Patel <an...@brainfault.org>
---

tests/arm32/README | 10 +-
tests/arm32/realview-eb-mpcore/README | 37 -
tests/arm32/realview-eb-mpcore/basic/Makefile | 57 -
tests/arm32/realview-eb-mpcore/basic/README | 70 -
.../realview-eb-mpcore/basic/arch_board.c | 524 ---
.../arm32/realview-eb-mpcore/basic/arch_smp.h | 30 -
.../arm32/realview-eb-mpcore/basic/arm_plat.h | 338 --
.../realview-eb-mpcore/basic/gic_config.h | 33 -
.../realview-eb-mpcore/basic/nor_flash.list | 1 -
tests/arm32/realview-eb-mpcore/linux/README | 101 -
tests/arm32/realview-eb-mpcore/linux/cmdlist | 4 -
.../linux/linux_extra.config | 3 -
.../realview-eb-mpcore/linux/nor_flash.list | 5 -
.../realview-eb-mpcore-guest.dts | 404 --
.../xscript/one_guest_ebmp.xscript | 8 -
.../xscript/two_guest_ebmp.xscript | 17 -
tests/arm32/realview-pb-a8/README | 40 -
tests/arm32/realview-pb-a8/atomthreads/README | 129 -
.../realview-pb-a8/atomthreads/nor_flash.list | 40 -
.../realview-pb-a8/atomthreads/qemu_test.tcl | 79 -
tests/arm32/realview-pb-a8/basic/Makefile | 55 -
tests/arm32/realview-pb-a8/basic/README | 70 -
tests/arm32/realview-pb-a8/basic/arch_board.c | 523 ---
tests/arm32/realview-pb-a8/basic/arm_plat.h | 330 --
tests/arm32/realview-pb-a8/basic/emulate.sh | 53 -
tests/arm32/realview-pb-a8/basic/gic_config.h | 33 -
.../arm32/realview-pb-a8/basic/nor_flash.list | 1 -
.../arm32/realview-pb-a8/basic/qemu_test.tcl | 244 -
tests/arm32/realview-pb-a8/linux/README | 101 -
tests/arm32/realview-pb-a8/linux/cmdlist | 4 -
.../realview-pb-a8/linux/linux_extra.config | 4 -
.../arm32/realview-pb-a8/linux/nor_flash.list | 5 -
.../realview-pb-a8/realview-pb-a8-guest.dts | 414 --
.../xscript/one_guest_pb-a8.xscript | 8 -
.../xscript/two_guest_pb-a8.xscript | 17 -
tests/arm32/sabrelite/basic/Makefile | 57 -
tests/arm32/sabrelite/basic/arch_board.c | 242 -
tests/arm32/sabrelite/basic/arch_smp.h | 30 -
tests/arm32/sabrelite/basic/arm_plat.h | 263 --
tests/arm32/sabrelite/basic/gic_config.h | 33 -
tests/arm32/sabrelite/linux/cmdlist | 4 -
.../sabrelite/linux/imx6q-nitrogen6x.dts | 81 -
tests/arm32/sabrelite/linux/imx6q.dtsi | 246 -
.../sabrelite/linux/imx6qdl-nitrogen6x.dtsi | 644 ---
tests/arm32/sabrelite/linux/imx6qdl.dtsi | 1884 --------
.../sabrelite/linux/linux-4.5.y_defconfig | 4077 -----------------
.../linux/linux-imx_3.10.17_defconfig | 3245 -------------
.../linux/linux-imx_3.14.28_defconfig | 3894 ----------------
tests/arm32/sabrelite/linux/nor_flash.list | 5 -
tests/arm32/sabrelite/linux/skeleton.dtsi | 13 -
tests/arm32/sabrelite/sabrelite.dts | 427 --
tests/arm32/versatilepb/README | 33 -
tests/arm32/versatilepb/basic/Makefile | 55 -
tests/arm32/versatilepb/basic/README | 70 -
tests/arm32/versatilepb/basic/arch_board.c | 266 --
tests/arm32/versatilepb/basic/arm_plat.h | 426 --
tests/arm32/versatilepb/basic/emulate.sh | 53 -
tests/arm32/versatilepb/basic/nor_flash.list | 1 -
tests/arm32/versatilepb/basic/qemu_test.tcl | 307 --
tests/arm32/versatilepb/linux/README | 101 -
tests/arm32/versatilepb/linux/cmdlist | 4 -
.../versatilepb/linux/linux_extra.config | 1 -
tests/arm32/versatilepb/linux/nor_flash.list | 5 -
tests/arm32/versatilepb/versatilepb-guest.dts | 358 --
.../xscript/one_guest_versatilepb.xscript | 8 -
.../xscript/two_guest_versatilepb.xscript | 17 -
tests/arm32/vexpress-a9/README | 37 -
tests/arm32/vexpress-a9/basic/Makefile | 56 -
tests/arm32/vexpress-a9/basic/README | 70 -
tests/arm32/vexpress-a9/basic/arch_board.c | 492 --
tests/arm32/vexpress-a9/basic/arch_smp.h | 30 -
tests/arm32/vexpress-a9/basic/arm_plat.h | 252 -
tests/arm32/vexpress-a9/basic/emulate.sh | 53 -
tests/arm32/vexpress-a9/basic/gic_config.h | 33 -
tests/arm32/vexpress-a9/basic/nor_flash.list | 1 -
tests/arm32/vexpress-a9/basic/qemu_test.tcl | 244 -
tests/arm32/vexpress-a9/freertos/Makefile | 229 -
tests/arm32/vexpress-a9/freertos/README | 174 -
.../arm32/vexpress-a9/freertos/arm_entry_v7.S | 301 --
tests/arm32/vexpress-a9/freertos/glue.c | 140 -
tests/arm32/vexpress-a9/freertos/main.c | 97 -
.../arm32/vexpress-a9/freertos/nor_flash.list | 1 -
.../freertos/patches/freertos-config.patch | 124 -
.../vexpress-a9/freertos/patches/ports.patch | 147 -
tests/arm32/vexpress-a9/freertos/stdio.h | 32 -
tests/arm32/vexpress-a9/freertos/string.h | 34 -
tests/arm32/vexpress-a9/linux/README | 101 -
tests/arm32/vexpress-a9/linux/cmdlist | 4 -
.../vexpress-a9/linux/linux_extra.config | 4 -
tests/arm32/vexpress-a9/linux/nor_flash.list | 5 -
tests/arm32/vexpress-a9/vexpress-a9-guest.dts | 413 --
.../xscript/one_guest_vexpress-a9.xscript | 8 -
.../xscript/two_guest_vexpress-a9.xscript | 17 -
tests/common/scripts/build-arm-images.sh | 133 +-
tests/common/scripts/build-images.sh | 22 -
95 files changed, 6 insertions(+), 23890 deletions(-)
delete mode 100644 tests/arm32/realview-eb-mpcore/README
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/Makefile
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/README
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/arch_board.c
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/arch_smp.h
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/arm_plat.h
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/gic_config.h
delete mode 100644 tests/arm32/realview-eb-mpcore/basic/nor_flash.list
delete mode 100644 tests/arm32/realview-eb-mpcore/linux/README
delete mode 100644 tests/arm32/realview-eb-mpcore/linux/cmdlist
delete mode 100644 tests/arm32/realview-eb-mpcore/linux/linux_extra.config
delete mode 100644 tests/arm32/realview-eb-mpcore/linux/nor_flash.list
delete mode 100644 tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts
delete mode 100644 tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript
delete mode 100644 tests/arm32/realview-eb-mpcore/xscript/two_guest_ebmp.xscript
delete mode 100644 tests/arm32/realview-pb-a8/README
delete mode 100644 tests/arm32/realview-pb-a8/atomthreads/README
delete mode 100644 tests/arm32/realview-pb-a8/atomthreads/nor_flash.list
delete mode 100755 tests/arm32/realview-pb-a8/atomthreads/qemu_test.tcl
delete mode 100644 tests/arm32/realview-pb-a8/basic/Makefile
delete mode 100644 tests/arm32/realview-pb-a8/basic/README
delete mode 100644 tests/arm32/realview-pb-a8/basic/arch_board.c
delete mode 100644 tests/arm32/realview-pb-a8/basic/arm_plat.h
delete mode 100755 tests/arm32/realview-pb-a8/basic/emulate.sh
delete mode 100644 tests/arm32/realview-pb-a8/basic/gic_config.h
delete mode 100644 tests/arm32/realview-pb-a8/basic/nor_flash.list
delete mode 100755 tests/arm32/realview-pb-a8/basic/qemu_test.tcl
delete mode 100644 tests/arm32/realview-pb-a8/linux/README
delete mode 100644 tests/arm32/realview-pb-a8/linux/cmdlist
delete mode 100644 tests/arm32/realview-pb-a8/linux/linux_extra.config
delete mode 100644 tests/arm32/realview-pb-a8/linux/nor_flash.list
delete mode 100644 tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts
delete mode 100644 tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript
delete mode 100644 tests/arm32/realview-pb-a8/xscript/two_guest_pb-a8.xscript
delete mode 100644 tests/arm32/sabrelite/basic/Makefile
delete mode 100644 tests/arm32/sabrelite/basic/arch_board.c
delete mode 100644 tests/arm32/sabrelite/basic/arch_smp.h
delete mode 100644 tests/arm32/sabrelite/basic/arm_plat.h
delete mode 100644 tests/arm32/sabrelite/basic/gic_config.h
delete mode 100644 tests/arm32/sabrelite/linux/cmdlist
delete mode 100644 tests/arm32/sabrelite/linux/imx6q-nitrogen6x.dts
delete mode 100644 tests/arm32/sabrelite/linux/imx6q.dtsi
delete mode 100644 tests/arm32/sabrelite/linux/imx6qdl-nitrogen6x.dtsi
delete mode 100644 tests/arm32/sabrelite/linux/imx6qdl.dtsi
delete mode 100644 tests/arm32/sabrelite/linux/linux-4.5.y_defconfig
delete mode 100644 tests/arm32/sabrelite/linux/linux-imx_3.10.17_defconfig
delete mode 100644 tests/arm32/sabrelite/linux/linux-imx_3.14.28_defconfig
delete mode 100644 tests/arm32/sabrelite/linux/nor_flash.list
delete mode 100644 tests/arm32/sabrelite/linux/skeleton.dtsi
delete mode 100644 tests/arm32/sabrelite/sabrelite.dts
delete mode 100644 tests/arm32/versatilepb/README
delete mode 100644 tests/arm32/versatilepb/basic/Makefile
delete mode 100644 tests/arm32/versatilepb/basic/README
delete mode 100644 tests/arm32/versatilepb/basic/arch_board.c
delete mode 100644 tests/arm32/versatilepb/basic/arm_plat.h
delete mode 100755 tests/arm32/versatilepb/basic/emulate.sh
delete mode 100644 tests/arm32/versatilepb/basic/nor_flash.list
delete mode 100755 tests/arm32/versatilepb/basic/qemu_test.tcl
delete mode 100644 tests/arm32/versatilepb/linux/README
delete mode 100644 tests/arm32/versatilepb/linux/cmdlist
delete mode 100644 tests/arm32/versatilepb/linux/linux_extra.config
delete mode 100644 tests/arm32/versatilepb/linux/nor_flash.list
delete mode 100644 tests/arm32/versatilepb/versatilepb-guest.dts
delete mode 100644 tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript
delete mode 100644 tests/arm32/versatilepb/xscript/two_guest_versatilepb.xscript
delete mode 100644 tests/arm32/vexpress-a9/README
delete mode 100644 tests/arm32/vexpress-a9/basic/Makefile
delete mode 100644 tests/arm32/vexpress-a9/basic/README
delete mode 100644 tests/arm32/vexpress-a9/basic/arch_board.c
delete mode 100644 tests/arm32/vexpress-a9/basic/arch_smp.h
delete mode 100644 tests/arm32/vexpress-a9/basic/arm_plat.h
delete mode 100755 tests/arm32/vexpress-a9/basic/emulate.sh
delete mode 100644 tests/arm32/vexpress-a9/basic/gic_config.h
delete mode 100644 tests/arm32/vexpress-a9/basic/nor_flash.list
delete mode 100755 tests/arm32/vexpress-a9/basic/qemu_test.tcl
delete mode 100644 tests/arm32/vexpress-a9/freertos/Makefile
delete mode 100644 tests/arm32/vexpress-a9/freertos/README
delete mode 100644 tests/arm32/vexpress-a9/freertos/arm_entry_v7.S
delete mode 100644 tests/arm32/vexpress-a9/freertos/glue.c
delete mode 100644 tests/arm32/vexpress-a9/freertos/main.c
delete mode 100644 tests/arm32/vexpress-a9/freertos/nor_flash.list
delete mode 100644 tests/arm32/vexpress-a9/freertos/patches/freertos-config.patch
delete mode 100644 tests/arm32/vexpress-a9/freertos/patches/ports.patch
delete mode 100644 tests/arm32/vexpress-a9/freertos/stdio.h
delete mode 100644 tests/arm32/vexpress-a9/freertos/string.h
delete mode 100644 tests/arm32/vexpress-a9/linux/README
delete mode 100644 tests/arm32/vexpress-a9/linux/cmdlist
delete mode 100644 tests/arm32/vexpress-a9/linux/linux_extra.config
delete mode 100644 tests/arm32/vexpress-a9/linux/nor_flash.list
delete mode 100644 tests/arm32/vexpress-a9/vexpress-a9-guest.dts
delete mode 100644 tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript
delete mode 100644 tests/arm32/vexpress-a9/xscript/two_guest_vexpress-a9.xscript

diff --git a/tests/arm32/README b/tests/arm32/README
index 7d19fd57..f10a5e50 100644
--- a/tests/arm32/README
+++ b/tests/arm32/README
@@ -3,13 +3,9 @@
This directory contains the following sub-directories:

1. common - Common code for all ARM32 guests
- 2. realview-eb-mpcore - Realview-EB-MPCore (ARMV6,ARM11MP) guest directory
- 3. realview-pb-a8 - Realview-PB-A8 (ARMV7A,Cortex-A8) guest directory
- 4. sabrelite - iMX6 Sabre LITE (ARMV7A,Cortex-A9) guest directory
- 5. vexpress-a9 - VExpress-A9 (ARMV7A,Cortex-A9) guest directory
- 6. vexpress-a15 - VExpress-A15 (ARMV7A,Cortex-A15) guest directory
- 7. virt-v7 - Virt-v7 (ARMV7A,Cortex-A15) guest directory
- 8. versatile - VersatilePB (ARMV5,ARM9) platform guest directory
+ 2. vexpress-a15 - VExpress-A15 (ARMV7A,Cortex-A15) guest directory
+ 3. virt-v7 - Virt-v7 (ARMV7A,Cortex-A15) guest directory
+ 4. versatile - VersatilePB (ARMV5,ARM9) platform guest directory

Please follow the README under specific directory for detailed
steps to configure, compile and run.
diff --git a/tests/arm32/realview-eb-mpcore/README b/tests/arm32/realview-eb-mpcore/README
deleted file mode 100644
index b8be132a..00000000
--- a/tests/arm32/realview-eb-mpcore/README

+++ /dev/null
@@ -1,37 +0,0 @@

- Realview-EB-MPCore Guest
-
-This guest has ARM11MPCore (MPCore ARMv6) CPU and various peripherals
-expected on a Realview Platform Base Board.
-
-We also have memory mapped VirtIO devices located at unused IO regions
-of the guest for providing VirtIO based paravirtualization.
-
-There are many reserved IO regions as per Realview-EB-MPCore User Guide. From
-these reserved IO regions, we will use the following IO regions for VirtIO:
-0x20000000–0x3FFFFFFF (512M) (Reserved)
-
-The VirtIO devices also require a IRQ line per device for functioning. The
-Realview-EB-MPCore guest has following unused or reserved IRQ lines:
-GIC: 48
-GIC: 68
-GIC: 69
-GIC: 73
-
-The memory map and irq of paravirt devices on Realivew-EB-MPCore guest is
-as follows:
-0x20000000–0x20000FFF (4K) (Guest/VM Info Device)
-0x20100000–0x20100FFF (4K) (IRQ=48) (VirtIO Network Device)
-0x20200000–0x20200FFF (4K) (IRQ=68) (VirtIO Block Device)
-0x20300000–0x20300FFF (4K) (IRQ=69) (VirtIO Console Device)
-0x20400000–0x20400FFF (4K) (IRQ=73) (VirtIO RPMSG Device)
-
-
- Realview-EB-MPCore Guest OSes
-
-We have tested following guest OSes for this guest:
-
- 1. basic - Basic firmware/bootloader
- 2. linux - Linux Kernel
-
-Please follow the README under specific guest OS directory for detailed
-steps to configure, compile and run.
diff --git a/tests/arm32/realview-eb-mpcore/basic/Makefile b/tests/arm32/realview-eb-mpcore/basic/Makefile
deleted file mode 100644
index 6e5b558b..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/Makefile

+++ /dev/null
@@ -1,57 +0,0 @@

-#/**
-# Copyright (c) 2013 Anup Patel.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile

-# @author Anup Patel (an...@brainfault.org)

-# @brief toplevel makefile to build firmware
-# */
-
-# Determine the build directory
-top_dir=$(CURDIR)/../../../..
-ifdef O
- build_dir=$(shell readlink -f $(O))
-else
- build_dir=$(top_dir)/build
-endif
-ifdef I
- install_dir=$(shell readlink -f $(I))
-else
- install_dir=$(top_dir)/install
-endif
-
-obj_dir=$(build_dir)/tests/arm32/realview-eb-mpcore/basic
-basic_dir=$(top_dir)/tests/common/basic
-arch_dir=$(top_dir)/tests/arm32/common/basic
-
-board_arch = v6
-board_text_start = 0x04000000
-board_objs = $(obj_dir)/arch_board.o \
- $(obj_dir)/pic/gic.o \
- $(obj_dir)/timer/sp804.o \
- $(obj_dir)/serial/pl01x.o \
- $(obj_dir)/sys/vminfo.o
-board_smp = y
-
-board_cppflags =
-board_cflags =
-board_asflags =
-board_ldflags =
-
-# Include common arch makefile for basic firmware
-include $(arch_dir)/Makefile.inc
-
diff --git a/tests/arm32/realview-eb-mpcore/basic/README b/tests/arm32/realview-eb-mpcore/basic/README
deleted file mode 100644
index 5111c219..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/README
+++ /dev/null
@@ -1,70 +0,0 @@
- Basic Firmware on Realview-EB-MPCore Guest
-
-The basic firmware currently sets up PIC, Timer, and UART and emulates
-a dummy terminal which reponds to various commands. It also includes an
-extensive MMU test suite and dhrystone benchmark.
-
-Hardware features tested by Basic Firmware:
- - Sensitive non-priviledged instructions
- - Virtual IRQs
- - Generic Interrupt Controller (GIC)
- - PrimeCell Dual-Mode Timer (SP804)
- - Serial Port (PL011)
-
-Please follow the steps below to build & run Basic Firmware on
-Realview-EB-MPCore Guest with Xvisor running on QEMU Realview-EB-MPCore Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v6 default settings]
- # make ARCH=arm generic-v6-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/realview-eb-mpcore/basic
-
- [6. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/realview-eb-mpcore
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/realview-eb-mpcore-guest.dtb ./tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts
- # cp -f ./build/tests/arm32/realview-eb-mpcore/basic/firmware.bin.patched ./build/disk/images/arm32/realview-eb-mpcore/firmware.bin
- # cp -f ./tests/arm32/realview-eb-mpcore/basic/nor_flash.list ./build/disk/images/arm32/realview-eb-mpcore/nor_flash.list
- # cp -f ./tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript ./build/disk/boot.xscript
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [7. Launch QEMU]
- # qemu-system-arm -M realview-eb-mpcore -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dtb -initrd build/disk.img
-
- [8. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [9. Bind to virtual UART]
- XVisor# vserial bind guest0/uart0
-
- [10. Say 'hi' to Basic Firmware]
- [guest0/uart0] basic# hi
-
- [11. Say 'hello' to Basic Firmware]
- [guest0/uart0] basic# hello
-
- [12. Check various commands of Basic Firmware]
- [guest0/uart0] basic# help
-
- [13. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] basic#
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/realview-eb-mpcore/basic/arch_board.c b/tests/arm32/realview-eb-mpcore/basic/arch_board.c
deleted file mode 100644
index 780b4b57..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/arch_board.c
+++ /dev/null
@@ -1,524 +0,0 @@

-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_board.c

- * @author Anup Patel (an...@brainfault.org)

- * @brief various platform specific functions
- */
-
-#include <arch_types.h>
-#include <arch_io.h>
-#include <arch_math.h>
-#include <arch_board.h>
-#include <arm_plat.h>
-#include <basic_stdio.h>
-#include <basic_string.h>
-#include <libfdt/libfdt.h>
-#include <libfdt/fdt_support.h>
-#include <pic/gic.h>
-#include <timer/sp804.h>
-#include <serial/pl01x.h>
-#include <sys/vminfo.h>
-
-void arch_board_reset(void)
-{
- arch_writel(0x0,
- (void *)(REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET));
- arch_writel(0x08,
- (void *)(REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET));
-}
-
-void arch_board_init(void)
-{
- /* Unlock Lockable reigsters */
- arch_writel(REALVIEW_SYS_LOCKVAL,
- (void *)(REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET));
-}
-
-char *arch_board_name(void)
-{
- return "ARM Realview-EB-MPCore";
-}
-
-physical_addr_t arch_board_ram_start(void)
-{
- return (physical_addr_t)vminfo_ram_base(REALVIEW_VMINFO_BASE, 0);
-}
-
-physical_size_t arch_board_ram_size(void)
-{
- return (physical_size_t)vminfo_ram_size(REALVIEW_VMINFO_BASE, 0);
-}
-
-void arch_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz)
-{
- basic_strcpy(cmdline, "root=/dev/ram rw earlyprintk "
- "earlycon=pl011,0x10009000 console=ttyAMA0");
-}
-
-void arch_board_fdt_fixup(void *fdt_addr)
-{
- u32 vals[5];
- char str[64];
- u32 intc_phandle;
- int rc, poff, noff;
-
- poff = fdt_path_offset(fdt_addr,
- "/soc/interrupt-controller@1f000100");
- if (poff < 0) {
- basic_printf("%s: failed to find nodeoffset of %s node\n",
- __func__, "/soc/interrupt-controller@1f000100");
- return;
- }
-
- intc_phandle = fdt_get_phandle(fdt_addr, poff);
- if (!intc_phandle) {
- basic_printf("%s: failed to find phandle for %s node\n",
- __func__, "/soc/interrupt-controller@1f000100");
- return;
- }
-
- poff = fdt_path_offset(fdt_addr, "/");
- if (poff < 0) {
- basic_printf("%s: failed to find nodeoffset of %s node\n",
- __func__, "/");
- return;
- }
-
- poff = fdt_add_subnode(fdt_addr, poff, "virt");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virt", "/");
- return;
- }
-
- basic_strcpy(str, "simple-bus");
- rc = fdt_setprop(fdt_addr, poff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(intc_phandle);
- rc = fdt_setprop(fdt_addr, poff, "interrupt-parent",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupt-parent", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#address-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#address-cells", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#size-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#size-cells", "virt");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, poff, "ranges", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "ranges", "virt");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_net");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_net", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20100000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(16);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_net");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_net");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_block");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_block", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20200000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(36);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_block");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_block");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_console");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_console", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20300000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(37);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_console");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_console");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_rpmsg");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_rpmsg", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20400000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(41);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_rpmsg");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_rpmsg");
- return;
- }
-}
-
-physical_addr_t arch_board_autoexec_addr(void)
-{
- return (REALVIEW_FLASH0_BASE + 0xFF000);
-}
-
-u32 arch_board_boot_delay(void)
-{
- return vminfo_boot_delay(REALVIEW_VMINFO_BASE);
-}
-
-u32 arch_board_iosection_count(void)
-{
- return 19;
-}
-
-physical_addr_t arch_board_iosection_addr(int num)
-{
- physical_addr_t ret = 0;
-
- switch (num) {
- case 0:
- ret = REALVIEW_SYS_BASE;

- break;
- case 1:

- ret = REALVIEW_GIC_CPU_BASE;

- break;
- case 2:

- ret = REALVIEW_VMINFO_BASE;

- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:

- case 8:
- case 9:
- case 10:
- case 11:
- case 12:

- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- ret = REALVIEW_FLASH0_BASE + (num - 3) * 0x100000;
- break;
- default:
- while (1);
- break;
- }
-
- return ret;
-}
-
-u32 arch_board_pic_nr_irqs(void)
-{
- return NR_IRQS_EB;
-}
-
-int arch_board_pic_init(void)

-{
- int rc;
-
- /*

- * Initialize Generic Interrupt Controller
- */
- rc = gic_dist_init(0, REALVIEW_GIC_DIST_BASE, IRQ_GIC_START);

- if (rc) {
- return rc;
- }

- rc = gic_cpu_init(0, REALVIEW_GIC_CPU_BASE);

- if (rc) {
- return rc;
- }
-

- return 0;
-}
-
-u32 arch_board_pic_active_irq(void)
-{
- return gic_active_irq(0);
-}
-
-int arch_board_pic_ack_irq(u32 irq)

-{
- return 0;
-}
-

-int arch_board_pic_eoi_irq(u32 irq)
-{
- return gic_eoi_irq(0, irq);
-}
-
-int arch_board_pic_mask(u32 irq)
-{
- return gic_mask(0, irq);
-}
-
-int arch_board_pic_unmask(u32 irq)
-{
- return gic_unmask(0, irq);
-}
-
-void arch_board_timer_enable(void)
-{
- return sp804_enable();
-}
-
-void arch_board_timer_disable(void)
-{
- return sp804_disable();
-}
-
-u64 arch_board_timer_irqcount(void)
-{
- return sp804_irqcount();
-}
-
-u64 arch_board_timer_irqdelay(void)
-{
- return sp804_irqdelay();
-}
-
-u64 arch_board_timer_timestamp(void)
-{
- return sp804_timestamp();
-}
-
-void arch_board_timer_change_period(u32 usecs)
-{
- return sp804_change_period(usecs);
-}
-
-int arch_board_timer_init(u32 usecs)
-{
- u32 val, irq;
- u64 counter_mult, counter_shift, counter_mask;
-
- counter_mask = 0xFFFFFFFFULL;
- counter_shift = 20;
- counter_mult = ((u64)1000000) << counter_shift;
- counter_mult += (((u64)1000) >> 1);
- counter_mult = arch_udiv64(counter_mult, ((u64)1000));
-
- irq = IRQ_EB11MP_TIMER0_1;
-
- /* set clock frequency:
- * REALVIEW_REFCLK is 32KHz
- * REALVIEW_TIMCLK is 1MHz
- */
- val = arch_readl((void *)REALVIEW_SCTL_BASE) | (REALVIEW_TIMCLK << 1);
- arch_writel(val, (void *)REALVIEW_SCTL_BASE);
-
- return sp804_init(usecs, REALVIEW_TIMER0_1_BASE, irq,
- counter_mask, counter_mult, counter_shift);
-}
-
-#define EBMP_UART_BASE 0x10009000
-#define EBMP_UART_TYPE PL01X_TYPE_1
-#define EBMP_UART_INCLK 24000000
-#define EBMP_UART_BAUD 115200
-
-int arch_board_serial_init(void)
-{
- pl01x_init(EBMP_UART_BASE,
- EBMP_UART_TYPE,
- EBMP_UART_BAUD,
- EBMP_UART_INCLK);

-
- return 0;
-}
-

-void arch_board_serial_putc(char ch)
-{
- if (ch == '\n') {
- pl01x_putc(EBMP_UART_BASE, EBMP_UART_TYPE, '\r');
- }
- pl01x_putc(EBMP_UART_BASE, EBMP_UART_TYPE, ch);
-}
-
-bool arch_board_serial_can_getc(void)
-{
- return pl01x_can_getc(EBMP_UART_BASE, EBMP_UART_TYPE);
-}
-
-char arch_board_serial_getc(void)
-{
- char ch = pl01x_getc(EBMP_UART_BASE, EBMP_UART_TYPE);
- if (ch == '\r') {
- ch = '\n';
- }
- arch_board_serial_putc(ch);
- return ch;
-}
diff --git a/tests/arm32/realview-eb-mpcore/basic/arch_smp.h b/tests/arm32/realview-eb-mpcore/basic/arch_smp.h
deleted file mode 100644
index 6701a78d..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/arch_smp.h

+++ /dev/null
@@ -1,30 +0,0 @@

-/**
- * Copyright (c) 2018 Anup Patel.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_smp.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief arch specific SMP defines
- */
-#ifndef __ARCH_SMP_H__
-#define __ARCH_SMP_H__
-
-#include <arm_plat.h>
-
-#define ARCH_SMP_SPIN_ADDR (REALVIEW_SYS_FLAGSSET)
-
-#endif
diff --git a/tests/arm32/realview-eb-mpcore/basic/arm_plat.h b/tests/arm32/realview-eb-mpcore/basic/arm_plat.h
deleted file mode 100644
index 85b39b62..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/arm_plat.h
+++ /dev/null
@@ -1,338 +0,0 @@

-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arm_plat.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM platform configuration
- */
-#ifndef _ARM_PLAT_H__
-#define _ARM_PLAT_H__
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
-#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
-#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
-#define REALVIEW_SCTL_BASE 0x1001A000 /* System Controller */
-#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
-#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */
-#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */
-#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */
-#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
-#define REALVIEW_FLASH0_BASE 0x40000000
-#define REALVIEW_FLASH0_SIZE SZ_64M
-#define REALVIEW_FLASH1_BASE 0x44000000
-#define REALVIEW_FLASH1_SIZE SZ_64M
-#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_USB_BASE 0x4F000000 /* USB */
-#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
-#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */
-#define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
-#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
-
-#define REALVIEW_SYS_PLD_CTRL1 0x74
-
-/*
- * PCI regions
- */
-#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
- * Irqs
- */
-#define IRQ_GIC_START 29
-
-#define IRQ_EB_GIC_START 32
-
-#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
-#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
-#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
-#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
-#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
-#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
-#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
-#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
-#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
-#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
-#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
-#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
-#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
-#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
-#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
-#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
-
-#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
-#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
-#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
-#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
-#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
-#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
-#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
-#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
-#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
-#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
-#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
-#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
-
-#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
-#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
-#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
-
-/*
- * The 11MPcore tile leaves the following unconnected.
- */
-#define IRQ_EB11MP_UART2 0
-#define IRQ_EB11MP_UART3 0
-#define IRQ_EB11MP_CLCD 0
-#define IRQ_EB11MP_DMA 0
-#define IRQ_EB11MP_WDOG 0
-#define IRQ_EB11MP_GPIO0 0
-#define IRQ_EB11MP_GPIO1 0
-#define IRQ_EB11MP_GPIO2 0
-#define IRQ_EB11MP_SCI 0
-#define IRQ_EB11MP_SSP 0
-
-#define NR_GIC_EB11MP 2
-
-/*
- * Only define NR_IRQS if less than NR_IRQS_EB
- */
-#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
-
-/*
- * Memory definitions
- */
-#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */
-#define REALVIEW_BOOT_ROM_HI 0x30000000
-#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
-#define REALVIEW_BOOT_ROM_SIZE SZ_64M
-
-#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
-#define REALVIEW_SSRAM_SIZE SZ_2M
-
-/*
- * SDRAM
- */
-#define REALVIEW_SDRAM_BASE 0x00000000
-
-/*
- * Logic expansion modules

- *
- */
-

-/* ------------------------------------------------------------------------
- * RealView Registers

- * ------------------------------------------------------------------------
- *
- */

-#define REALVIEW_SYS_ID_OFFSET 0x00
-#define REALVIEW_SYS_SW_OFFSET 0x04
-#define REALVIEW_SYS_LED_OFFSET 0x08
-#define REALVIEW_SYS_OSC0_OFFSET 0x0C
-
-#define REALVIEW_SYS_OSC1_OFFSET 0x10
-#define REALVIEW_SYS_OSC2_OFFSET 0x14
-#define REALVIEW_SYS_OSC3_OFFSET 0x18
-#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
-
-#define REALVIEW_SYS_LOCK_OFFSET 0x20
-#define REALVIEW_SYS_100HZ_OFFSET 0x24
-#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
-#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
-#define REALVIEW_SYS_FLAGS_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
-#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
-#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
-#define REALVIEW_SYS_PCICTL_OFFSET 0x44
-#define REALVIEW_SYS_MCI_OFFSET 0x48
-#define REALVIEW_SYS_FLASH_OFFSET 0x4C
-#define REALVIEW_SYS_CLCD_OFFSET 0x50
-#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
-#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
-#define REALVIEW_SYS_24MHz_OFFSET 0x5C
-#define REALVIEW_SYS_MISC_OFFSET 0x60
-#define REALVIEW_SYS_IOSEL_OFFSET 0x70
-#define REALVIEW_SYS_PROCID_OFFSET 0x84
-#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
-#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
-#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
-#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
-#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
-
-#define REALVIEW_SYS_BASE 0x10000000
-#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
-#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
-#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
-#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
-#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
-
-#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
-#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
-#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
-#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
-#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
-#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
-#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
-#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
-#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
-#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
-#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
-#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
-#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
-#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
-#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
-#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
-#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
-#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
-#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
-#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
-#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
-#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
-#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
-#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
-#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
-#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
-
-#define REALVIEW_SYS_CTRL_LED (1 << 0)
-
-/* ------------------------------------------------------------------------
- * RealView control registers

- * ------------------------------------------------------------------------
- */
-
-/*

- * REALVIEW_IDFIELD

- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4 = build value
- * 3:0 = revision number (0x1 = rev B (AHB))
- */
-
-/*

- * REALVIEW_SYS_LOCK

- * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
- * SYS_CLD, SYS_BOOTCS
- */

-#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
-#define REALVIEW_SYS_LOCKVAL 0xA05F
-#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
-
-/*
- * REALVIEW_SYS_FLASH
- */
-#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
-
-/*
- * REALVIEW_INTREG

- * - used to acknowledge and control MMCI and UART interrupts
- */

-#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
-#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
-#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */

- /* write 1 to acknowledge and clear */

-#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
-#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
-
-
-/*
- * LED settings, bits [7:0]
- */
-#define REALVIEW_SYS_LED0 (1 << 0)
-#define REALVIEW_SYS_LED1 (1 << 1)
-#define REALVIEW_SYS_LED2 (1 << 2)
-#define REALVIEW_SYS_LED3 (1 << 3)
-#define REALVIEW_SYS_LED4 (1 << 4)
-#define REALVIEW_SYS_LED5 (1 << 5)
-#define REALVIEW_SYS_LED6 (1 << 6)
-#define REALVIEW_SYS_LED7 (1 << 7)
-
-#define ALL_LEDS 0xFF
-
-#define LED_BANK REALVIEW_SYS_LED
-
-/*
- * Control registers
- */
-#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
-#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
-#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
-#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
-
-/*
- * Clean base - dummy
- *
- */
-#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
-
-/*
- * System controller bit assignment
- */
-#define REALVIEW_REFCLK 0
-#define REALVIEW_TIMCLK 1
-
-#define REALVIEW_TIMER1_EnSel 15
-#define REALVIEW_TIMER2_EnSel 17
-#define REALVIEW_TIMER3_EnSel 19
-#define REALVIEW_TIMER4_EnSel 21
-
-#define MAX_TIMER 2
-#define MAX_PERIOD 699050
-#define TICKS_PER_uSEC 1
-
-/*
- * These are useconds NOT ticks.
- *
- */
-#define mSEC_1 1000
-#define mSEC_5 (mSEC_1 * 5)
-#define mSEC_10 (mSEC_1 * 10)
-#define mSEC_25 (mSEC_1 * 25)
-#define SEC_1 (mSEC_1 * 1000)
-
-#define REALVIEW_CSR_BASE 0x10000000
-#define REALVIEW_CSR_SIZE 0x10000000
-
-/*
- * Defines required by basic firmware
- */
-#define REALVIEW_VMINFO_BASE 0x20000000
-
-#endif
diff --git a/tests/arm32/realview-eb-mpcore/basic/gic_config.h b/tests/arm32/realview-eb-mpcore/basic/gic_config.h
deleted file mode 100644
index 31555431..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/gic_config.h
+++ /dev/null
@@ -1,33 +0,0 @@

-/**
- * Copyright (c) 2013 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file gic_config.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM Generic Interrupt Controller configuration header
- */
-#ifndef _GIC_CONFIG_H__
-#define _GIC_CONFIG_H__
-
-#include <arm_plat.h>
-
-#define GIC_CPU_BASE REALVIEW_GIC_CPU_BASE
-#define GIC_DIST_BASE REALVIEW_GIC_DIST_BASE
-#define GIC_NR_IRQS NR_IRQS_EB
-#define GIC_MAX_NR NR_GIC_EB11MP
-
-#endif
diff --git a/tests/arm32/realview-eb-mpcore/basic/nor_flash.list b/tests/arm32/realview-eb-mpcore/basic/nor_flash.list
deleted file mode 100644
index 4f38aa4c..00000000
--- a/tests/arm32/realview-eb-mpcore/basic/nor_flash.list
+++ /dev/null
@@ -1 +0,0 @@
-0x40000000 ./firmware.bin
diff --git a/tests/arm32/realview-eb-mpcore/linux/README b/tests/arm32/realview-eb-mpcore/linux/README
deleted file mode 100644
index 28f0d815..00000000
--- a/tests/arm32/realview-eb-mpcore/linux/README
+++ /dev/null
@@ -1,101 +0,0 @@
- Linux on Xvisor Realview-EB-MPCore Guest
-
-Linux is a computer operating system which is based on free and open source
-software. the underlying source code can be used, freely modified, and
-redistributed, both commercially and non-commercially, by anyone under
-licenses such as the GNU General Public License. For more information on
-Linux read the wiki page http://en.wikipedia.org/wiki/Linux
-
-Linux already contains a support for Realview-EB-MPCore Board. We can use
-this kernel unmodified to run it as a xvisor guest. We have also provide
-Realview-EB-MPCore defconfig for various linux kernel versions for ease in
-building kernel. To obtain Linux kernel sources visit the following
-url: http://www.kernel.org
-
-Follow the steps below to build & run Linux kernel with Busybox RootFS on
-Realview-EB-MPCore Guest with Xvisor running on QEMU Realview-EB-MPCore Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v6 default settings]
- # make ARCH=arm generic-v6-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/realview-eb-mpcore/basic
-
- [6. GoTo Linux source directory]
- # cd <linux_source_directory>
-
- [7. Configure Linux in build directory]
- # sed -i 's/0xff800000UL/0xff000000UL/' arch/arm/include/asm/pgtable.h
- # cp arch/arm/configs/realview_defconfig arch/arm/configs/tmp-realview-eb-mpcore_defconfig
- # <xvisor_source_directory>/tests/common/scripts/update-linux-defconfig.sh -p arch/arm/configs/tmp-realview-eb-mpcore_defconfig -f <xvisor_source_directory>/tests/arm32/realview-eb-mpcore/linux/linux_extra.config
- # make O=<linux_build_directory> ARCH=arm tmp-realview-eb-mpcore_defconfig
-
- [8. Build Linux in build directory]
- # make O=<linux_build_directory> ARCH=arm Image dtbs
-
- [9. Patch Linux kernel to replace sensitive non-priviledged instructions]
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f <linux_build_directory>/vmlinux | <xvisor_source_directory>/build/tools/cpatch/cpatch32 <linux_build_directory>/vmlinux 0
-
- [10. Extract patched Linux kernel image]
- # ${CROSS_COMPILE}objcopy -O binary <linux_build_directory>/vmlinux <linux_build_directory>/arch/arm/boot/Image
-
- [11. Create BusyBox RAMDISK to be used as RootFS for Linux kernel]
- (Note: For subsequent steps, we will assume that your RAMDISK is located at <busybox_rootfs_directory>/rootfs.img)
- (Note: Please refer tests/common/busybox/README.md for creating rootfs.img using BusyBox)
-
- [12. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [13. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/realview-eb-mpcore
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/realview-eb-mpcore-guest.dtb ./tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts
- # cp -f ./build/tests/arm32/realview-eb-mpcore/basic/firmware.bin.patched ./build/disk/images/arm32/realview-eb-mpcore/firmware.bin
- # cp -f ./tests/arm32/realview-eb-mpcore/linux/nor_flash.list ./build/disk/images/arm32/realview-eb-mpcore/nor_flash.list
- # cp -f ./tests/arm32/realview-eb-mpcore/linux/cmdlist ./build/disk/images/arm32/realview-eb-mpcore/cmdlist
- # cp -f ./tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript ./build/disk/boot.xscript
- # cp -f <linux_build_directory>/arch/arm/boot/Image ./build/disk/images/arm32/realview-eb-mpcore/Image
- # cp -f <linux_build_directory>/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dtb ./build/disk/images/arm32/realview-eb-mpcore/arm-realview-eb-11mp-ctrevb.dtb
- # cp -f <busybox_rootfs_directory>/rootfs.img ./build/disk/images/arm32/realview-eb-mpcore/rootfs.img
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [14. Launch QEMU]
- # qemu-system-arm -M realview-eb-mpcore -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/arm-realview-eb-11mp-ctrevb.dtb -initrd build/disk.img
-
- [15. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [16. Bind to virtual UART0 of Linux Guest]
- XVisor# vserial bind guest0/uart0
-
- [17. Copy linux from NOR flash to RAM and start linux booting from RAM]
- [guest0/uart0] basic# autoexec
- (Note: "autoexec" is a short-cut command)
- (Note: The <xvisor_source_directory>/tests/arm32/realview-eb-mpcore/linux/cmdlist
- file which we have added to guest NOR flash contains set of commands for booting
- linux from NOR flash)
-
- [18. Wait for Linux prompt to come-up and then try out some commands]
- [guest0/uart0] / # ls
-
- [19. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] / #
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/realview-eb-mpcore/linux/cmdlist b/tests/arm32/realview-eb-mpcore/linux/cmdlist
deleted file mode 100644
index 9f0bafa9..00000000
--- a/tests/arm32/realview-eb-mpcore/linux/cmdlist
+++ /dev/null
@@ -1,4 +0,0 @@
-copy 0x00008000 0x40100000 0x16F0000
-copy 0x02000000 0x417F0000 0x10000
-copy 0x02100000 0x41800000 0x800000
-start_linux_fdt 0x00008000 0x02000000 0x02100000 0x800000
diff --git a/tests/arm32/realview-eb-mpcore/linux/linux_extra.config b/tests/arm32/realview-eb-mpcore/linux/linux_extra.config
deleted file mode 100644
index c933e79c..00000000
--- a/tests/arm32/realview-eb-mpcore/linux/linux_extra.config
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_NO_HZ_FULL=n
-CONFIG_NO_HZ_IDLE=y
-CONFIG_DRM=n
diff --git a/tests/arm32/realview-eb-mpcore/linux/nor_flash.list b/tests/arm32/realview-eb-mpcore/linux/nor_flash.list
deleted file mode 100644
index 79b114c5..00000000
--- a/tests/arm32/realview-eb-mpcore/linux/nor_flash.list
+++ /dev/null
@@ -1,5 +0,0 @@
-0x40000000 ./firmware.bin
-0x400FF000 ./cmdlist
-0x40100000 ./Image
-0x417F0000 ./arm-realview-eb-11mp-ctrevb.dtb
-0x41800000 ./rootfs.img
diff --git a/tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts b/tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts
deleted file mode 100644
index 2911af1d..00000000
--- a/tests/arm32/realview-eb-mpcore/realview-eb-mpcore-guest.dts

+++ /dev/null
@@ -1,404 +0,0 @@
-
-/dts-v1/;
-

-/ {
- model = "realview-eb-mpcore";
- device_type = "guest";
- psci_version = <2>;
-
- aliases {
- mem0 = &MEM0;
- net0 = &NET0;
- net1 = &NET1;
- disk0 = &DISK0;
- };
-
- vcpu_template {
- device_type = "vcpu";
- compatible = "armv6,arm11mp";
- start_pc = <0x40000000>;
- };
-
- aspace {
- guest_irq_count = <2048>;
-
- MEM0: mem0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x00000000>;
- physical_size = <0x00000000>; /* Override this before guest creation */
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_ram";
- };
-
- sysctl {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10000000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "realview,eb-mpcore";
- mux_in_irq = <1200 1201>;
- mux_out_irq = <1202>;
- };
-
- sysctrl0 { /* No SP810 sysctrl */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10001000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- i2c { /* No I2C */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10002000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- aaci { /* No Audio Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10004000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mmc0 { /* No Multimedia Card Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10005000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- kmi0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10006000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,keyboard";
- interrupts = <39>;
- };
-
- kmi1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10007000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,mouse";
- interrupts = <40>;
- };
-
- charlcd { /* No Character LCD */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10008000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- uart0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10009000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <36>;
- };
-
- uart1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000A000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <37>;
- };
-
- uart2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000B000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <78>;
- };
-
- uart3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000C000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <79>;
- };
-
- ssp0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000D000>;
- physical_size = <0x1000>;
- device_type = "spi-host";
- compatible = "primecell,arm,pl022";
- interrupts = <75>;
- };
-
- sci0 { /* No Smart card controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000E000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- wdt {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10010000>;
- physical_size = <0x1000>;
- device_type = "watchdog";
- compatible = "primecell,sp805";

- interrupts = <32>;
- };
-

- timer0_1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10011000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <33>;
- };
-
- timer2_3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10012000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <34>;
- };
-
- gpio0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10013000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <0 0 0 0 0 0 0 0>;
- gpio_in_irq = <1400 1401 1402 1403 1404 1405 1406 1407>;
- gpio_out_irq = <1408 1409 1410 1411 1412 1413 1414 1415>;
- interrupts = <70>;
- };
-
- gpio1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10014000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <0 0 0 0 0 0 0 0>;
- gpio_in_irq = <1300 1301 1302 1303 1304 1305 1306 1307>;
- gpio_out_irq = <1308 1309 1310 1311 1312 1313 1314 1315>;
- interrupts = <71>;
- };
-
- gpio2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10015000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <1 0 0 0 0 0 0 0>;
- gpio_in_irq = <1201 1200 1202 1203 1204 1205 1206 1207>;
- gpio_out_irq = <1208 1209 1210 1211 1212 1213 1214 1215>;
- interrupts = <72>;
- };
-
- rtc0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10017000>;
- physical_size = <0x1000>;
- device_type = "rtc";
- compatible = "primecell,pl031";
- interrupts = <38>;
- };
-
- sysctrl1 { /* No SP810 sysctrl */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1001A000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- clcd {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10020000>;
- physical_size = <0x1000>;
- device_type = "display";
- compatible = "primecell,pl111";

- interrupts = <47>;
- };
-

- dmac { /* No DMA Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10030000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- legacy_gic { /* No EB GIC Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10040000>;
- physical_size = <0x2000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- smc { /* No SMC */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10080000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- priv0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10100000>;
- physical_size = <0x2000>;
- device_type = "misc";
- compatible = "arm,arm11mpcore";
- timer_irq = <29 30>;
- parent_irq = <6>;
- };
-
- l2x0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10102000>;
- physical_size = <0x1000>;
- device_type = "cache";
- compatible = "corelink,l2c-310";
- };
-
- vminfo {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "sys";
- compatible = "vminfo-0.1";
- guest_physical_addr = <0x20000000>;
- physical_size = <0x1000>;
- ram0_base = <0x00000000>;
- };
-
- NET0: virtio-net0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <1>;
- guest_physical_addr = <0x20100000>;
- physical_size = <0x1000>;
- switch = ""; /* Override this before guest creation */
- interrupts = <48>;
- };
-
- DISK0: virtio-blk0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <2>;
- guest_physical_addr = <0x20200000>;
- physical_size = <0x1000>;
- blkdev = ""; /* Override this before guest creation */
- interrupts = <68>;
- };
-
- virtio-con0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <3>;
- guest_physical_addr = <0x20300000>;
- physical_size = <0x1000>;
- interrupts = <69>;
- };
-
- virtio-rpmsg0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <7>;
- guest_physical_addr = <0x20400000>;
- physical_size = <0x1000>;
- interrupts = <73>;
- node_ns_name = "rpmsg_chrdev";
- };
-
- nor_flash {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x40000000>;
- physical_size = <0x02000000>;
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_rom";
- };
-
- NET1: eth {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4E000000>;
- physical_size = <0x10000>;
- device_type = "nic";
- compatible = "smsc,smc91c111";
- switch = ""; /* Override this before guest creation */
- interrupts = <41>;
- };
-
- usb { /* No USB */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4F000000>;
- physical_size = <0x20000>;
- device_type = "misc";
- compatible = "zero";
- };
- };
-};
diff --git a/tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript b/tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript
deleted file mode 100644
index bc193fec..00000000
--- a/tests/arm32/realview-eb-mpcore/xscript/one_guest_ebmp.xscript
+++ /dev/null
@@ -1,8 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/realview-eb-mpcore-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/realview-eb-mpcore/nor_flash.list
diff --git a/tests/arm32/realview-eb-mpcore/xscript/two_guest_ebmp.xscript b/tests/arm32/realview-eb-mpcore/xscript/two_guest_ebmp.xscript
deleted file mode 100644
index f12d2d37..00000000
--- a/tests/arm32/realview-eb-mpcore/xscript/two_guest_ebmp.xscript
+++ /dev/null
@@ -1,17 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/realview-eb-mpcore-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/realview-eb-mpcore/nor_flash.list
-
-# Load guest1 device tree from file
-vfs guest_fdt_load guest1 /images/arm32/realview-eb-mpcore-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest1
-guest create guest1
-
-# Load guest1 images
-vfs guest_load_list guest1 /images/arm32/realview-eb-mpcore/nor_flash.list
diff --git a/tests/arm32/realview-pb-a8/README b/tests/arm32/realview-pb-a8/README
deleted file mode 100644
index 6ec5495b..00000000
--- a/tests/arm32/realview-pb-a8/README
+++ /dev/null
@@ -1,40 +0,0 @@
- Realview-PB-A8 Guest
-
-This guest has Cortex-A8 (Single Core ARMv7a) CPU and various peripherals
-expected on a Realview Platform Base Board.
-
-We also have memory mapped VirtIO devices located at unused IO regions
-of the guest for providing VirtIO based paravirtualization.
-
-There are many reserved IO regions as per Realview-PB-A8 User Guide. From
-these reserved IO regions, we will use the following IO regions for VirtIO:
-0x20000000–0x3FFFFFFF (512M) (Reserved)
-
-The VirtIO devices also require a IRQ line per device for functioning. The
-Realview-PB-A8 guest has following unused or reserved IRQ lines:
-GIC: 34-35
-GIC: 41
-GIC: 57
-GIC: 59
-GIC: 62-63
-GIC: 75-78
-
-The memory map and irq of paravirt devices on Realivew-PB-A8 guest is
-as follows:
-0x20000000–0x20000FFF (4K) (Guest/VM Info Device)
-0x20100000–0x20100FFF (4K) (IRQ=34) (VirtIO Network Device)
-0x20200000–0x20200FFF (4K) (IRQ=35) (VirtIO Block Device)
-0x20300000–0x20300FFF (4K) (IRQ=41) (VirtIO Console Device)
-0x20400000–0x20400FFF (4K) (IRQ=57) (VirtIO RPMSG Device)
-
-
- Realview-PB-A8 Guest OSes
-
-We have tested following guest OSes for this guest:
-
- 1. basic - Basic firmware/bootloader
- 2. atomthreads - Atomthreads RTOS
- 3. linux - Linux Kernel
-
-Please follow the README under specific guest OS directory for detailed
-steps to configure, compile and run.
diff --git a/tests/arm32/realview-pb-a8/atomthreads/README b/tests/arm32/realview-pb-a8/atomthreads/README
deleted file mode 100644
index 449120e2..00000000
--- a/tests/arm32/realview-pb-a8/atomthreads/README

+++ /dev/null
@@ -1,129 +0,0 @@

- Atomthreads on Realview-PB-A8 Guest
-
-Atomthreads is a free, lightweight, portable, real-time scheduler for
-embedded systems. Please visit: http://atomthreads.com/ for more details.
-
-The Realview-PB-A8 port of atomthreads is still not released officially, but
-you can obtain the sources from: https://github.com/avpatel/atomthreads-arm
-
-Atomthreads uses all the CPU & Hardware features except Memory managment unit
-(MMU) and Floating point unit (FPU).
-
-Please follow the steps below to build & run Atomthreads on Realview-PB-A8
-Guest with Xvisor running on QEMU Realview-PB-A8 Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v7 default settings]
- # make ARCH=arm generic-v7-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/realview-pb-a8/basic
-
- [6. GoTo Atomthreads source directory]
- # cd <atomthreads_source_directory>/ports/arm32
-
- [7. Build Atomthreads]
- # make
-
- [8. Patch Atomthreads objects to replace sensitive non-priviledged instructions]
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f build/arm_entry.o | <xvisor_source_directory>/build/tools/cpatch/cpatch32 build/arm_entry.o 0
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f build/arm_irq.o | <xvisor_source_directory>/build/tools/cpatch/cpatch32 build/arm_irq.o 0
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f build/atomport-asm.o | <xvisor_source_directory>/build/tools/cpatch/cpatch32 build/atomport-asm.o 0
-
- [9. Rebuild Atomthreads to reflect changed object files]
- # make
-
- [10. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [11. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/realview-pb-a8
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/realview-pb-a8-guest.dtb ./tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts
- # cp -f ./build/tests/arm32/realview-pb-a8/basic/firmware.bin.patched ./build/disk/images/arm32/realview-pb-a8/firmware.bin
- # cp -f ./tests/arm32/realview-pb-a8/atomthreads/nor_flash.list ./build/disk/images/arm32/realview-pb-a8/nor_flash.list
- # cp -f ./tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript ./build/disk/boot.xscript
- # cp -f <atomthreads_source_directory>/ports/arm32/build/kern1.bin ./build/disk/images/arm32/realview-pb-a8/kern1.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/kern2.bin ./build/disk/images/arm32/realview-pb-a8/kern2.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/kern3.bin ./build/disk/images/arm32/realview-pb-a8/kern3.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/kern4.bin ./build/disk/images/arm32/realview-pb-a8/kern4.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex1.bin ./build/disk/images/arm32/realview-pb-a8/mutex1.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex2.bin ./build/disk/images/arm32/realview-pb-a8/mutex2.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex3.bin ./build/disk/images/arm32/realview-pb-a8/mutex3.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex4.bin ./build/disk/images/arm32/realview-pb-a8/mutex4.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex5.bin ./build/disk/images/arm32/realview-pb-a8/mutex5.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex6.bin ./build/disk/images/arm32/realview-pb-a8/mutex6.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex7.bin ./build/disk/images/arm32/realview-pb-a8/mutex7.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex8.bin ./build/disk/images/arm32/realview-pb-a8/mutex8.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/mutex9.bin ./build/disk/images/arm32/realview-pb-a8/mutex9.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue1.bin ./build/disk/images/arm32/realview-pb-a8/queue1.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue2.bin ./build/disk/images/arm32/realview-pb-a8/queue2.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue3.bin ./build/disk/images/arm32/realview-pb-a8/queue3.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue4.bin ./build/disk/images/arm32/realview-pb-a8/queue4.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue5.bin ./build/disk/images/arm32/realview-pb-a8/queue5.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue6.bin ./build/disk/images/arm32/realview-pb-a8/queue6.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue7.bin ./build/disk/images/arm32/realview-pb-a8/queue7.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue8.bin ./build/disk/images/arm32/realview-pb-a8/queue8.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue9.bin ./build/disk/images/arm32/realview-pb-a8/queue9.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/queue10.bin ./build/disk/images/arm32/realview-pb-a8/queue10.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem1.bin ./build/disk/images/arm32/realview-pb-a8/sem1.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem2.bin ./build/disk/images/arm32/realview-pb-a8/sem2.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem3.bin ./build/disk/images/arm32/realview-pb-a8/sem3.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem4.bin ./build/disk/images/arm32/realview-pb-a8/sem4.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem5.bin ./build/disk/images/arm32/realview-pb-a8/sem5.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem6.bin ./build/disk/images/arm32/realview-pb-a8/sem6.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem7.bin ./build/disk/images/arm32/realview-pb-a8/sem7.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem8.bin ./build/disk/images/arm32/realview-pb-a8/sem8.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/sem9.bin ./build/disk/images/arm32/realview-pb-a8/sem9.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer1.bin ./build/disk/images/arm32/realview-pb-a8/timer1.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer2.bin ./build/disk/images/arm32/realview-pb-a8/timer2.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer3.bin ./build/disk/images/arm32/realview-pb-a8/timer3.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer4.bin ./build/disk/images/arm32/realview-pb-a8/timer4.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer5.bin ./build/disk/images/arm32/realview-pb-a8/timer5.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer6.bin ./build/disk/images/arm32/realview-pb-a8/timer6.bin
- # cp -f <atomthreads_source_directory>/ports/arm32/build/timer7.bin ./build/disk/images/arm32/realview-pb-a8/timer7.bin
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [12. Launch QEMU]
- # qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/arm-realview-pba8.dtb -initrd build/disk.img
-
- [13. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [14. Bind to virtual UART]
- XVisor# vserial bind guest0/uart0
-
- [15. Copy kern1.bin atomthreads test from NOR flash to DDR]
- [guest0/uart0] basic# copy 0x100000 0x40100000 0x20000
-
- [16. Start atomthreads]
- [guest0/uart0] basic# go 0x100000
-
- [17. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0]
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: step 15 copies kern1.bin test case to 0x100000 instead of this you
- can use kern2.bin, ..., mutex1.bin, ..., etc. testcases. All testcases are
- loaded to NOR flash location 0x40100000 at 0x20000 offset. All testcases are
- compiled for 0x100000 location so you have to copy them to same location and
- you can test only one test case at a time. To try another test after running
- a particular test we have to reset the guest from Xvisor prompt using guest
- command after step 17 and do step 15 to step 17 for another testcase.)
- (Note: step 15 & step 16 assume that text base address for atomthreads
- binary is 0x100000. You can change this in atomthreads source and modify
- the above steps accordingly.)
diff --git a/tests/arm32/realview-pb-a8/atomthreads/nor_flash.list b/tests/arm32/realview-pb-a8/atomthreads/nor_flash.list
deleted file mode 100644
index b30d5025..00000000
--- a/tests/arm32/realview-pb-a8/atomthreads/nor_flash.list
+++ /dev/null
@@ -1,40 +0,0 @@
-0x40000000 ./firmware.bin
-0x40100000 ./kern1.bin
-0x40120000 ./kern2.bin
-0x40140000 ./kern3.bin
-0x40160000 ./kern4.bin
-0x40180000 ./mutex1.bin
-0x401A0000 ./mutex2.bin
-0x401C0000 ./mutex3.bin
-0x401E0000 ./mutex4.bin
-0x40200000 ./mutex5.bin
-0x40220000 ./mutex6.bin
-0x40240000 ./mutex7.bin
-0x40260000 ./mutex8.bin
-0x40280000 ./mutex9.bin
-0x402A0000 ./queue1.bin
-0x402C0000 ./queue2.bin
-0x402E0000 ./queue3.bin
-0x40300000 ./queue4.bin
-0x40320000 ./queue5.bin
-0x40340000 ./queue6.bin
-0x40360000 ./queue7.bin
-0x40380000 ./queue8.bin
-0x403A0000 ./queue9.bin
-0x403C0000 ./queue10.bin
-0x403E0000 ./sem1.bin
-0x40400000 ./sem2.bin
-0x40420000 ./sem3.bin
-0x40440000 ./sem4.bin
-0x40460000 ./sem5.bin
-0x40480000 ./sem6.bin
-0x404A0000 ./sem7.bin
-0x404C0000 ./sem8.bin
-0x404E0000 ./sem9.bin
-0x40500000 ./timer1.bin
-0x40520000 ./timer2.bin
-0x40540000 ./timer3.bin
-0x40560000 ./timer4.bin
-0x40580000 ./timer5.bin
-0x405A0000 ./timer6.bin
-0x405C0000 ./timer7.bin
diff --git a/tests/arm32/realview-pb-a8/atomthreads/qemu_test.tcl b/tests/arm32/realview-pb-a8/atomthreads/qemu_test.tcl
deleted file mode 100755
index af1a5d3d..00000000
--- a/tests/arm32/realview-pb-a8/atomthreads/qemu_test.tcl

+++ /dev/null
@@ -1,79 +0,0 @@

-#!/usr/bin/expect -f
-#/**
-# Copyright (c) 2011 Sanjeev Pandita.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file qemu_test.tcl
-# @author Sanjeev Pandita (san.p...@gmail.com)
-# @brief Automation script to test the atomthreads
-# */
-
-set qemu_img [lrange $argv 0 0]
-set xvisor_prompt "XVisor#"
-set arm_prompt "basic#"
-set atomthreads_test_case_list "kern1 kern2 kern3 kern4 mutex1 mutex2 mutex3 mutex4 mutex5 mutex6 mutex7 mutex8 mutex9 queue1 queue2 queue3 queue4 queue5 queue6 queue7 queue8 queue9 queue10 sem1 sem2 sem3 sem4 sem5 sem6 sem7 sem8 sem9 timer1 timer2 timer3 timer4 timer5 timer6 timer7"
-
-# start the test
-spawn qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel $qemu_img
-
-expect $xvisor_prompt
-
-send -- "guest kick guest0\r"
-expect $xvisor_prompt
-set guest_kick_out $expect_out(buffer)
-if { [string first "guest0: Kicked" $guest_kick_out] > -1 } {
- puts "\n :: GUEST KICK TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: GUEST KICK TESTCASE FAIL :: \n\n"
-}
-
-send -- "vserial bind guest0/uart0\r"
-expect $arm_prompt
-set vserial_bind_out $expect_out(buffer)
-if { [string first "ARM Realview PB-A8 Basic Firmware" $vserial_bind_out] > -1 } {
- puts "\n :: VSERIAL BIND KICK TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: VSERIAL BIND TESTCASE FAIL :: \n\n"
-}
-
-set address 0x40100000
-set test_case_cnt 0
-foreach item $atomthreads_test_case_list {
- #Append the every item to $text
- puts "Executing the test case :$item:\n"
- send "\033xq"
- expect $xvisor_prompt
- send -- "guest reset guest0;guest kick guest0; vserial bind guest0/uart0 \r"
- expect $arm_prompt
- set cpy_str [format "copy 0x100000 0x%x 0x20000\r" $address ]
- send -- "$cpy_str"
- expect $arm_prompt
- send -- "go 0x100000\r"
- expect "Reset your board !!!!!"
- set go_out $expect_out(buffer)
- if { [string first "SUCCESS" $go_out] > -1 } {
- puts "\n :: $item TESTCASE PASS :: \n\n"
- } else {
- puts "\n :: $item TESTCASE FAIL :: \n\n"
- }
-
- incr address 0x20000
-}
-
-send \003
-expect eof
-
diff --git a/tests/arm32/realview-pb-a8/basic/Makefile b/tests/arm32/realview-pb-a8/basic/Makefile
deleted file mode 100644
index 31e1ba3d..00000000
--- a/tests/arm32/realview-pb-a8/basic/Makefile

+++ /dev/null
@@ -1,55 +0,0 @@

-#/**
-# Copyright (c) 2012 Anup Patel.
-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile

-# @author Anup Patel (an...@brainfault.org)

-# @brief toplevel makefile to build firmware
-# */
-
-# Determine the build directory
-top_dir=$(CURDIR)/../../../..
-ifdef O
- build_dir=$(shell readlink -f $(O))
-else
- build_dir=$(top_dir)/build
-endif
-ifdef I
- install_dir=$(shell readlink -f $(I))
-else
- install_dir=$(top_dir)/install
-endif
-
-obj_dir=$(build_dir)/tests/arm32/realview-pb-a8/basic
-basic_dir=$(top_dir)/tests/common/basic
-arch_dir=$(top_dir)/tests/arm32/common/basic
-
-board_arch = v7
-board_text_start = 0x74000000
-board_objs = $(obj_dir)/arch_board.o \
- $(obj_dir)/pic/gic.o \
- $(obj_dir)/timer/sp804.o \
- $(obj_dir)/serial/pl01x.o \
- $(obj_dir)/sys/vminfo.o
-
-board_cppflags =
-board_cflags = -mtune=cortex-a8
-board_asflags = -mtune=cortex-a8
-board_ldflags =
-
-# Include common arch makefile for basic firmware
-include $(arch_dir)/Makefile.inc
diff --git a/tests/arm32/realview-pb-a8/basic/README b/tests/arm32/realview-pb-a8/basic/README
deleted file mode 100644
index 2233b2db..00000000
--- a/tests/arm32/realview-pb-a8/basic/README
+++ /dev/null
@@ -1,70 +0,0 @@
- Basic Firmware on Realview-PB-A8 Guest
-
-The basic firmware currently sets up PIC, Timer, and UART and emulates
-a dummy terminal which reponds to various commands. It also includes an
-extensive MMU test suite and dhrystone benchmark.
-
-Hardware features tested by Basic firmware:
- - Sensitive non-priviledged instructions
- - Virtual IRQs
- - Generic Interrupt Controller (GIC)
- - PrimeCell Dual-Mode Timer (SP804)
- - Serial Port (PL011)
-
-Please follow the steps below to build & run Basic firmware on Realview-PB-A8
-Guest with Xvisor running on QEMU Realview-PB-A8 Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v7 default settings]
- # make ARCH=arm generic-v7-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/realview-pb-a8/basic
-
- [6. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/realview-pb-a8
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/realview-pb-a8-guest.dtb ./tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts
- # cp -f ./build/tests/arm32/realview-pb-a8/basic/firmware.bin.patched ./build/disk/images/arm32/realview-pb-a8/firmware.bin
- # cp -f ./tests/arm32/realview-pb-a8/basic/nor_flash.list ./build/disk/images/arm32/realview-pb-a8/nor_flash.list
- # cp -f ./tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript ./build/disk/boot.xscript
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [7. Launch QEMU]
- # qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/arm-realview-pba8.dtb -initrd build/disk.img
-
- [8. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [9. Bind to virtual UART]
- XVisor# vserial bind guest0/uart0
-
- [10. Say 'hi' to Basic Firmware Code]
- [guest0/uart0] basic# hi
-
- [11. Say 'hello' to Basic Firmware Code]
- [guest0/uart0] basic# hello
-
- [12. Check various commands of Basic Firmware Code]
- [guest0/uart0] basic# help
-
- [13. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] basic#
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/realview-pb-a8/basic/arch_board.c b/tests/arm32/realview-pb-a8/basic/arch_board.c
deleted file mode 100644
index 7e8c7459..00000000
--- a/tests/arm32/realview-pb-a8/basic/arch_board.c
+++ /dev/null
@@ -1,523 +0,0 @@

-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_board.c

- * @author Jean-Christophe Dubois (j...@tribudubois.net)

- * @brief various platform specific functions
- */
-
-#include <arch_types.h>
-#include <arch_io.h>
-#include <arch_math.h>
-#include <arch_board.h>
-#include <arm_plat.h>
-#include <basic_stdio.h>
-#include <basic_string.h>
-#include <libfdt/libfdt.h>
-#include <libfdt/fdt_support.h>
-#include <pic/gic.h>
-#include <timer/sp804.h>
-#include <serial/pl01x.h>
-#include <sys/vminfo.h>
-
-void arch_board_reset(void)
-{
- arch_writel(0x0,
- (void *)(REALVIEW_SYS_BASE+ REALVIEW_SYS_RESETCTL_OFFSET));
- arch_writel(0x04,
- (void *)(REALVIEW_SYS_BASE+ REALVIEW_SYS_RESETCTL_OFFSET));
-}
-
-void arch_board_init(void)
-{
- /* Unlock Lockable reigsters */
- arch_writel(REALVIEW_SYS_LOCKVAL,
- (void *)(REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET));
-}
-
-char *arch_board_name(void)
-{
- return "ARM Realview-PB-A8";
-}
-
-physical_addr_t arch_board_ram_start(void)
-{
- return (physical_addr_t)vminfo_ram_base(REALVIEW_VMINFO_BASE, 0);
-}
-
-physical_size_t arch_board_ram_size(void)
-{
- return (physical_size_t)vminfo_ram_size(REALVIEW_VMINFO_BASE, 0);
-}
-
-void arch_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz)
-{
- basic_strcpy(cmdline, "root=/dev/ram rw earlyprintk "
- "earlycon=pl011,0x10009000 console=ttyAMA0");
-}
-
-void arch_board_fdt_fixup(void *fdt_addr)
-{
- u32 vals[5];
- char str[64];
- u32 intc_phandle;
- int rc, poff, noff;
-
- poff = fdt_path_offset(fdt_addr, "/interrupt-controller@1e000000");
- if (poff < 0) {
- basic_printf("%s: failed to find nodeoffset of %s node\n",
- __func__, "/interrupt-controller@1e000000");
- return;
- }
-
- intc_phandle = fdt_get_phandle(fdt_addr, poff);
- if (!intc_phandle) {
- basic_printf("%s: failed to find phandle for %s node\n",
- __func__, "/interrupt-controller@1e000000");
- return;
- }
-
- poff = fdt_path_offset(fdt_addr, "/");
- if (poff < 0) {
- basic_printf("%s: failed to find nodeoffset of %s node\n",
- __func__, "/");
- return;
- }
-
- poff = fdt_add_subnode(fdt_addr, poff, "virt");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virt", "/");
- return;
- }
-
- basic_strcpy(str, "simple-bus");
- rc = fdt_setprop(fdt_addr, poff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(intc_phandle);
- rc = fdt_setprop(fdt_addr, poff, "interrupt-parent",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupt-parent", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#address-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#address-cells", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#size-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#size-cells", "virt");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, poff, "ranges", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "ranges", "virt");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_net");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_net", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20100000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(2);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_net");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_net");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_block");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_block", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20200000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(3);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_block");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_block");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_console");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_console", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20300000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(9);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_console");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_console");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_rpmsg");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_rpmsg", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20400000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(25);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_rpmsg");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_rpmsg");
- return;
- }
-}
-
-physical_addr_t arch_board_autoexec_addr(void)
-{
- return (REALVIEW_FLASH0_BASE + 0xFF000);
-}
-
-u32 arch_board_boot_delay(void)
-{
- return vminfo_boot_delay(REALVIEW_VMINFO_BASE);
-}
-
-u32 arch_board_iosection_count(void)
-{
- return 19;
-}
-
-physical_addr_t arch_board_iosection_addr(int num)
-{
- physical_addr_t ret = 0;
-
- switch (num) {
- case 0:
- ret = REALVIEW_SYS_BASE;

- break;
- case 1:

- ret = REALVIEW_GIC_CPU_BASE;

- break;
- case 2:

- ret = REALVIEW_VMINFO_BASE;

- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:

- case 8:
- case 9:
- case 10:
- case 11:
- case 12:

- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- ret = REALVIEW_FLASH0_BASE + (num - 3) * 0x100000;
- break;
- default:
- while (1);
- break;
- }
-
- return ret;
-}
-
-u32 arch_board_pic_nr_irqs(void)
-{
- return NR_IRQS_PBA8;
-}
-
-int arch_board_pic_init(void)

-{
- int rc;
-
- /*

- * Initialize Generic Interrupt Controller
- */
- rc = gic_dist_init(0, REALVIEW_GIC_DIST_BASE, IRQ_PBA8_GIC_START);

- if (rc) {
- return rc;
- }

- rc = gic_cpu_init(0, REALVIEW_GIC_CPU_BASE);

- if (rc) {
- return rc;
- }
-

- return 0;
-}
-
-u32 arch_board_pic_active_irq(void)
-{
- return gic_active_irq(0);
-}
-
-int arch_board_pic_ack_irq(u32 irq)

-{
- return 0;
-}
-

-int arch_board_pic_eoi_irq(u32 irq)
-{
- return gic_eoi_irq(0, irq);
-}
-
-int arch_board_pic_mask(u32 irq)
-{
- return gic_mask(0, irq);
-}
-
-int arch_board_pic_unmask(u32 irq)
-{
- return gic_unmask(0, irq);
-}
-
-void arch_board_timer_enable(void)
-{
- return sp804_enable();
-}
-
-void arch_board_timer_disable(void)
-{
- return sp804_disable();
-}
-
-u64 arch_board_timer_irqcount(void)
-{
- return sp804_irqcount();
-}
-
-u64 arch_board_timer_irqdelay(void)
-{
- return sp804_irqdelay();
-}
-
-u64 arch_board_timer_timestamp(void)
-{
- return sp804_timestamp();
-}
-
-void arch_board_timer_change_period(u32 usecs)
-{
- return sp804_change_period(usecs);
-}
-
-int arch_board_timer_init(u32 usecs)
-{
- u32 val, irq;
- u64 counter_mult, counter_shift, counter_mask;
-
- counter_mask = 0xFFFFFFFFULL;
- counter_shift = 20;
- counter_mult = ((u64)1000000) << counter_shift;
- counter_mult += (((u64)1000) >> 1);
- counter_mult = arch_udiv64(counter_mult, ((u64)1000));
-
- irq = IRQ_PBA8_TIMER0_1;
-
- /* set clock frequency:
- * REALVIEW_REFCLK is 32KHz
- * REALVIEW_TIMCLK is 1MHz
- */
- val = arch_readl((void *)REALVIEW_SCTL_BASE) | (REALVIEW_TIMCLK << 1);
- arch_writel(val, (void *)REALVIEW_SCTL_BASE);
-
- return sp804_init(usecs, REALVIEW_TIMER0_1_BASE, irq,
- counter_mask, counter_mult, counter_shift);
-}
-
-#define PBA8_UART_BASE 0x10009000
-#define PBA8_UART_TYPE PL01X_TYPE_1
-#define PBA8_UART_INCLK 24000000
-#define PBA8_UART_BAUD 115200
-
-int arch_board_serial_init(void)
-{
- pl01x_init(PBA8_UART_BASE,
- PBA8_UART_TYPE,
- PBA8_UART_BAUD,
- PBA8_UART_INCLK);

-
- return 0;
-}
-

-void arch_board_serial_putc(char ch)
-{
- if (ch == '\n') {
- pl01x_putc(PBA8_UART_BASE, PBA8_UART_TYPE, '\r');
- }
- pl01x_putc(PBA8_UART_BASE, PBA8_UART_TYPE, ch);
-}
-
-bool arch_board_serial_can_getc(void)
-{
- return pl01x_can_getc(PBA8_UART_BASE, PBA8_UART_TYPE);
-}
-
-char arch_board_serial_getc(void)
-{
- char ch = pl01x_getc(PBA8_UART_BASE, PBA8_UART_TYPE);
- if (ch == '\r') {
- ch = '\n';
- }
- arch_board_serial_putc(ch);
- return ch;
-}
diff --git a/tests/arm32/realview-pb-a8/basic/arm_plat.h b/tests/arm32/realview-pb-a8/basic/arm_plat.h
deleted file mode 100644
index ac58c61e..00000000
--- a/tests/arm32/realview-pb-a8/basic/arm_plat.h
+++ /dev/null
@@ -1,330 +0,0 @@

-/**
- * Copyright (c) 2011 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arm_plat.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM platform configuration
- */
-#ifndef _ARM_PLAT_H__
-#define _ARM_PLAT_H__
-
-/*
- * Peripheral addresses
- */
-#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
-#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
-#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
-#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
-#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
-#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
-#define REALVIEW_SCTL_BASE 0x1001A000 /* System Controller */
-#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
-#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
-#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */
-#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */
-#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */
-#define REALVIEW_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_FLASH0_BASE 0x40000000
-#define REALVIEW_FLASH0_SIZE SZ_64M
-#define REALVIEW_FLASH1_BASE 0x44000000
-#define REALVIEW_FLASH1_SIZE SZ_64M
-#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
-#define REALVIEW_USB_BASE 0x4F000000 /* USB */
-#define REALVIEW_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
-#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */
-#define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
-#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
-
-#define REALVIEW_SYS_PLD_CTRL1 0x74
-
-/*
- * PCI regions
- */
-#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */
-#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
-#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
-
-#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */
-#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */
-#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */
-
-/*
- * Memory definitions
- */
-#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */
-#define REALVIEW_BOOT_ROM_HI 0x30000000
-#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
-#define REALVIEW_BOOT_ROM_SIZE SZ_64M
-
-#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
-#define REALVIEW_SSRAM_SIZE SZ_2M
-
-/*
- * SDRAM
- */
-#define REALVIEW_SDRAM_BASE 0x00000000
-
-/*
- * Logic expansion modules
- *
- */
-#define IRQ_PBA8_GIC_START 32
-
-/*
- * PB-A8 on-board gic irq sources
- */
-#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
-#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
-#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
-#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
-#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
-#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
-#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
-#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
-#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
- /* 9 reserved */
-#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
-#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
-#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
-#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
-#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
-#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
-#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
-#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
-#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
-#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
-#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
-#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
-#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
-#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
-#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
-#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
-#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
-#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
-#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
-#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
-#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
-#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
-
-#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */
-
-/* ... */
-#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
-#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
-#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
-#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
-
-#define IRQ_PBA8_SMC -1
-#define IRQ_PBA8_SCTL -1
-
-#define NR_GIC_PBA8 1
-
-/*
- * Only define NR_IRQS if less than NR_IRQS_PBA8
- */
-#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64)
-
-/* ------------------------------------------------------------------------
- * RealView Registers

- * ------------------------------------------------------------------------
- *
- */

-#define REALVIEW_SYS_ID_OFFSET 0x00
-#define REALVIEW_SYS_SW_OFFSET 0x04
-#define REALVIEW_SYS_LED_OFFSET 0x08
-#define REALVIEW_SYS_OSC0_OFFSET 0x0C
-
-#define REALVIEW_SYS_OSC1_OFFSET 0x10
-#define REALVIEW_SYS_OSC2_OFFSET 0x14
-#define REALVIEW_SYS_OSC3_OFFSET 0x18
-#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
-
-#define REALVIEW_SYS_LOCK_OFFSET 0x20
-#define REALVIEW_SYS_100HZ_OFFSET 0x24
-#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
-#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
-#define REALVIEW_SYS_FLAGS_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
-#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
-#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
-#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
-#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
-#define REALVIEW_SYS_PCICTL_OFFSET 0x44
-#define REALVIEW_SYS_MCI_OFFSET 0x48
-#define REALVIEW_SYS_FLASH_OFFSET 0x4C
-#define REALVIEW_SYS_CLCD_OFFSET 0x50
-#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
-#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
-#define REALVIEW_SYS_24MHz_OFFSET 0x5C
-#define REALVIEW_SYS_MISC_OFFSET 0x60
-#define REALVIEW_SYS_IOSEL_OFFSET 0x70
-#define REALVIEW_SYS_PROCID_OFFSET 0x84
-#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
-#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
-#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
-#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
-#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
-
-#define REALVIEW_SYS_BASE 0x10000000
-#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
-#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
-#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
-#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
-#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
-
-#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
-#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
-#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
-#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
-#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
-#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
-#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
-#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
-#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
-#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
-#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
-#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
-#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
-#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
-#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
-#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
-#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
-#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
-#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
-#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
-#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
-#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
-#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
-#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
-#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
-#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
-
-#define REALVIEW_SYS_CTRL_LED (1 << 0)
-
-/* ------------------------------------------------------------------------
- * RealView control registers

- * ------------------------------------------------------------------------
- */
-
-/*

- * REALVIEW_IDFIELD

- *
- * 31:24 = manufacturer (0x41 = ARM)
- * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
- * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
- * 11:4 = build value
- * 3:0 = revision number (0x1 = rev B (AHB))
- */
-
-/*

- * REALVIEW_SYS_LOCK

- * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
- * SYS_CLD, SYS_BOOTCS
- */

-#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
-#define REALVIEW_SYS_LOCKVAL 0xA05F
-#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
-
-/*
- * REALVIEW_SYS_FLASH
- */
-#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
-
-/*
- * REALVIEW_INTREG

- * - used to acknowledge and control MMCI and UART interrupts
- */

-#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
-#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
-#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */

- /* write 1 to acknowledge and clear */

-#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
-#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
-
-/*
- * LED settings, bits [7:0]
- */
-#define REALVIEW_SYS_LED0 (1 << 0)
-#define REALVIEW_SYS_LED1 (1 << 1)
-#define REALVIEW_SYS_LED2 (1 << 2)
-#define REALVIEW_SYS_LED3 (1 << 3)
-#define REALVIEW_SYS_LED4 (1 << 4)
-#define REALVIEW_SYS_LED5 (1 << 5)
-#define REALVIEW_SYS_LED6 (1 << 6)
-#define REALVIEW_SYS_LED7 (1 << 7)
-
-#define ALL_LEDS 0xFF
-
-#define LED_BANK REALVIEW_SYS_LED
-
-/*
- * Control registers
- */
-#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
-#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
-#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
-#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
-
-/*
- * Clean base - dummy
- *
- */
-#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
-
-/*
- * System controller bit assignment
- */
-#define REALVIEW_REFCLK 0
-#define REALVIEW_TIMCLK 1
-
-#define REALVIEW_TIMER1_EnSel 15
-#define REALVIEW_TIMER2_EnSel 17
-#define REALVIEW_TIMER3_EnSel 19
-#define REALVIEW_TIMER4_EnSel 21
-
-#define MAX_TIMER 2
-#define MAX_PERIOD 699050
-#define TICKS_PER_uSEC 1
-
-/*
- * These are useconds NOT ticks.
- *
- */
-#define mSEC_1 1000
-#define mSEC_5 (mSEC_1 * 5)
-#define mSEC_10 (mSEC_1 * 10)
-#define mSEC_25 (mSEC_1 * 25)
-#define SEC_1 (mSEC_1 * 1000)
-
-#define REALVIEW_CSR_BASE 0x10000000
-#define REALVIEW_CSR_SIZE 0x10000000
-
-/*
- * Defines required by basic firmware
- */
-#define REALVIEW_VMINFO_BASE 0x20000000
-
-#endif
diff --git a/tests/arm32/realview-pb-a8/basic/emulate.sh b/tests/arm32/realview-pb-a8/basic/emulate.sh
deleted file mode 100755
index 735dbf73..00000000
--- a/tests/arm32/realview-pb-a8/basic/emulate.sh
+++ /dev/null
@@ -1,53 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2011 Jim Huang.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file emulate.sh
-# @author Jim Huang (js...@0xlab.org)
-# @brief execuate and validate Xvisor in QEMU
-
-CUR=`dirname $0`
-CMDS=`sed -n -e 's/\(^[^#].*\)/\1/p' test.script`
-
-emulate () {
- qemu-system-arm \
- -M realview-pb-a8 \
- -m 512M \
- -kernel $1 \
- -serial stdio \
- -parallel none \
- -display none \
- -monitor null <&0 & pid=$!
-}
-
-xvisor_qemu () {
- emulate $1 <<< "
-$CMDS
-"
- echo "Executing Xvisor in QEMU..."
- (sleep $2; kill $pid; sleep 1; kill -KILL $pid)& timer=$!
- if ! wait $pid; then
- kill $timer 2>/dev/null
- echo
- echo "Xvisor failed to execute in $2 seconds, giving up."
- exit -1
- fi
- kill $timer
-}
-
-xvisor_qemu $1 15
diff --git a/tests/arm32/realview-pb-a8/basic/gic_config.h b/tests/arm32/realview-pb-a8/basic/gic_config.h
deleted file mode 100644
index 3d4fc3dc..00000000
--- a/tests/arm32/realview-pb-a8/basic/gic_config.h
+++ /dev/null
@@ -1,33 +0,0 @@

-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file gic_config.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM Generic Interrupt Controller configuration header
- */
-#ifndef _GIC_CONFIG_H__
-#define _GIC_CONFIG_H__
-
-#include <arm_plat.h>
-
-#define GIC_CPU_BASE REALVIEW_PBA8_GIC_CPU_BASE
-#define GIC_DIST_BASE REALVIEW_PBA8_GIC_DIST_BASE
-#define GIC_NR_IRQS NR_IRQS_PBA8
-#define GIC_MAX_NR NR_GIC_PBA8
-
-#endif
diff --git a/tests/arm32/realview-pb-a8/basic/nor_flash.list b/tests/arm32/realview-pb-a8/basic/nor_flash.list
deleted file mode 100644
index 4f38aa4c..00000000
--- a/tests/arm32/realview-pb-a8/basic/nor_flash.list
+++ /dev/null
@@ -1 +0,0 @@
-0x40000000 ./firmware.bin
diff --git a/tests/arm32/realview-pb-a8/basic/qemu_test.tcl b/tests/arm32/realview-pb-a8/basic/qemu_test.tcl
deleted file mode 100755
index 61816db3..00000000
--- a/tests/arm32/realview-pb-a8/basic/qemu_test.tcl
+++ /dev/null
@@ -1,244 +0,0 @@
-#!/usr/bin/expect -f
-#/**
-# Copyright (c) 2011 Sanjeev Pandita.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file qemu_test.tcl
-# @author Sanjeev Pandita (san.p...@gmail.com)
-# @brief Automation script to test the Xvisor commands and Basic Firmware
-# */
-
-set qemu_img [lrange $argv 0 0]
-set xvisor_prompt "XVisor#"
-set arm_prompt "basic#"
-
-# start the test
-spawn qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel $qemu_img
-
-expect $xvisor_prompt
-send -- "help\r"
-expect $xvisor_prompt
-set help_out $expect_out(buffer)
-if { [string compare $help_out ""] == 0 } {
-# only checks Empty lines
- puts "\n :: HELP TESTCASE FAIL :: \n\n"
-
-} else {
-puts "\n :: HELP TESTCASE PASS :: \n\n"
-}
-
-send -- "version\r"
-expect $xvisor_prompt
-
-set version_out $expect_out(buffer)
-if { [string first "Version" $version_out] > -1 } {
- puts "\n :: Version TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: Version TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "reset\r"
-expect $xvisor_prompt
-
-set reset_out $expect_out(buffer)
-if { [string first "init: board final" $reset_out] > -1 } {
- puts "\n :: RESET TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: RESET TESTCASE FAIL :: \n\n"
-}
-
-send -- "host help\r"
-expect $xvisor_prompt
-
-set host_help_out $expect_out(buffer)
-if { [string first "host help" $host_help_out] > -1 } {
- puts "\n :: HOST HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "host vapool stats\r"
-expect $xvisor_prompt
-set host_vapool_stats_out $expect_out(buffer)
-if { [string first "Total Pages" $host_vapool_stats_out] > -1 } {
- puts "\n :: HOST VAPOOL STATS TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST VAPOOL STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "host vapool bitmap\r"
-expect $xvisor_prompt
-set host_vapool_bitmap_out $expect_out(buffer)
-if { [string first "1 : used" $host_vapool_bitmap_out] > -1 } {
- puts "\n :: HOST VAPOOL BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST VAPOOL BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "host ram stats\r"
-expect $xvisor_prompt
-set host_ram_stats_out $expect_out(buffer)
-if { [string first "Total Frames " $host_ram_stats_out] > -1 } {
- puts "\n :: HOST RAM STATS TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST RAM STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "host ram bitmap\r"
-expect $xvisor_prompt
-set host_ram_bitmap_out $expect_out(buffer)
-if { [string first "11111111111" $host_ram_bitmap_out] > -1 } {
- puts "\n :: HOST RAM BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST RAM BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree help\r"
-expect $xvisor_prompt
-set devtree_help_out $expect_out(buffer)
-if { [string first "devtree print" $devtree_help_out] > -1 } {
- puts "\n :: DEVTREE HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree node show /\r"
-expect $xvisor_prompt
-set devtree_node_show_out $expect_out(buffer)
-if { [string first "vmm" $devtree_node_show_out] > -1 } {
- puts "\n :: DEVTREE NODE SHOW TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE NODE SHOW TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree node dump /\r"
-expect $xvisor_prompt
-set devtree_node_dump_out $expect_out(buffer)
-if { [string first "vmm" $devtree_node_dump_out] > -1 } {
- puts "\n :: DEVTREE NODE DUMP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE NODE DUMP TESTCASE FAIL :: \n\n"
-}
-
-send -- "guest kick guest0\r"
-expect $xvisor_prompt
-set guest_kick_out $expect_out(buffer)
-if { [string first "guest0: Kicked" $guest_kick_out] > -1 } {
- puts "\n :: GUEST KICK TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: GUEST KICK TESTCASE FAIL :: \n\n"
-}
-
-send -- "vserial bind guest0/uart0\r"
-expect $arm_prompt
-set vserial_bind_out $expect_out(buffer)
-if { [string first "ARM Realview PB-A8 Basic Firmware" $vserial_bind_out] > -1 } {
- puts "\n :: VSERIAL BIND TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: VSERIAL BIND TESTCASE FAIL :: \n\n"
-}
-
-send -- "hi\r"
-expect $arm_prompt
-set hi_out $expect_out(buffer)
-if { [string first "hello" $hi_out] > -1 } {
- puts "\n :: HI TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HI TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "hello\r"
-expect $arm_prompt
-set hello_out $expect_out(buffer)
-if { [string first "hi" $hi_out] > -1 } {
- puts "The hello Command passed \n :: HELLO TESTCASE PASS :: \n\n"
-} else {
- puts "The hello Command Failed \n :: HELLO TESTCASE FAIL :: \n\n"
-}
-
-send -- "help\r"
-expect $arm_prompt
-set help_out $expect_out(buffer)
-if { [string first "reset" $help_out] > -1 } {
- puts "\n :: HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_setup\r"
-expect $arm_prompt
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-if { [string first "MMU Enabled" $mmu_state_out] > -1 } {
- puts "\n :: MMU SETUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU SETUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_cleanup\r"
-expect $arm_prompt
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-if { [string first "MMU Disabled" $mmu_state_out] > -1 } {
- puts "\n :: MMU CLEANUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU CLEANUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_test\r"
-expect $arm_prompt
-set mmu_test_out $expect_out(buffer)
-set first_fail [string first "Fail : 0" $mmu_test_out]
-set last_fail [string last "Fail : 0" $mmu_test_out]
-if { $last_fail > $first_fail } {
- puts "\n :: MMU TEST TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU TEST TESTCASE FAIL :: \n\n"
-}
-
-send -- "timer\r"
-expect $arm_prompt
-set timer_out $expect_out(buffer)
-if { [string first "Time Stamp:" $timer_out] > -1 } {
- puts "\n :: TIMER TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: TIMER TESTCASE FAIL :: \n\n"
-}
-
-send -- "dhrystone\r"
-expect $arm_prompt
-set dhrystone_out $expect_out(buffer)
-if { [string first "Dhrystones MIPS:" $dhrystone_out] > -1 } {
- puts "\n :: DHRYSTONE TESTCASE PASS :: \n\n"
- set temp_var [string last ":" $dhrystone_out]
- set temp_var [expr $temp_var + 25 ]
- set DMIPS [string range $dhrystone_out $temp_var end ]
- puts "DMIPS is $DMIPS"
-} else {
- puts "\n :: DHRYSTONE TESTCASE FAIL :: \n\n"
-}
-
-send -- "\n"
-
-expect "#"
-send \003
-expect eof
-
diff --git a/tests/arm32/realview-pb-a8/linux/README b/tests/arm32/realview-pb-a8/linux/README
deleted file mode 100644
index 6a1e5287..00000000
--- a/tests/arm32/realview-pb-a8/linux/README
+++ /dev/null
@@ -1,101 +0,0 @@
- Linux on Xvisor Realview-PB-A8 Guest
-
-Linux is a computer operating system which is based on free and open source
-software. the underlying source code can be used, freely modified, and
-redistributed, both commercially and non-commercially, by anyone under
-licenses such as the GNU General Public License. For more information on
-Linux read the wiki page http://en.wikipedia.org/wiki/Linux
-
-Linux already contains a support for Realview-PB-A8 Board. We can use
-this kernel unmodified to run it as a xvisor guest. We have also provide
-Realview-PB-A8 defconfig for various linux kernel versions for ease in
-building kernel. To obtain Linux kernel sources visit the following
-url: http://www.kernel.org
-
-Follow the steps below to build & run Linux kernel with Busybox RootFS on
-Realview-PB-A8 Guest with Xvisor running on QEMU Realview-PB-A8 Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v7 default settings]
- # make ARCH=arm generic-v7-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/realview-pb-a8/basic
-
- [6. GoTo Linux source directory]
- # cd <linux_source_directory>
-
- [7. Configure Linux in build directory]
- # sed -i 's/0xff800000UL/0xff000000UL/' arch/arm/include/asm/pgtable.h
- # cp arch/arm/configs/realview_defconfig arch/arm/configs/tmp-realview-pb-a8_defconfig
- # <xvisor_source_directory>/tests/common/scripts/update-linux-defconfig.sh -p arch/arm/configs/tmp-realview-pb-a8_defconfig -f <xvisor_source_directory>/tests/arm32/realview-pb-a8/linux/linux_extra.config
- # make O=<linux_build_directory> ARCH=arm tmp-realview-pb-a8_defconfig
-
- [8. Build Linux in build directory]
- # make O=<linux_build_directory> ARCH=arm Image dtbs
-
- [9. Patch Linux kernel to replace sensitive non-priviledged instructions]
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f <linux_build_directory>/vmlinux | <xvisor_source_directory>/build/tools/cpatch/cpatch32 <linux_build_directory>/vmlinux 0
-
- [10. Extract patched Linux kernel image]
- # ${CROSS_COMPILE}objcopy -O binary <linux_build_directory>/vmlinux <linux_build_directory>/arch/arm/boot/Image
-
- [11. Create BusyBox RAMDISK to be used as RootFS for Linux kernel]
- (Note: For subsequent steps, we will assume that your RAMDISK is located at <busybox_rootfs_directory>/rootfs.img)
- (Note: Please refer tests/common/busybox/README.md for creating rootfs.img using BusyBox)
-
- [12. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [13. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/realview-pb-a8
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/realview-pb-a8-guest.dtb ./tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts
- # cp -f ./build/tests/arm32/realview-pb-a8/basic/firmware.bin.patched ./build/disk/images/arm32/realview-pb-a8/firmware.bin
- # cp -f ./tests/arm32/realview-pb-a8/linux/nor_flash.list ./build/disk/images/arm32/realview-pb-a8/nor_flash.list
- # cp -f ./tests/arm32/realview-pb-a8/linux/cmdlist ./build/disk/images/arm32/realview-pb-a8/cmdlist
- # cp -f ./tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript ./build/disk/boot.xscript
- # cp -f <linux_build_directory>/arch/arm/boot/Image ./build/disk/images/arm32/realview-pb-a8/Image
- # cp -f <linux_build_directory>/arch/arm/boot/dts/arm-realview-pba8.dtb ./build/disk/images/arm32/realview-pb-a8/arm-realview-pba8.dtb
- # cp -f <busybox_rootfs_directory>/rootfs.img ./build/disk/images/arm32/realview-pb-a8/rootfs.img
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [14. Launch QEMU]
- # qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/arm-realview-pba8.dtb -initrd build/disk.img
-
- [15. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [16. Bind to virtual UART0 of Linux Guest]
- XVisor# vserial bind guest0/uart0
-
- [17. Copy linux from NOR flash to RAM and start linux booting from RAM]
- [guest0/uart0] basic# autoexec
- (Note: "autoexec" is a short-cut command)
- (Note: The <xvisor_source_directory>/tests/arm32/realview-pb-a8/linux/cmdlist
- file which we have added to guest NOR flash contains set of commands for booting
- linux from NOR flash)
-
- [18. Wait for Linux prompt to come-up and then try out some commands]
- [guest0/uart0] / # ls
-
- [19. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] / #
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/realview-pb-a8/linux/cmdlist b/tests/arm32/realview-pb-a8/linux/cmdlist
deleted file mode 100644
index d5885806..00000000
--- a/tests/arm32/realview-pb-a8/linux/cmdlist
+++ /dev/null
@@ -1,4 +0,0 @@
-copy 0x70008000 0x40100000 0x16F0000
-copy 0x72000000 0x417F0000 0x10000
-copy 0x72100000 0x41800000 0x800000
-start_linux_fdt 0x70008000 0x72000000 0x72100000 0x800000
diff --git a/tests/arm32/realview-pb-a8/linux/linux_extra.config b/tests/arm32/realview-pb-a8/linux/linux_extra.config
deleted file mode 100644
index 735803bf..00000000
--- a/tests/arm32/realview-pb-a8/linux/linux_extra.config
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_NO_HZ_FULL=n
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NEON=y
-CONFIG_DRM=n
diff --git a/tests/arm32/realview-pb-a8/linux/nor_flash.list b/tests/arm32/realview-pb-a8/linux/nor_flash.list
deleted file mode 100644
index 3d154198..00000000
--- a/tests/arm32/realview-pb-a8/linux/nor_flash.list
+++ /dev/null
@@ -1,5 +0,0 @@
-0x40000000 ./firmware.bin
-0x400FF000 ./cmdlist
-0x40100000 ./Image
-0x417F0000 ./arm-realview-pba8.dtb
-0x41800000 ./rootfs.img
diff --git a/tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts b/tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts
deleted file mode 100644
index 90e2ad15..00000000
--- a/tests/arm32/realview-pb-a8/realview-pb-a8-guest.dts

+++ /dev/null
@@ -1,414 +0,0 @@

-
-/dts-v1/;
-
-/ {
- model = "realview-pb-a8";
- device_type = "guest";
- psci_version = <2>;
-
- aliases {
- mem0 = &MEM0;
- net0 = &NET0;
- net1 = &NET1;
- disk0 = &DISK0;
- };
-
- vcpu_template {
- device_type = "vcpu";
- compatible = "armv7a,cortex-a8";
- start_pc = <0x40000000>;
- };
-
- aspace {
- guest_irq_count = <2048>;
-
- mem1 {
- manifest_type = "alias";
- address_type = "memory";
- guest_physical_addr = <0x00000000>;
- alias_physical_addr = <0x70000000>;
- physical_size = <0x06000000>;
- device_type = "ram";
- };
-
- MEM0: mem0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x70000000>;
- physical_size = <0x00000000>; /* Override this before guest creation */
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_ram";
- };
-
- sysctl {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10000000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "realview,pb-a8";
- mux_in_irq = <1200 1201>;
- mux_out_irq = <1202>;
- };
-
- sysctrl0 { /* No SP810 sysctrl */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10001000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- i2c { /* No I2C */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10002000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- aaci { /* No Audio Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10004000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mmc0 { /* No Multimedia Card Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10005000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- kmi0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10006000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,keyboard";
- interrupts = <52>;
- };
-
- kmi1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10007000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,mouse";

- interrupts = <53>;
- };
-

- uart0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10009000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <44>;
- };
-
- uart1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000A000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;

- interrupts = <45>;
- };
-

- uart2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000B000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;

- interrupts = <46>;
- };
-

- uart3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000C000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;

- interrupts = <47>;
- };
-

- ssp0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000D000>;
- physical_size = <0x1000>;
- device_type = "spi-host";
- compatible = "primecell,arm,pl022";
- interrupts = <43>;
- };
-
- sci0 { /* No Smart card controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000E000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- watchdog0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000F000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- watchdog {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10010000>;
- physical_size = <0x1000>;
- device_type = "watchdog";
- compatible = "primecell,sp805";

- interrupts = <32>;
- };
-

- timer0_1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10011000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <36>;
- };
-
- timer2_3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10012000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <37>;
- };
-
- gpio0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10013000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <0 0 0 0 0 0 0 0>;
- gpio_in_irq = <1400 1401 1402 1403 1404 1405 1406 1407>;
- gpio_out_irq = <1408 1409 1410 1411 1412 1413 1414 1415>;
- interrupts = <38>;
- };
-
- gpio1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10014000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <0 0 0 0 0 0 0 0>;
- gpio_in_irq = <1300 1301 1302 1303 1304 1305 1306 1307>;
- gpio_out_irq = <1308 1309 1310 1311 1312 1313 1314 1315>;
- interrupts = <39>;
- };
-
- gpio2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10015000>;
- physical_size = <0x1000>;
- device_type = "gpio";
- compatible = "primecell,pl061";
- gpio_in_invert = <1 0 0 0 0 0 0 0>;
- gpio_in_irq = <1201 1200 1202 1203 1204 1205 1206 1207>;
- gpio_out_irq = <1208 1209 1210 1211 1212 1213 1214 1215>;
- interrupts = <40>;
- };
-
- rtc0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10017000>;
- physical_size = <0x1000>;
- device_type = "rtc";
- compatible = "primecell,pl031";
- interrupts = <42>;
- };
-
- timer4_5 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10018000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <73>;
- };
-
- timer6_7 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10019000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";

- interrupts = <74>;
- };
-

- sysctrl1 { /* No SP810 sysctrl */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1001A000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- clcd {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10020000>;
- physical_size = <0x1000>;
- device_type = "display";
- compatible = "primecell,pl111";
- interrupts = <55>;
- };
-
- dmac { /* No DMA Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10030000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- smc { /* No SMC */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E1000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gic0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1E000000>;
- physical_size = <0x2000>;
- device_type = "pic";
- compatible = "realview,gic";
- parent_irq = <6>;
- };
-
- vminfo {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "sys";
- compatible = "vminfo-0.1";
- guest_physical_addr = <0x20000000>;
- physical_size = <0x1000>;
- ram0_base = <0x70000000>;
- };
-
- NET0: virtio-net0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <1>;
- guest_physical_addr = <0x20100000>;
- physical_size = <0x1000>;
- switch = ""; /* Override this before guest creation */
- interrupts = <34>;
- };
-
- DISK0: virtio-blk0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <2>;
- guest_physical_addr = <0x20200000>;
- physical_size = <0x1000>;
- blkdev = ""; /* Override this before guest creation */
- interrupts = <35>;
- };
-
- virtio-con0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <3>;
- guest_physical_addr = <0x20300000>;
- physical_size = <0x1000>;
- interrupts = <41>;
- };
-
- virtio-rpmsg0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <7>;
- guest_physical_addr = <0x20400000>;
- physical_size = <0x1000>;
- interrupts = <57>;
- node_ns_name = "rpmsg_chrdev";
- };
-
- nor_flash0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x40000000>;
- physical_size = <0x02000000>;
- device_type = "alloced_rom";
- align_order = <21>; /* Align alloced memory to 2MB */
- };
-
- NET1: lan9118 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4E000000>;
- physical_size = <0x10000>;
- device_type = "nic";
- compatible = "smsc,lan9118";
- switch = ""; /* Override this before guest creation */
- interrupts = <60>;
- };
-
- usb { /* No USB */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4F000000>;
- physical_size = <0x20000>;
- device_type = "misc";
- compatible = "zero";
- };
- };
-};
diff --git a/tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript b/tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript
deleted file mode 100644
index 35e9e03d..00000000
--- a/tests/arm32/realview-pb-a8/xscript/one_guest_pb-a8.xscript
+++ /dev/null
@@ -1,8 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/realview-pb-a8-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/realview-pb-a8/nor_flash.list
diff --git a/tests/arm32/realview-pb-a8/xscript/two_guest_pb-a8.xscript b/tests/arm32/realview-pb-a8/xscript/two_guest_pb-a8.xscript
deleted file mode 100644
index b4141caa..00000000
--- a/tests/arm32/realview-pb-a8/xscript/two_guest_pb-a8.xscript
+++ /dev/null
@@ -1,17 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/realview-pb-a8-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/realview-pb-a8/nor_flash.list
-
-# Load guest1 device tree from file
-vfs guest_fdt_load guest1 /images/arm32/realview-pb-a8-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest1
-guest create guest1
-
-# Load guest1 images
-vfs guest_load_list guest1 /images/arm32/realview-pb-a8/nor_flash.list
diff --git a/tests/arm32/sabrelite/basic/Makefile b/tests/arm32/sabrelite/basic/Makefile
deleted file mode 100644
index ef6f9c09..00000000
--- a/tests/arm32/sabrelite/basic/Makefile

+++ /dev/null
@@ -1,57 +0,0 @@

-#/**
-# Copyright (c) 2012 Sukanto Ghosh.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile
-# @author Sukanto Ghosh (sukant...@gmail.com)
-# @brief toplevel makefile to build firmware
-# */
-
-# Determine the build directory
-top_dir=$(CURDIR)/../../../..
-ifdef O
- build_dir=$(shell readlink -f $(O))
-else
- build_dir=$(top_dir)/build
-endif
-ifdef I
- install_dir=$(shell readlink -f $(I))
-else
- install_dir=$(top_dir)/install
-endif
-
-obj_dir=$(build_dir)/tests/arm32/sabrelite/basic
-basic_dir=$(top_dir)/tests/common/basic
-arch_dir=$(top_dir)/tests/arm32/common/basic
-
-board_arch = v7
-board_text_start = 0x14000000
-board_objs = $(obj_dir)/arch_board.o \
- $(obj_dir)/pic/gic.o \
- $(obj_dir)/timer/imx_gpt.o \
- $(obj_dir)/serial/imx.o \
- $(obj_dir)/sys/vminfo.o
-board_smp = y
-
-board_cppflags =
-board_cflags = -mtune=cortex-a9
-board_asflags = -mtune=cortex-a9
-board_ldflags =
-
-# Include common arch makefile for basic firmware
-include $(arch_dir)/Makefile.inc
-
diff --git a/tests/arm32/sabrelite/basic/arch_board.c b/tests/arm32/sabrelite/basic/arch_board.c
deleted file mode 100644
index 5240067c..00000000
--- a/tests/arm32/sabrelite/basic/arch_board.c

+++ /dev/null
@@ -1,242 +0,0 @@

-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_board.c

- * @author Jean-Christophe Dubois (j...@tribudubois.net)

- * @brief various platform specific functions
- */
-
-#include <arch_types.h>
-#include <arch_io.h>
-#include <arch_board.h>
-#include <arm_plat.h>
-#include <basic_string.h>
-#include <pic/gic.h>
-#include <timer/imx_gpt.h>
-#include <serial/imx.h>
-#include <sys/vminfo.h>
-
-void arch_board_reset(void)
-{
- /* Nothing to do */
-}
-
-void arch_board_init(void)
-{
- /* Nothing to do */
-}
-
-char *arch_board_name(void)
-{
- return "ARM SabreLite";
-}
-
-physical_addr_t arch_board_ram_start(void)
-{
- return (physical_addr_t)vminfo_ram_base(IMX_VMINFO_BASE, 0);
-}
-
-physical_size_t arch_board_ram_size(void)
-{
- return (physical_size_t)vminfo_ram_size(IMX_VMINFO_BASE, 0);
-}
-
-void arch_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz)
-{
- basic_strcpy(cmdline, "root=/dev/ram rw earlyprintk");
- /* VirtIO Network Device */
- basic_strcat(cmdline, " virtio_mmio.device=64K@0x20100000:42");
- /* SabreLite/Nitrogen6X specific */
- basic_strcat(cmdline, " enable_wait_mode=off "
- "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666 video=mxcfb1:off "
- "video=mxcfb2:off video=mxcfb3:off fbmem=10M "
- "console=ttymxc1,115200 vmalloc=400M consoleblank=0 "
- "mxc_hdmi.only_cea=1");
-}
-
-void arch_board_fdt_fixup(void *fdt_addr)

-{
- /* For now nothing to do here. */
-}

-
-physical_addr_t arch_board_autoexec_addr(void)
-{
- return (IMX_NOR + 0xFF000);
-}
-
-u32 arch_board_boot_delay(void)
-{
- return vminfo_boot_delay(IMX_VMINFO_BASE);
-}
-
-u32 arch_board_iosection_count(void)
-{
- return 6;
-}
-
-physical_addr_t arch_board_iosection_addr(int num)
-{
- physical_addr_t ret = 0;
-
- switch (num) {
- case 0:
- ret = IMX_IOMUX;

- break;
- case 1:

- ret = CT_CA9X4_MPIC;

- break;
- case 2:

- ret = IMX_NOR;

- break;
- case 3:

- ret = IMX_UART1;

- break;
- case 4:

- ret = IMX_TIMER0;

- break;
- case 5:

- ret = IMX_VMINFO_BASE;
- break;
- default:
- while (1);
- break;
- }
-
- return ret;
-}
-
-u32 arch_board_pic_nr_irqs(void)
-{
- return NR_IRQS_CA9X4;
-}
-
-int arch_board_pic_init(void)

-{
- int rc;
-
- /*

- * Initialize Generic Interrupt Controller
- */
- rc = gic_dist_init(0, A9_MPCORE_GIC_DIST, IRQ_CA9X4_GIC_START);

- if (rc) {
- return rc;
- }

- rc = gic_cpu_init(0, A9_MPCORE_GIC_CPU);

- if (rc) {
- return rc;
- }
-

- return 0;
-}
-
-u32 arch_board_pic_active_irq(void)
-{
- return gic_active_irq(0);
-}
-
-int arch_board_pic_ack_irq(u32 irq)

-{
- return 0;
-}
-

-int arch_board_pic_eoi_irq(u32 irq)
-{
- return gic_eoi_irq(0, irq);
-}
-
-int arch_board_pic_mask(u32 irq)
-{
- return gic_mask(0, irq);
-}
-
-int arch_board_pic_unmask(u32 irq)
-{
- return gic_unmask(0, irq);
-}
-
-void arch_board_timer_enable(void)
-{
- return imx_gpt_enable();
-}
-
-void arch_board_timer_disable(void)
-{
- return imx_gpt_disable();
-}
-
-u64 arch_board_timer_irqcount(void)
-{
- return imx_gpt_irqcount();
-}
-
-u64 arch_board_timer_irqdelay(void)
-{
- return imx_gpt_irqdelay();
-}
-
-u64 arch_board_timer_timestamp(void)
-{
- return imx_gpt_timestamp();
-}
-
-void arch_board_timer_change_period(u32 usecs)
-{
- return imx_gpt_change_period(usecs);
-}
-
-int arch_board_timer_init(u32 usecs)
-{
- arch_board_pic_unmask(IRQ_IMX_TIMER0);
-
- return imx_gpt_init(usecs, IMX_TIMER0, IRQ_IMX_TIMER0, 0);
-}
-
-#define IMX_UART_BASE IMX_UART1
-#define IMX_UART_INCLK 80000000
-#define IMX_UART_BAUD 115200
-
-int arch_board_serial_init(void)
-{
- imx_init(IMX_UART_BASE, IMX_UART_BAUD, IMX_UART_INCLK);

-
- return 0;
-}
-

-void arch_board_serial_putc(char ch)
-{
- if (ch == '\n') {
- imx_putc(IMX_UART_BASE, '\r');
- }
-
- imx_putc(IMX_UART_BASE, ch);
-}
-
-bool arch_board_serial_can_getc(void)
-{
- return imx_can_getc(IMX_UART_BASE);
-}
-
-char arch_board_serial_getc(void)
-{
- char ch = imx_getc(IMX_UART_BASE);
- if (ch == '\r') {
- ch = '\n';
- }
- arch_board_serial_putc(ch);
- return ch;
-}
diff --git a/tests/arm32/sabrelite/basic/arch_smp.h b/tests/arm32/sabrelite/basic/arch_smp.h
deleted file mode 100644
index 9a3d5dfb..00000000
--- a/tests/arm32/sabrelite/basic/arch_smp.h

+++ /dev/null
@@ -1,30 +0,0 @@

-/**
- * Copyright (c) 2018 Anup Patel.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_smp.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief arch specific SMP defines
- */
-#ifndef __ARCH_SMP_H__
-#define __ARCH_SMP_H__
-
-#include <arm_plat.h>
-
-#define ARCH_SMP_SPIN_ADDR (V2M_SYS_FLAGS)
-
-#endif
diff --git a/tests/arm32/sabrelite/basic/arm_plat.h b/tests/arm32/sabrelite/basic/arm_plat.h
deleted file mode 100644
index 6a3b63af..00000000
--- a/tests/arm32/sabrelite/basic/arm_plat.h
+++ /dev/null
@@ -1,263 +0,0 @@

-/**
- * Copyright (c) 2012 Sukanto Ghosh.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arm_plat.h

- * @author Sukanto Ghosh (sukant...@gmail.com)

- * @brief ARM platform configuration
- */
-#ifndef _ARM_PLAT_H__
-#define _ARM_PLAT_H__
-
-/*
- * On-Chip Peripherials Physical Addresses
- */
-/* #define CT_CA9X4_CLCDC (0x10020000) */
-/* #define CT_CA9X4_AXIRAM (0x10060000) */
-/* #define CT_CA9X4_DMC (0x100e0000) */
-/* #define CT_CA9X4_SMC (0x100e1000) */
-/* #define CT_CA9X4_SCC (0x100e2000) */
-/* #define CT_CA9X4_SP804_TIMER (0x100e4000) */
-/* #define CT_CA9X4_SP805_WDT (0x100e5000) */
-/* #define CT_CA9X4_TZPC (0x100e6000) */
-/* #define CT_CA9X4_GPIO (0x100e8000) */
-/* #define CT_CA9X4_FASTAXI (0x100e9000) */
-/* #define CT_CA9X4_SLOWAXI (0x100ea000) */
-/* #define CT_CA9X4_TZASC (0x100ec000) */
-/* #define CT_CA9X4_CORESIGHT (0x10200000) */
-/* #define CT_CA9X4_MPIC (0x1e000000 */
-/* #define CT_CA9X4_SYSTIMER (0x1e004000) */
-/* #define CT_CA9X4_SYSWDT (0x1e007000) */
-/* #define CT_CA9X4_L2CC (0x1e00a000) */
-
-/* #define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000) */
-/* #define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020) */
-
-#define CT_CA9X4_MPIC (0x00a00000)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
-
-/*
- * Interrupts. Those in {} are for AMBA devices
- */
-/* #define IRQ_CT_CA9X4_CLCDC { 76 } */
-/* #define IRQ_CT_CA9X4_DMC { -1 } */
-/* #define IRQ_CT_CA9X4_SMC { 77, 78 } */
-/* #define IRQ_CT_CA9X4_TIMER0 80 */
-/* #define IRQ_CT_CA9X4_TIMER1 81 */
-/* #define IRQ_CT_CA9X4_GPIO { 82 } */
-/* #define IRQ_CT_CA9X4_PMU_CPU0 92 */
-/* #define IRQ_CT_CA9X4_PMU_CPU1 93 */
-/* #define IRQ_CT_CA9X4_PMU_CPU2 94 */
-/* #define IRQ_CT_CA9X4_PMU_CPU3 95 */
-
-/* #define IRQ_CT_CA9X4_LOCALTIMER 29 */
-/* #define IRQ_CT_CA9X4_LOCALWDOG 30 */
-
-#define IRQ_CA9X4_GIC_START 29
-#define NR_IRQS_CA9X4 128
-#define NR_GIC_CA9X4 1
-
-/*
- * V2M Chip Select Physical Addresses
- */
-/* #define V2M_PA_CS0 0x40000000 */
-/* #define V2M_PA_CS1 0x44000000 */
-/* #define V2M_PA_CS2 0x48000000 */
-/* #define V2M_PA_CS3 0x4c000000 */
-/* #define V2M_PA_CS7 0x10000000 */
-
-#define IMX_PA_AIPS1 0x02000000
-#define IMX_PA_AIPS2 0x02100000
-#define IMX_PA_EIM 0x08000000
-
-/* /\* */
-/* * Physical addresses, offset from V2M_PA_CS0-3 */
-/* *\/ */
-/* #define V2M_NOR0 (V2M_PA_CS0) */
-/* #define V2M_NOR1 (V2M_PA_CS1) */
-/* #define V2M_SRAM (V2M_PA_CS2) */
-/* #define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) */
-/* #define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) */
-/* #define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) */
-
-/* /\* */
-/* * Physical addresses, offset from V2M_PA_CS7 */
-/* *\/ */
-/* #define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000) */
-/* #define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000) */
-/* #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000) */
-
-/* #define V2M_AACI (V2M_PA_CS7 + 0x00004000) */
-/* #define V2M_MMCI (V2M_PA_CS7 + 0x00005000) */
-/* #define V2M_KMI0 (V2M_PA_CS7 + 0x00006000) */
-/* #define V2M_KMI1 (V2M_PA_CS7 + 0x00007000) */
-
-#define IMX_NOR (IMX_PA_EIM)
-#define IMX_UART0 (IMX_PA_AIPS1 + 0x00020000)
-#define IMX_IOMUX (IMX_PA_AIPS1 + 0x000e0000)
-#define IMX_TIMER0 (IMX_PA_AIPS1 + 0x00098000)
-#define V2M_SYSREGS (IMX_PA_AIPS1 + 0x000F0000)
-#define IMX_UART1 (IMX_PA_AIPS2 + 0x000e8000)
-#define IMX_UART2 (IMX_PA_AIPS2 + 0x000ec000)
-#define IMX_UART3 (IMX_PA_AIPS2 + 0x000f0000)
-
-#define IRQ_IMX_TIMER0 (87)
-/* #define V2M_WDT (V2M_PA_CS7 + 0x0000f000) */
-
-/* #define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000) */
-/* #define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000) */
-
-/* #define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000) */
-/* #define V2M_RTC (V2M_PA_CS7 + 0x00017000) */
-
-/* #define V2M_CF (V2M_PA_CS7 + 0x0001a000) */
-/* #define V2M_CLCD (V2M_PA_CS7 + 0x0001f000) */
-
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-/* #define V2M_TIMER0 (V2M_TIMER01 + 0x000) */
-/* #define V2M_TIMER1 (V2M_TIMER01 + 0x020) */
-
-/* #define V2M_TIMER2 (V2M_TIMER23 + 0x000) */
-/* #define V2M_TIMER3 (V2M_TIMER23 + 0x020) */
-
-/*
- * Interrupts. Those in {} are for AMBA devices
- */
-/* #define IRQ_V2M_WDT { (32 + 0) } */
-/* #define IRQ_V2M_TIMER0 (32 + 2) */
-/* #define IRQ_V2M_TIMER1 (32 + 2) */
-/* #define IRQ_V2M_TIMER2 (32 + 3) */
-/* #define IRQ_V2M_TIMER3 (32 + 3) */
-/* #define IRQ_V2M_RTC { (32 + 4) } */
-/* #define IRQ_V2M_UART0 { (32 + 5) } */
-/* #define IRQ_V2M_UART1 { (32 + 6) } */
-/* #define IRQ_V2M_UART2 { (32 + 7) } */
-/* #define IRQ_V2M_UART3 { (32 + 8) } */
-/* #define IRQ_V2M_MMCI { (32 + 9), (32 + 10) } */
-/* #define IRQ_V2M_AACI { (32 + 11) } */
-/* #define IRQ_V2M_KMI0 { (32 + 12) } */
-/* #define IRQ_V2M_KMI1 { (32 + 13) } */
-/* #define IRQ_V2M_CLCD { (32 + 14) } */
-/* #define IRQ_V2M_LAN9118 (32 + 15) */
-/* #define IRQ_V2M_ISP1761 (32 + 16) */
-/* #define IRQ_V2M_PCIE (32 + 17) */
-
-/*
- * Configuration
- */
-/* #define SYS_CFG_START (1 << 31) */
-/* #define SYS_CFG_WRITE (1 << 30) */
-/* #define SYS_CFG_OSC (1 << 20) */
-/* #define SYS_CFG_VOLT (2 << 20) */
-/* #define SYS_CFG_AMP (3 << 20) */
-/* #define SYS_CFG_TEMP (4 << 20) */
-/* #define SYS_CFG_RESET (5 << 20) */
-/* #define SYS_CFG_SCC (6 << 20) */
-/* #define SYS_CFG_MUXFPGA (7 << 20) */
-/* #define SYS_CFG_SHUTDOWN (8 << 20) */
-/* #define SYS_CFG_REBOOT (9 << 20) */
-/* #define SYS_CFG_DVIMODE (11 << 20) */
-/* #define SYS_CFG_POWER (12 << 20) */
-/* #define SYS_CFG_SITE_MB (0 << 16) */
-/* #define SYS_CFG_SITE_DB1 (1 << 16) */
-/* #define SYS_CFG_SITE_DB2 (2 << 16) */
-/* #define SYS_CFG_STACK(n) ((n) << 12) */
-
-/* #define SYS_CFG_ERR (1 << 1) */
-/* #define SYS_CFG_COMPLETE (1 << 0) */
-
-/*
- * Core tile IDs
- */
-/* #define V2M_CT_ID_CA9 0x0c000191 */
-/* #define V2M_CT_ID_UNSUPPORTED 0xff000191 */
-/* #define V2M_CT_ID_MASK 0xff000fff */
-
-/* Following taken from sp810.h */
-
-/* sysctl registers offset */
-/* #define SCCTRL 0x000 */
-/* #define SCSYSSTAT 0x004 */
-/* #define SCIMCTRL 0x008 */
-/* #define SCIMSTAT 0x00C */
-/* #define SCXTALCTRL 0x010 */
-/* #define SCPLLCTRL 0x014 */
-/* #define SCPLLFCTRL 0x018 */
-/* #define SCPERCTRL0 0x01C */
-/* #define SCPERCTRL1 0x020 */
-/* #define SCPEREN 0x024 */
-/* #define SCPERDIS 0x028 */
-/* #define SCPERCLKEN 0x02C */
-/* #define SCPERSTAT 0x030 */
-/* #define SCSYSID0 0xEE0 */
-/* #define SCSYSID1 0xEE4 */
-/* #define SCSYSID2 0xEE8 */
-/* #define SCSYSID3 0xEEC */
-/* #define SCITCR 0xF00 */
-/* #define SCITIR0 0xF04 */
-/* #define SCITIR1 0xF08 */
-/* #define SCITOR 0xF0C */
-/* #define SCCNTCTRL 0xF10 */
-/* #define SCCNTDATA 0xF14 */
-/* #define SCCNTSTEP 0xF18 */
-/* #define SCPERIPHID0 0xFE0 */
-/* #define SCPERIPHID1 0xFE4 */
-/* #define SCPERIPHID2 0xFE8 */
-/* #define SCPERIPHID3 0xFEC */
-/* #define SCPCELLID0 0xFF0 */
-/* #define SCPCELLID1 0xFF4 */
-/* #define SCPCELLID2 0xFF8 */
-/* #define SCPCELLID3 0xFFC */
-
-/* #define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15) */
-/* #define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15) */
-
-/* #define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17) */
-/* #define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17) */
-
-/*
- * Defines required by basic firmware
- */
-#define IMX_VMINFO_BASE 0x0220b000
-
-#endif
diff --git a/tests/arm32/sabrelite/basic/gic_config.h b/tests/arm32/sabrelite/basic/gic_config.h
deleted file mode 100644
index 573a7e73..00000000
--- a/tests/arm32/sabrelite/basic/gic_config.h
+++ /dev/null
@@ -1,33 +0,0 @@

-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file gic_config.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM Generic Interrupt Controller configuration header
- */
-#ifndef _GIC_CONFIG_H__
-#define _GIC_CONFIG_H__
-
-#include <arm_plat.h>
-
-#define GIC_CPU_BASE A9_MPCORE_GIC_CPU
-#define GIC_DIST_BASE A9_MPCORE_GIC_DIST
-#define GIC_NR_IRQS NR_IRQS_CA9X4
-#define GIC_MAX_NR NR_GIC_CA9X4
-
-#endif
diff --git a/tests/arm32/sabrelite/linux/cmdlist b/tests/arm32/sabrelite/linux/cmdlist
deleted file mode 100644
index 2d09ebd4..00000000
--- a/tests/arm32/sabrelite/linux/cmdlist
+++ /dev/null
@@ -1,4 +0,0 @@
-copy 0x10008000 0x08100000 0xEF0000
-copy 0x12000000 0x08FF0000 0x010000
-copy 0x12100000 0x09000000 0x800000
-start_linux_fdt 0x10008000 0x12000000 0x12100000 0x800000
diff --git a/tests/arm32/sabrelite/linux/imx6q-nitrogen6x.dts b/tests/arm32/sabrelite/linux/imx6q-nitrogen6x.dts
deleted file mode 100644
index f5262384..00000000
--- a/tests/arm32/sabrelite/linux/imx6q-nitrogen6x.dts

+++ /dev/null
@@ -1,81 +0,0 @@

-/*
- * Copyright 2013 Boundary Devices
- * Copyright 2012 Freescale Semiconductor, Inc.

- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html

- */
-
-/dts-v1/;
-

-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6q.dtsi"
-#include "imx6qdl-nitrogen6x.dtsi"
-
-/ {
- model = "Freescale i.MX6 Quad Nitrogen6x Board";
- compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q";
-};
-
-/* &hdmi_core { */
-/* ipu_id = <1>; */
-/* }; */

-
-&mxcfb1 {
- status = "okay";

-};
-
-/* &mxcfb2 { */
-/* status = "okay"; */
-/* }; */
-
-/* &mxcfb3 { */
-/* status = "okay"; */
-/* }; */
-
-/* &mxcfb4 { */
-/* status = "okay"; */
-/* }; */
-
-/* &ov5640 { */
-/* ipu_id = <1>; */
-/* }; */
-
-/* &ov5640_mipi { */
-/* ipu_id = <1>; */
-/* csi_id = <0>; */
-/* }; */
-
-&pinctrl_ov5640 { /* parallel camera */
- fsl,pins = <
- MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1
- MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1
- MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1
- MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1
- MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1
- MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1
- MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1
- MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1
- MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1
- MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1
- MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1
- MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1
- >;
-};
-
-/* &sata { */
-/* status = "okay"; */
-/* }; */
-
-/* /\* ov5640_mipi *\/ */
-/* &v4l2_cap_1 { */
-/* ipu_id = <1>; */
-/* csi_id = <0>; */
-/* mipi_camera = <1>; */
-/* }; */
-
diff --git a/tests/arm32/sabrelite/linux/imx6q.dtsi b/tests/arm32/sabrelite/linux/imx6q.dtsi
deleted file mode 100644
index bee79258..00000000
--- a/tests/arm32/sabrelite/linux/imx6q.dtsi
+++ /dev/null
@@ -1,246 +0,0 @@
-

-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *

- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-

-#include "imx6q-pinfunc.h"
-#include "imx6qdl.dtsi"
-
-/ {
- /* aliases { */
- /* ipu1 = &ipu2; */
- /* }; */
-

- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-

- cpu0: cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
- operating-points = <
- /* kHz uV */
- 1200000 1275000
- 996000 1250000
- 852000 1250000
- 792000 1150000
- 396000 975000
- >;
- fsl,soc-operating-points = <
- /* ARM kHz SOC-PU uV */
- 1200000 1275000
- 996000 1250000
- 852000 1250000
- 792000 1175000
- 396000 1175000
- >;
- clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clks 104>, <&clks 6>, <&clks 16>,
- <&clks 17>, <&clks 170>;
- clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
- arm-supply = <&reg_arm>;
- pu-supply = <&reg_pu>;
- soc-supply = <&reg_soc>;
- };
-
- /* cpu@1 { */
- /* compatible = "arm,cortex-a9"; */
- /* device_type = "cpu"; */
- /* reg = <1>; */
- /* next-level-cache = <&L2>; */
- /* }; */
-
- /* cpu@2 { */
- /* compatible = "arm,cortex-a9"; */
- /* device_type = "cpu"; */
- /* reg = <2>; */
- /* next-level-cache = <&L2>; */
- /* }; */
-
- /* cpu@3 { */
- /* compatible = "arm,cortex-a9"; */
- /* device_type = "cpu"; */
- /* reg = <3>; */
- /* next-level-cache = <&L2>; */
- /* }; */
- };
-
- soc {
-
- busfreq { /* BUSFREQ */
- compatible = "fsl,imx6_busfreq";
- clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
- <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
- clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
- "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
- interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
- interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
- fsl,max_ddr_freq = <528000000>;
- };
-
- gpu: gpu@00130000 {
- compatible = "fsl,imx6q-gpu";
- reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
- <0x02204000 0x4000>, <0x0 0x0>;
- reg-names = "iobase_3d", "iobase_2d",
- "iobase_vg", "phys_baseaddr";
- interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
- interrupt-names = "irq_3d", "irq_2d", "irq_vg";
- clocks = <&clks 26>, <&clks 143>,
- <&clks 27>, <&clks 121>,
- <&clks 122>, <&clks 74>;
- clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
- "gpu3d_axi_clk", "gpu2d_clk",
- "gpu3d_clk", "gpu3d_shader_clk";
- resets = <&src 0>, <&src 3>, <&src 3>;
- reset-names = "gpu3d", "gpu2d", "gpuvg";
- pu-supply = <&reg_pu>;
- };
-
- ocram: sram@00900000 {

- compatible = "mmio-sram";
- reg = <0x00904000 0x3C000>;

- clocks = <&clks 142>;
- };
-
- /* hdmi_core: hdmi_core@00120000 { */
- /* compatible = "fsl,imx6q-hdmi-core"; */
- /* reg = <0x00120000 0x9000>; */
- /* clocks = <&clks 124>, <&clks 123>; */
- /* clock-names = "hdmi_isfr", "hdmi_iahb"; */
- /* status = "disabled"; */
- /* }; */
-
- /* hdmi_video: hdmi_video@020e0000 { */
- /* compatible = "fsl,imx6q-hdmi-video"; */
- /* reg = <0x020e0000 0x1000>; */
- /* reg-names = "hdmi_gpr"; */
- /* interrupts = <0 115 0x04>; */
- /* clocks = <&clks 124>, <&clks 123>; */
- /* clock-names = "hdmi_isfr", "hdmi_iahb"; */
- /* status = "disabled"; */
- /* }; */
-
- /* hdmi_audio: hdmi_audio@00120000 { */
- /* compatible = "fsl,imx6q-hdmi-audio"; */
- /* clocks = <&clks 124>, <&clks 123>; */
- /* clock-names = "hdmi_isfr", "hdmi_iahb"; */
- /* dmas = <&sdma 2 22 0>; */
- /* dma-names = "tx"; */
- /* status = "disabled"; */
- /* }; */
-
- /* hdmi_cec: hdmi_cec@00120000 { */
- /* compatible = "fsl,imx6q-hdmi-cec"; */
- /* interrupts = <0 115 0x04>; */
- /* status = "disabled"; */
- /* }; */
-
-
- aips-bus@02000000 { /* AIPS1 */
- /* spba-bus@02000000 { */
- /* ecspi5: ecspi@02018000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; */
- /* reg = <0x02018000 0x4000>; */
- /* interrupts = <0 35 0x04>; */
- /* clocks = <&clks 116>, <&clks 116>; */
- /* clock-names = "ipg", "per"; */
- /* status = "disabled"; */
- /* }; */
- /* }; */
-
- vpu@02040000 {

- status = "okay";
- };
-

- iomuxc: iomuxc@020e0000 {
- compatible = "fsl,imx6q-iomuxc";
- };
- };
-
- /* aips-bus@02100000 { /\* AIPS2 *\/ */
- /* mipi_dsi: mipi@021e0000 { */
- /* compatible = "fsl,imx6q-mipi-dsi"; */
- /* reg = <0x021e0000 0x4000>; */
- /* interrupts = <0 102 0x04>; */
- /* gpr = <&gpr>; */
- /* clocks = <&clks 138>, <&clks 204>; */
- /* clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; */
- /* status = "disabled"; */
- /* }; */
- /* }; */
-
- /* sata: sata@02200000 { */
- /* compatible = "fsl,imx6q-ahci"; */
- /* reg = <0x02200000 0x4000>; */
- /* interrupts = <0 39 0x04>; */
- /* clocks = <&clks 154>, <&clks 187>, <&clks 105>; */
- /* clock-names = "sata", "sata_ref", "ahb"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ipu2: ipu@02800000 { */
- /* compatible = "fsl,imx6q-ipu"; */
- /* reg = <0x02800000 0x400000>; */
- /* interrupts = <0 8 0x4 0 7 0x4>; */
- /* clocks = <&clks 133>, <&clks 134>, <&clks 137>, */
- /* <&clks 41>, <&clks 42>, */
- /* <&clks 135>, <&clks 136>, */
- /* <&clks 8>, <&clks 195>; */
- /* clock-names = "bus", "di0", "di1", */
- /* "di0_sel", "di1_sel", */
- /* "ldb_di0", "ldb_di1", */
- /* "540m", "video_pll"; */
- /* resets = <&src 4>; */
- /* bypass_reset = <0>; */
- /* }; */
- };
-};
-
-&iomuxc {
- ipu2 {
- pinctrl_ipu2_1: ipu2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
- >;
- };
- };
-};
diff --git a/tests/arm32/sabrelite/linux/imx6qdl-nitrogen6x.dtsi b/tests/arm32/sabrelite/linux/imx6qdl-nitrogen6x.dtsi
deleted file mode 100644
index 2164143a..00000000
--- a/tests/arm32/sabrelite/linux/imx6qdl-nitrogen6x.dtsi
+++ /dev/null
@@ -1,644 +0,0 @@
-/*
- * Copyright 2013 Boundary Devices
- * Copyright 2012 Freescale Semiconductor, Inc.

- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html

- */
-#include <dt-bindings/input/input.h>
-
-/ {
- aliases {
- mxcfb0 = &mxcfb1;
- /* mxcfb1 = &mxcfb2; */
- /* mxcfb2 = &mxcfb3; */
- /* mxcfb3 = &mxcfb4; */
- };
-
- memory {
- reg = <0x10000000 0x10000000>;
- };
-
- clocks {
- clk24m: clk24m {

- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;

- };

- };
-
- regulators {
- compatible = "simple-bus";
-

- reg_1p8v: 1p8v {
- compatible = "regulator-fixed";
- regulator-name = "1P8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_2p5v: 2p5v {
- compatible = "regulator-fixed";

- regulator-name = "2P5V";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;

- regulator-always-on;
- };
-
- reg_3p3v: 3p3v {
- compatible = "regulator-fixed";

- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;

- regulator-always-on;
- };
-
- /* reg_usb_otg_vbus: usb_otg_vbus { */
- /* compatible = "regulator-fixed"; */
- /* regulator-name = "usb_otg_vbus"; */
- /* regulator-min-microvolt = <5000000>; */
- /* regulator-max-microvolt = <5000000>; */
- /* gpio = <&gpio3 22 0>; */
- /* enable-active-high; */
- /* }; */
- };
-
- /* gpio-keys { */
- /* compatible = "gpio-keys"; */
- /* power { */
- /* label = "Power Button"; */
- /* gpios = <&gpio2 3 0>; */
- /* linux,code = <KEY_POWER>; /\* or KEY_SEARCH *\/ */
- /* gpio-key,wakeup; */
- /* }; */
-
- /* menu { */
- /* label = "Menu"; */
- /* gpios = <&gpio2 1 0>; */
- /* linux,code = <KEY_MENU>; */
- /* }; */
-
- /* home { */
- /* label = "Home"; */
- /* gpios = <&gpio2 4 0>; */
- /* linux,code = <KEY_HOME>; */
- /* }; */
-
- /* back { */
- /* label = "Back"; */
- /* gpios = <&gpio2 2 0>; */
- /* linux,code = <KEY_BACK>; */
- /* }; */
-
- /* volume-up { */
- /* label = "Volume Up"; */
- /* gpios = <&gpio7 13 0>; */
- /* linux,code = <KEY_VOLUMEUP>; */
- /* }; */
-
- /* volume-down { */
- /* label = "Volume Down"; */
- /* gpios = <&gpio4 5 0>; */
- /* linux,code = <KEY_VOLUMEDOWN>; */
- /* }; */
- /* }; */
-
- /* sound { */
- /* compatible = "fsl,imx6q-nitrogen6x-sgtl5000", */
- /* "fsl,imx-audio-sgtl5000"; */
- /* model = "imx6q-nitrogen6x-sgtl5000"; */
- /* ssi-controller = <&ssi1>; */
- /* audio-codec = <&codec>; */
- /* audio-routing = */
- /* "MIC_IN", "Mic Jack", */
- /* "Mic Jack", "Mic Bias", */
- /* "Headphone Jack", "HP_OUT"; */
- /* mux-int-port = <1>; */
- /* mux-ext-port = <3>; */
- /* }; */
- /* sound-hdmi { */
- /* compatible = "fsl,imx6q-audio-hdmi", */
- /* "fsl,imx-audio-hdmi"; */
- /* model = "imx-audio-hdmi"; */
- /* hdmi-controller = <&hdmi_audio>; */
- /* }; */
-

- mxcfb1: fb@0 {
- compatible = "fsl,mxc_sdc_fb";
- disp_dev = "ldb";

- interface_pix_fmt = "RGB666";
- mode_str ="LDB-XGA";
- default_bpp = <16>;

- int_clk = <0>;
- late_init = <0>;
- status = "disabled";
- };
-

- /* mxcfb2: fb@1 { */
- /* compatible = "fsl,mxc_sdc_fb"; */
- /* disp_dev = "hdmi"; */
- /* interface_pix_fmt = "RGB24"; */
- /* mode_str ="1920x1080M@60"; */
- /* default_bpp = <24>; */
- /* int_clk = <0>; */
- /* late_init = <0>; */
- /* status = "disabled"; */
- /* }; */
-
- /* mxcfb3: fb@2 { */
- /* compatible = "fsl,mxc_sdc_fb"; */
- /* disp_dev = "lcd"; */
- /* interface_pix_fmt = "RGB565"; */
- /* mode_str ="CLAA-WVGA"; */
- /* default_bpp = <16>; */
- /* int_clk = <0>; */
- /* late_init = <0>; */
- /* status = "disabled"; */
- /* }; */
-
- /* mxcfb4: fb@3 { */
- /* compatible = "fsl,mxc_sdc_fb"; */
- /* disp_dev = "ldb"; */
- /* interface_pix_fmt = "RGB666"; */
- /* mode_str ="LDB-XGA"; */
- /* default_bpp = <16>; */
- /* int_clk = <0>; */
- /* late_init = <0>; */
- /* status = "disabled"; */
- /* }; */
-
- /* lcd0: lcd@0 { */
- /* compatible = "fsl,lcd"; */
- /* ipu_id = <0>; */
- /* disp_id = <0>; */
- /* default_ifmt = "RGB565"; */
- /* pinctrl-names = "default"; */
- /* pinctrl-0 = <&pinctrl_ipu1_4>; */
- /* status = "okay"; */
- /* }; */
-
- /* backlight_lcd: backlight_lcd { */
- /* compatible = "pwm-backlight"; */
- /* pwms = <&pwm1 0 5000000>; */
- /* brightness-levels = <0 4 8 16 32 64 128 255>; */
- /* default-brightness-level = <7>; */
- /* }; */
-

- backlight_lvds {
- compatible = "pwm-backlight";
- pwms = <&pwm4 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;

- };
-
- /* v4l2_cap_0: v4l2_cap_0 { */
- /* compatible = "fsl,imx6q-v4l2-capture"; */
- /* ipu_id = <0>; */
- /* csi_id = <0>; */
- /* mclk_source = <0>; */
- /* status = "okay"; */
- /* }; */
-
- /* v4l2_cap_1: v4l2_cap_1 { */
- /* compatible = "fsl,imx6q-v4l2-capture"; */
- /* ipu_id = <0>; */
- /* csi_id = <1>; */
- /* mipi_camera = <1>; */
- /* mclk_source = <0>; */
- /* status = "okay"; */
- /* }; */
-
- /* v4l2_cap_2: v4l2_cap_2 { */
- /* compatible = "fsl,imx6q-v4l2-capture"; */
- /* ipu_id = <0>; */
- /* csi_id = <1>; */
- /* mclk_source = <0>; */
- /* status = "okay"; */
- /* }; */
-
- /* v4l2_cap_3: v4l2_cap_3 { */
- /* compatible = "fsl,imx6q-v4l2-capture"; */
- /* ipu_id = <0>; */
- /* csi_id = <0>; */
- /* mipi_camera = <1>; */
- /* mclk_source = <0>; */
- /* status = "okay"; */
- /* }; */
-
- v4l2_out {
- compatible = "fsl,mxc_v4l2_output";

- status = "okay";
- };
-

- /* wlan { */
- /* compatible = "ti,wilink6"; */
- /* interrupt-parent = <&gpio6>; */
- /* interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; */
- /* clocks = <&refclock>; */
- /* clock-names = "refclock"; */
-
- /* refclock: refclock { */
- /* compatible = "ti,wilink-clock"; */
- /* #clock-cells = <0>; */
- /* clock-frequency = <38400000>; */
- /* }; */
- /* }; */
-
- /* wlan_bt_rfkill { */
- /* compatible = "net,rfkill-gpio"; */
- /* name = "wlan_bt_rfkill"; */
- /* type = <2>; /\* bluetooth *\/ */
- /* gpios = <&gpio6 16 0>; */
- /* }; */
-};
-
-/* &audmux { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_audmux_2>; */
-/* status = "okay"; */
-/* }; */
-
-/* &ecspi1 { */
-/* fsl,spi-num-chipselects = <1>; */
-/* cs-gpios = <&gpio3 19 0>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_ecspi1_1>; */
-/* status = "okay"; */
-
-/* flash: m25p80@0 { */
-/* compatible = "sst,sst25vf016b"; */
-/* spi-max-frequency = <20000000>; */
-/* reg = <0>; */
-/* #address-cells = <1>; */
-/* #size-cells = <1>; */
-/* partition@0 { */
-/* label = "U-Boot"; */
-/* reg = <0x0 0xC0000>; */
-/* }; */
-/* partition@C0000 { */
-/* label = "env"; */
-/* reg = <0xC0000 0x2000>; */
-/* }; */
-/* partition@C2000 { */
-/* label = "splash"; */
-/* reg = <0xC2000 0x13e000>; */
-/* }; */
-/* }; */
-/* }; */
-
-/* &fec { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_enet_4>; */
-/* phy-mode = "rgmii"; */
-/* #if 0 */
-/* phy-reset-gpios = <&gpio1 27 0>; */
-/* #endif */
-/* status = "okay"; */
-
-/* #address-cells = <0>; */
-/* #size-cells = <1>; */
-/* phy_int { */
-/* reg = <0x6>; */
-/* interrupt-parent = <&gpio1>; */
-/* interrupts = <28 IRQ_TYPE_LEVEL_LOW>; */
-/* }; */
-/* }; */
-
-/* &flexcan1 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_flexcan1_1>; */
-/* trx-stby-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; */
-/* status = "okay"; */
-/* }; */
-
-/* &hdmi_audio { */
-/* status = "okay"; */
-/* }; */
-
-/* &hdmi_cec { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_hdmi_cec_2>; */
-/* status = "okay"; */
-/* }; */
-
-/* &hdmi_core { */
-/* ipu_id = <0>; */
-/* disp_id = <0>; */
-/* status = "okay"; */
-/* }; */
-
-/* &hdmi_video { */
-/* fsl,phy_reg_vlev = <0x0294>; */
-/* fsl,phy_reg_cksymtx = <0x800d>; */
-/* status = "okay"; */
-/* }; */
-
-/* &i2c1 { */
-/* clock-frequency = <100000>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_i2c1_1>; */
-/* status = "okay"; */
-
-/* codec: sgtl5000@0a { */
-/* compatible = "fsl,sgtl5000"; */
-/* reg = <0x0a>; */
-/* clocks = <&clks 201>; */
-/* VDDA-supply = <&reg_2p5v>; */
-/* VDDIO-supply = <&reg_3p3v>; */
-/* }; */
-/* isl1208@6f { */
-/* compatible = "isl,isl1208"; */
-/* reg = <0x6f>; */
-/* interrupt-parent = <&gpio6>; */
-/* interrupts = <7 IRQ_TYPE_EDGE_FALLING>; */
-/* }; */
-/* }; */
-
-/* &i2c2 { */
-/* clock-frequency = <100000>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_i2c2_2>; */
-/* status = "okay"; */
-
-/* hdmi: edid@50 { */
-/* compatible = "fsl,imx6-hdmi-i2c"; */
-/* reg = <0x50>; */
-/* }; */
-
-/* ov5642: ov5642@3d { */
-/* compatible = "ovti,ov5642"; */
-/* reg = <0x3d>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_ipu1_2>; */
-/* clocks = <&clks 200>; */
-/* clock-names = "csi_mclk"; */
-/* DOVDD-supply = <&reg_1p8v>; */
-/* AVDD-supply = <&reg_2p5v>; */
-/* DVDD-supply = <&reg_1p8v>; */
-/* pwn-gpios = <&gpio1 6 1>; */
-/* rst-gpios = <&gpio1 8 0>; */
-/* ipu_id = <0>; */
-/* csi_id = <0>; */
-/* mclk = <24000000>; */
-/* mclk_source = <0>; */
-/* }; */
-
-/* ov5640_mipi: ov5640_mipi@3e { */
-/* compatible = "ovti,ov5640_mipi"; */
-/* reg = <0x3e>; */
-/* clocks = <&clks 147>; */
-/* clock-names = "csi_mclk"; */
-/* DOVDD-supply = <&reg_1p8v>; */
-/* AVDD-supply = <&reg_2p5v>; */
-/* DVDD-supply = <&reg_1p8v>; */
-/* pwn-gpios = <&gpio6 9 1>; */
-/* rst-gpios = <&gpio2 5 0>; */
-/* ipu_id = <0>; */
-/* csi_id = <1>; */
-/* mclk = <22000000>; */
-/* mclk_source = <0>; */
-/* pwms = <&pwm3 0 45>; */
-/* }; */
-/* }; */
-
-/* &i2c3 { */
-/* clock-frequency = <100000>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_i2c3_3>; */
-/* status = "okay"; */
-
-/* egalax_ts@04 { */
-/* compatible = "eeti,egalax_ts"; */
-/* reg = <0x04>; */
-/* interrupt-parent = <&gpio1>; */
-/* interrupts = <9 2>; */
-/* wakeup-gpios = <&gpio1 9 0>; */
-/* }; */
-
-/* ft5x06_ts@38 { */
-/* compatible = "ft5x06-ts,ft5x06-ts"; */
-/* reg = <0x38>; */
-/* interrupt-parent = <&gpio1>; */
-/* interrupts = <9 2>; */
-/* wakeup-gpios = <&gpio1 9 0>; */
-/* }; */
-
-/* ili210x@41 { */
-/* compatible = "ili210x"; */
-/* reg = <0x41>; */
-/* interrupt-parent = <&gpio1>; */
-/* interrupts = <9 2>; */
-/* wakeup-gpios = <&gpio1 9 0>; */
-/* }; */
-
-/* ov5640: ov5640@3c { */
-/* compatible = "ovti,ov5640"; */
-/* reg = <0x3c>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_ov5640 &pinctrl_ov5640_gpios>; */
-/* clocks = <&clk24m 0>; */
-/* clock-names = "csi_mclk"; */
-/* DOVDD-supply = <&reg_1p8v>; */
-/* AVDD-supply = <&reg_2p5v>; */
-/* DVDD-supply = <&reg_1p8v>; */
-/* pwn-gpios = <&gpio3 13 1>; */
-/* rst-gpios = <&gpio3 14 0>; */
-/* csi_id = <1>; */
-/* mclk = <24000000>; */
-/* mclk_source = <0>; */
-/* }; */
-
-/* tsc2004: tsc2004@48 { */
-/* compatible = "tsc2004,tsc2004"; */
-/* reg = <0x48>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_tsc2004>; */
-/* interrupt-parent = <&gpio4>; */
-/* interrupts = <20 2>; */
-/* wakeup-gpios = <&gpio4 20 0>; */
-/* }; */
-/* }; */

- MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */

- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* ISL1208 interrupt */
- >;
- };
-

- pinctrl_ov5640: pinctrl_ov5640 {
- /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */
- };
-
- pinctrl_ov5640_gpios: pinctrl_ov5640_gpios {
- fsl,pins = <
- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 /* Power */
- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* Reset */
- >;
- };
-
- pinctrl_tsc2004: tsc2004grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 /* wl12xx_wl_en */

- >;
- };
- };
-};
-

-&ldb {
- ipu_id = <0>;

- disp_id = <1>;

- ext_ref = <1>;
- mode = "sin0";
- sec_ipu_id = <1>;
- sec_disp_id = <1>;
- status = "okay";
-};
-

-/* &mipi_csi { */
-/* lanes = <2>; */
-/* status = "okay"; */
-/* }; */
-
-/* &pcie { */
-/* status = "okay"; */
-/* }; */
-
-/* &pwm1 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_pwm1_1>; */
-/* status = "okay"; */
-/* }; */
-
-/* &pwm3 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_pwm3_2>; */
-/* status = "okay"; */
-/* }; */
-
-&pwm4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm4_2>;

- status = "okay";
-};
-

-/* &ssi1 { */
-/* fsl,mode = "i2s-slave"; */
-/* status = "okay"; */
-/* }; */
-
-/* &uart1 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_uart1_2>; */
-/* status = "okay"; */
-/* }; */
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2_1>;

- status = "okay";
-};
-

-/* &uart3 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_uart3_2>; */
-/* fsl,uart-has-rtscts; */
-/* status = "okay"; */
-/* }; */
-
-/* &usbh1 { */
-/* status = "okay"; */
-/* }; */
-
-/* &usbotg { */
-/* vbus-supply = <&reg_usb_otg_vbus>; */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_usbotg_1>; */
-/* disable-over-current; */
-/* status = "okay"; */
-/* }; */
-
-/* &usdhc2 { /\* uSDHC2, TiWi wl1271 *\/ */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_usdhc2>; */
-/* bus-width = <4>; */
-/* non-removable; */
-/* vmmc-supply = <&reg_3p3v>; */
-/* vqmmc-1-8-v; */
-/* power-gpio = <&gpio6 15 0>; */
-/* ocr-limit = <0x80>; /\* 1.65v - 1.95v *\/ */
-/* power-off-card; */
-/* keep-power-in-suspend; */
-/* status = "okay"; */
-/* }; */

-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3_2>;
- cd-gpios = <&gpio7 0 0>;

- vmmc-supply = <&reg_3p3v>;

- status = "okay";
-};
-

-/* &usdhc4 { */
-/* pinctrl-names = "default"; */
-/* pinctrl-0 = <&pinctrl_usdhc4_2>; */
-/* cd-gpios = <&gpio2 6 0>; */
-/* vmmc-supply = <&reg_3p3v>; */
-/* status = "okay"; */
-/* }; */
diff --git a/tests/arm32/sabrelite/linux/imx6qdl.dtsi b/tests/arm32/sabrelite/linux/imx6qdl.dtsi
deleted file mode 100644
index f66239b9..00000000
--- a/tests/arm32/sabrelite/linux/imx6qdl.dtsi
+++ /dev/null
@@ -1,1884 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.

- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html

- */
-
-#include "skeleton.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- aliases {
- /* flexcan0 = &flexcan1; */
- /* flexcan1 = &flexcan2; */
- /* gpio0 = &gpio1; */
- /* gpio1 = &gpio2; */
- /* gpio2 = &gpio3; */
- /* gpio3 = &gpio4; */
- /* gpio4 = &gpio5; */
- /* gpio5 = &gpio6; */
- /* gpio6 = &gpio7; */
- ipu0 = &ipu1;
- /* serial0 = &uart1; */
- serial1 = &uart2;
- /* serial2 = &uart3; */
- /* serial3 = &uart4; */
- /* serial4 = &uart5; */
- /* usbphy0 = &usbphy1; */
- /* usbphy1 = &usbphy2; */
- };
-
- intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;

- #address-cells = <1>;
- #size-cells = <1>;

- interrupt-controller;

- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;

- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ckil {

- compatible = "fsl,imx-ckil", "fixed-clock";

- clock-frequency = <32768>;
- };
-
- ckih1 {

- compatible = "fsl,imx-ckih1", "fixed-clock";

- clock-frequency = <0>;
- };
-
- osc {

- compatible = "fsl,imx-osc", "fixed-clock";

- clock-frequency = <24000000>;
- };
- };
-

- pu_dummy: pudummy_reg {
- compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
- };
-
- mxs_viim {
- compatible = "fsl,mxs_viim";
- reg = <0x02098000 0x1000>, /* GPT base */
- <0x021bc000 0x1000>; /* OCOTP base */

- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";

- interrupt-parent = <&intc>;
- ranges;
-
- /* caam_sm: caam-sm@00100000 { */
- /* compatible = "fsl,imx6q-caam-sm"; */
- /* reg = <0x00100000 0x3fff>; */
- /* }; */
-
- dma_apbh: dma-apbh@00110000 {
- compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
- reg = <0x00110000 0x2000>;
- interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
- #dma-cells = <1>;
- dma-channels = <4>;
- clocks = <&clks 106>;
- };
-
- /* irq_sec_vio: caam_secvio { */
- /* compatible = "fsl,imx6q-caam-secvio"; */
- /* interrupts = <0 20 0x04>; */
- /* secvio_src = <0x8000001d>; */
- /* }; */
-
- /* gpmi: gpmi-nand@00112000 { */
- /* compatible = "fsl,imx6q-gpmi-nand"; */
- /* #address-cells = <1>; */
- /* #size-cells = <1>; */
- /* reg = <0x00112000 0x2000>, <0x00114000 0x2000>; */
- /* reg-names = "gpmi-nand", "bch"; */
- /* interrupts = <0 15 0x04>; */
- /* interrupt-names = "bch"; */
- /* clocks = <&clks 152>, <&clks 153>, <&clks 151>, */
- /* <&clks 150>, <&clks 149>; */
- /* clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", */
- /* "gpmi_bch_apb", "per1_bch"; */
- /* dmas = <&dma_apbh 0>; */
- /* dma-names = "rx-tx"; */
- /* status = "disabled"; */
- /* }; */
-
- timer@00a00600 {

- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x00a00600 0x20>;

- interrupts = <1 13 0xf01>;
- clocks = <&clks 15>;
- };
-
- L2: l2-cache@00a02000 {
- compatible = "arm,pl310-cache";
- reg = <0x00a02000 0x1000>;
- interrupts = <0 92 0x04>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <4 2 3>;
- arm,data-latency = <4 2 3>;
- };
-
- /* pcie: pcie@0x01000000 { */
- /* compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; */
- /* reg = <0x01ffc000 0x04000>, */
- /* <0x01f00000 0x80000>; */
- /* reg-names = "dbi", "config"; */
- /* #address-cells = <3>; */
- /* #size-cells = <2>; */
- /* device_type = "pci"; */
- /* ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /\* configuration space *\/ */
- /* 0x81000000 0 0 0x01f80000 0 0x00010000 /\* downstream I/O *\/ */
- /* 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /\* non-prefetchable memory *\/ */
- /* num-lanes = <1>; */
- /* interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; */
- /* interrupt-names = "msi"; */
- /* #interrupt-cells = <1>; */
- /* clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>; */
- /* clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate"; */
- /* status = "disabled"; */
- /* }; */
-
- /* pmu { */
- /* compatible = "arm,cortex-a9-pmu"; */
- /* interrupts = <0 94 0x04>; */
- /* }; */
-
- aips-bus@02000000 { /* AIPS1 */

- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x02000000 0x100000>;
- ranges;
-

- spba-bus@02000000 {

- compatible = "fsl,spba-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;

- reg = <0x02000000 0x40000>;
- ranges;
-
- /* spdif: spdif@02004000 { */
- /* compatible = "fsl,imx6q-spdif", */
- /* "fsl,imx35-spdif"; */
- /* reg = <0x02004000 0x4000>; */
- /* interrupts = <0 52 0x04>; */
- /* dmas = <&sdma 14 18 0>, */
- /* <&sdma 15 18 0>; */
- /* dma-names = "rx", "tx"; */
- /* clocks = <&clks 197>, <&clks 3>, */
- /* <&clks 197>, <&clks 107>, */
- /* <&clks 0>, <&clks 118>, */
- /* <&clks 62>, <&clks 139>, */
- /* <&clks 0>, <&clks 156>; */
- /* clock-names = "core", "rxtx0", */
- /* "rxtx1", "rxtx2", */
- /* "rxtx3", "rxtx4", */
- /* "rxtx5", "rxtx6", */
- /* "rxtx7", "dma"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ecspi1: ecspi@02008000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; */
- /* reg = <0x02008000 0x4000>; */
- /* interrupts = <0 31 0x04>; */
- /* clocks = <&clks 112>, <&clks 112>; */
- /* clock-names = "ipg", "per"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ecspi2: ecspi@0200c000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; */
- /* reg = <0x0200c000 0x4000>; */
- /* interrupts = <0 32 0x04>; */
- /* clocks = <&clks 113>, <&clks 113>; */
- /* clock-names = "ipg", "per"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ecspi3: ecspi@02010000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; */
- /* reg = <0x02010000 0x4000>; */
- /* interrupts = <0 33 0x04>; */
- /* clocks = <&clks 114>, <&clks 114>; */
- /* clock-names = "ipg", "per"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ecspi4: ecspi@02014000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; */
- /* reg = <0x02014000 0x4000>; */
- /* interrupts = <0 34 0x04>; */
- /* clocks = <&clks 115>, <&clks 115>; */
- /* clock-names = "ipg", "per"; */
- /* status = "disabled"; */
- /* }; */
-
- /* uart1: serial@02020000 { */
- /* compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; */
- /* reg = <0x02020000 0x4000>; */
- /* interrupts = <0 26 0x04>; */
- /* clocks = <&clks 160>, <&clks 161>; */
- /* clock-names = "ipg", "per"; */
- /* dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; */
- /* dma-names = "rx", "tx"; */
- /* status = "disabled"; */
- /* }; */
-
- /* esai: esai@02024000 { */
- /* compatible = "fsl,imx6q-esai"; */
- /* reg = <0x02024000 0x4000>; */
- /* interrupts = <0 51 0x04>; */
- /* clocks = <&clks 118>, <&clks 156>; */
- /* clock-names = "core", "dma"; */
- /* fsl,esai-dma-events = <24 23>; */
- /* fsl,flags = <1>; */
- /* status = "disabled"; */
- /* }; */
-
- /* ssi1: ssi@02028000 { */
- /* compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; */
- /* reg = <0x02028000 0x4000>; */
- /* interrupts = <0 46 0x04>; */
- /* clocks = <&clks 178>, <&clks 157>; */
- /* clock-names = "ipg", "baud"; */
- /* dmas = <&sdma 37 1 0>, */
- /* <&sdma 38 1 0>; */
- /* dma-names = "rx", "tx"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ssi2: ssi@0202c000 { */
- /* compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; */
- /* reg = <0x0202c000 0x4000>; */
- /* interrupts = <0 47 0x04>; */
- /* clocks = <&clks 179>, <&clks 158>; */
- /* clock-names = "ipg", "baud"; */
- /* dmas = <&sdma 41 1 0>, */
- /* <&sdma 42 1 0>; */
- /* dma-names = "rx", "tx"; */
- /* status = "disabled"; */
- /* }; */
-
- /* ssi3: ssi@02030000 { */
- /* compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; */
- /* reg = <0x02030000 0x4000>; */
- /* interrupts = <0 48 0x04>; */
- /* clocks = <&clks 180>, <&clks 159>; */
- /* clock-names = "ipg", "baud"; */
- /* dmas = <&sdma 45 1 0>, */
- /* <&sdma 46 1 0>; */
- /* dma-names = "rx", "tx"; */
- /* status = "disabled"; */
- /* }; */
-
- asrc: asrc@02034000 {
- compatible = "fsl,imx53-asrc";
- reg = <0x02034000 0x4000>;
- interrupts = <0 50 0x04>;
- clocks = <&clks 107>, <&clks 156>;
- clock-names = "core", "dma";
- dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
- <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
- dma-names = "rxa", "rxb", "rxc",
- "txa", "txb", "txc";

- status = "okay";
- };
-

- /* asrc_p2p: asrc_p2p { */
- /* compatible = "fsl,imx6q-asrc-p2p"; */
- /* fsl,output-rate = <48000>; */
- /* fsl,output-width = <16>; */
- /* fsl,asrc-dma-rx-events = <17 18 19>; */
- /* fsl,asrc-dma-tx-events = <20 21 22>; */
- /* status = "okay"; */
- /* }; */
-
- /* spba@0203c000 { */
- /* reg = <0x0203c000 0x4000>; */
- /* }; */
- };
-
- vpu: vpu@02040000 {
- compatible = "fsl,imx6-vpu";
- reg = <0x02040000 0x3c000>;
- reg-names = "vpu_regs";
- interrupts = <0 3 0x01>, <0 12 0x04>;
- interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
- clocks = <&clks 168>, <&clks 140>, <&clks 142>;
- clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
- iramsize = <0x21000>;
- iram = <&ocram>;
- resets = <&src 1>;
- pu-supply = <&reg_pu>;

- status = "disabled";
- };
-

- /* aipstz@0207c000 { /\* AIPSTZ1 *\/ */
- /* reg = <0x0207c000 0x4000>; */
- /* }; */
-
- /* pwm1: pwm@02080000 { */
- /* #pwm-cells = <2>; */
- /* compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; */
- /* reg = <0x02080000 0x4000>; */
- /* interrupts = <0 83 0x04>; */
- /* clocks = <&clks 62>, <&clks 145>; */
- /* clock-names = "ipg", "per"; */
- /* }; */
-
- /* pwm2: pwm@02084000 { */
- /* #pwm-cells = <2>; */
- /* compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; */
- /* reg = <0x02084000 0x4000>; */
- /* interrupts = <0 84 0x04>; */
- /* clocks = <&clks 62>, <&clks 146>; */
- /* clock-names = "ipg", "per"; */
- /* }; */
-
- /* pwm3: pwm@02088000 { */
- /* #pwm-cells = <2>; */
- /* compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; */
- /* reg = <0x02088000 0x4000>; */
- /* interrupts = <0 85 0x04>; */
- /* clocks = <&clks 62>, <&clks 147>; */
- /* clock-names = "ipg", "per"; */
- /* }; */
-
- pwm4: pwm@0208c000 {

- #pwm-cells = <2>;
- compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
- reg = <0x0208c000 0x4000>;

- interrupts = <0 86 0x04>;
- clocks = <&clks 62>, <&clks 148>;

- clock-names = "ipg", "per";
- };
-

- /* flexcan1: can@02090000 { */
- /* compatible = "fsl,imx6q-flexcan"; */
- /* reg = <0x02090000 0x4000>; */
- /* interrupts = <0 110 0x04>; */
- /* clocks = <&clks 108>, <&clks 109>; */
- /* clock-names = "ipg", "per"; */
- /* gpr = <&gpr>; */
- /* status = "disabled"; */
- /* }; */
-
- /* flexcan2: can@02094000 { */
- /* compatible = "fsl,imx6q-flexcan"; */
- /* reg = <0x02094000 0x4000>; */
- /* interrupts = <0 111 0x04>; */
- /* clocks = <&clks 110>, <&clks 111>; */
- /* clock-names = "ipg", "per"; */
- /* gpr = <&gpr>; */
- /* status = "disabled"; */
- /* }; */
-
- gpt: gpt@02098000 {
- compatible = "fsl,imx6q-gpt";

- reg = <0x02098000 0x4000>;

- interrupts = <0 55 0x04>;
- clocks = <&clks 119>, <&clks 120>;

- clock-names = "ipg", "per";
- };
-

- /* gpio1: gpio@0209c000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x0209c000 0x4000>; */
- /* interrupts = <0 66 0x04 0 67 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- /* gpio2: gpio@020a0000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x020a0000 0x4000>; */
- /* interrupts = <0 68 0x04 0 69 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- /* gpio3: gpio@020a4000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x020a4000 0x4000>; */
- /* interrupts = <0 70 0x04 0 71 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- /* gpio4: gpio@020a8000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x020a8000 0x4000>; */
- /* interrupts = <0 72 0x04 0 73 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- /* gpio5: gpio@020ac000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x020ac000 0x4000>; */
- /* interrupts = <0 74 0x04 0 75 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- /* gpio6: gpio@020b0000 { */
- /* compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; */
- /* reg = <0x020b0000 0x4000>; */
- /* interrupts = <0 76 0x04 0 77 0x04>; */
- /* gpio-controller; */
- /* #gpio-cells = <2>; */
- /* interrupt-controller; */
- /* #interrupt-cells = <2>; */
- /* }; */
-
- gpio7: gpio@020b4000 {

- compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
- reg = <0x020b4000 0x4000>;

- interrupts = <0 78 0x04 0 79 0x04>;

- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-

- /* kpp: kpp@020b8000 { */
- /* reg = <0x020b8000 0x4000>; */
- /* interrupts = <0 82 0x04>; */
- /* }; */
-
- wdog1: wdog@020bc000 {
- compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
- reg = <0x020bc000 0x4000>;
- interrupts = <0 80 0x04>;
- clocks = <&clks 0>;
- };
-
- wdog2: wdog@020c0000 {
- compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
- reg = <0x020c0000 0x4000>;
- interrupts = <0 81 0x04>;
- clocks = <&clks 0>;

- status = "disabled";
- };
-

- clks: ccm@020c4000 {

- compatible = "fsl,imx6q-ccm";
- reg = <0x020c4000 0x4000>;

- interrupts = <0 87 0x04 0 88 0x04>;

- #clock-cells = <1>;
- };
-

- anatop: anatop@020c8000 {

- compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
- reg = <0x020c8000 0x1000>;

- interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
-
- regulator-1p1@110 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd1p1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1375000>;
- regulator-always-on;
- anatop-reg-offset = <0x110>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <4>;
- anatop-min-voltage = <800000>;
- anatop-max-voltage = <1375000>;
- };
-
- regulator-3p0@120 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd3p0";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
- anatop-reg-offset = <0x120>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <0>;
- anatop-min-voltage = <2625000>;
- anatop-max-voltage = <3400000>;
- };
-
- regulator-2p5@130 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd2p5";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2750000>;
- regulator-always-on;
- anatop-reg-offset = <0x130>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <0>;
- anatop-min-voltage = <2000000>;
- anatop-max-voltage = <2750000>;
- };
-
- reg_arm: regulator-vddcore@140 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "cpu";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <0>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <24>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
-
- reg_pu: regulator-vddpu@140 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddpu";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <9>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <26>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
-
- reg_soc: regulator-vddsoc@140 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddsoc";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <18>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <28>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
- };
-
- /* tempmon: tempmon { */
- /* compatible = "fsl,imx6q-tempmon"; */
- /* interrupts = <0 49 0x04>; */
- /* fsl,tempmon = <&anatop>; */
- /* fsl,tempmon-data = <&ocotp>; */
- /* clocks = <&clks 172>; */
- /* }; */
-
- /* usbphy1: usbphy@020c9000 { */
- /* compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; */
- /* reg = <0x020c9000 0x1000>; */
- /* interrupts = <0 44 0x04>; */
- /* clocks = <&clks 182>; */
- /* fsl,anatop = <&anatop>; */
- /* }; */
-
- /* usbphy2: usbphy@020ca000 { */
- /* compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; */
- /* reg = <0x020ca000 0x1000>; */
- /* interrupts = <0 45 0x04>; */
- /* clocks = <&clks 183>; */
- /* fsl,anatop = <&anatop>; */
- /* }; */
-
- /* usbphy_nop1: usbphy_nop1 { */
- /* compatible = "usb-nop-xceiv"; */
- /* clocks = <&clks 182>; */
- /* clock-names = "main_clk"; */
- /* }; */
-
- /* usbphy_nop2: usbphy_nop2 { */
- /* compatible = "usb-nop-xceiv"; */
- /* clocks = <&clks 182>; */
- /* clock-names = "main_clk"; */
- /* }; */
-
- /* caam_snvs: caam-snvs@020cc000 { */
- /* compatible = "fsl,imx6q-caam-snvs"; */
- /* reg = <0x020cc000 0x4000>; */
- /* }; */
-
- /* snvs@020cc000 { */
- /* compatible = "fsl,sec-v4.0-mon", "simple-bus"; */
- /* #address-cells = <1>; */
- /* #size-cells = <1>; */
- /* ranges = <0 0x020cc000 0x4000>; */
-
- /* snvs-rtc-lp@34 { */
- /* compatible = "fsl,sec-v4.0-mon-rtc-lp"; */
- /* reg = <0x34 0x58>; */
- /* interrupts = <0 19 0x04 0 20 0x04>; */
- /* }; */
- /* }; */
-
- /* epit1: epit@020d0000 { /\* EPIT1 *\/ */
- /* reg = <0x020d0000 0x4000>; */
- /* interrupts = <0 56 0x04>; */
- /* }; */
-
- /* epit2: epit@020d4000 { /\* EPIT2 *\/ */
- /* reg = <0x020d4000 0x4000>; */
- /* interrupts = <0 57 0x04>; */
- /* }; */
-
- src: src@020d8000 {

- compatible = "fsl,imx6q-src", "fsl,imx51-src";
- reg = <0x020d8000 0x4000>;

- interrupts = <0 91 0x04 0 96 0x04>;

- #reset-cells = <1>;
- };
-

- gpc: gpc@020dc000 {

- compatible = "fsl,imx6q-gpc";
- reg = <0x020dc000 0x4000>;

- interrupts = <0 89 0x04 0 90 0x04>;
- clocks = <&clks 122>, <&clks 74>, <&clks 121>,
- <&clks 26>, <&clks 143>, <&clks 168>, <&clks 62>;
- clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core",
- "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg";
- pu-supply = <&reg_pu>;
- };
-
- gpr: iomuxc-gpr@020e0000 {
- compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
- reg = <0x020e0000 0x38>;
- };
-
- iomuxc: iomuxc@020e0000 {

- reg = <0x020e0000 0x4000>;
- };
-

- ldb: ldb@020e0008 {

- compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
- reg = <0x020e0000 0x4000>;

- clocks = <&clks 135>, <&clks 136>,
- <&clks 39>, <&clks 40>,
- <&clks 41>, <&clks 42>,
- <&clks 184>, <&clks 185>,
- <&clks 205>, <&clks 206>,
- <&clks 207>, <&clks 208>;

- clock-names = "ldb_di0", "ldb_di1",
- "ipu1_di0_sel", "ipu1_di1_sel",
- "ipu2_di0_sel", "ipu2_di1_sel",
- "di0_div_3_5", "di1_div_3_5",
- "di0_div_7", "di1_div_7",
- "di0_div_sel", "di1_div_sel";
- status = "disabled";
- };
-

- /* dcic1: dcic@020e4000 { */
- /* reg = <0x020e4000 0x4000>; */
- /* interrupts = <0 124 0x04>; */
- /* }; */
-
- /* dcic2: dcic@020e8000 { */
- /* reg = <0x020e8000 0x4000>; */
- /* interrupts = <0 125 0x04>; */
- /* }; */
-
- sdma: sdma@020ec000 {
- compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
- reg = <0x020ec000 0x4000>;
- interrupts = <0 2 0x04>;
- clocks = <&clks 155>, <&clks 155>;

- clock-names = "ipg", "ahb";

- #dma-cells = <3>;
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
- };
- };
-
- aips-bus@02100000 { /* AIPS2 */

- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;

- reg = <0x02100000 0x100000>;
- ranges;
-
- /* crypto: caam@2100000 { */
- /* compatible = "fsl,sec-v4.0"; */
- /* #address-cells = <1>; */
- /* #size-cells = <1>; */
- /* reg = <0x2100000 0x40000>; */
- /* ranges = <0 0x2100000 0x40000>; */
- /* interrupt-parent = <&intc>; /\* interrupts = <0 92 0x4>; *\/ */
- /* clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>; */
- /* clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; */
-
- /* sec_jr0: jr0@1000 { */
- /* compatible = "fsl,sec-v4.0-job-ring"; */
- /* reg = <0x1000 0x1000>; */
- /* interrupt-parent = <&intc>; */
- /* interrupts = <0 105 0x4>; */
- /* }; */
-
- /* sec_jr1: jr1@2000 { */
- /* compatible = "fsl,sec-v4.0-job-ring"; */
- /* reg = <0x2000 0x1000>; */
- /* interrupt-parent = <&intc>; */
- /* interrupts = <0 106 0x4>; */
- /* }; */
- /* }; */
-
- aipstz@0217c000 { /* AIPSTZ2 */
- reg = <0x0217c000 0x4000>;
- };
-
- /* usbotg: usb@02184000 { */
- /* compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; */
- /* reg = <0x02184000 0x200>; */
- /* interrupts = <0 43 0x04>; */
- /* clocks = <&clks 162>; */
- /* fsl,usbphy = <&usbphy1>; */
- /* fsl,usbmisc = <&usbmisc 0>; */
- /* fsl,anatop = <&anatop>; */
- /* status = "disabled"; */
- /* }; */
-
- /* usbh1: usb@02184200 { */
- /* compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; */
- /* reg = <0x02184200 0x200>; */
- /* interrupts = <0 40 0x04>; */
- /* clocks = <&clks 162>; */
- /* fsl,usbphy = <&usbphy2>; */
- /* fsl,usbmisc = <&usbmisc 1>; */
- /* status = "disabled"; */
- /* }; */
-
- /* usbh2: usb@02184400 { */
- /* compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; */
- /* reg = <0x02184400 0x200>; */
- /* interrupts = <0 41 0x04>; */
- /* clocks = <&clks 162>; */
- /* fsl,usbmisc = <&usbmisc 2>; */
- /* phy_type = "hsic"; */
- /* fsl,usbphy = <&usbphy_nop1>; */
- /* fsl,anatop = <&anatop>; */
- /* status = "disabled"; */
- /* }; */
-
- /* usbh3: usb@02184600 { */
- /* compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; */
- /* reg = <0x02184600 0x200>; */
- /* interrupts = <0 42 0x04>; */
- /* clocks = <&clks 162>; */
- /* fsl,usbmisc = <&usbmisc 3>; */
- /* phy_type = "hsic"; */
- /* fsl,usbphy = <&usbphy_nop2>; */
- /* fsl,anatop = <&anatop>; */
- /* status = "disabled"; */
- /* }; */
-
- /* usbmisc: usbmisc: usbmisc@02184800 { */
- /* #index-cells = <1>; */
- /* compatible = "fsl,imx6q-usbmisc"; */
- /* reg = <0x02184800 0x200>; */
- /* clocks = <&clks 162>; */
- /* }; */
-
- /* fec: ethernet@02188000 { */
- /* compatible = "fsl,imx6q-fec"; */
- /* reg = <0x02188000 0x4000>; */
- /* interrupts-extended = <&intc 0 118 0x04>, */
- /* <&intc 0 119 0x04>; */
- /* clocks = <&clks 117>, <&clks 117>, <&clks 190>; */
- /* clock-names = "ipg", "ahb", "ptp"; */
- /* status = "disabled"; */
- /* }; */
-
- mlb: mlb@0218c000 {
- compatible = "fsl,imx6q-mlb150";
- reg = <0x0218c000 0x4000>;
- interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
- clocks = <&clks 139>, <&clks 175>;
- clock-names = "mlb", "pll8_mlb";
- iram = <&ocram>;

- status = "disabled";
- };
-

- /* usdhc1: usdhc@02190000 { */
- /* compatible = "fsl,imx6q-usdhc"; */
- /* reg = <0x02190000 0x4000>; */
- /* interrupts = <0 22 0x04>; */
- /* clocks = <&clks 163>, <&clks 163>, <&clks 163>; */
- /* clock-names = "ipg", "ahb", "per"; */
- /* bus-width = <4>; */
- /* status = "disabled"; */
- /* }; */
-
- /* usdhc2: usdhc@02194000 { */
- /* compatible = "fsl,imx6q-usdhc"; */
- /* reg = <0x02194000 0x4000>; */
- /* interrupts = <0 23 0x04>; */
- /* clocks = <&clks 164>, <&clks 164>, <&clks 164>; */
- /* clock-names = "ipg", "ahb", "per"; */
- /* bus-width = <4>; */
- /* status = "disabled"; */
- /* }; */
-
- usdhc3: usdhc@02198000 {

- compatible = "fsl,imx6q-usdhc";
- reg = <0x02198000 0x4000>;

- interrupts = <0 24 0x04>;
- clocks = <&clks 165>, <&clks 165>, <&clks 165>;

- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-

- /* usdhc4: usdhc@0219c000 { */
- /* compatible = "fsl,imx6q-usdhc"; */
- /* reg = <0x0219c000 0x4000>; */
- /* interrupts = <0 25 0x04>; */
- /* clocks = <&clks 166>, <&clks 166>, <&clks 166>; */
- /* clock-names = "ipg", "ahb", "per"; */
- /* bus-width = <4>; */
- /* status = "disabled"; */
- /* }; */
-
- /* i2c1: i2c@021a0000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; */
- /* reg = <0x021a0000 0x4000>; */
- /* interrupts = <0 36 0x04>; */
- /* clocks = <&clks 125>; */
- /* status = "disabled"; */
- /* }; */
-
- /* i2c2: i2c@021a4000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; */
- /* reg = <0x021a4000 0x4000>; */
- /* interrupts = <0 37 0x04>; */
- /* clocks = <&clks 126>; */
- /* status = "disabled"; */
- /* }; */
-
- /* i2c3: i2c@021a8000 { */
- /* #address-cells = <1>; */
- /* #size-cells = <0>; */
- /* compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; */
- /* reg = <0x021a8000 0x4000>; */
- /* interrupts = <0 38 0x04>; */
- /* clocks = <&clks 127>; */
- /* status = "disabled"; */
- /* }; */
-
- romcp@021ac000 {
- reg = <0x021ac000 0x4000>;
- };
-
- /* mmdc0-1@021b0000 { /\* MMDC0-1 *\/ */
- /* compatible = "fsl,imx6q-mmdc-combine"; */
- /* reg = <0x021b0000 0x8000>; */
- /* }; */
-
- /* mmdc0: mmdc@021b0000 { /\* MMDC0 *\/ */
- /* compatible = "fsl,imx6q-mmdc"; */
- /* reg = <0x021b0000 0x4000>; */
- /* }; */
-
- /* mmdc1: mmdc@021b4000 { /\* MMDC1 *\/ */
- /* reg = <0x021b4000 0x4000>; */
- /* }; */
-
- /* weim: weim@021b8000 { */
- /* compatible = "fsl,imx6q-weim"; */
- /* reg = <0x021b8000 0x4000>; */
- /* interrupts = <0 14 0x04>; */
- /* clocks = <&clks 196>; */
- /* }; */
-
- /* ocotp: ocotp-ctrl@021bc000 { */
- /* compatible = "syscon"; */
- /* reg = <0x021bc000 0x4000>; */
- /* }; */
-
- /* ocotp-fuse@021bc000 { */
- /* compatible = "fsl,imx6q-ocotp"; */
- /* reg = <0x021bc000 0x4000>; */
- /* clocks = <&clks 128>; */
- /* }; */
-
- /* tzasc@021d0000 { /\* TZASC1 *\/ */
- /* reg = <0x021d0000 0x4000>; */
- /* interrupts = <0 108 0x04>; */
- /* }; */
-
- /* tzasc@021d4000 { /\* TZASC2 *\/ */
- /* reg = <0x021d4000 0x4000>; */
- /* interrupts = <0 109 0x04>; */
- /* }; */
-
- /* audmux: audmux@021d8000 { */
- /* compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; */
- /* reg = <0x021d8000 0x4000>; */
- /* status = "disabled"; */
- /* }; */
-
- /* mipi_csi: mipi_csi@021dc000 { */
- /* compatible = "fsl,imx6q-mipi-csi2"; */
- /* reg = <0x021dc000 0x4000>; */
- /* interrupts = <0 100 0x04>, <0 101 0x04>; */
- /* clocks = <&clks 138>, <&clks 53>, <&clks 204>; */
- /* /\* Note: clks 138 is hsi_tx, however, the dphy_c */
- /* * hsi_tx and pll_refclk use the same clk gate. */
- /* * In current clk driver, open/close clk gate do */
- /* * use hsi_tx for a temporary debug purpose. */
- /* *\/ */
- /* clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; */
- /* status = "disabled"; */
- /* }; */
-
- vdoa@021e4000 {

- compatible = "fsl,imx6q-vdoa";
- reg = <0x021e4000 0x4000>;

- interrupts = <0 18 0x04>;
- clocks = <&clks 202>;

- iram = <&ocram>;
- };
-

- uart2: serial@021e8000 {
- compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

- reg = <0x021e8000 0x4000>;

- interrupts = <0 27 0x04>;
- clocks = <&clks 160>, <&clks 161>;

- clock-names = "ipg", "per";

- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
- dma-names = "rx", "tx";

- status = "disabled";
- };
-

- uart3: serial@021ec000 {
- compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

- reg = <0x021ec000 0x4000>;

- interrupts = <0 28 0x04>;
- clocks = <&clks 160>, <&clks 161>;

- clock-names = "ipg", "per";

- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
- dma-names = "rx", "tx";

- status = "disabled";
- };
-

- uart4: serial@021f0000 {
- compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

- reg = <0x021f0000 0x4000>;

- interrupts = <0 29 0x04>;
- clocks = <&clks 160>, <&clks 161>;

- clock-names = "ipg", "per";

- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
- dma-names = "rx", "tx";

- status = "disabled";
- };
-

- uart5: serial@021f4000 {
- compatible = "fsl,imx6q-uart", "fsl,imx21-uart";

- reg = <0x021f4000 0x4000>;

- interrupts = <0 30 0x04>;
- clocks = <&clks 160>, <&clks 161>;

- clock-names = "ipg", "per";

- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
- dma-names = "rx", "tx";

- status = "disabled";
- };
- };
-

- ipu1: ipu@02400000 {

- compatible = "fsl,imx6q-ipu";
- reg = <0x02400000 0x400000>;

- interrupts = <0 6 0x4 0 5 0x4>;
- clocks = <&clks 130>, <&clks 131>, <&clks 132>,
- <&clks 39>, <&clks 40>,
- <&clks 135>, <&clks 136>,
- <&clks 8>, <&clks 195>;

- clock-names = "bus", "di0", "di1",
- "di0_sel", "di1_sel",

- "ldb_di0", "ldb_di1",
- "540m", "video_pll";

- resets = <&src 2>;
- bypass_reset = <0>;
- };
- };

-};
-
-
-&iomuxc {
- audmux {
- pinctrl_audmux_1: audmux-1 {
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
- >;
- };
-
- pinctrl_audmux_2: audmux-2 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
- >;
- };
-
- pinctrl_audmux_3: audmux-3 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0

- >;
- };
- };
-
- ecspi1 {

- pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
- >;
- };
-

- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- >;
- };
-

- pinctrl_ecspi1_2: ecspi1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- >;
- };
- };
-
- ecspi3 {
- pinctrl_ecspi3_1: ecspi3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
- >;
- };
- };
-

- pinctrl_enet_3: enetgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- >;
- };
-
- pinctrl_enet_4: enetgrp-4 {
- fsl,pins = <

- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0

- >;
- };
-
- };
-
- esai {
- pinctrl_esai_1: esaigrp-1 {
- fsl,pins = <
- MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
- >;
- };
-
- pinctrl_esai_2: esaigrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
- >;
- };
- };
-
- flexcan1 {
- pinctrl_flexcan1_1: flexcan1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
- >;
- };
-
- pinctrl_flexcan1_2: flexcan1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
- >;
- };
- };
-
- flexcan2 {
- pinctrl_flexcan2_1: flexcan2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
- >;
- };
- };
-
- gpmi-nand {
- pinctrl_gpmi_nand_1: gpmi-nand-1 {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
- };
-
- hdmi_hdcp {
- pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
- >;
- };
- };
-
- hdmi_cec {
- pinctrl_hdmi_cec_1: hdmicecgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
- >;
- };
-
- pinctrl_hdmi_cec_2: hdmicecgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0

- ipu1 {
- pinctrl_ipu1_1: ipu1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
- >;
- };
-
- pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
- MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
- >;
- };
-
- pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
- >;
- };
-
- pinctrl_ipu1_4: ipu1grp-4 {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10

- >;
- };
-
- };
-

- mlb {
- pinctrl_mlb_1: mlbgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
- >;
- };
-
- pinctrl_mlb_2: mlbgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
- >;
- };
- };
-
- pwm1 {
- pinctrl_pwm1_1: pwm1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm1_2: pwm1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm1_3: pwm1grp-3 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
- >;
- };
- };
-
- pwm2 {
- pinctrl_pwm2_1: pwm2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm2_2: pwm2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm2_3: pwm2grp-3 {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
- >;
- };
- };
-
- pwm3 {
- pinctrl_pwm3_1: pwm3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm3_2: pwm3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
- };
-
- pwm4 {
- pinctrl_pwm4_1: pwm4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
- >;
- };
- pinctrl_pwm4_2: pwm4grp-2 {

- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
- >;
- };
- };
-

- spdif {
- pinctrl_spdif_1: spdifgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
- >;
- };
-
- pinctrl_spdif_2: spdifgrp-2 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
- >;
- };
- };
-
- uart1 {
- pinctrl_uart1_1: uart1grp-1 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart1_2: uart1grp-2 {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- >;
- };
- };
-
- uart2 {
- pinctrl_uart2_1: uart2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
- fsl,pins = <
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
- >;
- };
- };
-
- uart3 {
- pinctrl_uart3_1: uart3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
- >;
- };
- pinctrl_uart3_2: uart3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
- >;
- };
- };
-
- uart4 {
- pinctrl_uart4_1: uart4grp-1 {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
- };
-
- usbotg {
- pinctrl_usbotg_1: usbotggrp-1 {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usbotg_2: usbotggrp-2 {
- fsl,pins = <
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
- >;
- };
- };
-
- usbh2 {
- pinctrl_usbh2_1: usbh2grp-1 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
- >;
- };
-
- pinctrl_usbh2_2: usbh2grp-2 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
- >;
- };
- };
-
- usbh3 {
- pinctrl_usbh3_1: usbh3grp-1 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
- >;
- };
-
- pinctrl_usbh3_2: usbh3grp-2 {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030

- >;
- };
- };
-
- usdhc1 {
- pinctrl_usdhc1_1: usdhc1grp-1 {
- fsl,pins = <

- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071

- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9

- >;
- };
-
- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
- fsl,pins = <

- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9

- weim {
- pinctrl_weim_cs0_1: weim_cs0grp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
- >;
- };
-
- pinctrl_weim_nor_1: weim_norgrp-1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
- /* data */
- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
- /* address */
- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
- >;
- };
- };
-};
diff --git a/tests/arm32/sabrelite/linux/linux-4.5.y_defconfig b/tests/arm32/sabrelite/linux/linux-4.5.y_defconfig
deleted file mode 100644
index d862a072..00000000
--- a/tests/arm32/sabrelite/linux/linux-4.5.y_defconfig
+++ /dev/null
@@ -1,4077 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm 4.5.0 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_EXTABLE_SORT=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KERNEL_LZO=y
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_DEFAULT_HOSTNAME="(none)"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_FHANDLE=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_IRQ_DOMAIN_DEBUG is not set
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-# CONFIG_IRQ_TIME_ACCOUNTING is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-# CONFIG_TASKS_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_EXPEDITE_BOOT is not set
-CONFIG_BUILD_BIN2C=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_CGROUPS=y
-# CONFIG_MEMCG is not set
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUP_PIDS is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CPUSETS is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CHECKPOINT_RESTORE is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_HAVE_UID16=y
-CONFIG_BPF=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-# CONFIG_SGETMASK_SYSCALL is not set
-CONFIG_SYSFS_SYSCALL=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-# CONFIG_BPF_SYSCALL is not set
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_ADVISE_SYSCALLS=y
-# CONFIG_USERFAULTFD is not set
-CONFIG_PCI_QUIRKS=y
-CONFIG_MEMBARRIER=y
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLUB_CPU_PARTIAL=y
-# CONFIG_SYSTEM_DATA_VERIFICATION is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_JUMP_LABEL is not set
-# CONFIG_UPROBES is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-# CONFIG_CC_STACKPROTECTOR is not set
-CONFIG_CC_STACKPROTECTOR_NONE=y
-# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
-# CONFIG_CC_STACKPROTECTOR_STRONG is not set
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-# CONFIG_MODULE_COMPRESS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_BSGLIB is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-# CONFIG_BLK_CMDLINE_PARSER is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C24XX is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP1 is not set
-
-#
-# Multiple platform selection
-#
-
-#
-# CPU Core family selection
-#
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MULTI_V6_V7=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_VIRT is not set
-# CONFIG_ARCH_MVEBU is not set
-# CONFIG_ARCH_ALPINE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCM is not set
-# CONFIG_ARCH_BERLIN is not set
-# CONFIG_ARCH_CNS3XXX is not set
-# CONFIG_ARCH_DIGICOLOR is not set
-# CONFIG_ARCH_HIGHBANK is not set
-# CONFIG_ARCH_HISI is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_KEYSTONE is not set
-# CONFIG_ARCH_MESON is not set
-CONFIG_ARCH_MXC=y
-CONFIG_MXC_TZIC=y
-CONFIG_MXC_AVIC=y
-CONFIG_MXC_DEBUG_BOARD=y
-CONFIG_HAVE_EPIT=y
-# CONFIG_MXC_USE_EPIT is not set
-CONFIG_ARCH_HAS_RNGA=y
-CONFIG_HAVE_IMX_ANATOP=y
-CONFIG_HAVE_IMX_GPC=y
-CONFIG_HAVE_IMX_MMDC=y
-CONFIG_HAVE_IMX_SRC=y
-CONFIG_ARCH_MXC_IOMUX_V3=y
-CONFIG_SOC_IMX31=y
-CONFIG_SOC_IMX35=y
-
-#
-# MX31 platforms:
-#
-CONFIG_MACH_MX31ADS=y
-CONFIG_MACH_MX31LILLY=y
-CONFIG_MACH_MX31LITE=y
-CONFIG_MACH_PCM037=y
-CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31_3DS=y
-# CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT is not set
-CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_QONG=y
-CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_KZM_ARM11_01=y
-CONFIG_MACH_BUG=y
-CONFIG_MACH_IMX31_DT=y
-
-#
-# MX35 platforms:
-#
-CONFIG_MACH_IMX35_DT=y
-CONFIG_MACH_PCM043=y
-CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_VPR200=y
-
-#
-# Device tree only
-#
-
-#
-# Cortex-A platforms
-#
-CONFIG_SOC_IMX5=y
-CONFIG_SOC_IMX50=y
-CONFIG_SOC_IMX51=y
-CONFIG_SOC_IMX53=y
-CONFIG_SOC_IMX6=y
-CONFIG_SOC_IMX6Q=y
-CONFIG_SOC_IMX6SL=y
-CONFIG_SOC_IMX6SX=y
-CONFIG_SOC_IMX6UL=y
-CONFIG_SOC_IMX7D=y
-# CONFIG_SOC_LS1021A is not set
-
-#
-# Cortex-A/Cortex-M asymmetric multiprocessing platforms
-#
-CONFIG_SOC_VF610=y
-CONFIG_VF_USE_ARM_GLOBAL_TIMER=y
-# CONFIG_VF_USE_PIT_TIMER is not set
-CONFIG_IMX_HAVE_PLATFORM_FEC=y
-CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y
-CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
-CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
-CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_FB=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
-CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
-CONFIG_IMX_HAVE_PLATFORM_IPU_CORE=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_MMC=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_RTC=y
-CONFIG_IMX_HAVE_PLATFORM_MXC_W1=y
-CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
-CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
-# CONFIG_ARCH_MEDIATEK is not set
-
-#
-# TI OMAP/AM/DM/DRA Family
-#
-# CONFIG_ARCH_OMAP2 is not set
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_ARCH_OMAP4 is not set
-# CONFIG_SOC_OMAP5 is not set
-# CONFIG_SOC_AM33XX is not set
-# CONFIG_SOC_AM43XX is not set
-# CONFIG_SOC_DRA7XX is not set
-# CONFIG_ARCH_PICOXCELL is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_QCOM is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_ROCKCHIP is not set
-# CONFIG_ARCH_SOCFPGA is not set
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_STI is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS is not set
-# CONFIG_ARCH_RENESAS is not set
-# CONFIG_ARCH_SUNXI is not set
-# CONFIG_ARCH_SIRF is not set
-# CONFIG_ARCH_TANGO is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_UNIPHIER is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_WM8750 is not set
-# CONFIG_ARCH_WM8850 is not set
-# CONFIG_ARCH_ZX is not set
-# CONFIG_ARCH_ZYNQ is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV6=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_SWP_EMULATE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_KUSER_HELPERS=y
-# CONFIG_VDSO is not set
-CONFIG_DMA_CACHE_RWFO=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_KERNMEM_PERMS is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-# CONFIG_ARM_ERRATA_326103 is not set
-# CONFIG_ARM_ERRATA_411920 is not set
-# CONFIG_ARM_ERRATA_430973 is not set
-CONFIG_ARM_ERRATA_643719=y
-# CONFIG_ARM_ERRATA_720789 is not set
-CONFIG_ARM_ERRATA_754322=y
-# CONFIG_ARM_ERRATA_754327 is not set
-# CONFIG_ARM_ERRATA_364296 is not set
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-# CONFIG_ARM_ERRATA_798181 is not set
-# CONFIG_ARM_ERRATA_773022 is not set
-
-#
-# Bus support
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCI_MSI=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-# CONFIG_PCI_STUB is not set
-# CONFIG_PCI_IOV is not set
-# CONFIG_PCI_PRI is not set
-# CONFIG_PCI_PASID is not set
-
-#
-# PCI host controller drivers
-#
-# CONFIG_PCI_IMX6 is not set
-# CONFIG_PCI_HOST_GENERIC is not set
-# CONFIG_PCI_LAYERSCAPE is not set
-# CONFIG_PCIE_ALTERA is not set
-# CONFIG_PCIEPORTBUS is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_HAVE_SMP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_ARM_CPU_TOPOLOGY=y
-# CONFIG_SCHED_MC is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_HAVE_ARM_SCU=y
-# CONFIG_HAVE_ARM_ARCH_TIMER is not set
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_MCPM is not set
-# CONFIG_BIG_LITTLE is not set
-# CONFIG_VMSPLIT_3G is not set
-# CONFIG_VMSPLIT_3G_OPT is not set
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_NR_CPUS=4
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_ARM_PSCI is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_100=y
-# CONFIG_HZ_200 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_500 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=100
-CONFIG_SCHED_HRTICK=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-# CONFIG_HIGHMEM is not set
-CONFIG_CPU_SW_DOMAIN_PAN=y
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-# CONFIG_ARM_MODULE_PLTS is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_COMPACTION=y
-CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_AREAS=7
-# CONFIG_ZPOOL is not set
-# CONFIG_ZBUD is not set
-# CONFIG_ZSMALLOC is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_FRAME_VECTOR=y
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-# CONFIG_SECCOMP is not set
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-# CONFIG_PARAVIRT is not set
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-
-#
-# Boot options
-#
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-# CONFIG_ARM_APPENDED_DTB is not set
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_EXTEND is not set
-# CONFIG_CMDLINE_FORCE is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_EFI is not set
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-
-#
-# CPU frequency scaling drivers
-#
-# CONFIG_CPUFREQ_DT is not set
-# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
-# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
-# CONFIG_QORIQ_CPUFREQ is not set
-
-#
-# CPU Idle
-#
-# CONFIG_CPU_IDLE is not set
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-# CONFIG_KERNEL_MODE_NEON is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-
-#
-# Power management options
-#
-# CONFIG_SUSPEND is not set
-# CONFIG_HIBERNATION is not set
-# CONFIG_PM is not set
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_DIAG=y
-CONFIG_UNIX=y
-CONFIG_UNIX_DIAG=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-# CONFIG_NET_IP_TUNNEL is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_NET_UDP_TUNNEL is not set
-# CONFIG_NET_FOU is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_LRO=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NET_PTP_CLASSIFY is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-# CONFIG_DNS_RESOLVER is not set
-# CONFIG_BATMAN_ADV is not set
-# CONFIG_OPENVSWITCH is not set
-# CONFIG_VSOCKETS is not set
-# CONFIG_NETLINK_MMAP is not set
-# CONFIG_NETLINK_DIAG is not set
-# CONFIG_MPLS is not set
-# CONFIG_HSR is not set
-# CONFIG_NET_SWITCHDEV is not set
-# CONFIG_NET_L3_MASTER_DEV is not set
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-# CONFIG_SOCK_CGROUP_DATA is not set
-# CONFIG_CGROUP_NET_PRIO is not set
-# CONFIG_CGROUP_NET_CLASSID is not set
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-# CONFIG_BPF_JIT is not set
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-# CONFIG_NFC is not set
-# CONFIG_LWTUNNEL is not set
-CONFIG_HAVE_BPF_JIT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_GENERIC_CPU_DEVICES is not set
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_FENCE_TRACE is not set
-CONFIG_DMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=16
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-
-#
-# Bus devices
-#
-# CONFIG_ARM_CCI400_PMU is not set
-# CONFIG_ARM_CCI500_PMU is not set
-# CONFIG_ARM_CCN is not set
-# CONFIG_BRCMSTB_GISB_ARB is not set
-CONFIG_IMX_WEIM=y
-# CONFIG_VEXPRESS_CONFIG is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-# CONFIG_MTD_SWAP is not set
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_INTEL_VR_NOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-# CONFIG_MTD_DATAFLASH_OTP is not set
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SST25L=y
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOCG3 is not set
-CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_ECC_BCH is not set
-# CONFIG_MTD_SM_COMMON is not set
-# CONFIG_MTD_NAND_DENALI_PCI is not set
-# CONFIG_MTD_NAND_DENALI_DT is not set
-# CONFIG_MTD_NAND_GPIO is not set
-# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_RICOH is not set
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_DOCG4 is not set
-# CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_GPMI_NAND=y
-# CONFIG_MTD_NAND_BRCMNAND is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_NAND_VF610_NFC is not set
-CONFIG_MTD_NAND_MXC=y
-# CONFIG_MTD_NAND_HISI504 is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_LPDDR2_NVM is not set
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTD_MT81xx_NOR is not set
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_SPI_FSL_QUADSPI=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_DTC=y
-CONFIG_OF=y
-# CONFIG_OF_UNITTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_MTD=y
-CONFIG_OF_RESERVED_MEM=y
-# CONFIG_OF_OVERLAY is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_DRBD is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_VIRTIO_BLK=y
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
-# CONFIG_BLK_DEV_NVME is not set
-
-#
-# Misc devices
-#
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_AD525X_DPOT is not set
-# CONFIG_DUMMY_IRQ is not set
-# CONFIG_PHANTOM is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HP_ILO is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-# CONFIG_BMP085_I2C is not set
-# CONFIG_BMP085_SPI is not set
-# CONFIG_USB_SWITCH_FSA9480 is not set
-# CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_SRAM=y
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_EEPROM_93XX46 is not set
-# CONFIG_CB710_CORE is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-
-#
-# Altera FPGA firmware download module
-#
-# CONFIG_ALTERA_STAPL is not set
-
-#
-# Intel MIC Bus Driver
-#
-
-#
-# SCIF Bus Driver
-#
-
-#
-# Intel MIC Host Driver
-#
-
-#
-# Intel MIC Card Driver
-#
-
-#
-# SCIF Driver
-#
-
-#
-# Intel MIC Coprocessor State Management (COSM) Drivers
-#
-# CONFIG_ECHO is not set
-# CONFIG_CXL_BASE is not set
-# CONFIG_CXL_KERNEL_API is not set
-# CONFIG_CXL_EEH is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_MQ_DEFAULT is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=y
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-# CONFIG_SATA_AHCI is not set
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_AHCI_IMX=y
-# CONFIG_AHCI_CEVA is not set
-# CONFIG_AHCI_QORIQ is not set
-# CONFIG_SATA_INIC162X is not set
-# CONFIG_SATA_ACARD_AHCI is not set
-# CONFIG_SATA_SIL24 is not set
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
-# CONFIG_SATA_SX4 is not set
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_ATA_PIIX is not set
-# CONFIG_SATA_MV is not set
-# CONFIG_SATA_NV is not set
-# CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIS is not set
-# CONFIG_SATA_SVW is not set
-# CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
-# CONFIG_SATA_VITESSE is not set
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_ATP867X is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-CONFIG_PATA_IMX=y
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_NETCELL is not set
-# CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RDC is not set
-# CONFIG_PATA_SCH is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_SIL680 is not set
-# CONFIG_PATA_SIS is not set
-# CONFIG_PATA_TOSHIBA is not set
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_RZ1000 is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_LEGACY is not set
-# CONFIG_MD is not set
-# CONFIG_TARGET_CORE is not set
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_FIREWIRE_NOSY is not set
-# CONFIG_NETDEVICES is not set
-# CONFIG_VHOST_NET is not set
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-# CONFIG_NVM is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-CONFIG_INPUT_MATRIXKMAP=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=m
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_TCA8418 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_LM8333 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-CONFIG_KEYBOARD_SNVS_PWRKEY=y
-CONFIG_KEYBOARD_IMX=y
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_SAMSUNG is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_STMPE is not set
-# CONFIG_KEYBOARD_OMAP4 is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_CAP11XX is not set
-# CONFIG_KEYBOARD_BCM is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-# CONFIG_MOUSE_PS2_SENTELIC is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_FOCALTECH=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-# CONFIG_MOUSE_ELAN_I2C is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_GPIO is not set
-# CONFIG_MOUSE_SYNAPTICS_I2C is not set
-# CONFIG_MOUSE_SYNAPTICS_USB is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
-# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
-# CONFIG_TOUCHSCREEN_DA9052 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-CONFIG_TOUCHSCREEN_EGALAX=y
-# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
-# CONFIG_TOUCHSCREEN_FT6236 is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GOODIX is not set
-# CONFIG_TOUCHSCREEN_ILI210X is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELAN is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MMS114 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-CONFIG_TOUCHSCREEN_MC13783=y
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TS4800 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-# CONFIG_TOUCHSCREEN_TSC2004 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-CONFIG_TOUCHSCREEN_TSC2007=y
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-CONFIG_TOUCHSCREEN_STMPE=y
-# CONFIG_TOUCHSCREEN_SUR40 is not set
-CONFIG_TOUCHSCREEN_SX8654=y
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_TOUCHSCREEN_ZFORCE is not set
-# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
-# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_AD714X is not set
-# CONFIG_INPUT_BMA150 is not set
-# CONFIG_INPUT_E3X0_BUTTON is not set
-# CONFIG_INPUT_MC13783_PWRBUTTON is not set
-CONFIG_INPUT_MMA8450=y
-# CONFIG_INPUT_MPU3050 is not set
-# CONFIG_INPUT_GP2A is not set
-# CONFIG_INPUT_GPIO_BEEPER is not set
-# CONFIG_INPUT_GPIO_TILT_POLLED is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_KXTJ9 is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-# CONFIG_INPUT_UINPUT is not set
-# CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_PWM_BEEPER is not set
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-# CONFIG_INPUT_DA9052_ONKEY is not set
-# CONFIG_INPUT_ADXL34X is not set
-# CONFIG_INPUT_IMS_PCU is not set
-# CONFIG_INPUT_CMA3000 is not set
-# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
-# CONFIG_INPUT_DRV260X_HAPTICS is not set
-# CONFIG_INPUT_DRV2665_HAPTICS is not set
-# CONFIG_INPUT_DRV2667_HAPTICS is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=m
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_SERIO_PS2MULT is not set
-# CONFIG_SERIO_ARC_PS2 is not set
-# CONFIG_SERIO_APBPS2 is not set
-# CONFIG_USERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_NOZOMI is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-# CONFIG_SERIAL_8250 is not set
-# CONFIG_SERIAL_8250_INGENIC is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX310X is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_SERIAL_UARTLITE is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-# CONFIG_SERIAL_SCCNXP is not set
-# CONFIG_SERIAL_SC16IS7XX is not set
-# CONFIG_SERIAL_BCM63XX is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_SERIAL_ARC is not set
-# CONFIG_SERIAL_RP2 is not set
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
-# CONFIG_SERIAL_ST_ASC is not set
-# CONFIG_SERIAL_STM32 is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_TTY_PRINTK is not set
-CONFIG_HVC_DRIVER=y
-# CONFIG_HVC_DCC is not set
-CONFIG_VIRTIO_CONSOLE=y
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_MXC_RNGA=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_XILLYBUS is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-# CONFIG_I2C_MUX_PINCTRL is not set
-# CONFIG_I2C_MUX_REG is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-# CONFIG_I2C_SMBUS is not set
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_CBUS_GPIO is not set
-# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
-# CONFIG_I2C_DESIGNWARE_PCI is not set
-# CONFIG_I2C_EMEV2 is not set
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_RK3X is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_SLAVE is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_CADENCE is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_FSL_SPI is not set
-# CONFIG_SPI_FSL_DSPI is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PXA2XX is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_ROCKCHIP is not set
-# CONFIG_SPI_SC18IS602 is not set
-# CONFIG_SPI_XCOMM is not set
-# CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_ZYNQMP_GQSPI is not set
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_LOOPBACK_TEST is not set
-# CONFIG_SPI_TLE62X0 is not set
-# CONFIG_SPMI is not set
-# CONFIG_HSI is not set
-
-#
-# PPS support
-#
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-# CONFIG_PPS_CLIENT_LDISC is not set
-# CONFIG_PPS_CLIENT_GPIO is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-# CONFIG_PTP_1588_CLOCK is not set
-
-#
-# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
-#
-CONFIG_PINCTRL=y
-
-#
-# Pin controllers
-#
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-# CONFIG_PINCTRL_AMD is not set
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX35=y
-CONFIG_PINCTRL_IMX50=y
-CONFIG_PINCTRL_IMX51=y
-CONFIG_PINCTRL_IMX53=y
-CONFIG_PINCTRL_IMX6Q=y
-CONFIG_PINCTRL_IMX6SL=y
-CONFIG_PINCTRL_IMX6SX=y
-CONFIG_PINCTRL_IMX6UL=y
-CONFIG_PINCTRL_IMX7D=y
-CONFIG_PINCTRL_VF610=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_OF_GPIO=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC=y
-
-#
-# Memory mapped GPIO drivers
-#
-# CONFIG_GPIO_74XX_MMIO is not set
-# CONFIG_GPIO_ALTERA is not set
-# CONFIG_GPIO_DWAPB is not set
-# CONFIG_GPIO_EM is not set
-# CONFIG_GPIO_GENERIC_PLATFORM is not set
-# CONFIG_GPIO_GRGPIO is not set
-CONFIG_GPIO_MXC=y
-# CONFIG_GPIO_SYSCON is not set
-CONFIG_GPIO_VF610=y
-# CONFIG_GPIO_VX855 is not set
-# CONFIG_GPIO_XILINX is not set
-# CONFIG_GPIO_ZEVIO is not set
-# CONFIG_GPIO_ZX is not set
-
-#
-# I2C GPIO expanders
-#
-# CONFIG_GPIO_ADP5588 is not set
-# CONFIG_GPIO_ADNP is not set
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-CONFIG_GPIO_MC9S08DZ60=y
-CONFIG_GPIO_PCA953X=y
-# CONFIG_GPIO_PCA953X_IRQ is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-
-#
-# MFD GPIO expanders
-#
-# CONFIG_GPIO_DA9052 is not set
-CONFIG_GPIO_STMPE=y
-
-#
-# PCI GPIO expanders
-#
-# CONFIG_GPIO_AMD8111 is not set
-# CONFIG_GPIO_BT8XX is not set
-# CONFIG_GPIO_ML_IOH is not set
-# CONFIG_GPIO_RDC321X is not set
-
-#
-# SPI GPIO expanders
-#
-# CONFIG_GPIO_74X164 is not set
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# SPI or I2C GPIO expanders
-#
-# CONFIG_GPIO_MCP23S08 is not set
-
-#
-# USB GPIO expanders
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_GENERIC_ADC_BATTERY is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2781 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_SBS is not set
-# CONFIG_BATTERY_BQ27XXX is not set
-# CONFIG_BATTERY_DA9052 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_CHARGER_ISP1704 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_LP8727 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_CHARGER_BQ2415X is not set
-# CONFIG_CHARGER_BQ24190 is not set
-# CONFIG_CHARGER_BQ24257 is not set
-# CONFIG_CHARGER_BQ24735 is not set
-# CONFIG_CHARGER_BQ25890 is not set
-# CONFIG_CHARGER_SMB347 is not set
-# CONFIG_BATTERY_GAUGE_LTC2941 is not set
-# CONFIG_CHARGER_RT9455 is not set
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_BRCMSTB is not set
-# CONFIG_POWER_RESET_GPIO is not set
-# CONFIG_POWER_RESET_GPIO_RESTART is not set
-CONFIG_POWER_RESET_IMX=y
-# CONFIG_POWER_RESET_LTC2952 is not set
-# CONFIG_POWER_RESET_RESTART is not set
-# CONFIG_POWER_RESET_VERSATILE is not set
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-# CONFIG_POWER_AVS is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7314 is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7310 is not set
-# CONFIG_SENSORS_ADT7410 is not set
-# CONFIG_SENSORS_ADT7411 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ASC7621 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS620 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_DA9052_ADC is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_MC13783_ADC is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_G762 is not set
-CONFIG_SENSORS_GPIO_FAN=y
-# CONFIG_SENSORS_HIH6130 is not set
-# CONFIG_SENSORS_IIO_HWMON is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_JC42 is not set
-# CONFIG_SENSORS_POWR1220 is not set
-# CONFIG_SENSORS_LINEAGE is not set
-# CONFIG_SENSORS_LTC2945 is not set
-# CONFIG_SENSORS_LTC4151 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4222 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LTC4260 is not set
-# CONFIG_SENSORS_LTC4261 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX16065 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX1668 is not set
-# CONFIG_SENSORS_MAX197 is not set
-# CONFIG_SENSORS_MAX6639 is not set
-# CONFIG_SENSORS_MAX6642 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_MAX6697 is not set
-# CONFIG_SENSORS_MAX31790 is not set
-# CONFIG_SENSORS_MCP3021 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM73 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LM95234 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_LM95245 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_NTC_THERMISTOR is not set
-# CONFIG_SENSORS_NCT6683 is not set
-# CONFIG_SENSORS_NCT6775 is not set
-# CONFIG_SENSORS_NCT7802 is not set
-# CONFIG_SENSORS_NCT7904 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_PMBUS is not set
-# CONFIG_SENSORS_PWM_FAN is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_SHT21 is not set
-# CONFIG_SENSORS_SHTC1 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_EMC1403 is not set
-# CONFIG_SENSORS_EMC2103 is not set
-# CONFIG_SENSORS_EMC6W201 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SCH56XX_COMMON is not set
-# CONFIG_SENSORS_SCH5627 is not set
-# CONFIG_SENSORS_SCH5636 is not set
-# CONFIG_SENSORS_SMM665 is not set
-# CONFIG_SENSORS_ADC128D818 is not set
-# CONFIG_SENSORS_ADS1015 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_ADS7871 is not set
-# CONFIG_SENSORS_AMC6821 is not set
-# CONFIG_SENSORS_INA209 is not set
-# CONFIG_SENSORS_INA2XX is not set
-# CONFIG_SENSORS_TC74 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP102 is not set
-# CONFIG_SENSORS_TMP103 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83795 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THERMAL_WRITABLE_TRIPS is not set
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_BANG_BANG is not set
-# CONFIG_THERMAL_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
-CONFIG_CPU_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_IMX_THERMAL=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-# CONFIG_WATCHDOG_SYSFS is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_DA9052_WATCHDOG is not set
-# CONFIG_GPIO_WATCHDOG is not set
-# CONFIG_XILINX_WATCHDOG is not set
-# CONFIG_ZIIRAVE_WATCHDOG is not set
-# CONFIG_CADENCE_WATCHDOG is not set
-# CONFIG_DW_WATCHDOG is not set
-# CONFIG_TS4800_WATCHDOG is not set
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_IMX2_WDT=y
-# CONFIG_ALIM7101_WDT is not set
-# CONFIG_I6300ESB_WDT is not set
-# CONFIG_BCM7038_WDT is not set
-# CONFIG_MEN_A21_WDT is not set
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_ATMEL_FLEXCOM is not set
-# CONFIG_MFD_ATMEL_HLCDC is not set
-# CONFIG_MFD_BCM590XX is not set
-# CONFIG_MFD_AXP20X is not set
-# CONFIG_MFD_CROS_EC is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_PMIC_DA903X is not set
-CONFIG_PMIC_DA9052=y
-# CONFIG_MFD_DA9052_SPI is not set
-CONFIG_MFD_DA9052_I2C=y
-# CONFIG_MFD_DA9055 is not set
-# CONFIG_MFD_DA9062 is not set
-# CONFIG_MFD_DA9063 is not set
-# CONFIG_MFD_DA9150 is not set
-# CONFIG_MFD_DLN2 is not set
-CONFIG_MFD_MC13XXX=y
-CONFIG_MFD_MC13XXX_SPI=y
-CONFIG_MFD_MC13XXX_I2C=y
-# CONFIG_MFD_HI6421_PMIC is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_LPC_ICH is not set
-# CONFIG_LPC_SCH is not set
-# CONFIG_INTEL_SOC_PMIC is not set
-# CONFIG_MFD_JANZ_CMODIO is not set
-# CONFIG_MFD_KEMPLD is not set
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX14577 is not set
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-# CONFIG_MFD_MAX77843 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_MFD_MT6397 is not set
-# CONFIG_MFD_MENF21BMC is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_VIPERBOARD is not set
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_PM8921_CORE is not set
-# CONFIG_MFD_RDC321X is not set
-# CONFIG_MFD_RTSX_PCI is not set
-# CONFIG_MFD_RT5033 is not set
-# CONFIG_MFD_RTSX_USB is not set
-# CONFIG_MFD_RC5T583 is not set
-# CONFIG_MFD_RK808 is not set
-# CONFIG_MFD_RN5T618 is not set
-# CONFIG_MFD_SEC_CORE is not set
-# CONFIG_MFD_SI476X_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_SKY81452 is not set
-# CONFIG_MFD_SMSC is not set
-# CONFIG_ABX500_CORE is not set
-CONFIG_MFD_STMPE=y
-
-#
-# STMicroelectronics STMPE Interface Drivers
-#
-CONFIG_STMPE_I2C=y
-# CONFIG_STMPE_SPI is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_TI_AM335X_TSCADC is not set
-# CONFIG_MFD_LP3943 is not set
-# CONFIG_MFD_LP8788 is not set
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-# CONFIG_MFD_TPS65218 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_TPS65912 is not set
-# CONFIG_MFD_TPS65912_I2C is not set
-# CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_MFD_TPS80031 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_LM3533 is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_VX855 is not set
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_ARIZONA_SPI is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
-# CONFIG_REGULATOR is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
-# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
-# CONFIG_MEDIA_RADIO_SUPPORT is not set
-# CONFIG_MEDIA_SDR_SUPPORT is not set
-CONFIG_MEDIA_RC_SUPPORT=y
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_V4L2_MEM2MEM_DEV=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF2_CORE=y
-CONFIG_VIDEOBUF2_MEMOPS=y
-CONFIG_VIDEOBUF2_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_VMALLOC=y
-# CONFIG_TTPCI_EEPROM is not set
-
-#
-# Media drivers
-#
-CONFIG_RC_CORE=y
-CONFIG_RC_MAP=y
-CONFIG_RC_DECODERS=y
-# CONFIG_LIRC is not set
-CONFIG_IR_NEC_DECODER=y
-CONFIG_IR_RC5_DECODER=y
-CONFIG_IR_RC6_DECODER=y
-CONFIG_IR_JVC_DECODER=y
-CONFIG_IR_SONY_DECODER=y
-CONFIG_IR_SANYO_DECODER=y
-CONFIG_IR_SHARP_DECODER=y
-CONFIG_IR_MCE_KBD_DECODER=y
-CONFIG_IR_XMP_DECODER=y
-CONFIG_RC_DEVICES=y
-# CONFIG_RC_ATI_REMOTE is not set
-# CONFIG_IR_HIX5HD2 is not set
-# CONFIG_IR_IMON is not set
-# CONFIG_IR_MCEUSB is not set
-# CONFIG_IR_REDRAT3 is not set
-# CONFIG_IR_STREAMZAP is not set
-# CONFIG_IR_IGORPLUGUSB is not set
-# CONFIG_IR_IGUANA is not set
-# CONFIG_IR_TTUSBIR is not set
-# CONFIG_RC_LOOPBACK is not set
-CONFIG_IR_GPIO_CIR=y
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
-# CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_BENQ is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_CPIA1 is not set
-# CONFIG_USB_GSPCA_DTCS033 is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_JL2005BCD is not set
-# CONFIG_USB_GSPCA_KINECT is not set
-# CONFIG_USB_GSPCA_KONICA is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_NW80X is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_OV534_9 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7302 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SE401 is not set
-# CONFIG_USB_GSPCA_SN9C2028 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SPCA1528 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_SQ930X is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_STK1135 is not set
-# CONFIG_USB_GSPCA_STV0680 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TOPRO is not set
-# CONFIG_USB_GSPCA_TOUPTEK is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_VICAM is not set
-# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_MEDIA_PCI_SUPPORT is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_CAFE_CCIC is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-CONFIG_VIDEO_MX3=y
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_CODA=y
-# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
-# CONFIG_VIDEO_SH_VEU is not set
-# CONFIG_V4L_TEST_DRIVERS is not set
-
-#
-# Supported MMC/SDIO adapters
-#
-# CONFIG_CYPRESS_FIRMWARE is not set
-
-#
-# Media ancillary drivers (tuners, sensors, i2c, frontends)
-#
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-CONFIG_VIDEO_IR_I2C=y
-
-#
-# Audio decoders, processors and mixers
-#
-
-#
-# RDS decoders
-#
-
-#
-# Video decoders
-#
-
-#
-# Video and audio decoders
-#
-
-#
-# Video encoders
-#
-
-#
-# Camera sensor devices
-#
-
-#
-# Flash devices
-#
-
-#
-# Video improvement chips
-#
-
-#
-# Audio/Video compression chips
-#
-
-#
-# Miscellaneous helper chips
-#
-
-#
-# Sensors used on soc_camera driver
-#
-
-#
-# soc_camera sensor drivers
-#
-# CONFIG_SOC_CAMERA_IMX074 is not set
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-CONFIG_SOC_CAMERA_OV2640=y
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-
-#
-# Tools to develop new frontends
-#
-# CONFIG_DVB_DUMMY_FE is not set
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_IMX_IPUV3_CORE=y
-CONFIG_DRM=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_KMS_FB_HELPER=y
-CONFIG_DRM_FBDEV_EMULATION=y
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-CONFIG_DRM_TTM=y
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-
-#
-# I2C encoder or helper chips
-#
-# CONFIG_DRM_I2C_ADV7511 is not set
-# CONFIG_DRM_I2C_CH7006 is not set
-# CONFIG_DRM_I2C_SIL164 is not set
-# CONFIG_DRM_I2C_NXP_TDA998X is not set
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-# CONFIG_DRM_RADEON is not set
-# CONFIG_DRM_AMDGPU is not set
-# CONFIG_DRM_NOUVEAU is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_DRM_VGEM is not set
-# CONFIG_DRM_EXYNOS is not set
-# CONFIG_DRM_UDL is not set
-# CONFIG_DRM_AST is not set
-# CONFIG_DRM_MGAG200 is not set
-# CONFIG_DRM_CIRRUS_QEMU is not set
-# CONFIG_DRM_ARMADA is not set
-# CONFIG_DRM_OMAP is not set
-# CONFIG_DRM_TILCDC is not set
-# CONFIG_DRM_QXL is not set
-# CONFIG_DRM_BOCHS is not set
-CONFIG_DRM_VIRTIO_GPU=y
-# CONFIG_DRM_FSL_DCU is not set
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_SIMPLE=y
-# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
-# CONFIG_DRM_PANEL_LG_LG4573 is not set
-# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
-CONFIG_DRM_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_DW_HDMI=y
-# CONFIG_DRM_NXP_PTN3460 is not set
-# CONFIG_DRM_PARADE_PS8622 is not set
-# CONFIG_DRM_STI is not set
-CONFIG_DRM_IMX=y
-CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
-CONFIG_DRM_IMX_TVE=y
-CONFIG_DRM_IMX_LDB=y
-CONFIG_DRM_IMX_IPUV3=y
-CONFIG_DRM_IMX_HDMI=y
-CONFIG_DRM_ETNAVIV=y
-CONFIG_DRM_ETNAVIV_REGISTER_LOGGING=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_IMX is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_IBM_GXT4500 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_FB_MX3=y
-# CONFIG_FB_BROADSHEET is not set
-# CONFIG_FB_AUO_K190X is not set
-CONFIG_FB_MXS=y
-# CONFIG_FB_SIMPLE is not set
-# CONFIG_FB_SSD1307 is not set
-# CONFIG_FB_SM712 is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_L4F00242T03=y
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI922X is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-CONFIG_LCD_PLATFORM=y
-# CONFIG_LCD_S6E63M0 is not set
-# CONFIG_LCD_LD9040 is not set
-# CONFIG_LCD_AMS369FG06 is not set
-# CONFIG_LCD_LMS501KF03 is not set
-# CONFIG_LCD_HX8357 is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_BACKLIGHT_DA9052 is not set
-# CONFIG_BACKLIGHT_PM8941_WLED is not set
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-# CONFIG_BACKLIGHT_LM3630A is not set
-# CONFIG_BACKLIGHT_LM3639 is not set
-# CONFIG_BACKLIGHT_LP855X is not set
-CONFIG_BACKLIGHT_GPIO=y
-# CONFIG_BACKLIGHT_LV5207LP is not set
-# CONFIG_BACKLIGHT_BD6107 is not set
-# CONFIG_VGASTATE is not set
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
-
-#
-# HID support
-#
-CONFIG_HID=y
-# CONFIG_HID_BATTERY_STRENGTH is not set
-# CONFIG_HIDRAW is not set
-# CONFIG_UHID is not set
-CONFIG_HID_GENERIC=y
-
-#
-# Special HID drivers
-#
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_ACRUX is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_APPLEIR is not set
-# CONFIG_HID_AUREAL is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_BETOP_FF is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_CORSAIR is not set
-# CONFIG_HID_CP2112 is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EMS_FF is not set
-# CONFIG_HID_ELECOM is not set
-# CONFIG_HID_ELO is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_GEMBIRD is not set
-# CONFIG_HID_GFRM is not set
-# CONFIG_HID_HOLTEK is not set
-# CONFIG_HID_GT683R is not set
-# CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_UCLOGIC is not set
-# CONFIG_HID_WALTOP is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_ICADE is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LCPOWER is not set
-# CONFIG_HID_LENOVO is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MAGICMOUSE is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_MULTITOUCH is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PENMOUNT is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_PICOLCD is not set
-# CONFIG_HID_PLANTRONICS is not set
-# CONFIG_HID_PRIMAX is not set
-# CONFIG_HID_ROCCAT is not set
-# CONFIG_HID_SAITEK is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SPEEDLINK is not set
-# CONFIG_HID_STEELSERIES is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_RMI is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TIVO is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THINGM is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_XINMO is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-# CONFIG_HID_SENSOR_HUB is not set
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# I2C HID support
-#
-# CONFIG_I2C_HID is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=y
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_ULPI_BUS is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_XHCI_HCD is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_EHCI_MXC=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_FOTG210_HCD is not set
-# CONFIG_USB_MAX3421_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_IMX21_HCD is not set
-# CONFIG_USB_HCD_TEST_MODE is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-# CONFIG_USB_UAS is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USBIP_CORE is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_DWC3 is not set
-# CONFIG_USB_DWC2 is not set
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_OF=y
-CONFIG_USB_CHIPIDEA_PCI=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-# CONFIG_USB_ISP1760 is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_SIMPLE is not set
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-CONFIG_USB_SERIAL_FTDI_SIO=m
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_F81232 is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_METRO is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MXUPORT is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QCAUX is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_XSENS_MT is not set
-# CONFIG_USB_SERIAL_WISHBONE is not set
-# CONFIG_USB_SERIAL_SSU100 is not set
-# CONFIG_USB_SERIAL_QT2 is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-# CONFIG_USB_EZUSB_FX2 is not set
-# CONFIG_USB_HSIC_USB3503 is not set
-# CONFIG_USB_LINK_LAYER_TEST is not set
-# CONFIG_USB_CHAOSKEY is not set
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=y
-# CONFIG_AM335X_PHY_USB is not set
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ISP1301 is not set
-CONFIG_USB_MXS_PHY=y
-# CONFIG_USB_ULPI is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-# CONFIG_U_SERIAL_CONSOLE is not set
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FSL_USB2 is not set
-# CONFIG_USB_FUSB300 is not set
-# CONFIG_USB_FOTG210_UDC is not set
-# CONFIG_USB_GR_UDC is not set
-# CONFIG_USB_R8A66597 is not set
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-# CONFIG_USB_M66592 is not set
-# CONFIG_USB_BDC_UDC is not set
-# CONFIG_USB_AMD5536UDC is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_EG20T is not set
-# CONFIG_USB_GADGET_XILINX is not set
-# CONFIG_USB_DUMMY_HCD is not set
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-# CONFIG_USB_CONFIGFS_NCM is not set
-# CONFIG_USB_CONFIGFS_ECM is not set
-# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
-# CONFIG_USB_CONFIGFS_RNDIS is not set
-# CONFIG_USB_CONFIGFS_EEM is not set
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-# CONFIG_USB_CONFIGFS_F_HID is not set
-# CONFIG_USB_CONFIGFS_F_UVC is not set
-# CONFIG_USB_CONFIGFS_F_PRINTER is not set
-CONFIG_USB_ZERO=m
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_G_NCM is not set
-CONFIG_USB_GADGETFS=m
-# CONFIG_USB_FUNCTIONFS is not set
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_ACM_MS is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-# CONFIG_USB_LED_TRIG is not set
-# CONFIG_UWB is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_SDHCI_OF_ARASAN is not set
-# CONFIG_MMC_SDHCI_OF_AT91 is not set
-# CONFIG_MMC_SDHCI_OF_ESDHC is not set
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-# CONFIG_MMC_SDHCI_F_SDH30 is not set
-# CONFIG_MMC_MXC is not set
-# CONFIG_MMC_TIFM_SD is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MMC_CB710 is not set
-# CONFIG_MMC_VIA_SDMMC is not set
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MMC_USDHI6ROL0 is not set
-# CONFIG_MMC_TOSHIBA_PCI is not set
-# CONFIG_MMC_MTK is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-# CONFIG_LEDS_CLASS_FLASH is not set
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_BCM6328 is not set
-# CONFIG_LEDS_BCM6358 is not set
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_LM3642 is not set
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_LP5562 is not set
-# CONFIG_LEDS_LP8501 is not set
-# CONFIG_LEDS_LP8860 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_PCA963X is not set
-# CONFIG_LEDS_DA9052 is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_PWM is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_MC13783 is not set
-# CONFIG_LEDS_TCA6507 is not set
-# CONFIG_LEDS_TLC591XX is not set
-# CONFIG_LEDS_LM355x is not set
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-# CONFIG_LEDS_BLINKM is not set
-# CONFIG_LEDS_SYSCON is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-# CONFIG_LEDS_TRIGGER_CPU is not set
-CONFIG_LEDS_TRIGGER_GPIO=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
-# CONFIG_LEDS_TRIGGER_CAMERA is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_INFINIBAND is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EDAC is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_ABB5ZES3 is not set
-# CONFIG_RTC_DRV_ABX80X is not set
-CONFIG_RTC_DRV_DS1307=y
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_HYM8563 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_ISL1208=y
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_ISL12057 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF2127 is not set
-CONFIG_RTC_DRV_PCF8523=y
-CONFIG_RTC_DRV_PCF8563=y
-# CONFIG_RTC_DRV_PCF85063 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8010 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-# CONFIG_RTC_DRV_RV8803 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1343 is not set
-# CONFIG_RTC_DRV_DS1347 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-# CONFIG_RTC_DRV_RX4581 is not set
-# CONFIG_RTC_DRV_MCP795 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1685_FAMILY is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_DS2404 is not set
-# CONFIG_RTC_DRV_DA9052 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-# CONFIG_RTC_DRV_ZYNQMP is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_IMXDI is not set
-CONFIG_RTC_DRV_MC13XXX=y
-CONFIG_RTC_DRV_MXC=y
-CONFIG_RTC_DRV_SNVS=y
-
-#
-# HID Sensor RTC drivers
-#
-# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_OF=y
-CONFIG_FSL_EDMA=y
-# CONFIG_IMX_DMA is not set
-CONFIG_IMX_SDMA=y
-# CONFIG_INTEL_IDMA64 is not set
-CONFIG_MXS_DMA=y
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-# CONFIG_NBPFAXI_DMA is not set
-# CONFIG_DW_DMAC is not set
-# CONFIG_DW_DMAC_PCI is not set
-
-#
-# DMA Clients
-#
-# CONFIG_ASYNC_TX_DMA is not set
-# CONFIG_DMATEST is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-# CONFIG_VFIO is not set
-# CONFIG_VIRT_DRIVERS is not set
-CONFIG_VIRTIO=y
-
-#
-# Virtio drivers
-#
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_BALLOON is not set
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_STAGING=y
-# CONFIG_COMEDI is not set
-# CONFIG_RTS5208 is not set
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-# CONFIG_ADIS16201 is not set
-# CONFIG_ADIS16203 is not set
-# CONFIG_ADIS16204 is not set
-# CONFIG_ADIS16209 is not set
-# CONFIG_ADIS16220 is not set
-# CONFIG_ADIS16240 is not set
-# CONFIG_LIS3L02DQ is not set
-# CONFIG_SCA3000 is not set
-
-#
-# Analog to digital converters
-#
-# CONFIG_AD7606 is not set
-# CONFIG_AD7780 is not set
-# CONFIG_AD7816 is not set
-# CONFIG_AD7192 is not set
-# CONFIG_AD7280 is not set
-
-#
-# Analog digital bi-direction converters
-#
-# CONFIG_ADT7316 is not set
-
-#
-# Capacitance to digital converters
-#
-# CONFIG_AD7150 is not set
-# CONFIG_AD7152 is not set
-# CONFIG_AD7746 is not set
-
-#
-# Direct Digital Synthesis
-#
-# CONFIG_AD9832 is not set
-# CONFIG_AD9834 is not set
-
-#
-# Digital gyroscope sensors
-#
-# CONFIG_ADIS16060 is not set
-
-#
-# Network Analyzer, Impedance Converters
-#
-# CONFIG_AD5933 is not set
-
-#
-# Light sensors
-#
-# CONFIG_SENSORS_ISL29018 is not set
-# CONFIG_SENSORS_ISL29028 is not set
-# CONFIG_TSL2583 is not set
-# CONFIG_TSL2x7x is not set
-
-#
-# Magnetometer sensors
-#
-# CONFIG_SENSORS_HMC5843_I2C is not set
-# CONFIG_SENSORS_HMC5843_SPI is not set
-
-#
-# Active energy metering IC
-#
-# CONFIG_ADE7753 is not set
-# CONFIG_ADE7754 is not set
-# CONFIG_ADE7758 is not set
-# CONFIG_ADE7759 is not set
-# CONFIG_ADE7854 is not set
-
-#
-# Resolver to digital converters
-#
-# CONFIG_AD2S90 is not set
-# CONFIG_AD2S1200 is not set
-# CONFIG_AD2S1210 is not set
-
-#
-# Triggers - standalone
-#
-# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
-# CONFIG_FB_SM750 is not set
-# CONFIG_FB_XGI is not set
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-# CONFIG_STAGING_MEDIA is not set
-
-#
-# Android
-#
-# CONFIG_STAGING_BOARD is not set
-# CONFIG_WIMAX_GDM72XX is not set
-# CONFIG_LTE_GDM724X is not set
-# CONFIG_MTD_SPINAND_MT29F is not set
-# CONFIG_LUSTRE_FS is not set
-# CONFIG_DGNC is not set
-# CONFIG_DGAP is not set
-# CONFIG_GS_FPGABOOT is not set
-# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
-# CONFIG_FB_TFT is not set
-# CONFIG_MOST is not set
-# CONFIG_CHROME_PLATFORMS is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-
-#
-# Common Clock Framework
-#
-# CONFIG_COMMON_CLK_SI5351 is not set
-# CONFIG_COMMON_CLK_SI514 is not set
-# CONFIG_COMMON_CLK_SI570 is not set
-# CONFIG_COMMON_CLK_CDCE925 is not set
-# CONFIG_COMMON_CLK_CS2000_CP is not set
-# CONFIG_CLK_QORIQ is not set
-# CONFIG_COMMON_CLK_NXP is not set
-# CONFIG_COMMON_CLK_PWM is not set
-# CONFIG_COMMON_CLK_PXA is not set
-# CONFIG_COMMON_CLK_CDCE706 is not set
-
-#
-# Hardware Spinlock drivers
-#
-
-#
-# Clock Source drivers
-#
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_PROBE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_ARM_GLOBAL_TIMER=y
-# CONFIG_ARM_TIMER_SP804 is not set
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-# CONFIG_ATMEL_PIT is not set
-# CONFIG_SH_TIMER_CMT is not set
-# CONFIG_SH_TIMER_MTU2 is not set
-# CONFIG_SH_TIMER_TMU is not set
-# CONFIG_EM_TIMER_STI is not set
-CONFIG_CLKSRC_IMX_GPT=y
-# CONFIG_MAILBOX is not set
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_OF_IOMMU=y
-# CONFIG_ARM_SMMU is not set
-
-#
-# Remoteproc drivers
-#
-# CONFIG_STE_MODEM_RPROC is not set
-
-#
-# Rpmsg drivers
-#
-
-#
-# SOC (System On Chip) specific Drivers
-#
-# CONFIG_SOC_BRCMSTB is not set
-# CONFIG_SUNXI_SRAM is not set
-# CONFIG_SOC_TI is not set
-# CONFIG_PM_DEVFREQ is not set
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-# CONFIG_EXTCON_ADC_JACK is not set
-# CONFIG_EXTCON_GPIO is not set
-# CONFIG_EXTCON_MAX3355 is not set
-# CONFIG_EXTCON_RT8973A is not set
-# CONFIG_EXTCON_SM5502 is not set
-# CONFIG_EXTCON_USB_GPIO is not set
-# CONFIG_MEMORY is not set
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-# CONFIG_IIO_BUFFER_CB is not set
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-# CONFIG_IIO_CONFIGFS is not set
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-# CONFIG_IIO_SW_TRIGGER is not set
-
-#
-# Accelerometers
-#
-# CONFIG_BMA180 is not set
-# CONFIG_BMC150_ACCEL is not set
-# CONFIG_IIO_ST_ACCEL_3AXIS is not set
-# CONFIG_KXSD9 is not set
-# CONFIG_KXCJK1013 is not set
-# CONFIG_MMA7455_I2C is not set
-# CONFIG_MMA7455_SPI is not set
-# CONFIG_MMA8452 is not set
-# CONFIG_MMA9551 is not set
-# CONFIG_MMA9553 is not set
-# CONFIG_MXC4005 is not set
-# CONFIG_MXC6255 is not set
-# CONFIG_STK8312 is not set
-# CONFIG_STK8BA50 is not set
-
-#
-# Analog to digital converters
-#
-# CONFIG_AD7266 is not set
-# CONFIG_AD7291 is not set
-# CONFIG_AD7298 is not set
-# CONFIG_AD7476 is not set
-# CONFIG_AD7791 is not set
-# CONFIG_AD7793 is not set
-# CONFIG_AD7887 is not set
-# CONFIG_AD7923 is not set
-# CONFIG_AD799X is not set
-# CONFIG_HI8435 is not set
-# CONFIG_INA2XX_ADC is not set
-# CONFIG_IMX7D_ADC is not set
-# CONFIG_MAX1027 is not set
-# CONFIG_MAX1363 is not set
-# CONFIG_MCP320X is not set
-# CONFIG_MCP3422 is not set
-# CONFIG_NAU7802 is not set
-# CONFIG_TI_ADC081C is not set
-# CONFIG_TI_ADC128S052 is not set
-# CONFIG_TI_ADS8688 is not set
-CONFIG_VF610_ADC=y
-
-#
-# Amplifiers
-#
-# CONFIG_AD8366 is not set
-
-#
-# Chemical Sensors
-#
-# CONFIG_IAQCORE is not set
-# CONFIG_VZ89X is not set
-
-#
-# Hid Sensor IIO Common
-#
-
-#
-# SSP Sensor Common
-#
-# CONFIG_IIO_SSP_SENSORHUB is not set
-
-#
-# Digital to analog converters
-#
-# CONFIG_AD5064 is not set
-# CONFIG_AD5360 is not set
-# CONFIG_AD5380 is not set
-# CONFIG_AD5421 is not set
-# CONFIG_AD5446 is not set
-# CONFIG_AD5449 is not set
-# CONFIG_AD5504 is not set
-# CONFIG_AD5624R_SPI is not set
-# CONFIG_AD5686 is not set
-# CONFIG_AD5755 is not set
-# CONFIG_AD5764 is not set
-# CONFIG_AD5791 is not set
-# CONFIG_AD7303 is not set
-# CONFIG_M62332 is not set
-# CONFIG_MAX517 is not set
-# CONFIG_MAX5821 is not set
-# CONFIG_MCP4725 is not set
-# CONFIG_MCP4922 is not set
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-# CONFIG_AD9523 is not set
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-# CONFIG_ADF4350 is not set
-
-#
-# Digital gyroscope sensors
-#
-# CONFIG_ADIS16080 is not set
-# CONFIG_ADIS16130 is not set
-# CONFIG_ADIS16136 is not set
-# CONFIG_ADIS16260 is not set
-# CONFIG_ADXRS450 is not set
-# CONFIG_BMG160 is not set
-# CONFIG_IIO_ST_GYRO_3AXIS is not set
-# CONFIG_ITG3200 is not set
-
-#
-# Health sensors
-#
-# CONFIG_MAX30100 is not set
-
-#
-# Humidity sensors
-#
-# CONFIG_DHT11 is not set
-# CONFIG_HDC100X is not set
-# CONFIG_HTU21 is not set
-# CONFIG_SI7005 is not set
-# CONFIG_SI7020 is not set
-
-#
-# Inertial measurement units
-#
-# CONFIG_ADIS16400 is not set
-# CONFIG_ADIS16480 is not set
-# CONFIG_KMX61 is not set
-# CONFIG_INV_MPU6050_IIO is not set
-
-#
-# Light sensors
-#
-# CONFIG_ADJD_S311 is not set
-# CONFIG_AL3320A is not set
-# CONFIG_APDS9300 is not set
-# CONFIG_APDS9960 is not set
-# CONFIG_BH1750 is not set
-# CONFIG_CM32181 is not set
-# CONFIG_CM3232 is not set
-# CONFIG_CM3323 is not set
-# CONFIG_CM36651 is not set
-# CONFIG_GP2AP020A00F is not set
-# CONFIG_ISL29125 is not set
-# CONFIG_JSA1212 is not set
-# CONFIG_RPR0521 is not set
-# CONFIG_LTR501 is not set
-# CONFIG_OPT3001 is not set
-# CONFIG_PA12203001 is not set
-# CONFIG_STK3310 is not set
-# CONFIG_TCS3414 is not set
-# CONFIG_TCS3472 is not set
-# CONFIG_SENSORS_TSL2563 is not set
-# CONFIG_TSL4531 is not set
-# CONFIG_US5182D is not set
-# CONFIG_VCNL4000 is not set
-
-#
-# Magnetometer sensors
-#
-# CONFIG_AK8975 is not set
-# CONFIG_AK09911 is not set
-# CONFIG_BMC150_MAGN is not set
-# CONFIG_MAG3110 is not set
-# CONFIG_MMC35240 is not set
-# CONFIG_IIO_ST_MAGN_3AXIS is not set
-
-#
-# Inclinometer sensors
-#
-
-#
-# Triggers - standalone
-#
-# CONFIG_IIO_INTERRUPT_TRIGGER is not set
-# CONFIG_IIO_SYSFS_TRIGGER is not set
-
-#
-# Digital potentiometers
-#
-# CONFIG_MCP4531 is not set
-
-#
-# Pressure sensors
-#
-# CONFIG_BMP280 is not set
-# CONFIG_MPL115 is not set
-# CONFIG_MPL3115 is not set
-# CONFIG_MS5611 is not set
-# CONFIG_MS5637 is not set
-# CONFIG_IIO_ST_PRESS is not set
-# CONFIG_T5403 is not set
-
-#
-# Lightning sensors
-#
-# CONFIG_AS3935 is not set
-
-#
-# Proximity sensors
-#
-# CONFIG_LIDAR_LITE_V2 is not set
-# CONFIG_SX9500 is not set
-
-#
-# Temperature sensors
-#
-# CONFIG_MLX90614 is not set
-# CONFIG_TMP006 is not set
-# CONFIG_TSYS01 is not set
-# CONFIG_TSYS02D is not set
-# CONFIG_NTB is not set
-# CONFIG_VME_BUS is not set
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_FSL_FTM is not set
-CONFIG_PWM_IMX=y
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_MAX_NR=1
-# CONFIG_TS4800_IRQ is not set
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_FMC is not set
-
-#
-# PHY Subsystem
-#
-# CONFIG_GENERIC_PHY is not set
-# CONFIG_PHY_PXA_28NM_HSIC is not set
-# CONFIG_PHY_PXA_28NM_USB2 is not set
-# CONFIG_BCM_KONA_USB2_PHY is not set
-# CONFIG_POWERCAP is not set
-# CONFIG_MCB is not set
-
-#
-# Performance monitor support
-#
-CONFIG_ARM_PMU=y
-CONFIG_RAS=y
-# CONFIG_THUNDERBOLT is not set
-
-#
-# Android
-#
-# CONFIG_ANDROID is not set
-# CONFIG_NVMEM is not set
-# CONFIG_STM is not set
-# CONFIG_STM_DUMMY is not set
-# CONFIG_STM_SOURCE_CONSOLE is not set
-# CONFIG_INTEL_TH is not set
-
-#
-# FPGA Configuration Support
-#
-# CONFIG_FPGA is not set
-
-#
-# Firmware Drivers
-#
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_HAVE_ARM_SMCCC=y
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_ENCRYPTION is not set
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-# CONFIG_F2FS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-CONFIG_QUOTA=y
-# CONFIG_QUOTA_NETLINK_INTERFACE is not set
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-# CONFIG_OVERLAY_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PROC_CHILDREN is not set
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_TMPFS_XATTR is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=m
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_UBIFS_ATIME_SUPPORT is not set
-# CONFIG_LOGFS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_QNX6FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-# CONFIG_NFS_FS is not set
-# CONFIG_NFSD is not set
-# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_MAC_ROMAN is not set
-# CONFIG_NLS_MAC_CELTIC is not set
-# CONFIG_NLS_MAC_CENTEURO is not set
-# CONFIG_NLS_MAC_CROATIAN is not set
-# CONFIG_NLS_MAC_CYRILLIC is not set
-# CONFIG_NLS_MAC_GAELIC is not set
-# CONFIG_NLS_MAC_GREEK is not set
-# CONFIG_NLS_MAC_ICELAND is not set
-# CONFIG_NLS_MAC_INUIT is not set
-# CONFIG_NLS_MAC_ROMANIAN is not set
-# CONFIG_NLS_MAC_TURKISH is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_READABLE_ASM is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_PAGE_OWNER is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
-CONFIG_DEBUG_KERNEL=y
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_STATS is not set
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Lockups and Hangs
-#
-# CONFIG_LOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_TIMER_STATS is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_DEBUG_RT_MUTEXES is not set
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_PROVE_LOCKING=y
-CONFIG_LOCKDEP=y
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_LOCKDEP is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-CONFIG_TRACE_IRQFLAGS=y
-CONFIG_STACKTRACE=y
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PI_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_PROVE_RCU=y
-# CONFIG_PROVE_RCU_REPEATEDLY is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
-# CONFIG_TORTURE_TEST is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-
-#
-# Runtime Testing
-#
-# CONFIG_LKDTM is not set
-# CONFIG_TEST_LIST_SORT is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_RBTREE_TEST is not set
-# CONFIG_INTERVAL_TREE_TEST is not set
-# CONFIG_PERCPU_TEST is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_TEST_HEXDUMP is not set
-# CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_TEST_PRINTF is not set
-# CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_TEST_LKM is not set
-# CONFIG_TEST_USER_COPY is not set
-# CONFIG_TEST_BPF is not set
-# CONFIG_TEST_FIRMWARE is not set
-# CONFIG_TEST_UDELAY is not set
-# CONFIG_MEMTEST is not set
-# CONFIG_TEST_STATIC_KEYS is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_UBSAN is not set
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-# CONFIG_STRICT_DEVMEM is not set
-# CONFIG_ARM_PTDUMP is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_IMX31_UART is not set
-# CONFIG_DEBUG_IMX35_UART is not set
-# CONFIG_DEBUG_IMX50_UART is not set
-# CONFIG_DEBUG_IMX51_UART is not set
-# CONFIG_DEBUG_IMX53_UART is not set
-CONFIG_DEBUG_IMX6Q_UART=y
-# CONFIG_DEBUG_IMX6SL_UART is not set
-# CONFIG_DEBUG_IMX6SX_UART is not set
-# CONFIG_DEBUG_IMX6UL_UART is not set
-# CONFIG_DEBUG_IMX7D_UART is not set
-# CONFIG_DEBUG_VF_UART is not set
-# CONFIG_DEBUG_ICEDCC is not set
-# CONFIG_DEBUG_SEMIHOSTING is not set
-# CONFIG_DEBUG_LL_UART_8250 is not set
-# CONFIG_DEBUG_LL_UART_PL01X is not set
-CONFIG_DEBUG_IMX_UART_PORT=2
-CONFIG_DEBUG_VF_UART_PORT=1
-CONFIG_DEBUG_LL_INCLUDE="debug/imx.S"
-# CONFIG_DEBUG_UART_8250 is not set
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_EARLY_PRINTK=y
-# CONFIG_PID_IN_CONTEXTIDR is not set
-# CONFIG_DEBUG_SET_MODULE_RONX is not set
-# CONFIG_CORESIGHT is not set
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_PERSISTENT_KEYRINGS is not set
-# CONFIG_BIG_KEYS is not set
-# CONFIG_ENCRYPTED_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_AKCIPHER2=y
-# CONFIG_CRYPTO_RSA is not set
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_USER is not set
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-# CONFIG_CRYPTO_PCRYPT is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_MCRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=y
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_GCM=y
-# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-CONFIG_CRYPTO_CTR=y
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_KEYWRAP is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32 is not set
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=y
-# CONFIG_CRYPTO_POLY1305 is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_CHACHA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_842 is not set
-# CONFIG_CRYPTO_LZ4 is not set
-# CONFIG_CRYPTO_LZ4HC is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-# CONFIG_CRYPTO_DRBG_HASH is not set
-# CONFIG_CRYPTO_DRBG_CTR is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-# CONFIG_CRYPTO_USER_API_RNG is not set
-# CONFIG_CRYPTO_USER_API_AEAD is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_IMX=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_LE=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-# CONFIG_CRYPTO_DEV_SAHARA is not set
-# CONFIG_CRYPTO_DEV_MXS_DCP is not set
-# CONFIG_ASYMMETRIC_KEY_TYPE is not set
-
-#
-# Certificates for signature checking
-#
-# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
-# CONFIG_ARM_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IO=y
-CONFIG_STMP_DEVICE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-# CONFIG_CRC8 is not set
-# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-# CONFIG_CORDIC is not set
-# CONFIG_DDR is not set
-# CONFIG_IRQ_POLL is not set
-CONFIG_LIBFDT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_SG_SPLIT is not set
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_VIRTUALIZATION=y
diff --git a/tests/arm32/sabrelite/linux/linux-imx_3.10.17_defconfig b/tests/arm32/sabrelite/linux/linux-imx_3.10.17_defconfig
deleted file mode 100644
index fad19f96..00000000
--- a/tests/arm32/sabrelite/linux/linux-imx_3.10.17_defconfig
+++ /dev/null
@@ -1,3245 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.10.17 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_EXTABLE_SORT=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KERNEL_LZO=y
-CONFIG_DEFAULT_HOSTNAME="(none)"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_FHANDLE=y
-# CONFIG_AUDIT is not set
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-# CONFIG_IRQ_DOMAIN_DEBUG is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_IRQ_TIME_ACCOUNTING is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-# CONFIG_RCU_USER_QS is not set
-CONFIG_RCU_FANOUT=32
-CONFIG_RCU_FANOUT_LEAF=16
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_RCU_FAST_NO_HZ is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_NOCB_CPU is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_CHECKPOINT_RESTORE is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_UIDGID_CONVERTED=y
-# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_HAVE_UID16=y
-CONFIG_HOTPLUG=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_JUMP_LABEL is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_BSGLIB is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C24XX is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P64X0 is not set
-# CONFIG_ARCH_S5PC100 is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP1 is not set
-
-#
-# Multiple platform selection
-#
-
-#
-# CPU Core family selection
-#
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MULTI_V6_V7=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_MVEBU is not set
-# CONFIG_ARCH_BCM is not set
-CONFIG_GPIO_PCA953X=y
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-# CONFIG_ARCH_HIGHBANK is not set
-CONFIG_ARCH_MXC=y
-
-#
-# Freescale i.MX support
-#
-# CONFIG_MXC_IRQ_PRIOR is not set
-# CONFIG_MXC_DEBUG_BOARD is not set
-CONFIG_HAVE_IMX_RNG=y
-CONFIG_HAVE_IMX_ANATOP=y
-CONFIG_HAVE_IMX_GPC=y
-CONFIG_HAVE_IMX_MMDC=y
-CONFIG_HAVE_IMX_SRC=y
-
-#
-# i.MX51 machines:
-#
-# CONFIG_MACH_IMX51_DT is not set
-# CONFIG_MACH_MX51_BABBAGE is not set
-# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
-
-#
-# Device tree only
-#
-# CONFIG_SOC_IMX53 is not set
-CONFIG_SOC_IMX6Q=y
-CONFIG_SOC_IMX6SL=y
-# CONFIG_SOC_VF610 is not set
-# CONFIG_ARCH_OMAP2PLUS is not set
-# CONFIG_ARCH_SOCFPGA is not set
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_SUNXI is not set
-# CONFIG_ARCH_SIRF is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_VIRT is not set
-# CONFIG_ARCH_WM8850 is not set
-# CONFIG_ARCH_ZYNQ is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_LPAE is not set
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_SWP_EMULATE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_KUSER_HELPERS=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_ARM_NR_BANKS=8
-CONFIG_MULTI_IRQ_HANDLER=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_643719 is not set
-# CONFIG_ARM_ERRATA_720789 is not set
-CONFIG_ARM_ERRATA_794072=y
-CONFIG_ARM_ERRATA_761320=y
-CONFIG_ARM_ERRATA_754322=y
-# CONFIG_ARM_ERRATA_754327 is not set
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-# CONFIG_ARM_ERRATA_798181 is not set
-
-#
-# Bus support
-#
-# CONFIG_PCI is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_HAVE_SMP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_ARM_CPU_TOPOLOGY=y
-# CONFIG_SCHED_MC is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_HAVE_ARM_SCU=y
-# CONFIG_HAVE_ARM_ARCH_TIMER is not set
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_MCPM is not set
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0x80000000
-CONFIG_NR_CPUS=4
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_ARM_PSCI is not set
-CONFIG_LOCAL_TIMERS=y
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_SCHED_HRTICK=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-# CONFIG_HIGHMEM is not set
-# CONFIG_HIGHPTE is not set
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_COMPACTION=y
-CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_KSM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
-CONFIG_FORCE_MAX_ZONEORDER=14
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-CONFIG_SECCOMP=y
-# CONFIG_CC_STACKPROTECTOR is not set
-# CONFIG_XEN is not set
-
-#
-# Boot options
-#
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-# CONFIG_ARM_APPENDED_DTB is not set
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_EXTEND is not set
-# CONFIG_CMDLINE_FORCE is not set
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_AUTO_ZRELADDR=y
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-CONFIG_CPU_IDLE=y
-# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-# CONFIG_PM_AUTOSLEEP is not set
-# CONFIG_PM_WAKELOCKS is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-# CONFIG_PM_ADVANCED_DEBUG is not set
-CONFIG_PM_TEST_SUSPEND=y
-CONFIG_PM_SLEEP_DEBUG=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_HAS_OPP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_CLK=y
-CONFIG_CPU_PM=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_DIAG is not set
-CONFIG_UNIX=y
-# CONFIG_UNIX_DIAG is not set
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-CONFIG_NET_IP_TUNNEL=y
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_INET_UDP_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_IPV6_MIP6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=y
-# CONFIG_IPV6_SIT_6RD is not set
-CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_GRE is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK_ACCT is not set
-# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-# CONFIG_NETFILTER_NETLINK_LOG is not set
-# CONFIG_NF_CONNTRACK is not set
-# CONFIG_NETFILTER_XTABLES is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV4 is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# IPv6: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV6 is not set
-# CONFIG_IP6_NF_IPTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-# CONFIG_BRIDGE is not set
-CONFIG_HAVE_NET_DSA=y
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-CONFIG_DNS_RESOLVER=y
-# CONFIG_BATMAN_ADV is not set
-# CONFIG_OPENVSWITCH is not set
-# CONFIG_VSOCKETS is not set
-# CONFIG_NETLINK_MMAP is not set
-# CONFIG_NETLINK_DIAG is not set
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-# CONFIG_NETPRIO_CGROUP is not set
-CONFIG_BQL=y
-# CONFIG_BPF_JIT is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-
-#
-# CAN Device Drivers
-#
-# CONFIG_CAN_VCAN is not set
-# CONFIG_CAN_SLCAN is not set
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-# CONFIG_CAN_LEDS is not set
-# CONFIG_CAN_AT91 is not set
-# CONFIG_CAN_MCP251X is not set
-CONFIG_HAVE_CAN_FLEXCAN=y
-CONFIG_CAN_FLEXCAN=m
-# CONFIG_CAN_GRCAN is not set
-# CONFIG_CAN_SJA1000 is not set
-# CONFIG_CAN_C_CAN is not set
-# CONFIG_CAN_CC770 is not set
-
-#
-# CAN USB interfaces
-#
-# CONFIG_CAN_EMS_USB is not set
-# CONFIG_CAN_ESD_USB2 is not set
-# CONFIG_CAN_KVASER_USB is not set
-# CONFIG_CAN_PEAK_USB is not set
-# CONFIG_CAN_8DEV_USB is not set
-# CONFIG_CAN_SOFTING is not set
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-# CONFIG_BT_HCIUART_H4 is not set
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_ATH3K is not set
-CONFIG_BT_HCIUART_LL=y
-# CONFIG_BT_HCIUART_3WIRE is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-# CONFIG_BT_ATH3K is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=m
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_REG_DEBUG is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-# CONFIG_CFG80211_INTERNAL_REGDB is not set
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_LIB80211 is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-# CONFIG_MAC80211_RC_PID is not set
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_MINSTREL_HT=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-# CONFIG_MAC80211_MESH is not set
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-CONFIG_RFKILL_LEDS=y
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFKILL_GPIO=y
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-# CONFIG_NFC is not set
-CONFIG_HAVE_BPF_JIT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-CONFIG_FW_LOADER_USER_HELPER=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_GENERIC_CPU_DEVICES is not set
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_CMA=y
-CONFIG_CMA_DEBUG=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=16
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-
-#
-# Bus devices
-#
-CONFIG_IMX_WEIM=y
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-# CONFIG_MTD_SWAP is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_M25P80=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MTD_SST25L=y
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOCG3 is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_DTC=y
-CONFIG_OF=y
-
-#
-# Device Tree and Open Firmware support
-#
-# CONFIG_PROC_DEVICETREE is not set
-# CONFIG_OF_SELFTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_DEVICE=y
-CONFIG_OF_I2C=y
-CONFIG_OF_NET=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_DRBD is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_BLK_DEV_RBD is not set
-
-#
-# Misc devices
-#
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_AD525X_DPOT is not set
-# CONFIG_ATMEL_PWM is not set
-# CONFIG_DUMMY_IRQ is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ATMEL_SSC is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-# CONFIG_BMP085_I2C is not set
-# CONFIG_BMP085_SPI is not set
-# CONFIG_USB_SWITCH_FSA9480 is not set
-# CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_SRAM=y
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_EEPROM_93XX46 is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-
-#
-# Altera FPGA firmware download module
-#
-# CONFIG_ALTERA_STAPL is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=y
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_AHCI_IMX=y
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_SATA_HIGHBANK is not set
-# CONFIG_SATA_MV is not set
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ARASAN_CF is not set
-CONFIG_PATA_IMX=y
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_PLATFORM is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_MD is not set
-# CONFIG_TARGET_CORE is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_CORE=y
-# CONFIG_BONDING is not set
-# CONFIG_DUMMY is not set
-# CONFIG_EQUALIZER is not set
-CONFIG_MII=y
-# CONFIG_NET_TEAM is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_VXLAN is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-
-#
-# CAIF transport drivers
-#
-
-#
-# Distributed Switch Architecture drivers
-#
-# CONFIG_NET_DSA_MV88E6XXX is not set
-# CONFIG_NET_DSA_MV88E6060 is not set
-# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
-# CONFIG_NET_DSA_MV88E6131 is not set
-# CONFIG_NET_DSA_MV88E6123_61_65 is not set
-CONFIG_ETHERNET=y
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_CALXEDA_XGMAC is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_DM9000 is not set
-# CONFIG_DNET is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_FEC=y
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_ETHOC is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_AT803X_PHY is not set
-# CONFIG_AMD_PHY is not set
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_BCM87XX_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-CONFIG_MICREL_PHY=y
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
-# CONFIG_MICREL_KS8995MA is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_RTL8152 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_USB_IPHETH is not set
-CONFIG_WLAN=y
-# CONFIG_LIBERTAS_THINFIRM is not set
-# CONFIG_AT76C50X_USB is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_RTL8187 is not set
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_ATH_CARDS is not set
-# CONFIG_B43 is not set
-# CONFIG_B43LEGACY is not set
-# CONFIG_BRCMFMAC is not set
-# CONFIG_HOSTAP is not set
-# CONFIG_LIBERTAS is not set
-# CONFIG_P54_COMMON is not set
-# CONFIG_RT2X00 is not set
-# CONFIG_RTLWIFI is not set
-CONFIG_WL_TI=y
-# CONFIG_WL1251 is not set
-CONFIG_WL12XX=m
-# CONFIG_WL18XX is not set
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-# CONFIG_WILINK_PLATFORM_DATA is not set
-# CONFIG_ZD1211RW is not set
-# CONFIG_MWIFIEX is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-# CONFIG_WAN is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-CONFIG_INPUT_MATRIXKMAP=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_TCA8418 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_LM8333 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-CONFIG_KEYBOARD_IMX=y
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_SAMSUNG is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_CWC_HOOKSWITCH is not set
-CONFIG_INPUT_MOUSE=y
-# CONFIG_MOUSE_PS2 is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_GPIO is not set
-# CONFIG_MOUSE_SYNAPTICS_I2C is not set
-# CONFIG_MOUSE_SYNAPTICS_USB is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-CONFIG_TOUCHSCREEN_AR1020_I2C=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-CONFIG_TOUCHSCREEN_EGALAX=y
-# CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH is not set
-# CONFIG_TOUCHSCREEN_ELAN is not set
-CONFIG_TOUCHSCREEN_FT5X06=y
-# CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-CONFIG_TOUCHSCREEN_ILI210X=y
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MMS114 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-CONFIG_TOUCHSCREEN_TSC2004=y
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_SERIO_PS2MULT is not set
-# CONFIG_SERIO_ARC_PS2 is not set
-# CONFIG_SERIO_APBPS2 is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-# CONFIG_DEVKMEM is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_KGDB_NMI is not set
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX310X is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_CONSOLE_POLL=y
-# CONFIG_SERIAL_SC16IS7XX is not set
-# CONFIG_SERIAL_SCCNXP is not set
-# CONFIG_SERIAL_TIMBERDALE is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_SERIAL_ARC is not set
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-# CONFIG_TTY_PRINTK is not set
-# CONFIG_FSL_OTP is not set
-# CONFIG_HVC_DCC is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_HW_RANDOM_ATMEL is not set
-# CONFIG_HW_RANDOM_IMX_RNG is not set
-# CONFIG_HW_RANDOM_EXYNOS is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_MAGSTRIPE is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_SAS is not set
-# CONFIG_MXS_VIIM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-CONFIG_I2C_MUX_GPIO=y
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-# CONFIG_I2C_MUX_PINCTRL is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-# CONFIG_I2C_SMBUS is not set
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_CBUS_GPIO is not set
-# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_FSL_SPI is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_SC18IS602 is not set
-# CONFIG_SPI_XCOMM is not set
-# CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# Qualcomm MSM SSBI bus support
-#
-# CONFIG_SSBI is not set
-# CONFIG_HSI is not set
-
-#
-# PPS support
-#
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-# CONFIG_PPS_CLIENT_LDISC is not set
-# CONFIG_PPS_CLIENT_GPIO is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-
-#
-# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
-#
-# CONFIG_PTP_1588_CLOCK_PCH is not set
-CONFIG_PINCTRL=y
-
-#
-# Pin controllers
-#
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX6Q=y
-CONFIG_PINCTRL_IMX6SL=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_EXYNOS is not set
-# CONFIG_PINCTRL_EXYNOS5440 is not set
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIOLIB=y
-CONFIG_OF_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC=y
-
-#
-# Memory mapped GPIO drivers:
-#
-# CONFIG_GPIO_GENERIC_PLATFORM is not set
-# CONFIG_GPIO_EM is not set
-CONFIG_GPIO_MXC=y
-# CONFIG_GPIO_RCAR is not set
-# CONFIG_GPIO_TS5500 is not set
-# CONFIG_GPIO_GRGPIO is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X_IRQ is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-# CONFIG_GPIO_ADP5588 is not set
-# CONFIG_GPIO_ADNP is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_74X164 is not set
-
-#
-# AC97 GPIO expanders:
-#
-
-#
-# MODULbus GPIO expanders:
-#
-
-#
-# USB GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2781 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_SBS is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_CHARGER_ISP1704 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_LP8727 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_CHARGER_MANAGER is not set
-# CONFIG_CHARGER_BQ2415X is not set
-# CONFIG_CHARGER_SMB347 is not set
-# CONFIG_BATTERY_GOLDFISH is not set
-# CONFIG_IMX6_USB_CHARGER is not set
-# CONFIG_POWER_RESET is not set
-# CONFIG_POWER_RESET_RESTART is not set
-# CONFIG_POWER_AVS is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7314 is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7310 is not set
-# CONFIG_SENSORS_ADT7410 is not set
-# CONFIG_SENSORS_ADT7411 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ASC7621 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS620 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_GPIO_FAN is not set
-# CONFIG_SENSORS_HIH6130 is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_JC42 is not set
-# CONFIG_SENSORS_LINEAGE is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM73 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4151 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LTC4261 is not set
-# CONFIG_SENSORS_LM95234 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_LM95245 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX16065 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX1668 is not set
-# CONFIG_SENSORS_MAX17135 is not set
-# CONFIG_SENSORS_MAX197 is not set
-# CONFIG_SENSORS_MAX6639 is not set
-# CONFIG_SENSORS_MAX6642 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_MAX6697 is not set
-# CONFIG_SENSORS_MCP3021 is not set
-# CONFIG_SENSORS_NCT6775 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_PMBUS is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_SHT21 is not set
-# CONFIG_SENSORS_SMM665 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_EMC1403 is not set
-# CONFIG_SENSORS_EMC2103 is not set
-# CONFIG_SENSORS_EMC6W201 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SCH56XX_COMMON is not set
-# CONFIG_SENSORS_SCH5627 is not set
-# CONFIG_SENSORS_SCH5636 is not set
-# CONFIG_SENSORS_ADS1015 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_ADS7871 is not set
-# CONFIG_SENSORS_AMC6821 is not set
-# CONFIG_SENSORS_INA209 is not set
-# CONFIG_SENSORS_INA2XX is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP102 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83795 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_SENSORS_MAG3110=y
-CONFIG_MXC_MMA8451=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_DEVICE_THERMAL=y
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_CORE is not set
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_DW_WATCHDOG is not set
-# CONFIG_MPCORE_WATCHDOG is not set
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_IMX2_WDT=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_CROS_EC is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_DA9052_SPI is not set
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-CONFIG_MFD_MXC_HDMI=y
-# CONFIG_MFD_MC13XXX_SPI is not set
-# CONFIG_MFD_MC13XXX_I2C is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX17135 is not set
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_VIPERBOARD is not set
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_RC5T583 is not set
-# CONFIG_MFD_SEC_CORE is not set
-# CONFIG_MFD_SI476X_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_SMSC is not set
-# CONFIG_ABX500_CORE is not set
-# CONFIG_MFD_STMPE is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_TI_AM335X_TSCADC is not set
-# CONFIG_MFD_LP8788 is not set
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_TPS65912 is not set
-# CONFIG_MFD_TPS65912_I2C is not set
-# CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_MFD_TPS80031 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_LM3533 is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_ARIZONA_SPI is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_GPIO is not set
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_FAN53555 is not set
-CONFIG_REGULATOR_ANATOP=y
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_MAX8973 is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_LP872X is not set
-# CONFIG_REGULATOR_LP8755 is not set
-# CONFIG_REGULATOR_PFUZE100 is not set
-# CONFIG_REGULATOR_TPS51632 is not set
-# CONFIG_REGULATOR_TPS62360 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
-# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
-# CONFIG_MEDIA_RADIO_SUPPORT is not set
-# CONFIG_MEDIA_RC_SUPPORT is not set
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_CORE=y
-CONFIG_VIDEO_V4L2_INT_DEVICE=m
-# CONFIG_TTPCI_EEPROM is not set
-
-#
-# Media drivers
-#
-# CONFIG_MEDIA_USB_SUPPORT is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_TIMBERDALE is not set
-CONFIG_VIDEO_MXC_OUTPUT=y
-CONFIG_VIDEO_MXC_CAPTURE=m
-
-#
-# MXC Camera/V4L2 PRP Features support
-#
-CONFIG_VIDEO_MXC_IPU_CAMERA=y
-CONFIG_VIDEO_MXC_CSI_CAMERA=m
-CONFIG_MXC_CAMERA_OV5640=m
-CONFIG_MXC_CAMERA_OV5642=m
-CONFIG_MXC_CAMERA_OV5640_MIPI=m
-# CONFIG_MXC_VIDEO_GS2971 is not set
-# CONFIG_MXC_HDMI_CSI2_TC358743 is not set
-CONFIG_MXC_TVIN_ADV7180=m
-CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
-CONFIG_MXC_IPU_PRP_ENC=m
-CONFIG_MXC_IPU_CSI_ENC=m
-CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-# CONFIG_V4L_TEST_DRIVERS is not set
-
-#
-# Supported MMC/SDIO adapters
-#
-# CONFIG_CYPRESS_FIRMWARE is not set
-
-#
-# Media ancillary drivers (tuners, sensors, i2c, frontends)
-#
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-
-#
-# Encoders, decoders, sensors and other helper chips
-#
-
-#
-# Audio decoders, processors and mixers
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_UDA1342 is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-# CONFIG_VIDEO_SONY_BTF_MPX is not set
-
-#
-# RDS decoders
-#
-# CONFIG_VIDEO_SAA6588 is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_BT819 is not set
-# CONFIG_VIDEO_BT856 is not set
-# CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_KS0127 is not set
-# CONFIG_VIDEO_SAA7110 is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA7191 is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_TVP7002 is not set
-# CONFIG_VIDEO_TW2804 is not set
-# CONFIG_VIDEO_TW9903 is not set
-# CONFIG_VIDEO_TW9906 is not set
-# CONFIG_VIDEO_VPX3220 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-# CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_ADV7170 is not set
-# CONFIG_VIDEO_ADV7175 is not set
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_AK881X is not set
-
-#
-# Camera sensor devices
-#
-# CONFIG_VIDEO_OV7640 is not set
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_VS6624 is not set
-# CONFIG_VIDEO_MT9V011 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-
-#
-# Flash devices
-#
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-
-#
-# Miscelaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-# CONFIG_VIDEO_M52790 is not set
-
-#
-# Sensors used on soc_camera driver
-#
-
-#
-# soc_camera sensor drivers
-#
-# CONFIG_SOC_CAMERA_IMX074 is not set
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-
-#
-# Customise DVB Frontends
-#
-# CONFIG_DVB_AU8522_V4L is not set
-# CONFIG_DVB_TUNER_DIB0070 is not set
-# CONFIG_DVB_TUNER_DIB0090 is not set
-
-#
-# Tools to develop new frontends
-#
-# CONFIG_DVB_DUMMY_FE is not set
-
-#
-# Graphics support
-#
-CONFIG_DRM=y
-CONFIG_DRM_VIVANTE=y
-# CONFIG_DRM_EXYNOS is not set
-# CONFIG_DRM_UDL is not set
-# CONFIG_DRM_TILCDC is not set
-# CONFIG_TEGRA_HOST1X is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_TMIO is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_GOLDFISH is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_BROADSHEET is not set
-# CONFIG_FB_AUO_K190X is not set
-CONFIG_FB_MXS=y
-# CONFIG_FB_SIMPLE is not set
-# CONFIG_EXYNOS_VIDEO is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_L4F00242T03=y
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI922X is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-CONFIG_LCD_PLATFORM=y
-# CONFIG_LCD_S6E63M0 is not set
-# CONFIG_LCD_LD9040 is not set
-# CONFIG_LCD_AMS369FG06 is not set
-# CONFIG_LCD_LMS501KF03 is not set
-# CONFIG_LCD_HX8357 is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-# CONFIG_BACKLIGHT_LM3630 is not set
-# CONFIG_BACKLIGHT_LM3639 is not set
-# CONFIG_BACKLIGHT_LP855X is not set
-CONFIG_FB_MXC=y
-CONFIG_FB_MXC_SYNC_PANEL=y
-CONFIG_FB_MXC_LCDIF=y
-# CONFIG_FB_MXC_TVOUT_ADV739X is not set
-CONFIG_FB_MXC_LDB=y
-CONFIG_FB_MXC_MIPI_DSI=y
-CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
-CONFIG_FB_MXC_HDMI=y
-CONFIG_FB_MXC_EDID=y
-# CONFIG_FB_MXC_EINK_PANEL is not set
-# CONFIG_FB_MXS_SII902X is not set
-# CONFIG_HANNSTAR_CABC is not set
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_FB_SSD1307 is not set
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-# CONFIG_SND_ATMEL_SOC is not set
-# CONFIG_SND_DESIGNWARE_I2S is not set
-CONFIG_SND_SOC_FSL_SSI=y
-CONFIG_SND_SOC_FSL_ASRC=y
-CONFIG_SND_SOC_FSL_HDMI=y
-CONFIG_SND_SOC_FSL_UTILS=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_SOC_IMX_PCM_DMA=y
-CONFIG_SND_SOC_IMX_HDMI_DMA=y
-CONFIG_SND_SOC_IMX_AUDMUX=y
-# CONFIG_SND_SOC_IMX_CS42888 is not set
-# CONFIG_SND_SOC_IMX_WM8962 is not set
-CONFIG_SND_SOC_IMX_SGTL5000=y
-# CONFIG_SND_SOC_IMX_WM5102 is not set
-# CONFIG_SND_SOC_IMX_SPDIF is not set
-CONFIG_SND_SOC_IMX_HDMI=y
-# CONFIG_SND_SOC_IMX_SI476X is not set
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_OMAP_HDMI_CODEC=y
-CONFIG_SND_SOC_SGTL5000=y
-# CONFIG_SND_SIMPLE_CARD is not set
-# CONFIG_SOUND_PRIME is not set
-
-#
-# HID support
-#
-CONFIG_HID=y
-# CONFIG_HID_BATTERY_STRENGTH is not set
-# CONFIG_HIDRAW is not set
-# CONFIG_UHID is not set
-CONFIG_HID_GENERIC=y
-
-#
-# Special HID drivers
-#
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_ACRUX is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_APPLEIR is not set
-# CONFIG_HID_AUREAL is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_PRODIKEYS is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EMS_FF is not set
-# CONFIG_HID_ELECOM is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_HOLTEK is not set
-# CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_UCLOGIC is not set
-# CONFIG_HID_WALTOP is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_ICADE is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LCPOWER is not set
-# CONFIG_HID_LENOVO_TPKBD is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MAGICMOUSE is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_MULTITOUCH is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_PICOLCD is not set
-# CONFIG_HID_PRIMAX is not set
-# CONFIG_HID_PS3REMOTE is not set
-# CONFIG_HID_ROCCAT is not set
-# CONFIG_HID_SAITEK is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SPEEDLINK is not set
-# CONFIG_HID_STEELSERIES is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TIVO is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THINGM is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-# CONFIG_HID_SENSOR_HUB is not set
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# I2C HID support
-#
-# CONFIG_I2C_HID is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-# CONFIG_USB_EHCI_MXC is not set
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_IMX21_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_RENESAS_USBHS is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_DWC3 is not set
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-# CONFIG_USB_CHIPIDEA_DEBUG is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-CONFIG_USB_SERIAL_CP210X=y
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_F81232 is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-CONFIG_USB_SERIAL_KEYSPAN=y
-# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_METRO is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-CONFIG_USB_SERIAL_PL2303=y
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QCAUX is not set
-CONFIG_USB_SERIAL_QUALCOMM=y
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_WWAN=y
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
-# CONFIG_USB_SERIAL_XSENS_MT is not set
-# CONFIG_USB_SERIAL_ZIO is not set
-# CONFIG_USB_SERIAL_WISHBONE is not set
-# CONFIG_USB_SERIAL_ZTE is not set
-# CONFIG_USB_SERIAL_SSU100 is not set
-# CONFIG_USB_SERIAL_QT2 is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-CONFIG_USB_EZUSB_FX2=y
-# CONFIG_USB_HSIC_USB3503 is not set
-CONFIG_USB_PHY=y
-# CONFIG_NOP_USB_XCEIV is not set
-# CONFIG_OMAP_CONTROL_USB is not set
-# CONFIG_OMAP_USB3 is not set
-# CONFIG_SAMSUNG_USBPHY is not set
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ISP1301 is not set
-CONFIG_USB_MXS_PHY=y
-# CONFIG_USB_RCAR_PHY is not set
-# CONFIG_USB_ULPI is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FSL_USB2 is not set
-# CONFIG_USB_FUSB300 is not set
-# CONFIG_USB_R8A66597 is not set
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-# CONFIG_USB_M66592 is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_DUMMY_HCD is not set
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_ZERO=m
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-CONFIG_USB_FUNCTIONFS=m
-# CONFIG_USB_FUNCTIONFS_ETH is not set
-# CONFIG_USB_FUNCTIONFS_RNDIS is not set
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-# CONFIG_FSL_UTP is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_ACM_MS is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MMC_CLKGATE is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_PREFER_SAME_NUMBER is not set
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-# CONFIG_MMC_SDHCI_PXAV3 is not set
-# CONFIG_MMC_SDHCI_PXAV2 is not set
-# CONFIG_MMC_MXC is not set
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MEMSTICK is not set
-
-#
-# MXC support drivers
-#
-CONFIG_MXC_IPU=y
-
-#
-# MXC Vivante GPU support
-#
-CONFIG_MXC_GPU_VIV=y
-CONFIG_MXC_IPU_V3=y
-
-#
-# MXC Asynchronous Sample Rate Converter support
-#
-CONFIG_MXC_ASRC=y
-
-#
-# MXC VPU(Video Processing Unit) support
-#
-CONFIG_MXC_VPU=y
-# CONFIG_MXC_VPU_DEBUG is not set
-# CONFIG_MX6_VPU_352M is not set
-
-#
-# MXC HDMI CEC (Consumer Electronics Control) support
-#
-# CONFIG_MXC_HDMI_CEC is not set
-
-#
-# MXC MIPI Support
-#
-CONFIG_MXC_MIPI_CSI2=y
-
-#
-# MXC Media Local Bus Driver
-#
-# CONFIG_MXC_MLB150 is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_LM3642 is not set
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_LP5562 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_PCA9633 is not set
-# CONFIG_LEDS_DAC124S085 is not set
-CONFIG_LEDS_PWM=y
-# CONFIG_LEDS_REGULATOR is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_RENESAS_TPU is not set
-# CONFIG_LEDS_TCA6507 is not set
-# CONFIG_LEDS_LM355x is not set
-# CONFIG_LEDS_OT200 is not set
-# CONFIG_LEDS_BLINKM is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_ONESHOT is not set
-# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_CPU is not set
-# CONFIG_LEDS_TRIGGER_GPIO is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
-# CONFIG_LEDS_TRIGGER_CAMERA is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_EDAC is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_ISL1208=y
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8523 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-# CONFIG_RTC_DRV_RV4162 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-# CONFIG_RTC_DRV_RX4581 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-# CONFIG_RTC_DRV_DS2404 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-CONFIG_RTC_DRV_SNVS=y
-
-#
-# HID Sensor RTC drivers
-#
-# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-# CONFIG_DW_DMAC is not set
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_PXP_V2=y
-CONFIG_MXC_PXP_CLIENT_DEVICE=y
-# CONFIG_TIMB_DMA is not set
-CONFIG_IMX_SDMA=y
-# CONFIG_IMX_DMA is not set
-# CONFIG_MXS_DMA is not set
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-
-#
-# DMA Clients
-#
-# CONFIG_NET_DMA is not set
-# CONFIG_ASYNC_TX_DMA is not set
-# CONFIG_DMATEST is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-# CONFIG_VIRT_DRIVERS is not set
-
-#
-# Virtio drivers
-#
-# CONFIG_VIRTIO_MMIO is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_STAGING=y
-# CONFIG_USBIP_CORE is not set
-# CONFIG_W35UND is not set
-# CONFIG_PRISM2_USB is not set
-# CONFIG_ECHO is not set
-# CONFIG_COMEDI is not set
-# CONFIG_ASUS_OLED is not set
-# CONFIG_RTLLIB is not set
-# CONFIG_R8712U is not set
-# CONFIG_RTS5139 is not set
-# CONFIG_TRANZPORT is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_ZSMALLOC is not set
-# CONFIG_USB_ENESTORAGE is not set
-# CONFIG_BCM_WIMAX is not set
-# CONFIG_FT1000 is not set
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-# CONFIG_STAGING_MEDIA is not set
-
-#
-# Android
-#
-# CONFIG_ANDROID is not set
-# CONFIG_USB_WPAN_HCD is not set
-# CONFIG_WIMAX_GDM72XX is not set
-# CONFIG_CED1401 is not set
-# CONFIG_DRM_IMX is not set
-# CONFIG_DGRP is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-
-#
-# Common Clock Framework
-#
-CONFIG_COMMON_CLK_DEBUG=y
-# CONFIG_COMMON_CLK_SI5351 is not set
-
-#
-# Hardware Spinlock drivers
-#
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_MAILBOX is not set
-# CONFIG_IOMMU_SUPPORT is not set
-
-#
-# Remoteproc drivers
-#
-# CONFIG_STE_MODEM_RPROC is not set
-
-#
-# Rpmsg drivers
-#
-# CONFIG_PM_DEVFREQ is not set
-# CONFIG_EXTCON is not set
-# CONFIG_MEMORY is not set
-# CONFIG_IIO is not set
-CONFIG_PWM=y
-CONFIG_PWM_IMX=y
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_GPIO=y
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-# CONFIG_OVERLAYFS_FS is not set
-CONFIG_GENERIC_ACL=y
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=m
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_LOGFS is not set
-# CONFIG_CRAMFS is not set
-CONFIG_SQUASHFS=y
-# CONFIG_SQUASHFS_XATTR is not set
-CONFIG_SQUASHFS_ZLIB=y
-# CONFIG_SQUASHFS_LZO is not set
-# CONFIG_SQUASHFS_XZ is not set
-# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_QNX6FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_F2FS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V2=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-# CONFIG_NFS_SWAP is not set
-# CONFIG_NFS_V4_1 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_DEBUG is not set
-# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_MAC_ROMAN is not set
-# CONFIG_NLS_MAC_CELTIC is not set
-# CONFIG_NLS_MAC_CENTEURO is not set
-# CONFIG_NLS_MAC_CROATIAN is not set
-# CONFIG_NLS_MAC_CYRILLIC is not set
-# CONFIG_NLS_MAC_GAELIC is not set
-# CONFIG_NLS_MAC_GREEK is not set
-# CONFIG_NLS_MAC_ICELAND is not set
-# CONFIG_NLS_MAC_INUIT is not set
-# CONFIG_NLS_MAC_ROMANIAN is not set
-# CONFIG_NLS_MAC_TURKISH is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_READABLE_ASM is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_LOCKUP_DETECTOR is not set
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_INFO_REDUCED is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_TEST_LIST_SORT is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-
-#
-# RCU Debugging
-#
-# CONFIG_SPARSE_RCU_POINTER is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_CPU_STALL_INFO is not set
-# CONFIG_RCU_TRACE is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_LKDTM is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_RBTREE_TEST is not set
-# CONFIG_INTERVAL_TREE_TEST is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_KGDB=y
-CONFIG_KGDB_SERIAL_CONSOLE=y
-# CONFIG_KGDB_TESTS is not set
-# CONFIG_KGDB_KDB is not set
-# CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_STRICT_DEVMEM is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_IMX6Q_UART=y
-# CONFIG_DEBUG_IMX6SL_UART is not set
-# CONFIG_DEBUG_ICEDCC is not set
-# CONFIG_DEBUG_SEMIHOSTING is not set
-CONFIG_DEBUG_IMX_UART_PORT=2
-CONFIG_DEBUG_LL_INCLUDE="debug/imx.S"
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_EARLY_PRINTK=y
-# CONFIG_PID_IN_CONTEXTIDR is not set
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_ENCRYPTED_KEYS is not set
-# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_NULL=y
-# CONFIG_CRYPTO_PCRYPT is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=y
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_SEQIV=y
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=y
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_CMAC is not set
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32 is not set
-CONFIG_CRYPTO_GHASH=y
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA1_ARM is not set
-CONFIG_CRYPTO_SHA256=m
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_AES_ARM is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
-# CONFIG_ASYMMETRIC_KEY_TYPE is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IO=y
-CONFIG_STMP_DEVICE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-# CONFIG_CRC8 is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_XZ_DEC is not set
-# CONFIG_XZ_DEC_BCJ is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_NLATTR=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_AVERAGE=y
-# CONFIG_CORDIC is not set
-# CONFIG_DDR is not set
-CONFIG_OID_REGISTRY=y
-# CONFIG_VIRTUALIZATION is not set
diff --git a/tests/arm32/sabrelite/linux/linux-imx_3.14.28_defconfig b/tests/arm32/sabrelite/linux/linux-imx_3.14.28_defconfig
deleted file mode 100644
index 7b21ec38..00000000
--- a/tests/arm32/sabrelite/linux/linux-imx_3.14.28_defconfig
+++ /dev/null
@@ -1,3894 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.14.28 Kernel Configuration
-#
-CONFIG_ARM=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_EXTABLE_SORT=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KERNEL_LZO=y
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_DEFAULT_HOSTNAME="(none)"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_FHANDLE=y
-# CONFIG_AUDIT is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-# CONFIG_IRQ_DOMAIN_DEBUG is not set
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-# CONFIG_IRQ_TIME_ACCOUNTING is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-# CONFIG_RCU_USER_QS is not set
-CONFIG_RCU_FANOUT=32
-CONFIG_RCU_FANOUT_LEAF=16
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_RCU_FAST_NO_HZ is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_NOCB_CPU is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_BLK_CGROUP is not set
-# CONFIG_CHECKPOINT_RESTORE is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_HAVE_UID16=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLUB_CPU_PARTIAL=y
-# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_JUMP_LABEL is not set
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-# CONFIG_CC_STACKPROTECTOR is not set
-CONFIG_CC_STACKPROTECTOR_NONE=y
-# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
-# CONFIG_CC_STACKPROTECTOR_STRONG is not set
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_BSGLIB is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-# CONFIG_BLK_CMDLINE_PARSER is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_EFI_PARTITION=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_LPC32XX is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM_NODT is not set
-# CONFIG_ARCH_SHMOBILE_LEGACY is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C24XX is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P64X0 is not set
-# CONFIG_ARCH_S5PC100 is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_EXYNOS is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP1 is not set
-
-#
-# Multiple platform selection
-#
-
-#
-# CPU Core family selection
-#
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MULTI_V6_V7=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-# CONFIG_ARCH_MVEBU is not set
-# CONFIG_ARCH_BCM is not set
-# CONFIG_ARCH_BERLIN is not set
-CONFIG_GPIO_PCA953X=y
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
-# CONFIG_ARCH_HIGHBANK is not set
-# CONFIG_ARCH_HI3xxx is not set
-# CONFIG_ARCH_KEYSTONE is not set
-# CONFIG_ARCH_MSM_DT is not set
-CONFIG_ARCH_MXC=y
-
-#
-# Freescale i.MX support
-#
-# CONFIG_MXC_DEBUG_BOARD is not set
-CONFIG_HAVE_IMX_RNG=y
-CONFIG_HAVE_IMX_ANATOP=y
-CONFIG_HAVE_IMX_GPC=y
-CONFIG_HAVE_IMX_MMDC=y
-CONFIG_HAVE_IMX_SRC=y
-
-#
-# i.MX51 machines:
-#
-# CONFIG_MACH_IMX51_DT is not set
-# CONFIG_MACH_MX51_BABBAGE is not set
-# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
-
-#
-# Device tree only
-#
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX53 is not set
-CONFIG_SOC_IMX6=y
-CONFIG_SOC_IMX6Q=y
-CONFIG_SOC_IMX6SL=y
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_VF610 is not set
-# CONFIG_ARCH_OMAP3 is not set
-# CONFIG_ARCH_OMAP4 is not set
-# CONFIG_SOC_OMAP5 is not set
-# CONFIG_SOC_AM33XX is not set
-# CONFIG_SOC_AM43XX is not set
-# CONFIG_SOC_DRA7XX is not set
-# CONFIG_ARCH_ROCKCHIP is not set
-# CONFIG_ARCH_SOCFPGA is not set
-# CONFIG_PLAT_SPEAR is not set
-# CONFIG_ARCH_STI is not set
-# CONFIG_ARCH_SHMOBILE_MULTI is not set
-# CONFIG_ARCH_SUNXI is not set
-# CONFIG_ARCH_SIRF is not set
-# CONFIG_ARCH_TEGRA is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_VIRT is not set
-# CONFIG_ARCH_WM8850 is not set
-# CONFIG_ARCH_ZYNQ is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_LPAE is not set
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_SWP_EMULATE=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_KUSER_HELPERS=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_ARM_NR_BANKS=8
-CONFIG_MULTI_IRQ_HANDLER=y
-# CONFIG_ARM_ERRATA_430973 is not set
-CONFIG_PL310_ERRATA_588369=y
-# CONFIG_ARM_ERRATA_643719 is not set
-# CONFIG_ARM_ERRATA_720789 is not set
-CONFIG_PL310_ERRATA_727915=y
-# CONFIG_PL310_ERRATA_753970 is not set
-CONFIG_ARM_ERRATA_754322=y
-# CONFIG_ARM_ERRATA_754327 is not set
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_ARM_ERRATA_775420=y
-# CONFIG_ARM_ERRATA_798181 is not set
-# CONFIG_ARM_ERRATA_773022 is not set
-
-#
-# Bus support
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCI_MSI=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-# CONFIG_PCI_STUB is not set
-# CONFIG_PCI_IOV is not set
-# CONFIG_PCI_PRI is not set
-# CONFIG_PCI_PASID is not set
-
-#
-# PCI host controller drivers
-#
-CONFIG_PCIE_DW=y
-CONFIG_PCI_IMX6=y
-# CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE is not set
-# CONFIG_PCIE_FORCE_GEN1 is not set
-# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
-# CONFIG_RC_MODE_IN_EP_RC_SYS is not set
-# CONFIG_PCI_HOST_GENERIC is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIE_ECRC is not set
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEBUG is not set
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_HAVE_SMP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_ARM_CPU_TOPOLOGY=y
-# CONFIG_SCHED_MC is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_HAVE_ARM_SCU=y
-# CONFIG_HAVE_ARM_ARCH_TIMER is not set
-CONFIG_HAVE_ARM_TWD=y
-# CONFIG_MCPM is not set
-# CONFIG_BIG_LITTLE is not set
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_NR_CPUS=4
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_ARM_PSCI is not set
-CONFIG_ARCH_NR_GPIO=0
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_100=y
-# CONFIG_HZ_200 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_500 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=100
-CONFIG_SCHED_HRTICK=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_COMPACTION=y
-CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_KSM=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_ZBUD is not set
-# CONFIG_ZSMALLOC is not set
-CONFIG_FORCE_MAX_ZONEORDER=14
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-CONFIG_SECCOMP=y
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-# CONFIG_XEN is not set
-
-#
-# Boot options
-#
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-# CONFIG_ARM_APPENDED_DTB is not set
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_EXTEND is not set
-# CONFIG_CMDLINE_FORCE is not set
-# CONFIG_KEXEC is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_AUTO_ZRELADDR=y
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-# CONFIG_GENERIC_CPUFREQ_CPU0 is not set
-
-#
-# ARM CPU frequency scaling drivers
-#
-CONFIG_ARM_IMX6Q_CPUFREQ=y
-# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-
-#
-# ARM CPU Idle Drivers
-#
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-# CONFIG_KERNEL_MODE_NEON is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-# CONFIG_PM_AUTOSLEEP is not set
-# CONFIG_PM_WAKELOCKS is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_PM=y
-CONFIG_PM_DEBUG=y
-# CONFIG_PM_ADVANCED_DEBUG is not set
-CONFIG_PM_TEST_SUSPEND=y
-CONFIG_PM_SLEEP_DEBUG=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_HAS_OPP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_GENERIC_DOMAINS_RUNTIME=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_CPU_PM=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_DIAG is not set
-CONFIG_UNIX=y
-# CONFIG_UNIX_DIAG is not set
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE_DEMUX is not set
-CONFIG_NET_IP_TUNNEL=y
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_INET_UDP_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_IPV6_MIP6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-# CONFIG_IPV6_VTI is not set
-CONFIG_IPV6_SIT=y
-# CONFIG_IPV6_SIT_6RD is not set
-CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_GRE is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK_ACCT is not set
-# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-# CONFIG_NETFILTER_NETLINK_LOG is not set
-# CONFIG_NF_CONNTRACK is not set
-# CONFIG_NF_TABLES is not set
-# CONFIG_NETFILTER_XTABLES is not set
-# CONFIG_IP_SET is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV4 is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# IPv6: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV6 is not set
-# CONFIG_IP6_NF_IPTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_L2TP is not set
-# CONFIG_BRIDGE is not set
-CONFIG_HAVE_NET_DSA=y
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-CONFIG_6LOWPAN_IPHC=m
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-CONFIG_DNS_RESOLVER=y
-# CONFIG_BATMAN_ADV is not set
-# CONFIG_OPENVSWITCH is not set
-# CONFIG_VSOCKETS is not set
-# CONFIG_NETLINK_MMAP is not set
-# CONFIG_NETLINK_DIAG is not set
-# CONFIG_NET_MPLS_GSO is not set
-# CONFIG_HSR is not set
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-# CONFIG_CGROUP_NET_PRIO is not set
-# CONFIG_CGROUP_NET_CLASSID is not set
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-# CONFIG_BPF_JIT is not set
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-
-#
-# CAN Device Drivers
-#
-# CONFIG_CAN_VCAN is not set
-# CONFIG_CAN_SLCAN is not set
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-# CONFIG_CAN_LEDS is not set
-# CONFIG_CAN_AT91 is not set
-# CONFIG_CAN_TI_HECC is not set
-# CONFIG_CAN_MCP251X is not set
-CONFIG_CAN_FLEXCAN=m
-# CONFIG_PCH_CAN is not set
-# CONFIG_CAN_GRCAN is not set
-# CONFIG_CAN_M_CAN is not set
-# CONFIG_CAN_SJA1000 is not set
-# CONFIG_CAN_C_CAN is not set
-# CONFIG_CAN_CC770 is not set
-
-#
-# CAN USB interfaces
-#
-# CONFIG_CAN_EMS_USB is not set
-# CONFIG_CAN_ESD_USB2 is not set
-# CONFIG_CAN_KVASER_USB is not set
-# CONFIG_CAN_PEAK_USB is not set
-# CONFIG_CAN_8DEV_USB is not set
-# CONFIG_CAN_SOFTING is not set
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-# CONFIG_BT_HCIUART_H4 is not set
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_ATH3K is not set
-CONFIG_BT_HCIUART_LL=y
-# CONFIG_BT_HCIUART_3WIRE is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-# CONFIG_BT_ATH3K is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=m
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_REG_DEBUG is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-# CONFIG_CFG80211_INTERNAL_REGDB is not set
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_LIB80211 is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-# CONFIG_MAC80211_RC_PID is not set
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_MINSTREL_HT=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-# CONFIG_MAC80211_MESH is not set
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-# CONFIG_WIMAX is not set
-CONFIG_RFKILL=y
-CONFIG_RFKILL_LEDS=y
-# CONFIG_RFKILL_INPUT is not set
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFKILL_GPIO=y
-# CONFIG_NET_9P is not set
-# CONFIG_CAIF is not set
-# CONFIG_CEPH_LIB is not set
-# CONFIG_NFC is not set
-CONFIG_HAVE_BPF_JIT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-CONFIG_FW_LOADER_USER_HELPER=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_GENERIC_CPU_DEVICES is not set
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_CMA is not set
-
-#
-# Bus devices
-#
-CONFIG_IMX_WEIM=y
-# CONFIG_ARM_CCI is not set
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_OF_PARTS=y
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_SM_FTL is not set
-# CONFIG_MTD_OOPS is not set
-# CONFIG_MTD_SWAP is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_INTEL_VR_NOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_SST25L=y
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOCG3 is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_SPI_NOR is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_DTC=y
-CONFIG_OF=y
-
-#
-# Device Tree and Open Firmware support
-#
-# CONFIG_PROC_DEVICETREE is not set
-# CONFIG_OF_SELFTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_NET=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_MTD=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_DRBD is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_NVME is not set
-# CONFIG_BLK_DEV_SX8 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
-
-#
-# Misc devices
-#
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_AD525X_DPOT is not set
-# CONFIG_ATMEL_PWM is not set
-# CONFIG_DUMMY_IRQ is not set
-# CONFIG_PHANTOM is not set
-# CONFIG_LS_BRAILLE is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ATMEL_SSC is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HP_ILO is not set
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1780 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_TI_DAC7512 is not set
-# CONFIG_BMP085_I2C is not set
-# CONFIG_BMP085_SPI is not set
-# CONFIG_PCH_PHUB is not set
-# CONFIG_USB_SWITCH_FSA9480 is not set
-# CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_SRAM=y
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_EEPROM_93XX46 is not set
-# CONFIG_CB710_CORE is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-# CONFIG_TI_ST is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_SENSORS_LIS3_I2C is not set
-
-#
-# Altera FPGA firmware download module
-#
-# CONFIG_ALTERA_STAPL is not set
-
-#
-# Intel MIC Host Driver
-#
-
-#
-# Intel MIC Card Driver
-#
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=y
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-# CONFIG_SATA_AHCI is not set
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_AHCI_IMX=y
-# CONFIG_SATA_INIC162X is not set
-# CONFIG_SATA_ACARD_AHCI is not set
-# CONFIG_SATA_SIL24 is not set
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
-# CONFIG_SATA_SX4 is not set
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_ATA_PIIX is not set
-# CONFIG_SATA_MV is not set
-# CONFIG_SATA_NV is not set
-# CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIS is not set
-# CONFIG_SATA_SVW is not set
-# CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
-# CONFIG_SATA_VITESSE is not set
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_ATP867X is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-CONFIG_PATA_IMX=y
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_NETCELL is not set
-# CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RDC is not set
-# CONFIG_PATA_SCH is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_SIL680 is not set
-# CONFIG_PATA_SIS is not set
-# CONFIG_PATA_TOSHIBA is not set
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_RZ1000 is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_LEGACY is not set
-# CONFIG_MD is not set
-# CONFIG_TARGET_CORE is not set
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_FIREWIRE_NOSY is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_CORE=y
-# CONFIG_BONDING is not set
-# CONFIG_DUMMY is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_NET_FC is not set
-# CONFIG_NET_TEAM is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_VXLAN is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NLMON is not set
-# CONFIG_ARCNET is not set
-
-#
-# CAIF transport drivers
-#
-
-#
-# Distributed Switch Architecture drivers
-#
-# CONFIG_NET_DSA_MV88E6XXX is not set
-# CONFIG_NET_DSA_MV88E6060 is not set
-# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
-# CONFIG_NET_DSA_MV88E6131 is not set
-# CONFIG_NET_DSA_MV88E6123_61_65 is not set
-CONFIG_ETHERNET=y
-CONFIG_NET_VENDOR_3COM=y
-# CONFIG_VORTEX is not set
-# CONFIG_TYPHOON is not set
-CONFIG_NET_VENDOR_ADAPTEC=y
-# CONFIG_ADAPTEC_STARFIRE is not set
-CONFIG_NET_VENDOR_ALTEON=y
-# CONFIG_ACENIC is not set
-CONFIG_NET_VENDOR_AMD=y
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_PCNET32 is not set
-CONFIG_NET_VENDOR_ARC=y
-# CONFIG_ARC_EMAC is not set
-CONFIG_NET_VENDOR_ATHEROS=y
-# CONFIG_ATL2 is not set
-# CONFIG_ATL1 is not set
-# CONFIG_ATL1E is not set
-# CONFIG_ATL1C is not set
-# CONFIG_ALX is not set
-# CONFIG_NET_CADENCE is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-CONFIG_NET_VENDOR_BROCADE=y
-# CONFIG_BNA is not set
-# CONFIG_NET_CALXEDA_XGMAC is not set
-CONFIG_NET_VENDOR_CHELSIO=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_CHELSIO_T4 is not set
-# CONFIG_CHELSIO_T4VF is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-CONFIG_NET_VENDOR_CISCO=y
-# CONFIG_ENIC is not set
-# CONFIG_DM9000 is not set
-# CONFIG_DNET is not set
-CONFIG_NET_VENDOR_DEC=y
-# CONFIG_NET_TULIP is not set
-CONFIG_NET_VENDOR_DLINK=y
-# CONFIG_DL2K is not set
-# CONFIG_SUNDANCE is not set
-CONFIG_NET_VENDOR_EMULEX=y
-# CONFIG_BE2NET is not set
-CONFIG_NET_VENDOR_EXAR=y
-# CONFIG_S2IO is not set
-# CONFIG_VXGE is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_FEC=y
-CONFIG_NET_VENDOR_HP=y
-# CONFIG_HP100 is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_IP1000 is not set
-# CONFIG_JME is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-CONFIG_NET_VENDOR_MELLANOX=y
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_MLX5_CORE is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-CONFIG_NET_VENDOR_MYRI=y
-# CONFIG_MYRI10GE is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-CONFIG_NET_VENDOR_NVIDIA=y
-# CONFIG_FORCEDETH is not set
-CONFIG_NET_VENDOR_OKI=y
-# CONFIG_ETHOC is not set
-CONFIG_NET_PACKET_ENGINE=y
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-CONFIG_NET_VENDOR_QLOGIC=y
-# CONFIG_QLA3XXX is not set
-# CONFIG_QLCNIC is not set
-# CONFIG_QLGE is not set
-# CONFIG_NETXEN_NIC is not set
-CONFIG_NET_VENDOR_REALTEK=y
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_R8169 is not set
-# CONFIG_SH_ETH is not set
-CONFIG_NET_VENDOR_RDC=y
-# CONFIG_R6040 is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_NET_VENDOR_SILAN=y
-# CONFIG_SC92031 is not set
-CONFIG_NET_VENDOR_SIS=y
-# CONFIG_SIS900 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SFC is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_NET_VENDOR_SUN=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NIU is not set
-CONFIG_NET_VENDOR_TEHUTI=y
-# CONFIG_TEHUTI is not set
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TLAN is not set
-CONFIG_NET_VENDOR_VIA=y
-# CONFIG_VIA_RHINE is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_AT803X_PHY is not set
-# CONFIG_AMD_PHY is not set
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_BCM87XX_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-CONFIG_MICREL_PHY=y
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
-# CONFIG_MICREL_KS8995MA is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_RTL8152 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_HSO is not set
-# CONFIG_USB_IPHETH is not set
-CONFIG_WLAN=y
-# CONFIG_LIBERTAS_THINFIRM is not set
-# CONFIG_ATMEL is not set
-# CONFIG_AT76C50X_USB is not set
-# CONFIG_PRISM54 is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_RTL8180 is not set
-# CONFIG_RTL8187 is not set
-# CONFIG_ADM8211 is not set
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_MWL8K is not set
-# CONFIG_ATH_CARDS is not set
-# CONFIG_B43 is not set
-# CONFIG_B43LEGACY is not set
-# CONFIG_BRCMSMAC is not set
-# CONFIG_BRCMFMAC is not set
-# CONFIG_HOSTAP is not set
-# CONFIG_IPW2100 is not set
-CONFIG_IWLWIFI=m
-CONFIG_IWLDVM=m
-# CONFIG_IWLMVM is not set
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-# CONFIG_IWL4965 is not set
-# CONFIG_IWL3945 is not set
-# CONFIG_LIBERTAS is not set
-# CONFIG_P54_COMMON is not set
-# CONFIG_RT2X00 is not set
-CONFIG_RTL_CARDS=m
-# CONFIG_RTL8192CE is not set
-# CONFIG_RTL8192SE is not set
-# CONFIG_RTL8192DE is not set
-# CONFIG_RTL8723AE is not set
-# CONFIG_RTL8188EE is not set
-# CONFIG_RTL8192CU is not set
-CONFIG_WL_TI=y
-# CONFIG_WL1251 is not set
-CONFIG_WL12XX=m
-# CONFIG_WL18XX is not set
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-# CONFIG_WILINK_PLATFORM_DATA is not set
-# CONFIG_ZD1211RW is not set
-# CONFIG_MWIFIEX is not set
-# CONFIG_CW1200 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-# CONFIG_WAN is not set
-# CONFIG_VMXNET3 is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_SPARSEKMAP is not set
-CONFIG_INPUT_MATRIXKMAP=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_TCA8418 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_LM8333 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-CONFIG_KEYBOARD_IMX=y
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_SAMSUNG is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_CWC_HOOKSWITCH is not set
-CONFIG_INPUT_MOUSE=y
-# CONFIG_MOUSE_PS2 is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_GPIO is not set
-# CONFIG_MOUSE_SYNAPTICS_I2C is not set
-# CONFIG_MOUSE_SYNAPTICS_USB is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-CONFIG_TOUCHSCREEN_AR1020_I2C=y
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_CR_MULTI is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
-# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-CONFIG_TOUCHSCREEN_EGALAX=y
-# CONFIG_TOUCHSCREEN_ELAN is not set
-CONFIG_TOUCHSCREEN_FT5X06=y
-# CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-CONFIG_TOUCHSCREEN_ILI210X=y
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
-# CONFIG_TOUCHSCREEN_MAX11801 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MMS114 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-CONFIG_TOUCHSCREEN_TSC2004=y
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_TOUCHSCREEN_ST1232 is not set
-# CONFIG_TOUCHSCREEN_SUR40 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_TOUCHSCREEN_ZFORCE is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=m
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_SERIO_PS2MULT is not set
-# CONFIG_SERIO_ARC_PS2 is not set
-# CONFIG_SERIO_APBPS2 is not set
-# CONFIG_SERIO_OLPC_APSP is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_NOZOMI is not set
-# CONFIG_N_GSM is not set
-# CONFIG_TRACE_SINK is not set
-# CONFIG_DEVKMEM is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX310X is not set
-# CONFIG_SERIAL_MFD_HSU is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_SERIAL_SH_SCI is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-# CONFIG_SERIAL_SC16IS7XX is not set
-# CONFIG_SERIAL_SCCNXP is not set
-# CONFIG_SERIAL_TIMBERDALE is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
-# CONFIG_SERIAL_PCH_UART is not set
-# CONFIG_SERIAL_XILINX_PS_UART is not set
-# CONFIG_SERIAL_ARC is not set
-# CONFIG_SERIAL_RP2 is not set
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-# CONFIG_SERIAL_ST_ASC is not set
-# CONFIG_TTY_PRINTK is not set
-# CONFIG_FSL_OTP is not set
-# CONFIG_HVC_DCC is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_HW_RANDOM_ATMEL is not set
-# CONFIG_HW_RANDOM_IMX_RNG is not set
-# CONFIG_HW_RANDOM_EXYNOS is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_MAGSTRIPE is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-CONFIG_I2C_MUX_GPIO=y
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-# CONFIG_I2C_MUX_PINCTRL is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-# CONFIG_I2C_SMBUS is not set
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_CBUS_GPIO is not set
-# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
-# CONFIG_I2C_DESIGNWARE_PCI is not set
-# CONFIG_I2C_EG20T is not set
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_IMX=y
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PXA_PCI is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_FSL_SPI is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_PXA2XX is not set
-# CONFIG_SPI_PXA2XX_PCI is not set
-# CONFIG_SPI_SC18IS602 is not set
-# CONFIG_SPI_TOPCLIFF_PCH is not set
-# CONFIG_SPI_XCOMM is not set
-# CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SPI_TLE62X0 is not set
-# CONFIG_HSI is not set
-
-#
-# PPS support
-#
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-# CONFIG_PPS_CLIENT_LDISC is not set
-# CONFIG_PPS_CLIENT_GPIO is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-
-#
-# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
-#
-CONFIG_PINCTRL=y
-
-#
-# Pin controllers
-#
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-# CONFIG_PINCTRL_CAPRI is not set
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX6Q=y
-CONFIG_PINCTRL_IMX6SL=y
-# CONFIG_PINCTRL_MSM8X74 is not set
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_OF_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC=y
-
-#
-# Memory mapped GPIO drivers:
-#
-# CONFIG_GPIO_GENERIC_PLATFORM is not set
-# CONFIG_GPIO_EM is not set
-CONFIG_GPIO_MXC=y
-# CONFIG_GPIO_RCAR is not set
-# CONFIG_GPIO_SCH311X is not set
-# CONFIG_GPIO_TS5500 is not set
-# CONFIG_GPIO_VX855 is not set
-# CONFIG_GPIO_GRGPIO is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X_IRQ is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_SX150X is not set
-# CONFIG_GPIO_ADP5588 is not set
-# CONFIG_GPIO_ADNP is not set
-
-#
-# PCI GPIO expanders:
-#
-# CONFIG_GPIO_BT8XX is not set
-# CONFIG_GPIO_AMD8111 is not set
-# CONFIG_GPIO_ML_IOH is not set
-# CONFIG_GPIO_RDC321X is not set
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_74X164 is not set
-
-#
-# AC97 GPIO expanders:
-#
-
-#
-# LPC GPIO expanders:
-#
-
-#
-# MODULbus GPIO expanders:
-#
-# CONFIG_GPIO_BCM_KONA is not set
-
-#
-# USB GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_TEST_POWER is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2781 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_SBS is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_CHARGER_ISP1704 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_LP8727 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_CHARGER_MANAGER is not set
-# CONFIG_CHARGER_BQ2415X is not set
-# CONFIG_CHARGER_BQ24190 is not set
-# CONFIG_CHARGER_BQ24735 is not set
-# CONFIG_CHARGER_SMB347 is not set
-# CONFIG_IMX6_USB_CHARGER is not set
-# CONFIG_POWER_RESET is not set
-# CONFIG_POWER_RESET_RESTART is not set
-# CONFIG_POWER_AVS is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7314 is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7310 is not set
-# CONFIG_SENSORS_ADT7410 is not set
-# CONFIG_SENSORS_ADT7411 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ASC7621 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS620 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_G762 is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_GPIO_FAN is not set
-# CONFIG_SENSORS_HIH6130 is not set
-# CONFIG_SENSORS_HTU21 is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_JC42 is not set
-# CONFIG_SENSORS_LINEAGE is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM73 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4151 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LTC4261 is not set
-# CONFIG_SENSORS_LM95234 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_LM95245 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX16065 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX1668 is not set
-# CONFIG_SENSORS_MAX17135 is not set
-# CONFIG_SENSORS_MAX197 is not set
-# CONFIG_SENSORS_MAX6639 is not set
-# CONFIG_SENSORS_MAX6642 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_MAX6697 is not set
-# CONFIG_SENSORS_MCP3021 is not set
-# CONFIG_SENSORS_NCT6775 is not set
-# CONFIG_SENSORS_NTC_THERMISTOR is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_PMBUS is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_SHT21 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMM665 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_EMC1403 is not set
-# CONFIG_SENSORS_EMC2103 is not set
-# CONFIG_SENSORS_EMC6W201 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SCH56XX_COMMON is not set
-# CONFIG_SENSORS_SCH5627 is not set
-# CONFIG_SENSORS_SCH5636 is not set
-# CONFIG_SENSORS_ADS1000 is not set
-# CONFIG_SENSORS_ADS1015 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_ADS7871 is not set
-# CONFIG_SENSORS_AMC6821 is not set
-# CONFIG_SENSORS_INA209 is not set
-# CONFIG_SENSORS_INA2XX is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP102 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83795 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_SENSORS_MAG3110=y
-CONFIG_MXC_MMA8451=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_USER_SPACE is not set
-CONFIG_CPU_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_IMX_THERMAL=y
-CONFIG_DEVICE_THERMAL=y
-
-#
-# Texas Instruments thermal drivers
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_CORE is not set
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_GPIO_WATCHDOG is not set
-# CONFIG_DW_WATCHDOG is not set
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_IMX2_WDT=y
-# CONFIG_ALIM7101_WDT is not set
-# CONFIG_I6300ESB_WDT is not set
-# CONFIG_MEN_A21_WDT is not set
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-CONFIG_BCMA_POSSIBLE=y
-
-#
-# Broadcom specific AMBA
-#
-# CONFIG_BCMA is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_CROS_EC is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_DA9052_SPI is not set
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-# CONFIG_MFD_DA9063 is not set
-CONFIG_MFD_MXC_HDMI=y
-# CONFIG_MFD_MXC_HDMI_ANDROID is not set
-# CONFIG_MFD_MC13XXX_SPI is not set
-# CONFIG_MFD_MC13XXX_I2C is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_LPC_ICH is not set
-# CONFIG_LPC_SCH is not set
-# CONFIG_MFD_JANZ_CMODIO is not set
-# CONFIG_MFD_KEMPLD is not set
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX17135 is not set
-# CONFIG_MFD_MAX14577 is not set
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-# CONFIG_MFD_MAX77823 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_VIPERBOARD is not set
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_RDC321X is not set
-# CONFIG_MFD_RTSX_PCI is not set
-# CONFIG_MFD_RC5T583 is not set
-# CONFIG_MFD_SEC_CORE is not set
-# CONFIG_MFD_SI476X_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_SMSC is not set
-# CONFIG_ABX500_CORE is not set
-# CONFIG_MFD_STMPE is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_TI_AM335X_TSCADC is not set
-# CONFIG_MFD_LP3943 is not set
-# CONFIG_MFD_LP8788 is not set
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_TPS65912 is not set
-# CONFIG_MFD_TPS65912_I2C is not set
-# CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_MFD_TPS80031 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_LM3533 is not set
-# CONFIG_MFD_TIMBERDALE is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_VX855 is not set
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_ARIZONA_SPI is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
-# CONFIG_VEXPRESS_CONFIG is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_ACT8865 is not set
-# CONFIG_REGULATOR_AD5398 is not set
-CONFIG_REGULATOR_ANATOP=y
-# CONFIG_REGULATOR_DA9210 is not set
-# CONFIG_REGULATOR_FAN53555 is not set
-# CONFIG_REGULATOR_GPIO is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_LP872X is not set
-# CONFIG_REGULATOR_LP8755 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_MAX8973 is not set
-# CONFIG_REGULATOR_PFUZE100 is not set
-# CONFIG_REGULATOR_TPS51632 is not set
-# CONFIG_REGULATOR_TPS62360 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
-# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
-# CONFIG_MEDIA_RADIO_SUPPORT is not set
-# CONFIG_MEDIA_RC_SUPPORT is not set
-# CONFIG_MEDIA_CONTROLLER is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_CORE=y
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-# CONFIG_TTPCI_EEPROM is not set
-
-#
-# Media drivers
-#
-# CONFIG_MEDIA_USB_SUPPORT is not set
-# CONFIG_MEDIA_PCI_SUPPORT is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_CAFE_CCIC is not set
-# CONFIG_VIDEO_TIMBERDALE is not set
-CONFIG_VIDEO_MXC_OUTPUT=y
-CONFIG_VIDEO_MXC_CAPTURE=m
-CONFIG_VIDEO_V4L2_MXC_INT_DEVICE=m
-
-#
-# MXC Camera/V4L2 PRP Features support
-#
-CONFIG_VIDEO_MXC_IPU_CAMERA=y
-CONFIG_MXC_CAMERA_OV5640=m
-CONFIG_MXC_CAMERA_OV5642=m
-CONFIG_MXC_CAMERA_OV5640_MIPI=m
-# CONFIG_MXC_VIDEO_GS2971 is not set
-# CONFIG_MXC_HDMI_CSI2_TC358743 is not set
-CONFIG_MXC_TVIN_ADV7180=m
-CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
-CONFIG_MXC_IPU_PRP_ENC=m
-CONFIG_MXC_IPU_CSI_ENC=m
-CONFIG_VIDEO_MXC_IPU_OUTPUT=y
-# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
-CONFIG_VIDEO_MXC_CSI_CAMERA=m
-# CONFIG_MXC_CAMERA_SUBDEV_OV5640 is not set
-# CONFIG_MXC_CAMERA_SUBDEV_OV5642 is not set
-# CONFIG_MXC_VADC is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_VIDEO_RCAR_VIN is not set
-# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-# CONFIG_V4L_TEST_DRIVERS is not set
-
-#
-# Supported MMC/SDIO adapters
-#
-# CONFIG_CYPRESS_FIRMWARE is not set
-
-#
-# Media ancillary drivers (tuners, sensors, i2c, frontends)
-#
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-
-#
-# Encoders, decoders, sensors and other helper chips
-#
-
-#
-# Audio decoders, processors and mixers
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_UDA1342 is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-# CONFIG_VIDEO_SONY_BTF_MPX is not set
-
-#
-# RDS decoders
-#
-# CONFIG_VIDEO_SAA6588 is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_BT819 is not set
-# CONFIG_VIDEO_BT856 is not set
-# CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_KS0127 is not set
-# CONFIG_VIDEO_ML86V7667 is not set
-# CONFIG_VIDEO_SAA7110 is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA7191 is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_TVP7002 is not set
-# CONFIG_VIDEO_TW2804 is not set
-# CONFIG_VIDEO_TW9903 is not set
-# CONFIG_VIDEO_TW9906 is not set
-# CONFIG_VIDEO_VPX3220 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-# CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_ADV7170 is not set
-# CONFIG_VIDEO_ADV7175 is not set
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_AK881X is not set
-# CONFIG_VIDEO_THS8200 is not set
-
-#
-# Camera sensor devices
-#
-# CONFIG_VIDEO_OV7640 is not set
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_VS6624 is not set
-# CONFIG_VIDEO_MT9V011 is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-
-#
-# Flash devices
-#
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-
-#
-# Audio/Video compression chips
-#
-# CONFIG_VIDEO_SAA6752HS is not set
-
-#
-# Miscellaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-# CONFIG_VIDEO_M52790 is not set
-
-#
-# Sensors used on soc_camera driver
-#
-
-#
-# soc_camera sensor drivers
-#
-# CONFIG_SOC_CAMERA_IMX074 is not set
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-# CONFIG_SOC_CAMERA_MT9M111 is not set
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-
-#
-# Customise DVB Frontends
-#
-# CONFIG_DVB_AU8522_V4L is not set
-# CONFIG_DVB_TUNER_DIB0070 is not set
-# CONFIG_DVB_TUNER_DIB0090 is not set
-
-#
-# Tools to develop new frontends
-#
-# CONFIG_DVB_DUMMY_FE is not set
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_DRM=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-# CONFIG_DRM_RADEON is not set
-# CONFIG_DRM_NOUVEAU is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_DRM_VIVANTE=y
-# CONFIG_DRM_EXYNOS is not set
-# CONFIG_DRM_VMWGFX is not set
-# CONFIG_DRM_UDL is not set
-# CONFIG_DRM_AST is not set
-# CONFIG_DRM_MGAG200 is not set
-# CONFIG_DRM_CIRRUS_QEMU is not set
-# CONFIG_DRM_ARMADA is not set
-# CONFIG_DRM_RCAR_DU is not set
-# CONFIG_DRM_SHMOBILE is not set
-# CONFIG_DRM_TILCDC is not set
-# CONFIG_DRM_QXL is not set
-# CONFIG_DRM_BOCHS is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_DVI_TFP410 is not set
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_IMX is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_TMIO is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_GOLDFISH is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-# CONFIG_FB_AUO_K190X is not set
-CONFIG_FB_MXS=y
-# CONFIG_FB_SIMPLE is not set
-# CONFIG_EXYNOS_VIDEO is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_L4F00242T03=y
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI922X is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-CONFIG_LCD_PLATFORM=y
-# CONFIG_LCD_S6E63M0 is not set
-# CONFIG_LCD_LD9040 is not set
-# CONFIG_LCD_AMS369FG06 is not set
-# CONFIG_LCD_LMS501KF03 is not set
-# CONFIG_LCD_HX8357 is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_BACKLIGHT_ADP8860 is not set
-# CONFIG_BACKLIGHT_ADP8870 is not set
-# CONFIG_BACKLIGHT_LM3630A is not set
-# CONFIG_BACKLIGHT_LM3639 is not set
-# CONFIG_BACKLIGHT_LP855X is not set
-# CONFIG_BACKLIGHT_GPIO is not set
-# CONFIG_BACKLIGHT_LV5207LP is not set
-# CONFIG_BACKLIGHT_BD6107 is not set
-CONFIG_FB_MXC=y
-CONFIG_FB_MXC_SYNC_PANEL=y
-CONFIG_FB_MXC_LCDIF=y
-# CONFIG_FB_MXC_TVOUT_ADV739X is not set
-CONFIG_FB_MXC_LDB=y
-CONFIG_FB_MXC_MIPI_DSI=y
-CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
-CONFIG_FB_MXC_HDMI=y
-CONFIG_FB_MXC_EDID=y
-# CONFIG_FB_MXC_EINK_PANEL is not set
-# CONFIG_FB_MXS_SII902X is not set
-# CONFIG_FB_MXC_DCIC is not set
-# CONFIG_HANNSTAR_CABC is not set
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_FB_SSD1307 is not set
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_PCI=y
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AW2 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_OXYGEN is not set
-# CONFIG_SND_CS4281 is not set
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_CS5535AUDIO is not set
-# CONFIG_SND_CTXFI is not set
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-# CONFIG_SND_INDIGOIOX is not set
-# CONFIG_SND_INDIGODJX is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-# CONFIG_SND_FM801 is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_LOLA is not set
-# CONFIG_SND_LX6464ES is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VIRTUOSO is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-# CONFIG_SND_ATMEL_SOC is not set
-# CONFIG_SND_DESIGNWARE_I2S is not set
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=y
-CONFIG_SND_SOC_FSL_SAI=y
-CONFIG_SND_SOC_FSL_SSI=y
-# CONFIG_SND_SOC_FSL_SPDIF is not set
-# CONFIG_SND_SOC_FSL_ESAI is not set
-CONFIG_SND_SOC_FSL_HDMI=y
-CONFIG_SND_SOC_IMX_PCM_DMA=y
-CONFIG_SND_SOC_IMX_AUDMUX=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_SOC_IMX_HDMI_DMA=y
-
-#
-# SoC Audio support for Freescale i.MX boards:
-#
-# CONFIG_SND_SOC_IMX_CS42888 is not set
-# CONFIG_SND_SOC_IMX_WM8962 is not set
-CONFIG_SND_SOC_IMX_SGTL5000=y
-# CONFIG_SND_SOC_IMX_MQS is not set
-# CONFIG_SND_SOC_IMX_WM5102 is not set
-# CONFIG_SND_SOC_IMX_SPDIF is not set
-CONFIG_SND_SOC_IMX_HDMI=y
-# CONFIG_SND_SOC_IMX_SI476X is not set
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_CS42XX8_I2C is not set
-CONFIG_SND_SOC_HDMI_CODEC=y
-CONFIG_SND_SOC_SGTL5000=y
-# CONFIG_SND_SIMPLE_CARD is not set
-# CONFIG_SOUND_PRIME is not set
-
-#
-# HID support
-#
-CONFIG_HID=y
-# CONFIG_HID_BATTERY_STRENGTH is not set
-# CONFIG_HIDRAW is not set
-# CONFIG_UHID is not set
-CONFIG_HID_GENERIC=y
-
-#
-# Special HID drivers
-#
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_ACRUX is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_APPLEIR is not set
-# CONFIG_HID_AUREAL is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_PRODIKEYS is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EMS_FF is not set
-# CONFIG_HID_ELECOM is not set
-# CONFIG_HID_ELO is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_HOLTEK is not set
-# CONFIG_HID_HUION is not set
-# CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_UCLOGIC is not set
-# CONFIG_HID_WALTOP is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_ICADE is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LCPOWER is not set
-# CONFIG_HID_LENOVO_TPKBD is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MAGICMOUSE is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_MULTITOUCH is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_PICOLCD is not set
-# CONFIG_HID_PRIMAX is not set
-# CONFIG_HID_ROCCAT is not set
-# CONFIG_HID_SAITEK is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SPEEDLINK is not set
-# CONFIG_HID_STEELSERIES is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TIVO is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THINGM is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_WACOM is not set
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_XINMO is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-# CONFIG_HID_SENSOR_HUB is not set
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# I2C HID support
-#
-# CONFIG_I2C_HID is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_OTG_FSM is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_XHCI_HCD is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=y
-# CONFIG_USB_EHCI_MXC is not set
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-# CONFIG_USB_FUSBH200_HCD is not set
-# CONFIG_USB_FOTG210_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_IMX21_HCD is not set
-# CONFIG_USB_HCD_TEST_MODE is not set
-# CONFIG_USB_RENESAS_USBHS is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_REALTEK is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_STORAGE_ENE_UB6250 is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_DWC3 is not set
-# CONFIG_USB_DWC2 is not set
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-# CONFIG_USB_CHIPIDEA_DEBUG is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_SIMPLE is not set
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-CONFIG_USB_SERIAL_CP210X=y
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_F81232 is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-CONFIG_USB_SERIAL_KEYSPAN=y
-# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_METRO is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MXUPORT is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-CONFIG_USB_SERIAL_PL2303=y
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QCAUX is not set
-CONFIG_USB_SERIAL_QUALCOMM=y
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-CONFIG_USB_SERIAL_WWAN=y
-CONFIG_USB_SERIAL_OPTION=y
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_XSENS_MT is not set
-# CONFIG_USB_SERIAL_WISHBONE is not set
-# CONFIG_USB_SERIAL_ZTE is not set
-# CONFIG_USB_SERIAL_SSU100 is not set
-# CONFIG_USB_SERIAL_QT2 is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_EHSET_TEST_FIXTURE is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_YUREX is not set
-CONFIG_USB_EZUSB_FX2=y
-# CONFIG_USB_HSIC_USB3503 is not set
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-# CONFIG_NOP_USB_XCEIV is not set
-# CONFIG_AM335X_PHY_USB is not set
-# CONFIG_SAMSUNG_USB2PHY is not set
-# CONFIG_SAMSUNG_USB3PHY is not set
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ISP1301 is not set
-CONFIG_USB_MXS_PHY=y
-# CONFIG_USB_RCAR_PHY is not set
-# CONFIG_USB_ULPI is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FSL_USB2 is not set
-# CONFIG_USB_FUSB300 is not set
-# CONFIG_USB_FOTG210_UDC is not set
-# CONFIG_USB_GR_UDC is not set
-# CONFIG_USB_R8A66597 is not set
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_S3C_HSOTG is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-# CONFIG_USB_M66592 is not set
-# CONFIG_USB_AMD5536UDC is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_EG20T is not set
-# CONFIG_USB_DUMMY_HCD is not set
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-# CONFIG_USB_CONFIGFS is not set
-CONFIG_USB_ZERO=m
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_GADGETFS is not set
-CONFIG_USB_FUNCTIONFS=m
-# CONFIG_USB_FUNCTIONFS_ETH is not set
-# CONFIG_USB_FUNCTIONFS_RNDIS is not set
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-# CONFIG_FSL_UTP is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_ACM_MS is not set
-# CONFIG_USB_G_MULTI is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_WEBCAM is not set
-# CONFIG_UWB is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MMC_CLKGATE is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_SDHCI_OF_ARASAN is not set
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-# CONFIG_MMC_SDHCI_PXAV3 is not set
-# CONFIG_MMC_SDHCI_PXAV2 is not set
-# CONFIG_MMC_MXC is not set
-# CONFIG_MMC_TIFM_SD is not set
-# CONFIG_MMC_CB710 is not set
-# CONFIG_MMC_VIA_SDMMC is not set
-# CONFIG_MMC_DW is not set
-# CONFIG_MMC_VUB300 is not set
-# CONFIG_MMC_USHC is not set
-# CONFIG_MEMSTICK is not set
-
-#
-# MXC support drivers
-#
-CONFIG_MXC_IPU=y
-
-#
-# MXC Vivante GPU support
-#
-CONFIG_MXC_GPU_VIV=y
-CONFIG_MXC_IPU_V3=y
-
-#
-# MXC VPU(Video Processing Unit) support
-#
-CONFIG_MXC_VPU=y
-# CONFIG_MXC_VPU_DEBUG is not set
-# CONFIG_MX6_VPU_352M is not set
-
-#
-# MXC HDMI CEC (Consumer Electronics Control) support
-#
-# CONFIG_MXC_HDMI_CEC is not set
-
-#
-# MXC MIPI Support
-#
-CONFIG_MXC_MIPI_CSI2=y
-
-#
-# MXC Media Local Bus Driver
-#
-# CONFIG_MXC_MLB150 is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_LM3642 is not set
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_LP5562 is not set
-# CONFIG_LEDS_LP8501 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_PCA963X is not set
-# CONFIG_LEDS_PCA9685 is not set
-# CONFIG_LEDS_DAC124S085 is not set
-CONFIG_LEDS_PWM=y
-# CONFIG_LEDS_REGULATOR is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_TCA6507 is not set
-# CONFIG_LEDS_LM355x is not set
-# CONFIG_LEDS_OT200 is not set
-# CONFIG_LEDS_BLINKM is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_ONESHOT is not set
-# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_CPU is not set
-# CONFIG_LEDS_TRIGGER_GPIO is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
-# CONFIG_LEDS_TRIGGER_CAMERA is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_INFINIBAND is not set
-# CONFIG_EDAC is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_HYM8563 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_ISL1208=y
-# CONFIG_RTC_DRV_ISL12022 is not set
-# CONFIG_RTC_DRV_ISL12057 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF2127 is not set
-# CONFIG_RTC_DRV_PCF8523 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3029C2 is not set
-# CONFIG_RTC_DRV_RV4162 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-# CONFIG_RTC_DRV_RX4581 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-# CONFIG_RTC_DRV_DS2404 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MXC is not set
-CONFIG_RTC_DRV_SNVS=y
-# CONFIG_RTC_DRV_MOXART is not set
-
-#
-# HID Sensor RTC drivers
-#
-# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-# CONFIG_DW_DMAC_CORE is not set
-# CONFIG_DW_DMAC is not set
-# CONFIG_DW_DMAC_PCI is not set
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_PXP_V2=y
-CONFIG_MXC_PXP_CLIENT_DEVICE=y
-# CONFIG_TIMB_DMA is not set
-CONFIG_IMX_SDMA=y
-# CONFIG_IMX_DMA is not set
-# CONFIG_MXS_DMA is not set
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-
-#
-# DMA Clients
-#
-# CONFIG_ASYNC_TX_DMA is not set
-# CONFIG_DMATEST is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-# CONFIG_VIRT_DRIVERS is not set
-
-#
-# Virtio drivers
-#
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_MMIO is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_STAGING=y
-# CONFIG_DRM_ANX78XX is not set
-# CONFIG_ET131X is not set
-# CONFIG_USBIP_CORE is not set
-# CONFIG_W35UND is not set
-# CONFIG_PRISM2_USB is not set
-# CONFIG_ECHO is not set
-# CONFIG_COMEDI is not set
-# CONFIG_R8187SE is not set
-# CONFIG_RTL8192U is not set
-# CONFIG_RTLLIB is not set
-# CONFIG_R8712U is not set
-# CONFIG_R8188EU is not set
-# CONFIG_R8821AE is not set
-# CONFIG_RTS5139 is not set
-# CONFIG_RTS5208 is not set
-# CONFIG_TRANZPORT is not set
-# CONFIG_IDE_PHISON is not set
-# CONFIG_LINE6_USB is not set
-# CONFIG_USB_SERIAL_QUATECH2 is not set
-# CONFIG_VT6655 is not set
-# CONFIG_VT6656 is not set
-# CONFIG_DX_SEP is not set
-# CONFIG_FB_SM7XX is not set
-# CONFIG_CRYSTALHD is not set
-# CONFIG_FB_XGI is not set
-# CONFIG_USB_ENESTORAGE is not set
-# CONFIG_BCM_WIMAX is not set
-# CONFIG_FT1000 is not set
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
-# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-# CONFIG_STAGING_MEDIA is not set
-
-#
-# Android
-#
-# CONFIG_ANDROID is not set
-# CONFIG_USB_WPAN_HCD is not set
-# CONFIG_WIMAX_GDM72XX is not set
-# CONFIG_LTE_GDM724X is not set
-CONFIG_NET_VENDOR_SILICOM=y
-# CONFIG_SBYPASS is not set
-# CONFIG_BPCTL is not set
-# CONFIG_CED1401 is not set
-# CONFIG_DRM_IMX is not set
-# CONFIG_DGRP is not set
-# CONFIG_LUSTRE_FS is not set
-# CONFIG_XILLYBUS is not set
-# CONFIG_DGNC is not set
-# CONFIG_DGAP is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-
-#
-# Common Clock Framework
-#
-# CONFIG_COMMON_CLK_SI5351 is not set
-# CONFIG_COMMON_CLK_SI570 is not set
-# CONFIG_COMMON_CLK_QCOM is not set
-
-#
-# Hardware Spinlock drivers
-#
-CONFIG_CLKSRC_OF=y
-CONFIG_CLKSRC_MMIO=y
-# CONFIG_MAILBOX is not set
-# CONFIG_IOMMU_SUPPORT is not set
-
-#
-# Remoteproc drivers
-#
-# CONFIG_STE_MODEM_RPROC is not set
-
-#
-# Rpmsg drivers
-#
-# CONFIG_PM_DEVFREQ is not set
-# CONFIG_EXTCON is not set
-# CONFIG_MEMORY is not set
-# CONFIG_IIO is not set
-# CONFIG_VME_BUS is not set
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_PWM_IMX=y
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_GPIO=y
-# CONFIG_FMC is not set
-
-#
-# PHY Subsystem
-#
-# CONFIG_GENERIC_PHY is not set
-# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
-# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
-# CONFIG_POWERCAP is not set
-# CONFIG_BATTERY_SAMSUNG is not set
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_FANOTIFY is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-# CONFIG_CUSE is not set
-# CONFIG_OVERLAYFS_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=m
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_LOGFS is not set
-# CONFIG_CRAMFS is not set
-CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-# CONFIG_SQUASHFS_DECOMP_MULTI is not set
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-# CONFIG_SQUASHFS_XATTR is not set
-CONFIG_SQUASHFS_ZLIB=y
-# CONFIG_SQUASHFS_LZO is not set
-# CONFIG_SQUASHFS_XZ is not set
-# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_QNX6FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_PSTORE is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_F2FS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V2=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-# CONFIG_NFS_SWAP is not set
-# CONFIG_NFS_V4_1 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_DEBUG is not set
-# CONFIG_CEPH_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_MAC_ROMAN is not set
-# CONFIG_NLS_MAC_CELTIC is not set
-# CONFIG_NLS_MAC_CENTEURO is not set
-# CONFIG_NLS_MAC_CROATIAN is not set
-# CONFIG_NLS_MAC_CYRILLIC is not set
-# CONFIG_NLS_MAC_GAELIC is not set
-# CONFIG_NLS_MAC_GREEK is not set
-# CONFIG_NLS_MAC_ICELAND is not set
-# CONFIG_NLS_MAC_INUIT is not set
-# CONFIG_NLS_MAC_ROMANIAN is not set
-# CONFIG_NLS_MAC_TURKISH is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_READABLE_ASM is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
-CONFIG_DEBUG_KERNEL=y
-
-#
-# Memory Debugging
-#
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Lockups and Hangs
-#
-# CONFIG_LOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-# CONFIG_SPARSE_RCU_POINTER is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_CPU_STALL_INFO is not set
-# CONFIG_RCU_TRACE is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-
-#
-# Runtime Testing
-#
-# CONFIG_LKDTM is not set
-# CONFIG_TEST_LIST_SORT is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_RBTREE_TEST is not set
-# CONFIG_INTERVAL_TREE_TEST is not set
-# CONFIG_PERCPU_TEST is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_TEST_MODULE is not set
-# CONFIG_TEST_USER_COPY is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_ARM_PTDUMP is not set
-# CONFIG_STRICT_DEVMEM is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_IMX6Q_UART=y
-# CONFIG_DEBUG_IMX6SL_UART is not set
-# CONFIG_DEBUG_ICEDCC is not set
-# CONFIG_DEBUG_SEMIHOSTING is not set
-# CONFIG_DEBUG_LL_UART_8250 is not set
-# CONFIG_DEBUG_LL_UART_PL01X is not set
-CONFIG_DEBUG_IMX_UART_PORT=1
-CONFIG_DEBUG_LL_INCLUDE="debug/imx.S"
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_UART_8250 is not set
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_EARLY_PRINTK=y
-# CONFIG_PID_IN_CONTEXTIDR is not set
-# CONFIG_DEBUG_SET_MODULE_RONX is not set
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_PERSISTENT_KEYRINGS is not set
-# CONFIG_BIG_KEYS is not set
-# CONFIG_ENCRYPTED_KEYS is not set
-# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_NULL=y
-# CONFIG_CRYPTO_PCRYPT is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=y
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_SEQIV=y
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=y
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_CMAC is not set
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32 is not set
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=y
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA1_ARM is not set
-CONFIG_CRYPTO_SHA256=m
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_AES_ARM is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_LZ4 is not set
-# CONFIG_CRYPTO_LZ4HC is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_USER_API_HASH is not set
-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
-CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-# CONFIG_CRYPTO_DEV_SAHARA is not set
-# CONFIG_ASYMMETRIC_KEY_TYPE is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IO=y
-CONFIG_STMP_DEVICE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-# CONFIG_CRC8 is not set
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_XZ_DEC is not set
-# CONFIG_XZ_DEC_BCJ is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_NLATTR=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_AVERAGE=y
-# CONFIG_CORDIC is not set
-# CONFIG_DDR is not set
-CONFIG_OID_REGISTRY=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_VIRTUALIZATION is not set
diff --git a/tests/arm32/sabrelite/linux/nor_flash.list b/tests/arm32/sabrelite/linux/nor_flash.list
deleted file mode 100644
index 4bf19ff4..00000000
--- a/tests/arm32/sabrelite/linux/nor_flash.list
+++ /dev/null
@@ -1,5 +0,0 @@
-0x08000000 ./firmware.bin
-0x080FF000 ./cmdlist
-0x08100000 ./Image
-0x08FF0000 ./imx6q-nitrogen6x.dtb
-0x09000000 ./rootfs.img
diff --git a/tests/arm32/sabrelite/linux/skeleton.dtsi b/tests/arm32/sabrelite/linux/skeleton.dtsi
deleted file mode 100644
index b41d241d..00000000
--- a/tests/arm32/sabrelite/linux/skeleton.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value. The bootloader will typically populate the memory
- * node.
- */
-
-/ {

- #address-cells = <1>;
- #size-cells = <1>;

- chosen { };
- aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/tests/arm32/sabrelite/sabrelite.dts b/tests/arm32/sabrelite/sabrelite.dts
deleted file mode 100644
index 723c02e5..00000000
--- a/tests/arm32/sabrelite/sabrelite.dts

+++ /dev/null
@@ -1,427 +0,0 @@

-
-/dts-v1/;
-
-/ {
- model = "arm,vexpress,v2p-ca9";
- device_type = "guest";
- psci_version = <2>;
-
- aliases {
- mem0 = &MEM0;
- net0 = &NET0;
- };
-
- vcpus {
- vcpu0 {
- device_type = "vcpu";
- compatible = "armv7a,cortex-a9";
- start_pc = <0x11000000>;
- };
-
- /* vcpu1 { */
- /* device_type = "vcpu"; */
- /* compatible = "armv7a,cortex-a9"; */
- /* start_pc = <0xC1000000>; */
- /* }; */
- };
-
- aspace {
- guest_irq_count = <2048>;
-
- MEM0: mem0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x10000000>;
- physical_size = <0x00000000>; /* Override this before guest creation */
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_ram";
- };
-
- gpu_3d {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x00130000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpu_2d {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x00134000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpu_vg {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02204000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- ocram {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x00900000>;
- physical_size = <0x00040000>;
- align_order = <12>; /* Align alloced memory to 4K */
- device_type = "alloced_ram";
- };
-
- ocram-alias1 {
- manifest_type = "alias";
- address_type = "memory";
- guest_physical_addr = <0x00940000>;
- alias_physical_addr = <0x00900000>;
- physical_size = <0x00040000>;
- device_type = "ram";
- };
-
- ocram-alias2 {
- manifest_type = "alias";
- address_type = "memory";
- guest_physical_addr = <0x00980000>;
- alias_physical_addr = <0x00900000>;
- physical_size = <0x00040000>;
- device_type = "ram";
- };
-
- ocram-alias3 {
- manifest_type = "alias";
- address_type = "memory";
- guest_physical_addr = <0x009C0000>;
- alias_physical_addr = <0x00900000>;
- physical_size = <0x00040000>;
- device_type = "ram";
- };
-
- ipu1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02400000>;
- physical_size = <0x00400000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- ipu2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02A00000>;
- physical_size = <0x00400000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- iomux {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020e0000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- dma_apbh {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x00110000>;
- physical_size = <0x00002000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- priv0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x00A00000>;
- physical_size = <0x2000>;
- device_type = "misc";
- compatible = "arm,a9mpcore";
- num_irq = <192>;
- timer_irq = <29 30>;
- parent_irq = <6>;
- };
-
- pwm1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02080000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- pwm2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02084000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- pwm3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02088000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- pwm4 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x0208C000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- l2x0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x00A02000>;
- physical_size = <0x1000>;
- device_type = "cache";
- compatible = "corelink,l2c-310";
- };
-
- wdog1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020BC000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- wdog2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020C0000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- uart0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x021e8000>;
- physical_size = <0x4000>;
- device_type = "serial";
- compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
- interrupts = <59>;
- };
-
- spba {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x0203c000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- sdma {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020ec000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- asrc {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02034000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- usdhc3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02198000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- vpu {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02040000>;
- physical_size = <0x0003c000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- /* /\* Emulate EPIT with a SP804 for now*\/ */
- /* timer0_1_legacy { */
- /* manifest_type = "virtual"; */
- /* address_type = "memory"; */
- /* guest_physical_addr = <0x020D0000>; */
- /* physical_size = <0x1000>; */
- /* device_type = "timer"; */
- /* compatible = "primecell,sp804"; */
- /* interrupts = <34>; */
- /* }; */
-
- /* epit1 { */
- /* manifest_type = "virtual"; */
- /* address_type = "memory"; */
- /* guest_physical_addr = <0x020d0000>; */
- /* physical_size = <0x1000>; */
- /* device_type = "misc"; */
- /* compatible = "zero"; */
- /* }; */
-
- /* timer2_3_legacy { */
- /* manifest_type = "virtual"; */
- /* address_type = "memory"; */
- /* guest_physical_addr = <0x10012000>; */
- /* physical_size = <0x1000>; */
- /* device_type = "timer"; */
- /* compatible = "primecell,sp804"; */
- /* interrupts = <35>; */
- /* }; */
-
- vminfo {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "sys";
- compatible = "vminfo-0.1";
- guest_physical_addr = <0x0220b000>;
- physical_size = <0x1000>;
- ram0_base = <0x10000000>;
- };
-
- NET0: virtio-net0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <1>;
- guest_physical_addr = <0x0220c000>;
- physical_size = <0x1000>;
- switch = ""; /* Override this before guest creation */
- interrupts = <42>;
- };
-
- gpio1: gpio@0209c000 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x0209c000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpio3: gpio@020a4000 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020a4000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpio7: gpio@020b4000 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020b4000>;
- physical_size = <0x00004000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- virtio-con0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <3>;
- guest_physical_addr = <0x0220d000>;
- physical_size = <0x1000>;
- interrupts = <86>;
- };
-
- nor_flash0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x08000000>;
- physical_size = <0x02000000>;
- device_type = "alloced_rom";
- align_order = <21>; /* Align alloced memory to 2MB */
- };
-
- /* Use a reserved i.MX6 area to emulate VExpress-A9 sysctl */
- sysctl {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020F0000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "vexpress,a9";
- mux_in_irq = <1200 1201>;
- mux_out_irq = <1202>;
- };
-
- ccm {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020c4000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "fsl,imx6q-ccm";
- };
-
- anatop {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020c8000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "fsl,imx6q-anatop";
- };
-
- src {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020d8000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpc: gpc@020dc000 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x020dc000>;
- physical_size = <0x4000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpt: gpt@02098000 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x02098000>;
- physical_size = <0x4000>;
- device_type = "timer";
- compatible = "fsl,imx6q-gpt";
- clock-frequency = <32000>;
- interrupts = <87>;
- };
- };
-};
diff --git a/tests/arm32/versatilepb/README b/tests/arm32/versatilepb/README
deleted file mode 100644
index 16e9d373..00000000
--- a/tests/arm32/versatilepb/README
+++ /dev/null
@@ -1,33 +0,0 @@
- VersatilePB Guest
-
-This guest has ARM9 (Single Core ARMv5) CPU and various peripherals
-expected on a VersatileAB (i.e. Application Base) Board.
-
-We also have memory mapped VirtIO devices located at unused IO regions
-of the guest for providing VirtIO based paravirtualization.
-
-There are many reserved IO regions as per VersatilePB and VersatileAB
-User Guides. From these reserved IO regions, we will use the following
-IO regions for VirtIO:
-0x14000000–0x1FFFFFFF (192M) (Reserved for Logic Tile Expansion)
-
-The VirtIO devices also require a IRQ line per device for functioning. The
-VersatilePB guest has following unused or reserved IRQ lines:
-VIC: 20
-SIC: 42-52 (nested)
-SIC: 63 (nested)
-
-The memory map and irq of paravirt devices on VersatilePB guest is
-as follows:
-0x14000000–0x14000FFF (4K) (Guest/VM Info Device)
-
-
- VersatilePB Guest OSes
-
-We have tested following guest OSes for this guest:
-
- 1. basic - Basic firmware/bootloader
- 2. linux - Linux Kernel
-
-Please follow the README under specific guest OS directory for detailed
-steps to configure, compile and run.
diff --git a/tests/arm32/versatilepb/basic/Makefile b/tests/arm32/versatilepb/basic/Makefile
deleted file mode 100644
index c6fb9e56..00000000
--- a/tests/arm32/versatilepb/basic/Makefile

+++ /dev/null
@@ -1,55 +0,0 @@

-#/**
-# Copyright (c) 2012 Jean-Christophe Dubois.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile

-# @author Jean-Christophe Dubois (j...@tribudubois.net)

-# @brief toplevel makefile to build firmware
-# */
-
-# Determine the build directory
-top_dir=$(CURDIR)/../../../..
-ifdef O
- build_dir=$(shell readlink -f $(O))
-else
- build_dir=$(top_dir)/build
-endif
-ifdef I
- install_dir=$(shell readlink -f $(I))
-else
- install_dir=$(top_dir)/install
-endif
-
-obj_dir=$(build_dir)/tests/arm32/versatilepb/basic
-basic_dir=$(top_dir)/tests/common/basic
-arch_dir=$(top_dir)/tests/arm32/common/basic
-
-board_arch = v5
-board_text_start = 0x04000000
-board_objs = $(obj_dir)/arch_board.o \
- $(obj_dir)/pic/pl190.o \
- $(obj_dir)/timer/sp804.o \
- $(obj_dir)/serial/pl01x.o \
- $(obj_dir)/sys/vminfo.o
-
-board_cppflags =
-board_cflags =
-board_asflags =
-board_ldflags =
-
-# Include common arch makefile for basic firmware
-include $(arch_dir)/Makefile.inc
diff --git a/tests/arm32/versatilepb/basic/README b/tests/arm32/versatilepb/basic/README
deleted file mode 100644
index 30158f07..00000000
--- a/tests/arm32/versatilepb/basic/README
+++ /dev/null
@@ -1,70 +0,0 @@
- Basic Firmware on VersatilePB Guest
-
-The basic firmware currently sets up PIC, Timer, and UART and emulates
-a dummy terminal which reponds to various commands. It also includes an
-extensive MMU test suite and dhrystone benchmark.
-
-Hardware features tested by Basic Firmware:
- - Sensitive non-priviledged instructions
- - Virtual IRQs
- - Generic Interrupt Controller (PL190)
- - PrimeCell Dual-Mode Timer (SP804)
- - Serial Port (PL011)
-
-Please follow the steps below to build & run Basic Firmware on VersatilePB
-Guest with Xvisor running on QEMU VersatilePB Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v5 default settings]
- # make ARCH=arm generic-v5-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/versatilepb/basic
-
- [6. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/versatilepb
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/versatilepb-guest.dtb ./tests/arm32/versatilepb/versatilepb-guest.dts
- # cp -f ./build/tests/arm32/versatilepb/basic/firmware.bin.patched ./build/disk/images/arm32/versatilepb/firmware.bin
- # cp -f ./tests/arm32/versatilepb/basic/nor_flash.list ./build/disk/images/arm32/versatilepb/nor_flash.list
- # cp -f ./tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript ./build/disk/boot.xscript
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [7. Launch QEMU]
- # qemu-system-arm -M versatilepb -m 256M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/versatile-pb.dtb -initrd build/disk.img
-
- [8. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [9. Bind to virtual UART]
- XVisor# vserial bind guest0/uart0
-
- [10. Say 'hi' to Basic Firmware]
- [guest0/uart0] basic# hi
-
- [11. Say 'hello' to Basic Firmware]
- [guest0/uart0] basic# hello
-
- [12. Check various commands of Basic Firmware]
- [guest0/uart0] basic# help
-
- [13. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] basic#
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/versatilepb/basic/arch_board.c b/tests/arm32/versatilepb/basic/arch_board.c
deleted file mode 100644
index 92307fe9..00000000
--- a/tests/arm32/versatilepb/basic/arch_board.c
+++ /dev/null
@@ -1,266 +0,0 @@

-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_board.c

- * @author Jean-Christophe Dubois (j...@tribudubois.net)

- * @brief various platform specific functions
- */
-
-#include <arch_types.h>
-#include <arch_io.h>
-#include <arch_math.h>
-#include <arch_board.h>
-#include <arm_plat.h>
-#include <basic_string.h>
-#include <pic/pl190.h>
-#include <timer/sp804.h>
-#include <serial/pl01x.h>
-#include <sys/vminfo.h>
-
-void arch_board_reset(void)
-{
- arch_writel(0x101,
- (void *)(VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET));
-}
-
-void arch_board_init(void)
-{
- /* Unlock Lockable reigsters */
- arch_writel(VERSATILE_SYS_LOCKVAL,
- (void *)(VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET));
-}
-
-char *arch_board_name(void)
-{
- return "ARM VersatilePB";
-}
-
-physical_addr_t arch_board_ram_start(void)
-{
- return (physical_addr_t)vminfo_ram_base(VERSATILE_VMINFO_BASE, 0);
-}
-
-physical_size_t arch_board_ram_size(void)
-{
- return (physical_size_t)vminfo_ram_size(VERSATILE_VMINFO_BASE, 0);
-}
-
-void arch_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz)
-{
- basic_strcpy(cmdline, "root=/dev/ram rw earlyprintk "
- "earlycon=pl011,0x101f1000 console=ttyAMA0");
-}
-
-void arch_board_fdt_fixup(void *fdt_addr)

-{
- /* For now nothing to do here. */
-}

-
-physical_addr_t arch_board_autoexec_addr(void)
-{
- return (VERSATILE_FLASH_BASE + 0xFF000);
-}
-
-u32 arch_board_boot_delay(void)
-{
- return vminfo_boot_delay(VERSATILE_VMINFO_BASE);
-}
-
-u32 arch_board_iosection_count(void)
-{
- return 19;
-}
-
-physical_addr_t arch_board_iosection_addr(int num)
-{
- physical_addr_t ret = 0;
-
- switch (num) {
- case 0:
- ret = VERSATILE_SYS_BASE;

- break;
- case 1:

- ret = VERSATILE_VIC_BASE;

- break;
- case 2:

- ret = VERSATILE_VMINFO_BASE;

- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:

- case 8:
- case 9:
- case 10:
- case 11:
- case 12:

- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- ret = VERSATILE_FLASH_BASE + (num - 3) * 0x100000;
- break;
- default:
- while (1);
- break;
- }
-
- return ret;
-}
-
-#define NR_IRQS_VERSATILE 64
-
-u32 arch_board_pic_nr_irqs(void)
-{
- return NR_IRQS_VERSATILE;
-}
-
-int arch_board_pic_init(void)

-{
- int rc;
-
- /*

- * Initialize Vectored Interrupt Controller
- */
- rc = pl190_cpu_init(0, VERSATILE_VIC_BASE);

- if (rc) {
- return rc;
- }
-

- return 0;
-}
-
-u32 arch_board_pic_active_irq(void)
-{
- return pl190_active_irq(0);
-}
-
-int arch_board_pic_ack_irq(u32 irq)

-{
- return 0;
-}
-

-int arch_board_pic_eoi_irq(u32 irq)
-{
- return pl190_eoi_irq(0, irq);
-}
-
-int arch_board_pic_mask(u32 irq)
-{
- return pl190_mask(0, irq);
-}
-
-int arch_board_pic_unmask(u32 irq)
-{
- return pl190_unmask(0, irq);
-}
-
-void arch_board_timer_enable(void)
-{
- return sp804_enable();
-}
-
-void arch_board_timer_disable(void)
-{
- return sp804_disable();
-}
-
-u64 arch_board_timer_irqcount(void)
-{
- return sp804_irqcount();
-}
-
-u64 arch_board_timer_irqdelay(void)
-{
- return sp804_irqdelay();
-}
-
-u64 arch_board_timer_timestamp(void)
-{
- return sp804_timestamp();
-}
-
-void arch_board_timer_change_period(u32 usecs)
-{
- return sp804_change_period(usecs);
-}
-
-int arch_board_timer_init(u32 usecs)
-{
- u32 val, irq;
- u64 counter_mult, counter_shift, counter_mask;
-
- counter_mask = 0xFFFFFFFFULL;
- counter_shift = 20;
- counter_mult = ((u64)1000000) << counter_shift;
- counter_mult += (((u64)1000) >> 1);
- counter_mult = arch_udiv64(counter_mult, ((u64)1000));
-
- irq = INT_TIMERINT0_1;
-
- /* set clock frequency:
- * VERSATILE_REFCLK is 32KHz
- * VERSATILE_TIMCLK is 1MHz
- */
- val = arch_readl((void *)VERSATILE_SCTL_BASE) | (VERSATILE_TIMCLK << 1);
- arch_writel(val, (void *)VERSATILE_SCTL_BASE);
-
- return sp804_init(usecs, VERSATILE_TIMER0_1_BASE, irq,
- counter_mask, counter_mult, counter_shift);
-}
-
-#define VERSATILE_UART_BASE 0x101F1000
-#define VERSATILE_UART_TYPE PL01X_TYPE_1
-#define VERSATILE_UART_INCLK 24000000
-#define VERSATILE_UART_BAUD 115200
-
-int arch_board_serial_init(void)
-{
- pl01x_init(VERSATILE_UART_BASE,
- VERSATILE_UART_TYPE,
- VERSATILE_UART_BAUD,
- VERSATILE_UART_INCLK);

-
- return 0;
-}
-

-void arch_board_serial_putc(char ch)
-{
- if (ch == '\n') {
- pl01x_putc(VERSATILE_UART_BASE, VERSATILE_UART_TYPE, '\r');
- }
- pl01x_putc(VERSATILE_UART_BASE, VERSATILE_UART_TYPE, ch);
-}
-
-bool arch_board_serial_can_getc(void)
-{
- return pl01x_can_getc(VERSATILE_UART_BASE, VERSATILE_UART_TYPE);
-}
-
-char arch_board_serial_getc(void)
-{
- char ch = pl01x_getc(VERSATILE_UART_BASE, VERSATILE_UART_TYPE);
- if (ch == '\r') {
- ch = '\n';
- }
- arch_board_serial_putc(ch);
- return ch;
-}
diff --git a/tests/arm32/versatilepb/basic/arm_plat.h b/tests/arm32/versatilepb/basic/arm_plat.h
deleted file mode 100644
index 9323ee41..00000000
--- a/tests/arm32/versatilepb/basic/arm_plat.h

+++ /dev/null
@@ -1,426 +0,0 @@
-/**

- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file versatile_config.h

- * @author Jean-Christophe Dubois (j...@tribudubois.net)

- * @brief Versatile Platform Configuration Header
- *
- * This file is mostly a copy of the following file in linux source tree
- * arch/arm/mach-versatile/include/mach/platform.h
- */
-
-#ifndef VERSATILE_PLAT_H
-#define VERSATILE_PLAT_H 1
-
-/*
- * Memory definitions
- */
-#define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
-#define VERSATILE_BOOT_ROM_HI 0x30000000
-#define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */
-#define VERSATILE_BOOT_ROM_SIZE SZ_64M
-
-#define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */
-#define VERSATILE_SSRAM_SIZE SZ_2M
-
-#define VERSATILE_FLASH_BASE 0x34000000
-#define VERSATILE_FLASH_SIZE SZ_64M
-
-/*
- * SDRAM
- */
-#define VERSATILE_SDRAM_BASE 0x00000000
-
-/*
- * Logic expansion modules

- *
- */
-

-
-/* ------------------------------------------------------------------------
- * Versatile Registers
- * ------------------------------------------------------------------------
- *
- */
-#define VERSATILE_SYS_ID_OFFSET 0x00
-#define VERSATILE_SYS_SW_OFFSET 0x04
-#define VERSATILE_SYS_LED_OFFSET 0x08
-#define VERSATILE_SYS_OSC0_OFFSET 0x0C
-

-#if defined(CONFIG_ARCH_VERSATILE_PB)

-#define VERSATILE_SYS_OSC1_OFFSET 0x10
-#define VERSATILE_SYS_OSC2_OFFSET 0x14
-#define VERSATILE_SYS_OSC3_OFFSET 0x18
-#define VERSATILE_SYS_OSC4_OFFSET 0x1C

-#elif defined(CONFIG_MACH_VERSATILE_AB)
-#define VERSATILE_SYS_OSC1_OFFSET 0x1C
-#endif

-#define VERSATILE_SYS_BASE 0x10000000
-#define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
-#define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
-#define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
-#define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
-#define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
-
-#if defined(CONFIG_ARCH_VERSATILE_PB)
-#define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
-#define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
-#define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
-#endif
-
-#define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
-#define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
-#define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
-#define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
-#define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
-#define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
-#define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
-#define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
-#define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
-#define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
-#define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
-#define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET)
-#define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
-#define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-#define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
-#define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
-#define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
-#define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
-#define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
-#define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
-#define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
-#define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
-#define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
-#define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)

- * VERSATILE peripheral addresses
- */
-#define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */
-#define VERSATILE_I2C_BASE 0x10002000 /* I2C control */
-#define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */
-#define VERSATILE_AACI_BASE 0x10004000 /* Audio */
-#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
-#define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */
-#define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */
-#define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */
-#define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */
-#define VERSATILE_SCI1_BASE 0x1000A000
-#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
- /* 0x1000C000 - 0x1000CFFF = reserved */
-#define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */
-#define VERSATILE_USB_BASE 0x10020000 /* USB */
- /* 0x10030000 - 0x100FFFFF = reserved */
-#define VERSATILE_SMC_BASE 0x10100000 /* SMC */
-#define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */
-#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
-#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
-#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
-#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
- /* 0x10000000 - 0x100FFFFF */
-#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
-#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
-#define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */
-#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
-#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
-#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
-#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
-#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
-#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
-#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
- /* 0x101E9000 - reserved */
-#define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */
-#define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */
-#define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */
-#define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */
-#define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */
-
-#define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */
-#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
-#define VERSATILE_MBX_BASE 0x40000000 /* MBX */
-
-/* PCI space */
-#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
-#define VERSATILE_PCI_CFG_BASE 0x42000000
-#define VERSATILE_PCI_MEM_BASE0 0x44000000
-#define VERSATILE_PCI_MEM_BASE1 0x50000000
-#define VERSATILE_PCI_MEM_BASE2 0x60000000
-/* Sizes of above maps */
-#define VERSATILE_PCI_BASE_SIZE 0x01000000
-#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
-#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
-#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
-#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
-
-#define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
-#define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */
-
-/*
- * Disk on Chip
- */
-#define VERSATILE_DOC_BASE 0x2C000000
-#define VERSATILE_DOC_SIZE (16 << 20)
-#define VERSATILE_DOC_PAGE_SIZE 512
-#define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
-
-#define ERASE_UNIT_PAGES 32
-#define START_PAGE 0x80
-
-/*
- * LED settings, bits [7:0]
- */
-#define VERSATILE_SYS_LED0 (1 << 0)
-#define VERSATILE_SYS_LED1 (1 << 1)
-#define VERSATILE_SYS_LED2 (1 << 2)
-#define VERSATILE_SYS_LED3 (1 << 3)
-#define VERSATILE_SYS_LED4 (1 << 4)
-#define VERSATILE_SYS_LED5 (1 << 5)
-#define VERSATILE_SYS_LED6 (1 << 6)
-#define VERSATILE_SYS_LED7 (1 << 7)
-
-#define ALL_LEDS 0xFF
-
-#define LED_BANK VERSATILE_SYS_LED
-
-/*
- * Control registers
- */
-#define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */
-#define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */
-#define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */
-#define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */
-
-
-/* ------------------------------------------------------------------------
- * Versatile Interrupt Controller - control registers

- * ------------------------------------------------------------------------
- *

- * Offsets from interrupt controller base
- *
- * System Controller interrupt controller base is
- *
- * VERSATILE_IC_BASE
- *
- * Core Module interrupt controller base is
- *
- * VERSATILE_SYS_IC
- *
- */
-/* VIC definitions in include/asm-arm/hardware/vic.h */
-
-#define SIC_IRQ_STATUS 0
-#define SIC_IRQ_RAW_STATUS 0x04
-#define SIC_IRQ_ENABLE 0x08
-#define SIC_IRQ_ENABLE_SET 0x08
-#define SIC_IRQ_ENABLE_CLEAR 0x0C
-#define SIC_INT_SOFT_SET 0x10
-#define SIC_INT_SOFT_CLEAR 0x14
-#define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */
-#define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */
-#define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */
-
-/* ------------------------------------------------------------------------
- * Interrupts - bit assignment (primary)

- * ------------------------------------------------------------------------
- */
-

-#define INT_WDOGINT 0 /* Watchdog timer */
-#define INT_SOFTINT 1 /* Software interrupt */
-#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
-#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
-#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
-#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
-#define INT_GPIOINT0 6 /* GPIO 0 */
-#define INT_GPIOINT1 7 /* GPIO 1 */
-#define INT_GPIOINT2 8 /* GPIO 2 */
-#define INT_GPIOINT3 9 /* GPIO 3 */
-#define INT_RTCINT 10 /* Real Time Clock */
-#define INT_SSPINT 11 /* Synchronous Serial Port */
-#define INT_UARTINT0 12 /* UART 0 on development chip */
-#define INT_UARTINT1 13 /* UART 1 on development chip */
-#define INT_UARTINT2 14 /* UART 2 on development chip */
-#define INT_SCIINT 15 /* Smart Card Interface */
-#define INT_CLCDINT 16 /* CLCD controller */
-#define INT_DMAINT 17 /* DMA controller */
-#define INT_PWRFAILINT 18 /* Power failure */
-#define INT_MBXINT 19 /* Graphics processor */
-#define INT_GNDINT 20 /* Reserved */
- /* External interrupt signals from logic tiles or secondary controller */
-#define INT_VICSOURCE21 21 /* Disk on Chip */
-#define INT_VICSOURCE22 22 /* MCI0A */
-#define INT_VICSOURCE23 23 /* MCI1A */
-#define INT_VICSOURCE24 24 /* AACI */
-#define INT_VICSOURCE25 25 /* Ethernet */
-#define INT_VICSOURCE26 26 /* USB */
-#define INT_VICSOURCE27 27 /* PCI 0 */
-#define INT_VICSOURCE28 28 /* PCI 1 */
-#define INT_VICSOURCE29 29 /* PCI 2 */
-#define INT_VICSOURCE30 30 /* PCI 3 */
-#define INT_VICSOURCE31 31 /* SIC source */
-
-#define VERSATILE_SC_VALID_INT 0x003FFFFF
-
-#define MAXIRQNUM 31
-#define MAXFIQNUM 31
-#define MAXSWINUM 31
-
-/* ------------------------------------------------------------------------
- * Interrupts - bit assignment (secondary)

- * ------------------------------------------------------------------------
- */

-#define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */
-#define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */
-#define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */
-#define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */
-#define SIC_INT_SCI3 5 /* Smart Card interface */
-#define SIC_INT_UART3 6 /* UART 3 empty or data available */
-#define SIC_INT_CLCD 7 /* Character LCD */
-#define SIC_INT_TOUCH 8 /* Touchscreen */
-#define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */
- /* 10:20 - reserved */
-#define SIC_INT_DoC 21 /* Disk on Chip memory controller */
-#define SIC_INT_MMCI0A 22 /* MMC 0A */
-#define SIC_INT_MMCI1A 23 /* MMC 1A */
-#define SIC_INT_AACI 24 /* Audio Codec */
-#define SIC_INT_ETH 25 /* Ethernet controller */
-#define SIC_INT_USB 26 /* USB controller */
-#define SIC_INT_PCI0 27
-#define SIC_INT_PCI1 28
-#define SIC_INT_PCI2 29
-#define SIC_INT_PCI3 30
-
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK 0
-#define VERSATILE_TIMCLK 1
-
-#define VERSATILE_TIMER1_EnSel 15
-#define VERSATILE_TIMER2_EnSel 17
-#define VERSATILE_TIMER3_EnSel 19
-#define VERSATILE_TIMER4_EnSel 21
-
-
-#define VERSATILE_CSR_BASE 0x10000000
-#define VERSATILE_CSR_SIZE 0x10000000
-
-#ifdef CONFIG_MACH_VERSATILE_AB
-/*
- * IB2 Versatile/AB expansion board definitions
- */
-#define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE
-#define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000)
-
-/* VICINTSOURCE27 */
-#define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000)
-#define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0)
-#define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4)
-
-#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
-#define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0)
-#define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4)
-#endif
-
-/*
- * Defines required by basic firmware
- */
-#define VERSATILE_VMINFO_BASE 0x14000000
-
-#endif /* VERSATILE_PLAT_H */
diff --git a/tests/arm32/versatilepb/basic/emulate.sh b/tests/arm32/versatilepb/basic/emulate.sh
deleted file mode 100755
index 05901541..00000000
--- a/tests/arm32/versatilepb/basic/emulate.sh
+++ /dev/null
@@ -1,53 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2011 Jim Huang.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file emulate.sh
-# @author Jim Huang (js...@0xlab.org)
-# @brief execuate and validate Xvisor in QEMU
-
-CUR=`dirname $0`
-CMDS=`sed -n -e 's/\(^[^#].*\)/\1/p' test.script`
-
-emulate () {
- qemu-system-arm \
- -M versatilepb \
- -m 512M \
- -kernel $1 \
- -serial stdio \
- -parallel none \
- -display none \
- -monitor null <&0 & pid=$!
-}
-
-xvisor_qemu () {
- emulate $1 <<< "
-$CMDS
-"
- echo "Executing Xvisor in QEMU..."
- (sleep $2; kill $pid; sleep 1; kill -KILL $pid)& timer=$!
- if ! wait $pid; then
- kill $timer 2>/dev/null
- echo
- echo "Xvisor failed to execute in $2 seconds, giving up."
- exit -1
- fi
- kill $timer
-}
-
-xvisor_qemu $1 15
diff --git a/tests/arm32/versatilepb/basic/nor_flash.list b/tests/arm32/versatilepb/basic/nor_flash.list
deleted file mode 100644
index c97c5b8f..00000000
--- a/tests/arm32/versatilepb/basic/nor_flash.list
+++ /dev/null
@@ -1 +0,0 @@
-0x34000000 ./firmware.bin
diff --git a/tests/arm32/versatilepb/basic/qemu_test.tcl b/tests/arm32/versatilepb/basic/qemu_test.tcl
deleted file mode 100755
index 239812fd..00000000
--- a/tests/arm32/versatilepb/basic/qemu_test.tcl
+++ /dev/null
@@ -1,307 +0,0 @@
-#!/usr/bin/expect -f
-#/**
-# Copyright (c) 2011 Sanjeev Pandita.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file qemu_test.tcl
-# @author Sanjeev Pandita (san.p...@gmail.com)
-# @brief Automation script to test the Xvisor commands and Basic Firmware
-# */
-
-set qemu_img [lrange $argv 0 0]
-set xvisor_prompt "XVisor#"
-set arm_prompt "basic#"
-
-# start the test
-spawn qemu-system-arm -M realview-pb-a8 -m 512M -display none -serial stdio -kernel $qemu_img
-
-expect $xvisor_prompt
-send -- "help\r"
-expect $xvisor_prompt
-set help_out $expect_out(buffer)
-#puts $help_out
-if { [string compare $help_out ""] == 0 } {
-# only checks Empty lines
- puts "The Help Command Failed \n :: HELP TESTCASE FAIL :: \n\n"
-
-} else {
-puts "The Help Command passed \n :: HELP TESTCASE PASS :: \n\n"
-}
-
-send -- "version\r"
-expect $xvisor_prompt
-
-set version_out $expect_out(buffer)
-#puts $version_out
-if { [string first "Version" $version_out] > -1 } {
- puts "The Version Command passed \n :: Version TESTCASE PASS :: \n\n"
-} else {
- puts "The Version Command Failed \n :: Version TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "reset\r"
-expect $xvisor_prompt
-
-set reset_out $expect_out(buffer)
-#puts $reset_out
-if { [string first "init: board final" $reset_out] > -1 } {
- puts "The reset Command passed \n :: RESET TESTCASE PASS :: \n\n"
-} else {
- puts "The reset Command Failed \n :: RESET TESTCASE FAIL :: \n\n"
-}
-
-send -- "vapool help\r"
-expect $xvisor_prompt
-
-set vapool_help_out $expect_out(buffer)
-#puts $vapool_help_out
-if { [string first "vapool help" $vapool_help_out] > -1 } {
- puts "The vapool help Command passed \n :: VAPOOL HELP TESTCASE PASS :: \n\n"
-} else {
- puts "The vapool help Command Failed \n :: VAPOOL HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "vapool stats\r"
-expect $xvisor_prompt
-set vapool_stats_out $expect_out(buffer)
-#puts $vapool_stats_out
-if { [string first "Total Pages" $vapool_stats_out] > -1 } {
- puts "The vapool stats Command passed \n :: VAPOOL STATS TESTCASE PASS :: \n\n"
-} else {
- puts "The vapool stats Command Failed \n :: VAPOOL STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "vapool bitmap\r"
-expect $xvisor_prompt
-set vapool_bitmap_out $expect_out(buffer)
-#puts $vapool_bitmap_out
-if { [string first "1 : used" $vapool_bitmap_out] > -1 } {
- puts "The vapool bitmap Command passed \n :: VAPOOL BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "The vapool bitmap Command Failed \n :: VAPOOL BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "ram help\r"
-expect $xvisor_prompt
-
-set ram_help_out $expect_out(buffer)
-#puts $ram_help_out
-if { [string first "ram bitmap" $ram_help_out] > -1 } {
- puts "The ram help Command passed \n :: RAM HELP TESTCASE PASS :: \n\n"
-} else {
- puts "The ram help Command Failed \n :: RAM HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "ram stats\r"
-expect $xvisor_prompt
-
-set ram_stats_out $expect_out(buffer)
-#puts $ram_stats_out
-if { [string first "Total Frames " $ram_stats_out] > -1 } {
- puts "The ram stats Command passed \n :: RAM STATS TESTCASE PASS :: \n\n"
-} else {
- puts "The ram stats Command Failed \n :: RAM STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "ram bitmap\r"
-expect $xvisor_prompt
-
-set ram_bitmap_out $expect_out(buffer)
-#puts $ram_bitmap_out
-if { [string first "11111111111" $ram_bitmap_out] > -1 } {
- puts "The ram bitmap Command passed \n :: RAM BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "The ram bitmap Command Failed \n :: RAM BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree help\r"
-expect $xvisor_prompt
-set devtree_help_out $expect_out(buffer)
-#puts $devtree_help_out
-if { [string first "devtree print" $devtree_help_out] > -1 } {
- puts "The devtree help Command passed \n :: DEVTREE HELP TESTCASE PASS :: \n\n"
-} else {
- puts "The devtree help Command Failed \n :: DEVTREE HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree curpath\r"
-expect $xvisor_prompt
-
-set devtree_curpath_out $expect_out(buffer)
-#puts $devtree_curpath_out
-if { [string first "/" $devtree_curpath_out] > -1 } {
- puts "The devtree curpath Command passed \n :: DEVTREE CURPATH TESTCASE PASS :: \n\n"
-} else {
- puts "The devtree curpath Command Failed \n :: DEVTREE CURPATH TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree chpath /\r"
-expect $xvisor_prompt
-
-set devtree_chpath_out $expect_out(buffer)
-#puts $devtree_chpath_out
-if { [string first "/" $devtree_chpath_out] > -1 } {
- puts "The devtree chpath Command passed \n :: DEVTREE CHPATH TESTCASE PASS :: \n\n"
-} else {
- puts "The devtree chpath Command Failed \n :: DEVTREE CHPATH TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree print /\r"
-expect $xvisor_prompt
-
-set devtree_print_out $expect_out(buffer)
-#puts $devtree_print_out
-if { [string first "vmm" $devtree_print_out] > -1 } {
- puts "The devtree print Command passed \n :: DEVTREE PRINT TESTCASE PASS :: \n\n"
-} else {
- puts "The devtree print Command Failed \n :: DEVTREE PRINT TESTCASE FAIL :: \n\n"
-}
-
-send -- "guest kick guest0\r"
-expect $xvisor_prompt
-
-set guest_kick_out $expect_out(buffer)
-#puts $guest_kick_out
-if { [string first "guest0: Kicked" $guest_kick_out] > -1 } {
- puts "The guest kick Command passed \n :: GUEST KICK TESTCASE PASS :: \n\n"
-} else {
- puts "The guest kick Command Failed \n :: GUEST KICK TESTCASE FAIL :: \n\n"
-}
-
-send -- "vserial bind guest0/uart0\r"
-expect $arm_prompt
-
-set vserial_bind_out $expect_out(buffer)
-#puts $vserial_bind_out
-if { [string first "ARM VersatilePB Basic Firmware" $vserial_bind_out] > -1 } {
- puts "The vserial bind Command passed \n :: VSERIAL BIND KICK TESTCASE PASS :: \n\n"
-} else {
- puts "The vserial bind Command Failed \n :: VSERIAL BIND TESTCASE FAIL :: \n\n"
-}
-
-
-#send -- "help\r"
-send -- "hi\r"
-#expect "hello"
-expect $arm_prompt
-
-set hi_out $expect_out(buffer)
-#puts $hi_out
-if { [string first "hello" $hi_out] > -1 } {
- puts "The hi Command passed \n :: HI TESTCASE PASS :: \n\n"
-} else {
- puts "The hi Command Failed \n :: HI TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "hello\r"
-#expect "hi"
-expect $arm_prompt
-
-set hello_out $expect_out(buffer)
-#puts $hi_out
-if { [string first "hi" $hi_out] > -1 } {
- puts "The hello Command passed \n :: HELLO TESTCASE PASS :: \n\n"
-} else {
- puts "The hello Command Failed \n :: HELLO TESTCASE FAIL :: \n\n"
-}
-
-send -- "help\r"
-#expect "hi"
-expect $arm_prompt
-
-set help_out $expect_out(buffer)
-#puts $help_out
-if { [string first "reset" $help_out] > -1 } {
- puts "The help Command passed \n :: HELP TESTCASE PASS :: \n\n"
-} else {
- puts "The help Command Failed \n :: HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_setup\r"
-expect $arm_prompt
-
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-#puts $mmu_state_out
-if { [string first "MMU Enabled" $mmu_state_out] > -1 } {
- puts "The mmu_setup Command passed \n :: MMU SETUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "The mmu_setup Command Failed \n :: MMU SETUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "mmu_cleanup\r"
-expect $arm_prompt
-
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-#puts $mmu_state_out
-if { [string first "MMU Disabled" $mmu_state_out] > -1 } {
- puts "The mmu_cleanup Command passed \n :: MMU CLEANUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "The mmu_cleanup Command Failed \n :: MMU CLEANUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "mmu_test\r"
-expect $arm_prompt
-set mmu_test_out $expect_out(buffer)
-#puts $mmu_test_out
-set first_fail [string first "Fail : 0" $mmu_test_out]
-set last_fail [string last "Fail : 0" $mmu_test_out]
-
-if { $last_fail > $first_fail } {
-# puts "The mmu_test Command passed First is $first_fail and last is $last_fail \n :: MMU TEST TESTCASE PASS :: \n\n"
-puts "The mmu_test Command passed \n :: MMU TEST TESTCASE PASS :: \n\n"
-} else {
- puts "The mmu_test Command Failed \n :: MMU TEST TESTCASE FAIL :: \n\n"
-}
-
-send -- "timer\r"
-expect $arm_prompt
-set timer_out $expect_out(buffer)
-#puts $timer_out
-if { [string first "Time Stamp:" $timer_out] > -1 } {
- puts "The timer Command passed \n :: TIMER TESTCASE PASS :: \n\n"
-} else {
- puts "The timer Command Failed \n :: TIMER TESTCASE FAIL :: \n\n"
-}
-
-send -- "dhrystone\r"
-expect $arm_prompt
-set dhrystone_out $expect_out(buffer)
-#puts $dhrystone_out
-if { [string first "Dhrystones MIPS:" $dhrystone_out] > -1 } {
- puts "The Dhrystone Command passed \n :: DHRYSTONE TESTCASE PASS :: \n\n"
- set temp_var [string last ":" $dhrystone_out]
- set temp_var [expr $temp_var + 25 ]
- set DMIPS [string range $dhrystone_out $temp_var end ]
- puts "DMIPS is $DMIPS"
-} else {
- puts "The Dhrystone Command Failed \n :: DHRYSTONE TESTCASE FAIL :: \n\n"
-}
-
-send -- "\n"
-
-expect "#"
-send \003
-expect eof
-
diff --git a/tests/arm32/versatilepb/linux/README b/tests/arm32/versatilepb/linux/README
deleted file mode 100644
index 7e6d19ad..00000000
--- a/tests/arm32/versatilepb/linux/README
+++ /dev/null
@@ -1,101 +0,0 @@
- Linux on Xvisor VersatilePB Guest
-
-Linux is a computer operating system which is based on free and open source
-software. the underlying source code can be used, freely modified, and
-redistributed, both commercially and non-commercially, by anyone under
-licenses such as the GNU General Public License. For more information on
-Linux read the wiki page http://en.wikipedia.org/wiki/Linux
-
-Linux already contains a support for VersatilePB Board. We can use
-this kernel unmodified to run it as a xvisor guest. We have also provide
-VersatilePB defconfig for various linux kernel versions for ease in
-building kernel. To obtain Linux kernel sources visit the following
-url: http://www.kernel.org
-
-Please follow the steps below to build & run Linux kernel with Busybox
-RootFS on VersatilePB Guest with Xvisor running on QEMU VersatilePB Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v5 default settings]
- # make ARCH=arm generic-v5-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/versatilepb/basic
-
- [6. GoTo Linux source directory]
- # cd <linux_source_directory>
-
- [7. Configure Linux in build directory]
- # sed -i 's/0xff800000UL/0xff000000UL/' arch/arm/include/asm/pgtable.h
- # cp arch/arm/configs/versatile_defconfig arch/arm/configs/tmp-versatilepb_defconfig
- # <xvisor_source_directory>/tests/common/scripts/update-linux-defconfig.sh -p arch/arm/configs/tmp-versatilepb_defconfig -f <xvisor_source_directory>/tests/arm32/versatilepb/linux/linux_extra.config
- # make O=<linux_build_directory> ARCH=arm tmp-versatilepb_defconfig
-
- [8. Build Linux in build directory]
- # make O=<linux_build_directory> ARCH=arm Image dtbs
-
- [9. Patch Linux kernel to replace sensitive non-priviledged instructions]
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f <linux_build_directory>/vmlinux | <xvisor_source_directory>/build/tools/cpatch/cpatch32 <linux_build_directory>/vmlinux 0
-
- [10. Extract patched Linux kernel image]
- # ${CROSS_COMPILE}objcopy -O binary <linux_build_directory>/vmlinux <linux_build_directory>/arch/arm/boot/Image
-
- [11. Create BusyBox RAMDISK to be used as RootFS for Linux kernel]
- (Note: For subsequent steps, we will assume that your RAMDISK is located at <busybox_rootfs_directory>/rootfs.img)
- (Note: Please refer tests/common/busybox/README.md for creating rootfs.img using BusyBox)
-
- [12. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [13. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/versatilepb
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/versatilepb-guest.dtb ./tests/arm32/versatilepb/versatilepb-guest.dts
- # cp -f ./build/tests/arm32/versatilepb/basic/firmware.bin.patched ./build/disk/images/arm32/versatilepb/firmware.bin
- # cp -f ./tests/arm32/versatilepb/linux/nor_flash.list ./build/disk/images/arm32/versatilepb/nor_flash.list
- # cp -f ./tests/arm32/versatilepb/linux/cmdlist ./build/disk/images/arm32/versatilepb/cmdlist
- # cp -f ./tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript ./build/disk/boot.xscript
- # cp -f <linux_build_directory>/arch/arm/boot/Image ./build/disk/images/arm32/versatilepb/Image
- # cp -f <linux_build_directory>/arch/arm/boot/dts/versatile-pb.dtb ./build/disk/images/arm32/versatilepb/versatile-pb.dtb
- # cp -f <busybox_rootfs_directory>/rootfs.img ./build/disk/images/arm32/versatilepb/rootfs.img
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [14. Launch QEMU]
- # qemu-system-arm -M versatilepb -m 256M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/versatile-pb.dtb -initrd build/disk.img
-
- [15. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [16. Bind to virtual UART0 of Linux Guest]
- XVisor# vserial bind guest0/uart0
-
- [17. Copy linux from NOR flash to RAM and start linux booting from RAM]
- [guest0/uart0] basic# autoexec
- (Note: "autoexec" is a short-cut command for executing commands from NOR flash)
- (Note: The <xvisor_source_directory>/tests/arm32/versatilepb/linux/cmdlist file
- which we have added to guest NOR flash contains set of commands for booting
- linux from NOR flash)
-
- [18. Wait for Linux prompt to come-up and then try out some commands]
- [guest0/uart0] / # ls
-
- [19. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] / #
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/versatilepb/linux/cmdlist b/tests/arm32/versatilepb/linux/cmdlist
deleted file mode 100644
index 10806c07..00000000
--- a/tests/arm32/versatilepb/linux/cmdlist
+++ /dev/null
@@ -1,4 +0,0 @@
-copy 0x00008000 0x34100000 0x16F0000
-copy 0x02000000 0x357F0000 0x10000
-copy 0x02100000 0x35800000 0x800000
-start_linux_fdt 0x00008000 0x02000000 0x02100000 0x800000
diff --git a/tests/arm32/versatilepb/linux/linux_extra.config b/tests/arm32/versatilepb/linux/linux_extra.config
deleted file mode 100644
index be76dd92..00000000
--- a/tests/arm32/versatilepb/linux/linux_extra.config
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_VFP=n
diff --git a/tests/arm32/versatilepb/linux/nor_flash.list b/tests/arm32/versatilepb/linux/nor_flash.list
deleted file mode 100644
index 334a314a..00000000
--- a/tests/arm32/versatilepb/linux/nor_flash.list
+++ /dev/null
@@ -1,5 +0,0 @@
-0x34000000 ./firmware.bin
-0x340FF000 ./cmdlist
-0x34100000 ./Image
-0x357F0000 ./versatile-pb.dtb
-0x35800000 ./rootfs.img
diff --git a/tests/arm32/versatilepb/versatilepb-guest.dts b/tests/arm32/versatilepb/versatilepb-guest.dts
deleted file mode 100644
index 27881299..00000000
--- a/tests/arm32/versatilepb/versatilepb-guest.dts
+++ /dev/null
@@ -1,358 +0,0 @@
-
-/dts-v1/;
-
-/ {
- model = "arm,versatile-pb";
- device_type = "guest";
- psci_version = <2>;
-
- aliases {
- mem0 = &MEM0;
- net0 = &NET0;
- };
-
- vcpu_template {
- device_type = "vcpu";
- compatible = "armv5te,arm926ej";
- start_pc = <0x34000000>;
- };
-
- aspace {
- guest_irq_count = <2048>;
-
- MEM0: mem0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x00000000>;
- physical_size = <0x00000000>; /* Override this before guest creation */
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_ram";
- };
-
- sysctl {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10000000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "versatilepb,arm926";
- mux_in_irq = <1200 1201>;
- mux_out_irq = <1202>;
- };
-
- i2c { /* No I2C */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10002000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- sic {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10003000>;
- physical_size = <0x1000>;
- device_type = "pic";
- compatible = "versatilepb,pl190";
- base_irq = <32>;
- parent_irq = <31>;
- child_pic = <1>;
- };
-
- aaci { /* No Audio Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10004000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mmc0 { /* No Multimedia Card 0 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10005000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- kmi0 { /* No Keyboard/Mouse Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10006000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- kmi1 { /* No Keyboard/Mouse Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10007000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- lcd { /* No character LCD Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10008000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- uart3 { /* No uart3 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10009000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- sci1 { /* No MMC 1 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000A000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mmc1 { /* No MMC 1 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000B000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- NET0: eth {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10010000>;
- physical_size = <0x10000>;
- device_type = "nic";
- compatible = "smsc,smc91c111";
- interrupts = <25>;
- switch = ""; /* Override this before guest creation */
- };
-
- usb { /* No USB Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10020000>;
- physical_size = <0x10000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- ssmc { /* No SSMC Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10100000>;
- physical_size = <0x10000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mpmc { /* No MPMC Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10110000>;
- physical_size = <0x10000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- clcd { /* No colour LCD Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10120000>;
- physical_size = <0x10000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- dmac { /* No DMAC Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10130000>;
- physical_size = <0x10000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- pic {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10140000>;
- physical_size = <0x10000>;
- device_type = "pic";
- compatible = "versatilepb,pl190";
- parent_irq = <6>;
- };
-
- sysctrl0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E0000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "primecell,sp810";
- };
-
- wdog {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E1000>;
- physical_size = <0x1000>;
- device_type = "watchdog";
- compatible = "primecell,sp805";
- interrupts = <0>;
- };
-
- timer0_1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E2000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <4>;
- };
-
- timer2_3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E3000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <5>;
- };
-
- gpio0 { /* No GPIO 0 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E4000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpio1 { /* No GPIO 1 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E5000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpio2 { /* No GPIO 2 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E6000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- gpio3 { /* No GPIO 3 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E7000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- rtc0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101E8000>;
- physical_size = <0x1000>;
- device_type = "rtc";
- compatible = "primecell,pl031";

- interrupts = <10>;
- };
-

- sci0 { /* No Smart Card 0 Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101F0000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- uart0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101F1000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;

- interrupts = <12>;
- };
-

- uart1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101F2000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <13>;
- };
-
- uart2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101F3000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <14>;
- };
-
- ssp0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x101F4000>;
- physical_size = <0x1000>;
- device_type = "spi-host";
- compatible = "primecell,arm,pl022";
- interrupts = <11>;
- };
-
- vminfo {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "sys";
- compatible = "vminfo-0.1";
- guest_physical_addr = <0x14000000>;
- physical_size = <0x1000>;
- ram0_base = <0x00000000>;
- };
-
- nor_flash0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x34000000>;
- physical_size = <0x02000000>;
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_rom";
- };
- };
-};
diff --git a/tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript b/tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript
deleted file mode 100644
index abe3d89b..00000000
--- a/tests/arm32/versatilepb/xscript/one_guest_versatilepb.xscript
+++ /dev/null
@@ -1,8 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/versatilepb-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/versatilepb/nor_flash.list
diff --git a/tests/arm32/versatilepb/xscript/two_guest_versatilepb.xscript b/tests/arm32/versatilepb/xscript/two_guest_versatilepb.xscript
deleted file mode 100644
index 07786c7c..00000000
--- a/tests/arm32/versatilepb/xscript/two_guest_versatilepb.xscript
+++ /dev/null
@@ -1,17 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/versatilepb-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/versatilepb/nor_flash.list
-
-# Load guest1 device tree from file
-vfs guest_fdt_load guest1 /images/arm32/versatilepb-guest.dtb 1 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0
-
-# Create guest1
-guest create guest1
-
-# Load guest1 images
-vfs guest_load_list guest1 /images/arm32/versatilepb/nor_flash.list
diff --git a/tests/arm32/vexpress-a9/README b/tests/arm32/vexpress-a9/README
deleted file mode 100644
index 97dd3072..00000000
--- a/tests/arm32/vexpress-a9/README

+++ /dev/null
@@ -1,37 +0,0 @@

- VExpress-A9 Guest
-
-This guest has Cortex-A9 (MPCore ARMv7) CPU and various peripherals expected
-on a Versatile Platform Base Board.
-
-We also have memory mapped VirtIO devices located at unused IO regions
-of the guest for providing VirtIO based paravirtualization.
-
-There are many reserved IO regions as per CoreTile Express A9x4 reference
-manual. From these reserved IO regions, we will use the following IO regions
-for VirtIO:
-0x20000000–0x3FFFFFFF (512M) (Reserved)
-
-The VirtIO devices also require a IRQ line per device for functioning. The
-VExpress-A9 guest has following unused or reserved IRQ lines:
-GIC: 82
-GIC: 85-91
-
-The memory map and irq of paravirt devices on VExpress-A9 guest is as
-follows:
-0x20000000–0x20000FFF (4K) (Guest/VM Info Device)
-0x20100000–0x20100FFF (4K) (IRQ=82) (VirtIO Network Device)
-0x20200000–0x20200FFF (4K) (IRQ=85) (VirtIO Block Device)
-0x20300000–0x20300FFF (4K) (IRQ=86) (VirtIO Console Device)
-0x20400000–0x20400FFF (4K) (IRQ=87) (VirtIO RPMSG Device)
-
-
- VExpress-A9 Guest OSes
-
-We have tested following guest OSes for this guest:
-
- 1. basic - Basic firmware/bootloader
- 2. linux - Linux Kernel
- 3. freertos - FreeRTOS v9.0.0
-
-Please follow the README under specific guest OS directory for detailed steps
-to configure, compile and run.
diff --git a/tests/arm32/vexpress-a9/basic/Makefile b/tests/arm32/vexpress-a9/basic/Makefile
deleted file mode 100644
index 4be3804d..00000000
--- a/tests/arm32/vexpress-a9/basic/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-#/**
-# Copyright (c) 2012 Sukanto Ghosh.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile
-# @author Sukanto Ghosh (sukant...@gmail.com)
-# @brief toplevel makefile to build firmware
-# */
-
-# Determine the build directory
-top_dir=$(CURDIR)/../../../..
-ifdef O
- build_dir=$(shell readlink -f $(O))
-else
- build_dir=$(top_dir)/build
-endif
-ifdef I
- install_dir=$(shell readlink -f $(I))
-else
- install_dir=$(top_dir)/install
-endif
-
-obj_dir=$(build_dir)/tests/arm32/vexpress-a9/basic
-basic_dir=$(top_dir)/tests/common/basic
-arch_dir=$(top_dir)/tests/arm32/common/basic
-
-board_arch = v7
-board_text_start = 0x48000000
-board_objs = $(obj_dir)/arch_board.o \
- $(obj_dir)/pic/gic.o \
- $(obj_dir)/timer/sp804.o \
- $(obj_dir)/serial/pl01x.o \
- $(obj_dir)/sys/vminfo.o
-board_smp = y
-
-board_cppflags =
-board_cflags = -mtune=cortex-a9
-board_asflags = -mtune=cortex-a9
-board_ldflags =
-
-# Include common arch makefile for basic firmware
-include $(arch_dir)/Makefile.inc
diff --git a/tests/arm32/vexpress-a9/basic/README b/tests/arm32/vexpress-a9/basic/README
deleted file mode 100644
index d8140cfa..00000000
--- a/tests/arm32/vexpress-a9/basic/README
+++ /dev/null
@@ -1,70 +0,0 @@
- Basic Firmware on VExpress-A9 Guest
-
-The basic firmware currently sets up PIC, Timer, and UART and emulates
-a dummy terminal which reponds to various commands. It also includes an
-extensive MMU test suite and dhrystone benchmark.
-
-Hardware features tested by Basic Firmware:
- - Sensitive non-priviledged instructions
- - Virtual IRQs
- - Generic Interrupt Controller (GIC)
- - PrimeCell Dual-Mode Timer (SP804)
- - Serial Port (PL011)
-
-Please follow the steps below to build & run Basic Firmware on VExpress-A9
-Guest with Xvisor running on QEMU VExpress-A9 Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v7 default settings]
- # make ARCH=arm generic-v7-defconfig
-
- [4. Build Xvisor]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/vexpress-a9/basic
-
- [6. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/vexpress-a9
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/vexpress-a9-guest.dtb ./tests/arm32/vexpress-a9/vexpress-a9-guest.dts
- # cp -f ./build/tests/arm32/vexpress-a9/basic/firmware.bin.patched ./build/disk/images/arm32/vexpress-a9/firmware.bin
- # cp -f ./tests/arm32/vexpress-a9/basic/nor_flash.list ./build/disk/images/arm32/vexpress-a9/nor_flash.list
- # cp -f ./tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript ./build/disk/boot.xscript
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [7. Launch QEMU]
- # qemu-system-arm -M vexpress-a9 -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/vexpress-v2p-ca9.dtb -initrd build/disk.img
-
- [8. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [9. Bind to virtual UART]
- XVisor# vserial bind guest0/uart0
-
- [10. Say 'hi' to Basic Firmware]
- [guest0/uart0] basic# hi
-
- [11. Say 'hello' to Basic Firmware]
- [guest0/uart0] basic# hello
-
- [12. Check various commands of Basic Firmware]
- [guest0/uart0] basic# help
-
- [13. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] basic#
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/vexpress-a9/basic/arch_board.c b/tests/arm32/vexpress-a9/basic/arch_board.c
deleted file mode 100644
index 9960695e..00000000
--- a/tests/arm32/vexpress-a9/basic/arch_board.c
+++ /dev/null
@@ -1,492 +0,0 @@

-/**
- * Copyright (c) 2012 Jean-Christophe Dubois.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_board.c

- * @author Jean-Christophe Dubois (j...@tribudubois.net)

- * @brief various platform specific functions
- */
-
-#include <arch_types.h>
-#include <arch_io.h>
-#include <arch_math.h>
-#include <arch_board.h>
-#include <arm_plat.h>
-#include <basic_stdio.h>
-#include <basic_string.h>
-#include <libfdt/libfdt.h>
-#include <libfdt/fdt_support.h>
-#include <pic/gic.h>
-#include <timer/sp804.h>
-#include <serial/pl01x.h>
-#include <sys/vminfo.h>
-
-void arch_board_reset(void)
-{
- arch_writel(~0x0, (void *)(V2M_SYS_FLAGSCLR));
- arch_writel(0x0, (void *)(V2M_SYS_FLAGSSET));
- arch_writel(0xc0900000, (void *)(V2M_SYS_CFGCTRL));
-}
-
-void arch_board_init(void)
-{
- /* Nothing to do */
-}
-
-char *arch_board_name(void)
-{
- return "ARM VExpress-A9";
-}
-
-physical_addr_t arch_board_ram_start(void)
-{
- return (physical_addr_t)vminfo_ram_base(V2M_VMINFO_BASE, 0);
-}
-
-physical_size_t arch_board_ram_size(void)
-{
- return (physical_size_t)vminfo_ram_size(V2M_VMINFO_BASE, 0);
-}
-
-void arch_board_linux_default_cmdline(char *cmdline, u32 cmdline_sz)
-{
- basic_strcpy(cmdline, "root=/dev/ram rw earlyprintk "
- "earlycon=pl011,0x10009000 console=ttyAMA0");
-}
-
-void arch_board_fdt_fixup(void *fdt_addr)
-{
- u32 vals[5];
- char str[64];
- int rc, poff, noff;
-
- poff = fdt_path_offset(fdt_addr, "/");
- if (poff < 0) {
- basic_printf("%s: failed to find nodeoffset of / node\n",
- __func__);
- return;
- }
-
- poff = fdt_add_subnode(fdt_addr, poff, "virt");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virt", "/");
- return;
- }
-
- basic_strcpy(str, "simple-bus");
- rc = fdt_setprop(fdt_addr, poff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#address-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#address-cells", "virt");
- return;
- }
-
- vals[0] = cpu_to_fdt32(1);
- rc = fdt_setprop(fdt_addr, poff, "#size-cells",
- vals, sizeof(u32));
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "#size-cells", "virt");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, poff, "ranges", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "ranges", "virt");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_net");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_net", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20100000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_net");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(50);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_net");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_net");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_block");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_block", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20200000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_block");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(53);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_block");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_block");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_console");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_console", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20300000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_console");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(54);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_console");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_console");
- return;
- }
-
- noff = fdt_add_subnode(fdt_addr, poff, "virtio_rpmsg");
- if (poff < 0) {
- basic_printf("%s: failed to add %s subnode in %s node\n",
- __func__, "virtio_rpmsg", "virt");
- return;
- }
-
- basic_strcpy(str, "virtio,mmio");
- rc = fdt_setprop(fdt_addr, noff, "compatible",
- str, basic_strlen(str)+1);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "compatible", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0x20400000);
- vals[1] = cpu_to_fdt32(0x1000);
- rc = fdt_setprop(fdt_addr, noff, "reg",
- vals, sizeof(u32)*2);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "reg", "virtio_rpmsg");
- return;
- }
-
- vals[0] = cpu_to_fdt32(0);
- vals[1] = cpu_to_fdt32(55);
- vals[2] = cpu_to_fdt32(4);
- rc = fdt_setprop(fdt_addr, noff, "interrupts",
- vals, sizeof(u32)*3);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "interrupts", "virtio_rpmsg");
- return;
- }
-
- rc = fdt_setprop(fdt_addr, noff, "dma-coherent", NULL, 0);
- if (rc < 0) {
- basic_printf("%s: failed to setprop %s in %s node\n",
- __func__, "dma-coherent", "virtio_rpmsg");
- return;
- }
-}
-
-physical_addr_t arch_board_autoexec_addr(void)
-{
- return (V2M_NOR0 + 0xFF000);
-}
-
-u32 arch_board_boot_delay(void)
-{
- return vminfo_boot_delay(V2M_VMINFO_BASE);
-}
-
-u32 arch_board_iosection_count(void)
-{
- return 19;
-}
-
-physical_addr_t arch_board_iosection_addr(int num)
-{
- physical_addr_t ret = 0;
-
- switch (num) {
- case 0:
- ret = V2M_PA_CS7;

- break;
- case 1:

- ret = CT_CA9X4_MPIC;

- break;
- case 2:

- ret = V2M_VMINFO_BASE;

- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:

- case 8:
- case 9:
- case 10:
- case 11:
- case 12:

- case 13:
- case 14:
- case 15:
- case 16:
- case 17:
- case 18:
- ret = V2M_NOR0 + (num - 3) * 0x100000;
- break;
- default:
- while (1);
- break;
- }
-
- return ret;
-}
-
-u32 arch_board_pic_nr_irqs(void)
-{
- return NR_IRQS_CA9X4;
-}
-
-int arch_board_pic_init(void)

-{
- int rc;
-
- /*

- * Initialize Generic Interrupt Controller
- */
- rc = gic_dist_init(0, A9_MPCORE_GIC_DIST, IRQ_CA9X4_GIC_START);

- if (rc) {
- return rc;
- }

- rc = gic_cpu_init(0, A9_MPCORE_GIC_CPU);

- if (rc) {
- return rc;
- }
-

- return 0;
-}
-
-u32 arch_board_pic_active_irq(void)
-{
- return gic_active_irq(0);
-}
-
-int arch_board_pic_ack_irq(u32 irq)

-{
- return 0;
-}
-

-int arch_board_pic_eoi_irq(u32 irq)
-{
- return gic_eoi_irq(0, irq);
-}
-
-int arch_board_pic_mask(u32 irq)
-{
- return gic_mask(0, irq);
-}
-
-int arch_board_pic_unmask(u32 irq)
-{
- return gic_unmask(0, irq);
-}
-
-void arch_board_timer_enable(void)
-{
- return sp804_enable();
-}
-
-void arch_board_timer_disable(void)
-{
- return sp804_disable();
-}
-
-u64 arch_board_timer_irqcount(void)
-{
- return sp804_irqcount();
-}
-
-u64 arch_board_timer_irqdelay(void)
-{
- return sp804_irqdelay();
-}
-
-u64 arch_board_timer_timestamp(void)
-{
- return sp804_timestamp();
-}
-
-void arch_board_timer_change_period(u32 usecs)
-{
- return sp804_change_period(usecs);
-}
-
-int arch_board_timer_init(u32 usecs)
-{
- u32 val, irq;
- u64 counter_mult, counter_shift, counter_mask;
-
- counter_mask = 0xFFFFFFFFULL;
- counter_shift = 20;
- counter_mult = ((u64)1000000) << counter_shift;
- counter_mult += (((u64)1000) >> 1);
- counter_mult = arch_udiv64(counter_mult, ((u64)1000));
-
- irq = IRQ_V2M_TIMER0;
-
- val = arch_readl((void *)V2M_SYSCTL) | SCCTRL_TIMEREN0SEL_TIMCLK;
- arch_writel(val, (void *)V2M_SYSCTL);
-
- return sp804_init(usecs, V2M_TIMER0, irq,
- counter_mask, counter_mult, counter_shift);
-}
-
-#define CA9X4_UART_BASE V2M_UART0
-#define CA9X4_UART_TYPE PL01X_TYPE_1
-#define CA9X4_UART_INCLK 24000000
-#define CA9X4_UART_BAUD 115200
-
-int arch_board_serial_init(void)
-{
- pl01x_init(CA9X4_UART_BASE,
- CA9X4_UART_TYPE,
- CA9X4_UART_BAUD,
- CA9X4_UART_INCLK);

-
- return 0;
-}
-

-void arch_board_serial_putc(char ch)
-{
- if (ch == '\n') {
- pl01x_putc(CA9X4_UART_BASE, CA9X4_UART_TYPE, '\r');
- }
- pl01x_putc(CA9X4_UART_BASE, CA9X4_UART_TYPE, ch);
-}
-
-bool arch_board_serial_can_getc(void)
-{
- return pl01x_can_getc(CA9X4_UART_BASE, CA9X4_UART_TYPE);
-}
-
-char arch_board_serial_getc(void)
-{
- char ch = pl01x_getc(CA9X4_UART_BASE, CA9X4_UART_TYPE);
- if (ch == '\r') {
- ch = '\n';
- }
- arch_board_serial_putc(ch);
- return ch;
-}
diff --git a/tests/arm32/vexpress-a9/basic/arch_smp.h b/tests/arm32/vexpress-a9/basic/arch_smp.h
deleted file mode 100644
index 9a3d5dfb..00000000
--- a/tests/arm32/vexpress-a9/basic/arch_smp.h

+++ /dev/null
@@ -1,30 +0,0 @@

-/**
- * Copyright (c) 2018 Anup Patel.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arch_smp.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief arch specific SMP defines
- */
-#ifndef __ARCH_SMP_H__
-#define __ARCH_SMP_H__
-
-#include <arm_plat.h>
-
-#define ARCH_SMP_SPIN_ADDR (V2M_SYS_FLAGS)
-
-#endif
diff --git a/tests/arm32/vexpress-a9/basic/arm_plat.h b/tests/arm32/vexpress-a9/basic/arm_plat.h
deleted file mode 100644
index 06bdd94f..00000000
--- a/tests/arm32/vexpress-a9/basic/arm_plat.h

+++ /dev/null
@@ -1,252 +0,0 @@
-/**

- * Copyright (c) 2012 Sukanto Ghosh.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arm_plat.h

- * @author Sukanto Ghosh (sukant...@gmail.com)

- * @brief ARM platform configuration
- */
-#ifndef _ARM_PLAT_H__
-#define _ARM_PLAT_H__
-
-/*
- * On-Chip Peripherials Physical Addresses
- */
-#define CT_CA9X4_CLCDC (0x10020000)
-#define CT_CA9X4_AXIRAM (0x10060000)
-#define CT_CA9X4_DMC (0x100e0000)
-#define CT_CA9X4_SMC (0x100e1000)
-#define CT_CA9X4_SCC (0x100e2000)
-#define CT_CA9X4_SP804_TIMER (0x100e4000)
-#define CT_CA9X4_SP805_WDT (0x100e5000)
-#define CT_CA9X4_TZPC (0x100e6000)
-#define CT_CA9X4_GPIO (0x100e8000)
-#define CT_CA9X4_FASTAXI (0x100e9000)
-#define CT_CA9X4_SLOWAXI (0x100ea000)
-#define CT_CA9X4_TZASC (0x100ec000)
-#define CT_CA9X4_CORESIGHT (0x10200000)
-#define CT_CA9X4_MPIC (0x1e000000)
-#define CT_CA9X4_SYSTIMER (0x1e004000)
-#define CT_CA9X4_SYSWDT (0x1e007000)
-#define CT_CA9X4_L2CC (0x1e00a000)
-
-#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
-
-/*
- * Interrupts. Those in {} are for AMBA devices
- */
-#define IRQ_CT_CA9X4_CLCDC { 76 }
-#define IRQ_CT_CA9X4_DMC { -1 }
-#define IRQ_CT_CA9X4_SMC { 77, 78 }
-#define IRQ_CT_CA9X4_TIMER0 80
-#define IRQ_CT_CA9X4_TIMER1 81
-#define IRQ_CT_CA9X4_GPIO { 82 }
-#define IRQ_CT_CA9X4_PMU_CPU0 92
-#define IRQ_CT_CA9X4_PMU_CPU1 93
-#define IRQ_CT_CA9X4_PMU_CPU2 94
-#define IRQ_CT_CA9X4_PMU_CPU3 95
-
-#define IRQ_CT_CA9X4_LOCALTIMER 29
-#define IRQ_CT_CA9X4_LOCALWDOG 30
-
-#define IRQ_CA9X4_GIC_START 29
-#define NR_IRQS_CA9X4 128
-#define NR_GIC_CA9X4 1
-
-/*
- * V2M Chip Select Physical Addresses
- */
-#define V2M_PA_CS0 0x40000000
-#define V2M_PA_CS1 0x44000000
-#define V2M_PA_CS2 0x48000000
-#define V2M_PA_CS3 0x4c000000
-#define V2M_PA_CS7 0x10000000
-
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0 (V2M_PA_CS0)
-#define V2M_NOR1 (V2M_PA_CS1)
-#define V2M_SRAM (V2M_PA_CS2)
-#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
-#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
-#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
-
-/*
- * Physical addresses, offset from V2M_PA_CS7
- */
-#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000)
-#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000)
-#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000)
-
-#define V2M_AACI (V2M_PA_CS7 + 0x00004000)
-#define V2M_MMCI (V2M_PA_CS7 + 0x00005000)
-#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000)
-#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000)
-
-#define V2M_UART0 (V2M_PA_CS7 + 0x00009000)
-#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000)
-#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000)
-#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000)
-
-#define V2M_WDT (V2M_PA_CS7 + 0x0000f000)
-
-#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000)
-#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000)
-
-#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000)
-#define V2M_RTC (V2M_PA_CS7 + 0x00017000)
-
-#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
-#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
-
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
-
-/*
- * Interrupts. Those in {} are for AMBA devices
- */
-#define IRQ_V2M_WDT { (32 + 0) }
-#define IRQ_V2M_TIMER0 (32 + 2)
-#define IRQ_V2M_TIMER1 (32 + 2)
-#define IRQ_V2M_TIMER2 (32 + 3)
-#define IRQ_V2M_TIMER3 (32 + 3)
-#define IRQ_V2M_RTC { (32 + 4) }
-#define IRQ_V2M_UART0 { (32 + 5) }
-#define IRQ_V2M_UART1 { (32 + 6) }
-#define IRQ_V2M_UART2 { (32 + 7) }
-#define IRQ_V2M_UART3 { (32 + 8) }
-#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) }
-#define IRQ_V2M_AACI { (32 + 11) }
-#define IRQ_V2M_KMI0 { (32 + 12) }
-#define IRQ_V2M_KMI1 { (32 + 13) }
-#define IRQ_V2M_CLCD { (32 + 14) }
-#define IRQ_V2M_LAN9118 (32 + 15)
-#define IRQ_V2M_ISP1761 (32 + 16)
-#define IRQ_V2M_PCIE (32 + 17)
-
-/*
- * Configuration
- */
-#define SYS_CFG_START (1 << 31)
-#define SYS_CFG_WRITE (1 << 30)
-#define SYS_CFG_OSC (1 << 20)
-#define SYS_CFG_VOLT (2 << 20)
-#define SYS_CFG_AMP (3 << 20)
-#define SYS_CFG_TEMP (4 << 20)
-#define SYS_CFG_RESET (5 << 20)
-#define SYS_CFG_SCC (6 << 20)
-#define SYS_CFG_MUXFPGA (7 << 20)
-#define SYS_CFG_SHUTDOWN (8 << 20)
-#define SYS_CFG_REBOOT (9 << 20)
-#define SYS_CFG_DVIMODE (11 << 20)
-#define SYS_CFG_POWER (12 << 20)
-#define SYS_CFG_SITE_MB (0 << 16)
-#define SYS_CFG_SITE_DB1 (1 << 16)
-#define SYS_CFG_SITE_DB2 (2 << 16)
-#define SYS_CFG_STACK(n) ((n) << 12)
-
-#define SYS_CFG_ERR (1 << 1)
-#define SYS_CFG_COMPLETE (1 << 0)
-
-/*
- * Core tile IDs
- */
-#define V2M_CT_ID_CA9 0x0c000191
-#define V2M_CT_ID_UNSUPPORTED 0xff000191
-#define V2M_CT_ID_MASK 0xff000fff
-
-/* Following taken from sp810.h */
-
-/* sysctl registers offset */
-#define SCCTRL 0x000
-#define SCSYSSTAT 0x004
-#define SCIMCTRL 0x008
-#define SCIMSTAT 0x00C
-#define SCXTALCTRL 0x010
-#define SCPLLCTRL 0x014
-#define SCPLLFCTRL 0x018
-#define SCPERCTRL0 0x01C
-#define SCPERCTRL1 0x020
-#define SCPEREN 0x024
-#define SCPERDIS 0x028
-#define SCPERCLKEN 0x02C
-#define SCPERSTAT 0x030
-#define SCSYSID0 0xEE0
-#define SCSYSID1 0xEE4
-#define SCSYSID2 0xEE8
-#define SCSYSID3 0xEEC
-#define SCITCR 0xF00
-#define SCITIR0 0xF04
-#define SCITIR1 0xF08
-#define SCITOR 0xF0C
-#define SCCNTCTRL 0xF10
-#define SCCNTDATA 0xF14
-#define SCCNTSTEP 0xF18
-#define SCPERIPHID0 0xFE0
-#define SCPERIPHID1 0xFE4
-#define SCPERIPHID2 0xFE8
-#define SCPERIPHID3 0xFEC
-#define SCPCELLID0 0xFF0
-#define SCPCELLID1 0xFF4
-#define SCPCELLID2 0xFF8
-#define SCPCELLID3 0xFFC
-
-#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
-#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
-
-#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
-#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
-
-/*
- * Defines required by basic firmware
- */
-#define V2M_VMINFO_BASE 0x20000000
-
-#endif
diff --git a/tests/arm32/vexpress-a9/basic/emulate.sh b/tests/arm32/vexpress-a9/basic/emulate.sh
deleted file mode 100755
index e815581c..00000000
--- a/tests/arm32/vexpress-a9/basic/emulate.sh
+++ /dev/null
@@ -1,53 +0,0 @@
-#!/bin/bash
-
-# Copyright (c) 2011 Jim Huang.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file emulate.sh
-# @author Jim Huang (js...@0xlab.org)
-# @brief execuate and validate Xvisor in QEMU
-
-CUR=`dirname $0`
-CMDS=`sed -n -e 's/\(^[^#].*\)/\1/p' test.script`
-
-emulate () {
- qemu-system-arm \
- -M vexpress-a9 \
- -m 512M \
- -kernel $1 \
- -serial stdio \
- -parallel none \
- -display none \
- -monitor null <&0 & pid=$!
-}
-
-xvisor_qemu () {
- emulate $1 <<< "
-$CMDS
-"
- echo "Executing Xvisor in QEMU..."
- (sleep $2; kill $pid; sleep 1; kill -KILL $pid)& timer=$!
- if ! wait $pid; then
- kill $timer 2>/dev/null
- echo
- echo "Xvisor failed to execute in $2 seconds, giving up."
- exit -1
- fi
- kill $timer
-}
-
-xvisor_qemu $1 15
diff --git a/tests/arm32/vexpress-a9/basic/gic_config.h b/tests/arm32/vexpress-a9/basic/gic_config.h
deleted file mode 100644
index 573a7e73..00000000
--- a/tests/arm32/vexpress-a9/basic/gic_config.h
+++ /dev/null
@@ -1,33 +0,0 @@

-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file gic_config.h

- * @author Anup Patel (an...@brainfault.org)

- * @brief ARM Generic Interrupt Controller configuration header
- */
-#ifndef _GIC_CONFIG_H__
-#define _GIC_CONFIG_H__
-
-#include <arm_plat.h>
-
-#define GIC_CPU_BASE A9_MPCORE_GIC_CPU
-#define GIC_DIST_BASE A9_MPCORE_GIC_DIST
-#define GIC_NR_IRQS NR_IRQS_CA9X4
-#define GIC_MAX_NR NR_GIC_CA9X4
-
-#endif
diff --git a/tests/arm32/vexpress-a9/basic/nor_flash.list b/tests/arm32/vexpress-a9/basic/nor_flash.list
deleted file mode 100644
index 4f38aa4c..00000000
--- a/tests/arm32/vexpress-a9/basic/nor_flash.list
+++ /dev/null
@@ -1 +0,0 @@
-0x40000000 ./firmware.bin
diff --git a/tests/arm32/vexpress-a9/basic/qemu_test.tcl b/tests/arm32/vexpress-a9/basic/qemu_test.tcl
deleted file mode 100755
index a8523a8b..00000000
--- a/tests/arm32/vexpress-a9/basic/qemu_test.tcl
+++ /dev/null
@@ -1,244 +0,0 @@
-#!/usr/bin/expect -f
-#/**
-# Copyright (c) 2011 Sanjeev Pandita.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file qemu_test.tcl
-# @author Sanjeev Pandita (san.p...@gmail.com)
-# @brief Automation script to test the Xvisor commands and Basic Firmware
-# */
-
-set qemu_img [lrange $argv 0 0]
-set xvisor_prompt "XVisor#"
-set arm_prompt "basic#"
-
-# start the test
-spawn qemu-system-arm -M vexpress-a9 -m 512M -display none -serial stdio -kernel $qemu_img
-
-expect $xvisor_prompt
-send -- "help\r"
-expect $xvisor_prompt
-set help_out $expect_out(buffer)
-if { [string compare $help_out ""] == 0 } {
-# only checks Empty lines
- puts "\n :: HELP TESTCASE FAIL :: \n\n"
-
-} else {
-puts "\n :: HELP TESTCASE PASS :: \n\n"
-}
-
-send -- "version\r"
-expect $xvisor_prompt
-
-set version_out $expect_out(buffer)
-if { [string first "Version" $version_out] > -1 } {
- puts "\n :: Version TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: Version TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "reset\r"
-expect $xvisor_prompt
-
-set reset_out $expect_out(buffer)
-if { [string first "init: board final" $reset_out] > -1 } {
- puts "\n :: RESET TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: RESET TESTCASE FAIL :: \n\n"
-}
-
-send -- "host help\r"
-expect $xvisor_prompt
-
-set host_help_out $expect_out(buffer)
-if { [string first "host help" $host_help_out] > -1 } {
- puts "\n :: HOST HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "host vapool stats\r"
-expect $xvisor_prompt
-set host_vapool_stats_out $expect_out(buffer)
-if { [string first "Total Pages" $host_vapool_stats_out] > -1 } {
- puts "\n :: HOST VAPOOL STATS TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST VAPOOL STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "host vapool bitmap\r"
-expect $xvisor_prompt
-set host_vapool_bitmap_out $expect_out(buffer)
-if { [string first "1 : used" $host_vapool_bitmap_out] > -1 } {
- puts "\n :: HOST VAPOOL BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST VAPOOL BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "host ram stats\r"
-expect $xvisor_prompt
-set host_ram_stats_out $expect_out(buffer)
-if { [string first "Total Frames " $host_ram_stats_out] > -1 } {
- puts "\n :: HOST RAM STATS TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST RAM STATS TESTCASE FAIL :: \n\n"
-}
-
-send -- "host ram bitmap\r"
-expect $xvisor_prompt
-set host_ram_bitmap_out $expect_out(buffer)
-if { [string first "11111111111" $host_ram_bitmap_out] > -1 } {
- puts "\n :: HOST RAM BITMAP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HOST RAM BITMAP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree help\r"
-expect $xvisor_prompt
-set devtree_help_out $expect_out(buffer)
-if { [string first "devtree print" $devtree_help_out] > -1 } {
- puts "\n :: DEVTREE HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree node show /\r"
-expect $xvisor_prompt
-set devtree_node_show_out $expect_out(buffer)
-if { [string first "vmm" $devtree_node_show_out] > -1 } {
- puts "\n :: DEVTREE NODE SHOW TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE NODE SHOW TESTCASE FAIL :: \n\n"
-}
-
-send -- "devtree node dump /\r"
-expect $xvisor_prompt
-set devtree_node_dump_out $expect_out(buffer)
-if { [string first "vmm" $devtree_node_dump_out] > -1 } {
- puts "\n :: DEVTREE NODE DUMP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: DEVTREE NODE DUMP TESTCASE FAIL :: \n\n"
-}
-
-send -- "guest kick guest0\r"
-expect $xvisor_prompt
-set guest_kick_out $expect_out(buffer)
-if { [string first "guest0: Kicked" $guest_kick_out] > -1 } {
- puts "\n :: GUEST KICK TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: GUEST KICK TESTCASE FAIL :: \n\n"
-}
-
-send -- "vserial bind guest0/uart0\r"
-expect $arm_prompt
-set vserial_bind_out $expect_out(buffer)
-if { [string first "ARM VExpress-A9 Basic Firmware" $vserial_bind_out] > -1 } {
- puts "\n :: VSERIAL BIND TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: VSERIAL BIND TESTCASE FAIL :: \n\n"
-}
-
-send -- "hi\r"
-expect $arm_prompt
-set hi_out $expect_out(buffer)
-if { [string first "hello" $hi_out] > -1 } {
- puts "\n :: HI TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HI TESTCASE FAIL :: \n\n"
-}
-
-
-send -- "hello\r"
-expect $arm_prompt
-set hello_out $expect_out(buffer)
-if { [string first "hi" $hi_out] > -1 } {
- puts "The hello Command passed \n :: HELLO TESTCASE PASS :: \n\n"
-} else {
- puts "The hello Command Failed \n :: HELLO TESTCASE FAIL :: \n\n"
-}
-
-send -- "help\r"
-expect $arm_prompt
-set help_out $expect_out(buffer)
-if { [string first "reset" $help_out] > -1 } {
- puts "\n :: HELP TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: HELP TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_setup\r"
-expect $arm_prompt
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-if { [string first "MMU Enabled" $mmu_state_out] > -1 } {
- puts "\n :: MMU SETUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU SETUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_cleanup\r"
-expect $arm_prompt
-send -- "mmu_state\r"
-expect $arm_prompt
-set mmu_state_out $expect_out(buffer)
-if { [string first "MMU Disabled" $mmu_state_out] > -1 } {
- puts "\n :: MMU CLEANUP & MMU STATE TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU CLEANUP & MMU STATE TESTCASE FAIL :: \n\n"
-}
-
-send -- "mmu_test\r"
-expect $arm_prompt
-set mmu_test_out $expect_out(buffer)
-set first_fail [string first "Fail : 0" $mmu_test_out]
-set last_fail [string last "Fail : 0" $mmu_test_out]
-if { $last_fail > $first_fail } {
- puts "\n :: MMU TEST TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: MMU TEST TESTCASE FAIL :: \n\n"
-}
-
-send -- "timer\r"
-expect $arm_prompt
-set timer_out $expect_out(buffer)
-if { [string first "Time Stamp:" $timer_out] > -1 } {
- puts "\n :: TIMER TESTCASE PASS :: \n\n"
-} else {
- puts "\n :: TIMER TESTCASE FAIL :: \n\n"
-}
-
-send -- "dhrystone\r"
-expect $arm_prompt
-set dhrystone_out $expect_out(buffer)
-if { [string first "Dhrystones MIPS:" $dhrystone_out] > -1 } {
- puts "\n :: DHRYSTONE TESTCASE PASS :: \n\n"
- set temp_var [string last ":" $dhrystone_out]
- set temp_var [expr $temp_var + 25 ]
- set DMIPS [string range $dhrystone_out $temp_var end ]
- puts "DMIPS is $DMIPS"
-} else {
- puts "\n :: DHRYSTONE TESTCASE FAIL :: \n\n"
-}
-
-send -- "\n"
-
-expect "#"
-send \003
-expect eof
-
diff --git a/tests/arm32/vexpress-a9/freertos/Makefile b/tests/arm32/vexpress-a9/freertos/Makefile
deleted file mode 100644
index f0ff2e71..00000000
--- a/tests/arm32/vexpress-a9/freertos/Makefile
+++ /dev/null
@@ -1,229 +0,0 @@
-# -*- makefile-gnu -*-
-# Copyright (c) 2016 Philipp Ittershagen.

-# All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#

-# @file Makefile
-# @author Philipp Ittershagen <p...@shgn.de>
-# @brief Makefile to build an Xvisor FreeRTOS guest image
-#
-
-# support VERBOSE=yes
-Q := $(if $(filter-out yesPlease,$(strip $(VERBOSE))Please),@)
-
-# --------- directory settings
-
-basedir = ../../../..
-builddir = $(basedir)/build
-
-srcdir = $(basedir)/tests/arm32/vexpress-a9/freertos
-common_srcdir = $(srcdir)/../../../common/basic
-common_arch_srcdir = $(srcdir)/../../common/basic
-freertos_srcdir = $(srcdir)/FreeRTOS/Source
-
-objdir = $(patsubst $(basedir)/%,$(builddir)/%, $(srcdir))
-
-# board features
-BOARD_SMP = y
-BOARD_SECURE_EXTN = n
-
-BOARD_TEXT_START = 0x48000000
-BOARD_USR_STACK_SIZE = 16384
-
-# --------- source files
-
-# FreeRTOS heap allocator implementation choice
-FREERTOS_HEAP_IMPL = $(freertos_srcdir)/portable/MemMang/heap_2.c
-
-# platform-independent FreeRTOS source files
-FREERTOS_GLOBS = $(addprefix $(freertos_srcdir)/, *.c)
-
-FREERTOS_SRCS = $(wildcard $(FREERTOS_GLOBS)) $(FREERTOS_HEAP_IMPL)
-
-# sources from the common firmware directory (relative to $common_srcdir)
-COMMON_SRCS = basic_irq.c basic_stdio.c basic_string.c pic/gic.c \
- serial/pl01x.c sys/vminfo.c timer/sp804.c \
- libfdt/fdt.c libfdt/fdt_ro.c libfdt/fdt_rw.o \
- libfdt/fdt_strerror.c libfdt/fdt_support.c \
- libfdt/fdt_sw.c libfdt/fdt_wip.c
-COMMON_ARCH_SRCS = arch_math.c arch_irq.c arch_cache_v7.S
-
-# FreeRTOS specific glue and application source (relative to $srcdir)
-OTHER_SRCS = port/port.c port/portASM.S ../basic/arch_board.c \
- arm_entry_v7.S glue.c main.c
-
-CC = $(CROSS_COMPILE)gcc
-CPP = $(CROSS_COMPILE)cpp
-LD = $(CROSS_COMPILE)ld
-AS = $(CROSS_COMPILE)as
-OBJCOPY = $(CROSS_COMPILE)objcopy
-
-RM = rm
-MKDIR_P = mkdir -p
-
-ELF2CPATCH = $(basedir)/arch/arm/cpu/arm32/elf2cpatch.py
-CPATCH32 = $(builddir)/tools/cpatch/cpatch32
-
-# --------- compiler/linker flags
-
-LINK_SCRIPT = $(common_arch_srcdir)/firmware.ld
-
-CPPFLAGS = -I$(srcdir)/../basic -I$(common_srcdir) -I$(common_arch_srcdir) \
- -I$(freertos_srcdir)/include -I$(srcdir) -I$(srcdir)/port \
- -DTEXT_START=$(BOARD_TEXT_START) \
- -DUSR_STACK_SIZE=$(BOARD_USR_STACK_SIZE)
-
-ifeq ($(BOARD_SMP), y)
-CPPFLAGS += -DBOARD_SMP
-endif
-ifeq ($(BOARD_SECURE_EXTN),y)
-CPPFLAGS += -DARM_SECURE_EXTN_IMPLEMENTED
-endif
-
-CFLAGS = -mtune=cortex-a9 -march=armv7-a -Wall -Werror \
- -nostdlib -msoft-float -marm
-ASFLAGS = -D__ASSEMBLY__ $(CFLAGS)
-LDFLAGS = -Wl,-T$(LINK_SCRIPT_GEN) -nostdlib -Wl,--build-id=none
-LDLIBS = -lgcc -Wl,-T$(LINK_SCRIPT_GEN)
-
-# --------- binary and elf targets
-
-TARGET_NAME = freertos
-BIN_TARGETS = $(objdir)/$(TARGET_NAME).bin $(objdir)/$(TARGET_NAME).patched.bin
-TARGETS = $(BIN_TARGETS) $(BIN_TARGETS:%.bin=%.elf)
-
-# assemble final list of source and object files
-SRCS = $(sort $(FREERTOS_SRCS) \
- $(addprefix $(common_srcdir)/,$(COMMON_SRCS)) \
- $(addprefix $(common_arch_srcdir)/,$(COMMON_ARCH_SRCS)) \
- $(addprefix $(srcdir)/,$(OTHER_SRCS)))
-OBJS = $(patsubst $(basedir)/%,$(builddir)/%.o,$(basename $(SRCS)))
-
-LINK_SCRIPT_GEN = $(patsubst $(basedir)/%,$(builddir)/%.lnk,$(basename $(LINK_SCRIPT)))
-
-ALL_DEPS = $(OBJS:%.o=%.d)
-
-all: $(TARGETS)
-PHONY += all
-
-$(objdir)/%.bin: $(objdir)/%.elf
- $(call cmd-objcopy,$@,$<)
-
-$(objdir)/%.patched.elf: $(objdir)/%.elf
- $(call cmd-patch-elf,$@,$<)
-
-$(objdir)/$(TARGET_NAME).elf: $(LINK_SCRIPT_GEN)
-
-$(objdir)/$(TARGET_NAME).elf: $(OBJS)
- $(call cmd-ld,$@,$^)
-
-$(builddir)/%.lnk: $(basedir)/%.ld
- $(call cmd-cpp,$@,$<)
-
-$(builddir)/%.o: $(basedir)/%.c
- $(call cmd-cc,$@,$<)
-
-$(builddir)/%.o: $(basedir)/%.S
- $(call cmd-as,$@,$<)
-
-$(builddir)/%.d: $(basedir)/%.c
- $(call cmd-cc-dep,$@,$<)
-
-$(builddir)/%.d: $(basedir)/%.S
- $(call cmd-cc-dep,$@,$<)
-
-CLEAN_TARGETS = clean-deps clean-objs clean-targets clean-gen
-PHONY += $(CLEAN_TARGETS)
-
-clean-deps:
- $(call cmd-delete,$(OBJS:%.o=%.d))
-
-clean-objs:
- $(call cmd-delete,$(OBJS))
-
-clean-targets:
- $(call cmd-delete,$(TARGETS))
-
-clean-gen:
- $(call cmd-delete,$(LINK_SCRIPT_GEN))
-
-clean: $(CLEAN_TARGETS)
-
-
--include $(ALL_DEPS)
-
-
-## convenience functions
-
-cmd-pp = @echo "($(1)) $(subst $(builddir)/,,$(2))"
-
-define cmd-patch-elf
- $(call cmd-pp,patch,$(1))
- $(Q)CROSS_COMPILE=$(CROSS_COMPILE) && \
- cp $(2) $(1) && \
- $(ELF2CPATCH) -f $(1) | $(CPATCH32) $(1) 0 >/dev/null
-endef
-
-define cmd-cc
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,cc,$(1))
- $(Q)$(CC) -c $(CPPFLAGS) $(CFLAGS) $(2) -o $(1)
-endef
-
-define cmd-as
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,as,$(1))
- $(Q)$(CC) -c $(CPPFLAGS) $(ASFLAGS) $(2) -o $(1)
-endef
-
-define cmd-cpp
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,cpp,$(1))
- $(Q)$(CPP) $(CPPFLAGS) $(2) | grep -v "\#" > $(1)
-endef
-
-define cmd-ld
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,ld,$(1))
- $(Q)$(CC) $(LDFLAGS) -o $(1) $(2) $(LDLIBS)
-endef
-
-define cmd-objcopy
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,copy,$(1))
- $(Q)$(OBJCOPY) -O binary $(2) $(1)
-endef
-
-define cmd-cc-dep
- $(Q)$(MKDIR_P) $(dir $@)
- $(call cmd-pp,dep,$(1))
- $(Q)echo -n `dirname $(1)`/ > $(1) && \
- $(CPP) $(CPPFLAGS) -MM $(2) >> $(1) || rm -f $(1)
-endef
-
-# empty line required
-define cmd-delete
- $(call cmd-pp,clean,$(1))
- $(Q)rm -f $(1)
-
-endef
-
-
-.PHONY: $(PHONY)
-.SUFFIXES:
-
-# Taf!
-
diff --git a/tests/arm32/vexpress-a9/freertos/README b/tests/arm32/vexpress-a9/freertos/README
deleted file mode 100644
index 6375175e..00000000
--- a/tests/arm32/vexpress-a9/freertos/README

+++ /dev/null
@@ -1,174 +0,0 @@

- _______________________________________________
-
- FREERTOS V9.0.0 ON VERSATILE EXPRESS A9 GUEST
-
- Philipp Ittershagen
- p...@shgn.de
- _______________________________________________
-
-
-From the [FreeRTOS website]:
- FreeRTOS is a market leading RTOS from Real Time Engineers
- Ltd. that supports 35 architectures and received >113000
- downloads during 2014. It is professionally developed,
- strictly quality controlled, robust, supported, and free to
- embed in commercial products without any requirement to
- expose your proprietary source code.
-
-This document describes the steps necessary to run FreeRTOS v9.0.0 as a
-guest OS in Xvisor versatile a9. The port is based on the available
-Cortex A9 Zynq ZC702 port, which is distributed in the archive under
-`Demo/CORTEX_A9_Zynq_ZC702'. Refer to the patches in `patches/' for more
-information. The provided minimal FreeRTOS demo application will set up
-two tasks communicating through a shared message queue of size 1 to
-force preemption. The interrupt handling, timer ticks, and serial I/O
-have been successfully tested.
-
-
-[FreeRTOS website] http://www.freertos.org/
-
-
-1 Build Instructions
-====================
-
- Please follow the steps below to build & run FreeRTOS v9.0.0 on a
- Versatile Express-A9 Guest with Xvisor running on QEMU Versatile
- Express-A9 host.
-
-
-1.1 Configure and build Xvisor
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
- 1. Set the build environment for Xvisor:
-
- ,----
- | export CROSS_COMPILE=arm-none-gnueabi-
- `----
-
- 2. Switch to the Xvisor source directory:
-
- ,----
- | export xvisor_src="<xvisor_source_directory>"
- | cd $xvisor_src
- `----
-
- 3. Configure Xvisor with Generic v7 default settings:
-
- ,----
- | make ARCH=arm generic-v7-defconfig
- `----
-
- 4. Build Xvisor and DTBs:
-
- ,----
- | make
- `----
-
-
-1.2 Download and build FreeRTOS v9.0.0
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
- 1. Download the FreeRTOS source zip from the [FreeRTOS download page]
- and extract the archive (the location is henceforth denoted as
- `$dl_dir').
- 2. Copy the extracted folder `FreeRTOSv9.0.0/FreeRTOS' into the xvisor
- tree at `$xvisor_src/tests/arm32/vexpress-a9/freertos':
-
- ,----
- | cp -r $dl_dir/FreeRTOSv9.0.0/FreeRTOS \
- | tests/arm32/vexpress-a9/freertos
- `----
-
- 3. Switch to the Xvisor freertos guest directory and copy the existing
- Cortex A9 port files to apply the patches[1] for the vexpress-a9
- board:
-
- ,----
- | cd tests/arm32/vexpress-a9/freertos
- | mkdir -p port
- | cp FreeRTOS/Source/portable/GCC/ARM_CA9/* port/
- | patch -p0 < patches/ports.patch
- `----
-
- 4. Copy the existing `FreeRTOSConfig.h' from the Zynq application and
- apply the patch[2]:
-
- ,----
- | cp FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h .
- | patch -p0 < patches/freertos-config.patch
- `----
-
- 5. Build the FreeRTOS image (remember to set `$CROSS_COMPILE' if you
- perform this step separately):
-
- ,----
- | export CROSS_COMPILE=arm-none-eabi-
- | make
- `----
-
-
- [FreeRTOS download page] http://www.freertos.org/a00104.html
-
-
-1.3 Create the disk image and launch QEMU
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
- 1. Switch to `$xvisor_src' and create the disk image for Xvisor:
-
- ,----
- | cd $xvisor_src
- | dtc=dtc
- | bindir=./build/disk/images/arm32/vexpress-a9
- | system_dir=./build/disk/system
- | img_dir=./build/disk/images/arm32
- | srcdir=./tests/arm32/vexpress-a9
- |
- | mkdir -p $system_dir
- | mkdir -p $bindir
- |
- | cp -f ./docs/banner/roman.txt $system_dir/banner.txt
- | cp -f ./docs/logo/xvisor_logo_name.ppm $system_dir/logo.ppm
- | $dtc -q -I dts -O dtb -o $img_dir/vexpress-a9-guest.dtb $srcdir/vexpress-a9-guest.dts
- | cp -f ./build/$srcdir/freertos/freertos.patched.bin $bindir/freertos.bin
- | cp -f $srcdir/freertos/nor_flash.list $bindir/nor_flash.list
- | cp -f $srcdir/xscript/one_guest_vexpress-a9.xscript ./build/disk/boot.xscript
- | genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
- `----
-
- 2. Launch QEMU:
-
- ,----
- | qemu-system-arm -M vexpress-a9 -m 512M -display none -serial stdio \
- | -kernel build/vmm.bin \
- | -dtb build/arch/arm/dts/arm/vexpress-v2p-ca9.dtb \
- | -initrd build/disk.img
- `----
-
- 3. Kick Guest0 for starting FreeRTOS:
-
- ,----
- | XVisor# guest kick guest0
- `----
-
- 4. Bind to virtual UART:
-
- ,----
- | XVisor# vserial bind guest0/uart0
- `----
-
- You should now see output from the send and receive tasks.
-
-
-
-Footnotes
-_________
-
-[1] The main difference in porting the existing FreeRTOS implementation
-is the lack of a hardware FPU which forces us to manually remove the
-unsupported assembly instructions. Refer to the patch files for more
-information.
-
-[2] The configuration is based on the provided demo application for the
-Zynq board. We disable some calls to the Xilinx board-support package
-and adjust the interrupt settings. Refer to the patch files for more
-information.
diff --git a/tests/arm32/vexpress-a9/freertos/arm_entry_v7.S b/tests/arm32/vexpress-a9/freertos/arm_entry_v7.S
deleted file mode 100644
index f35048f7..00000000
--- a/tests/arm32/vexpress-a9/freertos/arm_entry_v7.S
+++ /dev/null
@@ -1,301 +0,0 @@

-/**
- * Copyright (c) 2012 Anup Patel.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file arm_entry_v7.S

- * @author Anup Patel (an...@brainfault.org)

- * @author Sukanto Ghosh (sukant...@gmail.com)

- * @author Philipp Ittershagen <p...@shgn.de>
- * @brief Entry point code for FreeRTOS
- */
-
-#include <arm_asm_macro.h>
-#include <gic_config.h>
-#include <arch_smp.h>
-
-.extern FreeRTOS_IRQ_Handler
-.extern FreeRTOS_SWI_Handler
-
- /*
- * Basic firmware could be loaded any where in memory by
- * boot loaders.
- * The _start function ensures that it exectues from intended
- * base address provided at compile time.
- */
- .section .expvect, "ax", %progbits
- .globl _start
-_start:
- add r0, pc, #-0x8
- cpsid if
-
-#ifdef BOARD_SMP
- /* Core-1 should spin and core-0 should go ahead */
- mrc p15, 0, r5, c0, c0, 5
- ands r5, r5, #0x3
- bne _secondary_loop
-#endif
-
- ldr r1, __code_start
- sub r6, r0, r1 /* r1 -> Load Start - Exec Start */
- /*
- * r6 -> offset between binary execution and load addresses
- * We need to ensure that when we jump to reset code, we are executing
- * from intended execution address. If necessary do relocation from
- * load memory to execution memory.
- */
- ldr r1, __reloc_region_start /* r1 -> execution address of reloc_region_start */
- ldr r2, __reloc_region_end
- sub r2, r2, r1 /* r2 -> reloc_region size */
- add r0, r1, r6 /* r0 -> load address of reloc_region start */
- bl _reloc_region
-
- /*
- * Manually zero out the zero region (bss + heap)
- */
- ldr r1, __zero_region_start
- ldr r2, __zero_region_end
- mov r7, #0x0
- mov r8, #0x0
- mov r9, #0x0
- mov r10, #0x0
-_zeroing_loop:
- cmp r1, r2
- bge _zeroing_done
- stmia r1!, {r7 - r10}
- b _zeroing_loop
-_zeroing_done:
-
- /*
- * Enable I-Cache
- */
- mrc p15, 0, r0, c1, c0, 0
- ldr r1, __sctlr_mmu_clear
- ldr r2, __sctlr_mmu_set

- and r0, r0, r1

- orr r0, r0, r2

- mcr p15, 0, r0, c1, c0, 0
-

-_jump_to_exec:

- ldr pc, __reset
-

-__code_start:
- .word _code_start
-__reloc_region_start:
- .word _reloc_region_start
-__reloc_region_end:
- .word _reloc_region_end
-__zero_region_start:
- .word _zero_region_start
-__zero_region_end:
- .word _zero_region_end
-__heap_start:
- .word _heap_start
-__heap_end:
- .word _heap_end
-__sctlr_mmu_clear:
- .word ~(SCTLR_A_MASK)
-__sctlr_mmu_set:
- .word (SCTLR_I_MASK)
-
- /*
- * Copies data from source to destination taking care of even
- * overlapping regions

- * Arguments:
- * r0 -> source address
- * r1 -> destination address
- * r2 -> byte count

- * Unmodified gprs: r4, r5, r6, r11, r12
- */
-_reloc_region:
- mov r3, #0
- cmp r0, r1
- beq _reloc_done
- blt _rev_copy
-_fwd_loop:
- cmp r3, r2
- bge _reloc_done
- ldmia r0!, {r7 - r10}
- stmia r1!, {r7 - r10}
- add r3, r3, #16
- b _fwd_loop
-_rev_copy:

- add r0, r0, r2

- add r1, r1, r2
-_rev_loop:
- cmp r3, r2
- bge _reloc_done
- ldmdb r0!, {r7 - r10}
- stmdb r1!, {r7 - r10}
- add r3, r3, #16
- b _rev_loop
-_reloc_done:

- bx lr
-
-

-#ifdef BOARD_SMP
-_secondary_loop:
- /* Enable the GIC CPU interface for this core */
- ldr r0, _gic_cpu_addr
- mov r1, #1
- str r1, [r0]
- mov r1, #0xFF
- str r1, [r0, #4]
- ldr r0, _sys_flags_addr
-1:
- /* Wait for interrupt before checking SPIN_ADDR */
- wfi
- ldr r1, [r0]
- teq r1, #0
- /* Repeat if SPIN_ADDR == 0 */
- beq 1b
- /* Jump to the address stored the the SPIN_ADDR register */
- bx r1
-
-_gic_cpu_addr:
- .word GIC_CPU_BASE
-_sys_flags_addr:
- .word ARCH_SMP_SPIN_ADDR
-#endif
-
- .section .expvect, "ax", %progbits
- .align 5 /* Required for VBAR */

- .globl _start_vect
-_start_vect:
- ldr pc, __reset
- ldr pc, __undefined_instruction
- ldr pc, __software_interrupt
- ldr pc, __prefetch_abort
- ldr pc, __data_abort
- ldr pc, __not_used
- ldr pc, __irq
- ldr pc, __fiq
-__reset:
- .word _reset
-__undefined_instruction:

- .word _undefined_instruction
-__software_interrupt:
- .word FreeRTOS_SWI_Handler

-__prefetch_abort:
- .word _prefetch_abort
-__data_abort:
- .word _data_abort
-__not_used:
- .word _not_used
-__irq:

- .word FreeRTOS_IRQ_Handler

-__fiq:
- .word _fiq
- .global _end_vect
-_end_vect:
-

-__svc_stack_end:
- .word _svc_stack_end
-__und_stack_end:
- .word _und_stack_end
-__abt_stack_end:
- .word _abt_stack_end
-__irq_stack_end:
- .word _irq_stack_end
-__fiq_stack_end:
- .word _fiq_stack_end

-__usr_stack_end:
- .word _usr_stack_end
-
- .globl _reset
-_reset:

- /* Clear a register for temporary usage */
- mov r8, #0
- /* Disable IRQ & FIQ */

- cpsid if

- /* Set Supervisor Mode Stack */

- SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
- SET_CURRENT_STACK __svc_stack_end

- /* Set Undefined Mode Stack */

- SET_CURRENT_MODE CPSR_MODE_UNDEFINED
- SET_CURRENT_STACK __und_stack_end

- /* Set Abort Mode Stack */

- SET_CURRENT_MODE CPSR_MODE_ABORT
- SET_CURRENT_STACK __abt_stack_end

- /* Set IRQ Mode Stack */

- SET_CURRENT_MODE CPSR_MODE_IRQ
- SET_CURRENT_STACK __irq_stack_end

- /* Set FIQ Mode Stack */

- SET_CURRENT_MODE CPSR_MODE_FIQ
- SET_CURRENT_STACK __fiq_stack_end
- /* Set System Mode Stack */
- SET_CURRENT_MODE CPSR_MODE_SYSTEM
- SET_CURRENT_STACK __usr_stack_end

- /* Set to Supervisor Mode */

- SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
- /* Call init function */
- bl arm_init
- /* Call main function */
- bl arm_main

- /* We should never reach here */
- b .
-

- .globl _switch_to_user_mode
-_switch_to_user_mode:
- sub r0, sp
- mov r1, lr
- SET_CURRENT_MODE CPSR_MODE_USER
- mov sp, r0
- mov lr, r1
- bx lr
-
-START_EXCEPTION_HANDLER _undefined_instruction, 4
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_undefined_instruction
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _software_interrupt, 4
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_software_interrupt
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _prefetch_abort, 4
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_prefetch_abort
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _data_abort, 8
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_data_abort
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _not_used, 4
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_not_used
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _irq, 4
- PUSH_USER_REGS
- CALL_EXCEPTION_CFUNC do_irq
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
-START_EXCEPTION_HANDLER _fiq, 4
- PUSH_FIQUSER_REGS
- CALL_EXCEPTION_CFUNC do_fiq
- PULL_USER_REGS
-END_EXCEPTION_HANDLER
-
diff --git a/tests/arm32/vexpress-a9/freertos/glue.c b/tests/arm32/vexpress-a9/freertos/glue.c
deleted file mode 100644
index ce567386..00000000
--- a/tests/arm32/vexpress-a9/freertos/glue.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/**
- * Copyright (c) 2016 Philipp Ittershagen.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file glue.c
- * @author Philipp Ittershagen <p...@shgn.de>
- * @brief Implementation of architecture-dependent FreeRTOS functions.
- */
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#include <arch_io.h>
-#include <arm_plat.h>
-#include <arch_board.h>
-#include <basic_irq.h>
-#include <basic_stdio.h>
-
-extern void main_blinky(void);
-
-/* no MMU support, disabling firmware interrupt handlers */
-void arm_mmu_syscall(struct pt_regs *regs) {}
-void arm_mmu_prefetch_abort(struct pt_regs *regs) {}
-void arm_mmu_data_abort(struct pt_regs *regs) {}
-
-#define TIMER_INTCLR 0x0c
-
-static int timer_tick_handler(u32 irq, struct pt_regs *regs)
-{
- FreeRTOS_Tick_Handler();
- arch_writel(1, (void *)(V2M_TIMER0 + TIMER_INTCLR));

- return 0;
-}
-

-/* configure the timer for FreeRTOS */
-void vConfigureTickInterrupt()
-{
- arch_board_timer_init(configTICK_RATE_HZ);
-
- /* 'steal' interrupt handler */
- basic_irq_register(IRQ_V2M_TIMER0, &timer_tick_handler);
-
- arch_board_timer_enable();
-}
-
-#define MAX_IRQS 1024
-
-void vApplicationIRQHandler(u32 irq)
-{
- extern irq_handler_t irq_hndls[MAX_IRQS];
- if (arch_board_pic_ack_irq(irq)) {
- while (1)
- ;
- }
- if (irq_hndls[irq]) {
- if (irq_hndls[irq](irq, NULL))
- while (1)
- ;
- }
-}
-
-void vAssertCalled(const char *pcFile, unsigned long ulLine)
-{
- volatile unsigned long ul = 0;
-
- (void)pcFile;
- (void)ulLine;
-
- taskENTER_CRITICAL();
- {
- basic_printf("%s: file=%s, line=%d!\n", __func__, pcFile, (int)ulLine);
- /* Set ul to a non-zero value using the debugger to
- step out of this function. */
- while (ul == 0) {
- portNOP();
- }
- }
- taskEXIT_CRITICAL();
-}
-
-void arm_init(void)
-{
- basic_irq_disable();
- basic_irq_setup();
- basic_stdio_init();
-
- /* FreeRTOS will call vConfigureTickInterrupt and enable IRQs */
-}
-
-int arm_main(void)
-{
- basic_puts("Welcome to FreeRTOS!\n");
-
- main_blinky();
-
- /* Don't expect to reach here. */

- return 0;
-}
-

-/* configUSE_STATIC_ALLOCATION is set to 1, so the application must
-provide an implementation of vApplicationGetIdleTaskMemory() to
-provide the memory that is used by the Idle task. */
-void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer,
- StackType_t **ppxIdleTaskStackBuffer,
- uint32_t *pulIdleTaskStackSize)
-{
- /* If the buffers to be provided to the Idle task are declared
- inside this function then they must be declared static -
- otherwise they will be allocated on the stack and so not
- exists after this function exits. */
- static StaticTask_t xIdleTaskTCB;
- static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
-
- /* Pass out a pointer to the StaticTask_t structure in which
- the Idle task's state will be stored. */
- *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
-
- /* Pass out the array that will be used as the Idle task's stack. */
- *ppxIdleTaskStackBuffer = uxIdleTaskStack;
-
- /* Pass out the size of the array pointed to by
- *ppxIdleTaskStackBuffer. Note that, as the array is
- necessarily of type StackType_t, configMINIMAL_STACK_SIZE is
- specified in words, not bytes. */
- *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
-}
diff --git a/tests/arm32/vexpress-a9/freertos/main.c b/tests/arm32/vexpress-a9/freertos/main.c
deleted file mode 100644
index 081c962a..00000000
--- a/tests/arm32/vexpress-a9/freertos/main.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- * Copyright (c) 2016 Philipp Ittershagen.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file main.c
- * @author Philipp Ittershagen <p...@shgn.de>
- * @brief FreeRTOS sample application
- */
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-#include <basic_stdio.h>
-
-/* priorities at which the tasks are created. */
-#define mainQUEUE_RECEIVE_TASK_PRIORITY (tskIDLE_PRIORITY + 2)
-#define mainQUEUE_SEND_TASK_PRIORITY (tskIDLE_PRIORITY + 1)
-
-/* The rate at which data is sent to the queue. The 200ms value is
-converted to ticks using the portTICK_PERIOD_MS constant. */
-#define mainQUEUE_SEND_FREQUENCY_MS (20 / portTICK_PERIOD_MS)
-
-/* The number of items the queue can hold. This is 1 as the receive
-task will remove items as they are added, meaning the send task should
-always find the queue empty. */
-#define mainQUEUE_LENGTH (1)
-
-static void recv_task(void *params);
-static void send_task(void *params);
-
-static QueueHandle_t queue_hndl = NULL;
-
-void main_blinky(void)
-{
- queue_hndl = xQueueCreate(mainQUEUE_LENGTH, sizeof(uint32_t));
-
- if (queue_hndl != NULL) {
-
- xTaskCreate(recv_task, "RX", configMINIMAL_STACK_SIZE, NULL,
- mainQUEUE_RECEIVE_TASK_PRIORITY, NULL);
-
- xTaskCreate(send_task, "TX", configMINIMAL_STACK_SIZE, NULL,
- mainQUEUE_SEND_TASK_PRIORITY, NULL);
-
- vTaskStartScheduler();
- }
-
- for (;;)
- ;
-}
-
-static void send_task(void *params)
-{
- TickType_t next_wake_time = 0;
- const unsigned long send_val = 100UL;
-
- (void)params;
-
- for (;;) {
- vTaskDelayUntil(&next_wake_time, mainQUEUE_SEND_FREQUENCY_MS);
-
-#if configUSE_TRACE_FACILITY == 1
- basic_printf("%s @%d\n", __func__, xTaskGetTickCount());
-#endif
-
- xQueueSend(queue_hndl, &send_val, 0U);
- }
-}
-
-static void recv_task(void *params)
-{
- unsigned long rxval;
- (void)params;
-
- for (;;) {
- xQueueReceive(queue_hndl, &rxval, portMAX_DELAY);
-
-#if configUSE_TRACE_FACILITY == 1
- basic_printf("%s @%d\n", __func__, xTaskGetTickCount());
-#endif
- }
-}
diff --git a/tests/arm32/vexpress-a9/freertos/nor_flash.list b/tests/arm32/vexpress-a9/freertos/nor_flash.list
deleted file mode 100644
index 5f55b44a..00000000
--- a/tests/arm32/vexpress-a9/freertos/nor_flash.list
+++ /dev/null
@@ -1 +0,0 @@
-0x40000000 ./freertos.bin
diff --git a/tests/arm32/vexpress-a9/freertos/patches/freertos-config.patch b/tests/arm32/vexpress-a9/freertos/patches/freertos-config.patch
deleted file mode 100644
index 0ad37137..00000000
--- a/tests/arm32/vexpress-a9/freertos/patches/freertos-config.patch

+++ /dev/null
@@ -1,124 +0,0 @@

---- FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h 2016-08-27 23:12:32.305660356 +0200
-+++ ./FreeRTOSConfig.h 2016-08-28 02:08:32.757019993 +0200
-@@ -67,10 +67,12 @@
- 1 tab == 4 spaces!
- */
-
-+#include <arm_plat.h>
-+#include <timer/sp804.h>
-+
- #ifndef FREERTOS_CONFIG_H
- #define FREERTOS_CONFIG_H
-
--#include "xparameters.h"
-
- /*-----------------------------------------------------------
- * Application specific definitions.
-@@ -108,7 +110,7 @@
- * setting configMAX_API_CALL_INTERRUPT_PRIORITY 255 represents the lowest
- * priority.
- */
--#define configMAX_API_CALL_INTERRUPT_PRIORITY 18
-+#define configMAX_API_CALL_INTERRUPT_PRIORITY 10
-
- #define configCPU_CLOCK_HZ 100000000UL
- #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-@@ -116,8 +118,8 @@
- #define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
- #define configPERIPHERAL_CLOCK_HZ ( 33333000UL )
- #define configUSE_PREEMPTION 1
--#define configUSE_IDLE_HOOK 1
--#define configUSE_TICK_HOOK 1
-+#define configUSE_IDLE_HOOK 0
-+#define configUSE_TICK_HOOK 0
- #define configMAX_PRIORITIES ( 7 )
- #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 250 ) /* Large in case configUSE_TASK_FPU_SUPPORT is 2 in which case all tasks have an FPU context. */
- #define configTOTAL_HEAP_SIZE ( 90 * 1024 )
-@@ -127,13 +129,20 @@
- #define configIDLE_SHOULD_YIELD 1
- #define configUSE_MUTEXES 1
- #define configQUEUE_REGISTRY_SIZE 8
--#define configCHECK_FOR_STACK_OVERFLOW 2
-+#define configCHECK_FOR_STACK_OVERFLOW 0
- #define configUSE_RECURSIVE_MUTEXES 1
--#define configUSE_MALLOC_FAILED_HOOK 1
-+#define configUSE_MALLOC_FAILED_HOOK 0
- #define configUSE_APPLICATION_TASK_TAG 0
- #define configUSE_COUNTING_SEMAPHORES 1
--#define configUSE_QUEUE_SETS 1
-+#define configUSE_QUEUE_SETS 0
- #define configSUPPORT_STATIC_ALLOCATION 1
-+#define configAPPLICATION_ALLOCATED_HEAP 1
-+#define ucHeap _heap_start
-+
-+#define configGENERATE_RUN_TIME_STATS 0
-+
-+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
-+#define portGET_RUN_TIME_COUNTER_VALUE() sp804_timestamp()
-
- /* Include the query-heap CLI command to query the free heap space. */
- #define configINCLUDE_QUERY_HEAP_COMMAND 1
-@@ -143,28 +152,21 @@
- #define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
- /* Software timer definitions. */
--#define configUSE_TIMERS 1
-+#define configUSE_TIMERS 0
- #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
- #define configTIMER_QUEUE_LENGTH 5
- #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
-
--/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or undefined) then each task will
--be created without an FPU context, and a task must call vTaskUsesFPU() before
--making use of any FPU registers. If configUSE_TASK_FPU_SUPPORT is set to 2 then
--tasks are created with an FPU context by default, and calling vTaskUsesFPU() has
--no effect. */
--#define configUSE_TASK_FPU_SUPPORT 2
--
- /* Set the following definitions to 1 to include the API function, or zero
- to exclude the API function. */
- #define INCLUDE_vTaskPrioritySet 1
- #define INCLUDE_uxTaskPriorityGet 1
--#define INCLUDE_vTaskDelete 1
-+#define INCLUDE_vTaskDelete 0
- #define INCLUDE_vTaskCleanUpResources 1
- #define INCLUDE_vTaskSuspend 1
- #define INCLUDE_vTaskDelayUntil 1
- #define INCLUDE_vTaskDelay 1
--#define INCLUDE_xTimerPendFunctionCall 1
-+#define INCLUDE_xTimerPendFunctionCall 0
- #define INCLUDE_eTaskGetState 1
- #define INCLUDE_xTaskAbortDelay 1
- #define INCLUDE_xTaskGetTaskHandle 1
-@@ -176,14 +178,6 @@
- FreeRTOS/Source/tasks.c for limitations. */
- #define configUSE_STATS_FORMATTING_FUNCTIONS 1
-
--/* The private watchdog is used to generate run time stats. */
--#include "xscuwdt.h"
--extern XScuWdt xWatchDogInstance;
--extern void vInitialiseTimerForRunTimeStats( void );
--#define configGENERATE_RUN_TIME_STATS 1
--#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseTimerForRunTimeStats()
--#define portGET_RUN_TIME_COUNTER_VALUE() ( ( 0xffffffffUL - XScuWdt_ReadReg( xWatchDogInstance.Config.BaseAddr, XSCUWDT_COUNTER_OFFSET ) ) >> 1 )
--
- /* The size of the global output buffer that is available for use when there
- are multiple command interpreters running at once (for example, one on a UART
- and one on TCP/IP). This is done to prevent an output buffer being defined by
-@@ -216,14 +210,11 @@
- void vConfigureTickInterrupt( void );
- #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()
-
--void vClearTickInterrupt( void );
--#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()
--
- /* The following constant describe the hardware, and are correct for the
- Zynq MPU. */
--#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_PS7_SCUGIC_0_DIST_BASEADDR )
-+#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( A9_MPCORE_GIC_DIST )
- #define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( -0xf00 )
--#define configUNIQUE_INTERRUPT_PRIORITIES 32
-+#define configUNIQUE_INTERRUPT_PRIORITIES 16
-
-
-
diff --git a/tests/arm32/vexpress-a9/freertos/patches/ports.patch b/tests/arm32/vexpress-a9/freertos/patches/ports.patch
deleted file mode 100644
index d498923f..00000000
--- a/tests/arm32/vexpress-a9/freertos/patches/ports.patch

+++ /dev/null
@@ -1,147 +0,0 @@

---- FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S 2016-08-27 23:12:33.373647831 +0200
-+++ port/portASM.S 2016-08-28 00:28:06.170382688 +0200
-@@ -93,21 +93,6 @@
- LDR R1, [R2]
- PUSH {R1}
-
-- /* Does the task have a floating point context that needs saving? If
-- ulPortTaskHasFPUContext is 0 then no. */
-- LDR R2, ulPortTaskHasFPUContextConst
-- LDR R3, [R2]
-- CMP R3, #0
--
-- /* Save the floating point context, if any. */
-- FMRXNE R1, FPSCR
-- VPUSHNE {D0-D15}
-- VPUSHNE {D16-D31}
-- PUSHNE {R1}
--
-- /* Save ulPortTaskHasFPUContext itself. */
-- PUSH {R3}
--
- /* Save the stack pointer in the TCB. */
- LDR R0, pxCurrentTCBConst
- LDR R1, [R0]
-@@ -124,19 +109,6 @@
- LDR R1, [R0]
- LDR SP, [R1]
-
-- /* Is there a floating point context to restore? If the restored
-- ulPortTaskHasFPUContext is zero then no. */
-- LDR R0, ulPortTaskHasFPUContextConst
-- POP {R1}
-- STR R1, [R0]
-- CMP R1, #0
--
-- /* Restore the floating point context, if any. */
-- POPNE {R0}
-- VPOPNE {D16-D31}
-- VPOPNE {D0-D15}
-- VMSRNE FPSCR, R0
--
- /* Restore the critical section nesting depth. */
- LDR R0, ulCriticalNestingConst
- POP {R1}
-@@ -290,44 +262,6 @@
- portRESTORE_CONTEXT
-
-
--/******************************************************************************
-- * If the application provides an implementation of vApplicationIRQHandler(),
-- * then it will get called directly without saving the FPU registers on
-- * interrupt entry, and this weak implementation of
-- * vApplicationIRQHandler() will not get called.
-- *
-- * If the application provides its own implementation of
-- * vApplicationFPUSafeIRQHandler() then this implementation of
-- * vApplicationIRQHandler() will be called, save the FPU registers, and then
-- * call vApplicationFPUSafeIRQHandler().
-- *
-- * Therefore, if the application writer wants FPU registers to be saved on
-- * interrupt entry their IRQ handler must be called
-- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
-- * FPU registers to be saved on interrupt entry their IRQ handler must be
-- * called vApplicationIRQHandler().
-- *****************************************************************************/
--
--.align 4
--.weak vApplicationIRQHandler
--.type vApplicationIRQHandler, %function
--vApplicationIRQHandler:
-- PUSH {LR}
-- FMRX R1, FPSCR
-- VPUSH {D0-D15}
-- VPUSH {D16-D31}
-- PUSH {R1}
--
-- LDR r1, vApplicationFPUSafeIRQHandlerConst
-- BLX r1
--
-- POP {R0}
-- VPOP {D16-D31}
-- VPOP {D0-D15}
-- VMSR FPSCR, R0
--
-- POP {PC}
--
-
- ulICCIARConst: .word ulICCIAR
- ulICCEOIRConst: .word ulICCEOIR
---- FreeRTOS/Source/portable/GCC/ARM_CA9/port.c 2016-08-27 23:12:33.373647831 +0200
-+++ port/port.c 2016-08-28 00:28:22.170211408 +0200
-@@ -320,31 +320,6 @@
- enabled. */
- *pxTopOfStack = portNO_CRITICAL_NESTING;
-
-- #if( configUSE_TASK_FPU_SUPPORT == 1 )
-- {
-- /* The task will start without a floating point context. A task that
-- uses the floating point hardware must call vPortTaskUsesFPU() before
-- executing any floating point instructions. */
-- pxTopOfStack--;
-- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-- }
-- #elif( configUSE_TASK_FPU_SUPPORT == 2 )
-- {
-- /* The task will start with a floating point context. Leave enough
-- space for the registers - and ensure they are initialised to 0. */
-- pxTopOfStack -= portFPU_REGISTER_WORDS;
-- memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
--
-- pxTopOfStack--;
-- *pxTopOfStack = pdTRUE;
-- ulPortTaskHasFPUContext = pdTRUE;
-- }
-- #else
-- {
-- #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
-- }
-- #endif
--
- return pxTopOfStack;
- }
- /*-----------------------------------------------------------*/
-@@ -516,23 +491,6 @@
- }
- /*-----------------------------------------------------------*/
-
--#if( configUSE_TASK_FPU_SUPPORT != 2 )
--
-- void vPortTaskUsesFPU( void )
-- {
-- uint32_t ulInitialFPSCR = 0;
--
-- /* A task is registering the fact that it needs an FPU context. Set the
-- FPU flag (which is saved as part of the task context). */
-- ulPortTaskHasFPUContext = pdTRUE;
--
-- /* Initialise the floating point status register. */
-- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
-- }
--
--#endif /* configUSE_TASK_FPU_SUPPORT */
--/*-----------------------------------------------------------*/
--
- void vPortClearInterruptMask( uint32_t ulNewMaskValue )
- {
- if( ulNewMaskValue == pdFALSE )
diff --git a/tests/arm32/vexpress-a9/freertos/stdio.h b/tests/arm32/vexpress-a9/freertos/stdio.h
deleted file mode 100644
index 7fbf1a2c..00000000
--- a/tests/arm32/vexpress-a9/freertos/stdio.h

+++ /dev/null
@@ -1,32 +0,0 @@
-/**

- * Copyright (c) 2016 Philipp Ittershagen.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file stdio.h
- * @author Philipp Ittershagen <p...@shgn.de>
- * @brief Header wrapper for FreeRTOS
- */
-
-#ifndef STDIO_WRAPPER_H_INCLUDED_
-#define STDIO_WRAPPER_H_INCLUDED_
-
-#include <arch_types.h>
-#include <basic_stdio.h>
-
-#define sprintf basic_sprintf
-
-#endif /* STDIO_WRAPPER_H_INCLUDED_ */
diff --git a/tests/arm32/vexpress-a9/freertos/string.h b/tests/arm32/vexpress-a9/freertos/string.h
deleted file mode 100644
index 8958ee03..00000000
--- a/tests/arm32/vexpress-a9/freertos/string.h

+++ /dev/null
@@ -1,34 +0,0 @@

-/**
- * Copyright (c) 2016 Philipp Ittershagen.

- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *

- * @file string.h
- * @author Philipp Ittershagen <p...@shgn.de>
- * @brief Header wrapper for FreeRTOS
- */
-
-#ifndef STRING_WRAPPER_H_INCLUDED_
-#define STRING_WRAPPER_H_INCLUDED_
-
-#include <basic_string.h>
-
-#define memcpy basic_memcpy
-#define memset basic_memset
-#define strlen basic_strlen
-#define strcpy basic_strcpy
-
-#endif /* STRING_WRAPPER_H_INCLUDED_ */
diff --git a/tests/arm32/vexpress-a9/linux/README b/tests/arm32/vexpress-a9/linux/README
deleted file mode 100644
index 340172d4..00000000
--- a/tests/arm32/vexpress-a9/linux/README
+++ /dev/null
@@ -1,101 +0,0 @@
- Linux on Xvisor VExpress-A9 SMP Guest
-
-Linux is a computer operating system which is based on free and open source
-software. the underlying source code can be used, freely modified, and
-redistributed, both commercially and non-commercially, by anyone under
-licenses such as the GNU General Public License. For more information on
-Linux read the wiki page http://en.wikipedia.org/wiki/Linux
-
-Linux already contains a support for VExpress-A9 Board. We can use
-this kernel unmodified to run it as a xvisor guest. We have also provide
-VExpress-A9 defconfig for various linux kernel versions for ease in
-building kernel. To obtain Linux kernel sources visit the following
-url: http://www.kernel.org
-
-Follow the steps below to build & run Linux kernel with Busybox RootFS on
-VExpress-A9 Guest with Xvisor running on QEMU VExpress-A9 Host:
-
- [1. Build environment for Xvisor]
- # export CROSS_COMPILE=arm-none-linux-gnueabihf-
-
- [2. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [3. Configure Xvisor with Generic v7 default settings]
- # make ARCH=arm generic-v7-defconfig
-
- [4. Build Xvisor & DTBs]
- # make
-
- [5. Build Basic Firmware]
- # make -C tests/arm32/vexpress-a9/basic
-
- [6. GoTo Linux source directory]
- # cd <linux_source_directory>
-
- [7. Configure Linux in build directory]
- # sed -i 's/0xff800000UL/0xff000000UL/' arch/arm/include/asm/pgtable.h
- # cp arch/arm/configs/vexpress_defconfig arch/arm/configs/tmp-vexpress-a9_defconfig
- # <xvisor_source_directory>/tests/common/scripts/update-linux-defconfig.sh -p arch/arm/configs/tmp-vexpress-a9_defconfig -f <xvisor_source_directory>/tests/arm32/vexpress-a9/linux/linux_extra.config
- # make O=<linux_build_directory> ARCH=arm tmp-vexpress-a9_defconfig
-
- [8. Build Linux in build directory]
- # make O=<linux_build_directory> ARCH=arm Image dtbs
-
- [9. Patch Linux kernel to replace sensitive non-priviledged instructions]
- # <xvisor_source_directory>/arch/arm/cpu/arm32/elf2cpatch.py -f <linux_build_directory>/vmlinux | <xvisor_source_directory>/build/tools/cpatch/cpatch32 <linux_build_directory>/vmlinux 0
-
- [10. Extract patched Linux kernel image]
- # ${CROSS_COMPILE}objcopy -O binary <linux_build_directory>/vmlinux <linux_build_directory>/arch/arm/boot/Image
-
- [11. Create BusyBox RAMDISK to be used as RootFS for Linux kernel]
- (Note: For subsequent steps, we will assume that your RAMDISK is located at <busybox_rootfs_directory>/rootfs.img)
- (Note: Please refer tests/common/busybox/README.md for creating rootfs.img using BusyBox)
-
- [12. GoTo Xvisor source directory]
- # cd <xvisor_source_directory>
-
- [13. Create disk image for Xvisor]
- # mkdir -p ./build/disk/tmp
- # mkdir -p ./build/disk/system
- # cp -f ./docs/banner/roman.txt ./build/disk/system/banner.txt
- # cp -f ./docs/logo/xvisor_logo_name.ppm ./build/disk/system/logo.ppm
- # mkdir -p ./build/disk/images/arm32/vexpress-a9
- # dtc -q -I dts -O dtb -o ./build/disk/images/arm32/vexpress-a9-guest.dtb ./tests/arm32/vexpress-a9/vexpress-a9-guest.dts
- # cp -f ./build/tests/arm32/vexpress-a9/basic/firmware.bin.patched ./build/disk/images/arm32/vexpress-a9/firmware.bin
- # cp -f ./tests/arm32/vexpress-a9/linux/nor_flash.list ./build/disk/images/arm32/vexpress-a9/nor_flash.list
- # cp -f ./tests/arm32/vexpress-a9/linux/cmdlist ./build/disk/images/arm32/vexpress-a9/cmdlist
- # cp -f ./tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript ./build/disk/boot.xscript
- # cp -f <linux_build_directory>/arch/arm/boot/Image ./build/disk/images/arm32/vexpress-a9/Image
- # cp -f <linux_build_directory>/arch/arm/boot/dts/vexpress-v2p-ca9.dtb ./build/disk/images/arm32/vexpress-a9/vexpress-v2p-ca9.dtb
- # cp -f <busybox_rootfs_directory>/rootfs.img ./build/disk/images/arm32/vexpress-a9/rootfs.img
- # genext2fs -B 1024 -b 32768 -d ./build/disk ./build/disk.img
-
- [14. Launch QEMU]
- # qemu-system-arm -M vexpress-a9 -m 512M -display none -serial stdio -kernel build/vmm.bin -dtb build/arch/arm/dts/arm/vexpress-v2p-ca9.dtb -initrd build/disk.img
-
- [15. Kick Guest0 for starting Basic Firmware]
- XVisor# guest kick guest0
-
- [16. Bind to virtual UART0 of Linux Guest]
- XVisor# vserial bind guest0/uart0
-
- [17. Copy linux from NOR flash to RAM and start linux booting from RAM]
- [guest0/uart0] basic# autoexec
- (Note: "autoexec" is a short-cut command)
- (Note: The <xvisor_source_directory>/tests/arm32/vexpress-a9/linux/cmdlist file
- which we have added to guest NOR flash contains set of commands for booting
- linux from NOR flash)
-
- [18. Wait for Linux prompt to come-up and then try out some commands]
- [guest0/uart0] / # ls
-
- [19. Enter character seqence 'ESCAPE+x+q" return to Xvisor prompt]
- [guest0/uart0] / #
-
- (Note: replace all <> brackets based on your workspace)
- (Note: some of the above steps will need to be adapted for other
- types of ARM host)
- (Note: for more info on your desired ARM host refer docs/arm/)
- (Note: you are free to change the ordering of above steps based
- on your workspace)
diff --git a/tests/arm32/vexpress-a9/linux/cmdlist b/tests/arm32/vexpress-a9/linux/cmdlist
deleted file mode 100644
index 4653538a..00000000
--- a/tests/arm32/vexpress-a9/linux/cmdlist
+++ /dev/null
@@ -1,4 +0,0 @@
-copy 0x60008000 0x40100000 0x16F0000
-copy 0x62000000 0x417F0000 0x010000
-copy 0x62100000 0x41800000 0x800000
-start_linux_fdt 0x60008000 0x62000000 0x62100000 0x800000
diff --git a/tests/arm32/vexpress-a9/linux/linux_extra.config b/tests/arm32/vexpress-a9/linux/linux_extra.config
deleted file mode 100644
index d7158dc9..00000000
--- a/tests/arm32/vexpress-a9/linux/linux_extra.config
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SWAP=n
-CONFIG_NO_HZ_FULL=n
-CONFIG_NO_HZ_IDLE=y
-CONFIG_DRM=n
diff --git a/tests/arm32/vexpress-a9/linux/nor_flash.list b/tests/arm32/vexpress-a9/linux/nor_flash.list
deleted file mode 100644
index cd4fc7f1..00000000
--- a/tests/arm32/vexpress-a9/linux/nor_flash.list
+++ /dev/null
@@ -1,5 +0,0 @@
-0x40000000 ./firmware.bin
-0x400FF000 ./cmdlist
-0x40100000 ./Image
-0x417F0000 ./vexpress-v2p-ca9.dtb
-0x41800000 ./rootfs.img
diff --git a/tests/arm32/vexpress-a9/vexpress-a9-guest.dts b/tests/arm32/vexpress-a9/vexpress-a9-guest.dts
deleted file mode 100644
index b1dea51e..00000000
--- a/tests/arm32/vexpress-a9/vexpress-a9-guest.dts
+++ /dev/null
@@ -1,413 +0,0 @@
-
-/dts-v1/;
-
-/ {
- model = "arm,vexpress,v2p-ca9";
- device_type = "guest";
- psci_version = <2>;
-
- aliases {
- mem0 = &MEM0;
- net0 = &NET0;
- net1 = &NET1;
- disk0 = &DISK0;
- };
-
- vcpu_template {
- device_type = "vcpu";
- compatible = "armv7a,cortex-a9";
- start_pc = <0x40000000>;
- };
-
- aspace {
- guest_irq_count = <2048>;
-
- /* Assume the REMAP region is mapped to DDR */
- mem1 {
- manifest_type = "alias";
- address_type = "memory";
- guest_physical_addr = <0x00000000>;
- alias_physical_addr = <0x60000000>;
- physical_size = <0x04000000>;
- device_type = "ram";
- };
-
- MEM0: mem0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x60000000>;
- physical_size = <0x00000000>; /* Override this before guest creation */
- align_order = <21>; /* Align alloced memory to 2MB */
- device_type = "alloced_ram";
- };
-
- sysctl {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10000000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "vexpress,a9";
- mux_in_irq = <1200 1201>;
- mux_out_irq = <1202>;
- };
-
- sysctrl0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10001000>;
- physical_size = <0x1000>;
- device_type = "sys";
- compatible = "primecell,sp810";
- };
-
- pcie_i2c { /* No I2C */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10002000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- aaci { /* No Audio Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10004000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- mmc0 { /* No Multimedia Card Interface */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10005000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- kmi0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10006000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,keyboard";
- interrupts = <44>;
- };
-
- kmi1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10007000>;
- physical_size = <0x1000>;
- device_type = "input";
- compatible = "primecell,arm,pl050,mouse";

- interrupts = <45>;
- };
-

- uart0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10009000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <37>;
- };
-
- uart1 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000A000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <38>;
- };
-
- uart2 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000B000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <39>;
- };
-
- uart3 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000C000>;
- physical_size = <0x1000>;
- device_type = "serial";
- compatible = "primecell,arm,pl011";
- fifo_size = <1024>;
- interrupts = <40>;
- };
-
- wdt {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1000F000>;
- physical_size = <0x1000>;
- device_type = "watchdog";
- compatible = "primecell,sp805";

- interrupts = <32>;
- };
-

- timer0_1_legacy {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10011000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <34>;
- };
-
- timer2_3_legacy {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10012000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <35>;
- };
-
- ddc_i2c { /* No I2C */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10016000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- rtc0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10017000>;
- physical_size = <0x1000>;
- device_type = "rtc";
- compatible = "primecell,pl031";
- interrupts = <36>;
- };
-
- cf { /* No PATA Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1001A000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- legacy-clcd { /* No Legacy CLCD */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1001F000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- clcd {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x10020000>;
- physical_size = <0x1000>;
- device_type = "display";
- compatible = "primecell,pl111";

- interrupts = <46>;
- };
-

- dmc { /* No DMC */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E0000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- smc { /* No SMC */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E1000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- timer_daughter {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E4000>;
- physical_size = <0x1000>;
- device_type = "timer";
- compatible = "primecell,sp804";
- interrupts = <80>;
- };
-
- watchdog {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E5000>;
- physical_size = <0x1000>;
- device_type = "watchdog";
- compatible = "primecell,sp805";
- interrupts = <84>;
- };
-
- gpio { /* No GPIO */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x100E8000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
-
- priv0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1E000000>;
- physical_size = <0x2000>;
- device_type = "misc";
- compatible = "arm,a9mpcore";
- timer_irq = <29 30>;
- parent_irq = <6>;
- };
-
- l2x0 {
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x1E00A000>;
- physical_size = <0x1000>;
- device_type = "cache";
- compatible = "corelink,l2c-310";
- };
-
- vminfo {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "sys";
- compatible = "vminfo-0.1";
- guest_physical_addr = <0x20000000>;
- physical_size = <0x1000>;
- ram0_base = <0x60000000>;
- };
-
- NET0: virtio-net0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <1>;
- guest_physical_addr = <0x20100000>;
- physical_size = <0x1000>;
- switch = ""; /* Override this before guest creation */
- interrupts = <82>;
- };
-
- DISK0: virtio-blk0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <2>;
- guest_physical_addr = <0x20200000>;
- physical_size = <0x1000>;
- blkdev = ""; /* Override this before guest creation */
- interrupts = <85>;
- };
-
- virtio-con0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <3>;
- guest_physical_addr = <0x20300000>;
- physical_size = <0x1000>;
- interrupts = <86>;
- };
-
- virtio-rpmsg0 {
- manifest_type = "virtual";
- address_type = "memory";
- device_type = "virtio";
- compatible = "virtio,mmio";
- virtio_type = <7>;
- guest_physical_addr = <0x20400000>;
- physical_size = <0x1000>;
- interrupts = <87>;
- node_ns_name = "rpmsg_chrdev";
- };
-
- nor_flash0 {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x40000000>;
- physical_size = <0x02000000>;
- device_type = "alloced_rom";
- align_order = <21>; /* Align alloced memory to 2MB */
- };
-
- nor_flash1 { /* No Second NOR flash */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x44000000>;
- physical_size = <0x01000000>; /* 16 MB */
- device_type = "misc";
- compatible = "zero";
- };
-
- sram {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x48000000>;
- physical_size = <0x02000000>;
- device_type = "alloced_ram";
- align_order = <21>; /* Align alloced memory to 2MB */
- };
-
- videoram {
- manifest_type = "real";
- address_type = "memory";
- guest_physical_addr = <0x4C000000>;
- physical_size = <0x00800000>;
- device_type = "alloced_ram";
- align_order = <21>; /* Align alloced memory to 2MB */
- map_order = <23>; /* Allocate memory in-terms of 8MB mappings */
- };
-
- NET1: lan9118 { /* Ethernet Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4E000000>;
- physical_size = <0x10000>;
- device_type = "nic";
- compatible = "smsc,lan9118";
- switch = ""; /* Override this before guest creation */

- interrupts = <47>;
- };
-

- isp1760 { /* No USB Controller */
- manifest_type = "virtual";
- address_type = "memory";
- guest_physical_addr = <0x4F000000>;
- physical_size = <0x1000>;
- device_type = "misc";
- compatible = "zero";
- };
- };
-};
diff --git a/tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript b/tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript
deleted file mode 100644
index 795a8508..00000000
--- a/tests/arm32/vexpress-a9/xscript/one_guest_vexpress-a9.xscript
+++ /dev/null
@@ -1,8 +0,0 @@
-# Load guest0 device tree from file */
-vfs guest_fdt_load guest0 /images/arm32/vexpress-a9-guest.dtb 2 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/vexpress-a9/nor_flash.list
diff --git a/tests/arm32/vexpress-a9/xscript/two_guest_vexpress-a9.xscript b/tests/arm32/vexpress-a9/xscript/two_guest_vexpress-a9.xscript
deleted file mode 100644
index 04477b6b..00000000
--- a/tests/arm32/vexpress-a9/xscript/two_guest_vexpress-a9.xscript
+++ /dev/null
@@ -1,17 +0,0 @@
-# Load guest0 device tree from file
-vfs guest_fdt_load guest0 /images/arm32/vexpress-a9-guest.dtb 2 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest0
-guest create guest0
-
-# Load guest0 images
-vfs guest_load_list guest0 /images/arm32/vexpress-a9/nor_flash.list
-
-# All the same for guest1
-vfs guest_fdt_load guest1 /images/arm32/vexpress-a9-guest.dtb 2 mem0,physical_size,physsize,0x06000000 net0,switch,string,br0 net1,switch,string,br0
-
-# Create guest1
-guest create guest1
-
-# Load guest1 images
-vfs guest_load_list guest1 /images/arm32/vexpress-a9/nor_flash.list
diff --git a/tests/common/scripts/build-arm-images.sh b/tests/common/scripts/build-arm-images.sh
index 062a1bf8..4efe1550 100755
--- a/tests/common/scripts/build-arm-images.sh
+++ b/tests/common/scripts/build-arm-images.sh
@@ -8,13 +8,9 @@ function usage()
echo " -h Display help or usage (Optional)"
echo " -a <arm_family> Xvisor ARM architecture family (Mandatory)"
echo " Allowed values:"
- echo " v5, v6, v7, v7-ve, v8"
+ echo " v7-ve, v8"
echo " -g <guest_type> Xvisor Guest type (Mandatory)"
echo " Allowed values:"
- echo " realview-eb-mpcore"
- echo " realview-pb-a8"
- echo " versatilepb"
- echo " vexpress-a9"
echo " vexpress-a15"
echo " virt-v7"
echo " virt-v8"
@@ -60,7 +56,6 @@ BUILD_XVISOR_BASIC_FIRMWARE_SOURCE_PATH=
BUILD_XVISOR_LINUX_DTS_PATH=
BUILD_XVISOR_DISK_LINUX_PATH=
BUILD_XVISOR_DISK_LINUX_EXT2_PATH=
-BUILD_LINUX_CPATCH="no"
BUILD_LINUX_ARCH=
BUILD_LINUX_CROSS_COMPILE=
BUILD_LINUX_TARBALL=
@@ -143,34 +138,9 @@ if [ -z "${BUILD_ARM_FAMILY}" ]; then
fi

case "${BUILD_ARM_FAMILY}" in
-v5)
- BUILD_XVISOR_ARCH="arm"
- BUILD_XVISOR_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_LINUX_CPATCH="yes"
- BUILD_LINUX_ARCH="arm"
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabi-
- ;;
-v6)
- BUILD_XVISOR_ARCH="arm"
- BUILD_XVISOR_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_LINUX_CPATCH="yes"
- BUILD_LINUX_ARCH="arm"
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabi-
- ;;
-v7)
- BUILD_XVISOR_ARCH="arm"
- BUILD_XVISOR_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_LINUX_CPATCH="yes"
- BUILD_LINUX_ARCH="arm"
- BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabi-
- ;;
v7-ve)
BUILD_XVISOR_ARCH="arm"
BUILD_XVISOR_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
- BUILD_LINUX_CPATCH="no"
BUILD_LINUX_ARCH="arm"
BUILD_LINUX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
BUILD_BUSYBOX_CROSS_COMPILE_PREFERRED=arm-none-linux-gnueabihf-
@@ -178,7 +148,6 @@ v7-ve)
v8)
BUILD_XVISOR_ARCH="arm"
BUILD_XVISOR_CROSS_COMPILE_PREFERRED=aarch64-none-linux-gnu-
- BUILD_LINUX_CPATCH="no"
if [ "${BUILD_GUEST_TYPE}" == "virt-v8" ]; then
BUILD_LINUX_ARCH="arm64"
BUILD_LINUX_CROSS_COMPILE_PREFERRED=aarch64-none-linux-gnu-
@@ -214,71 +183,7 @@ if [ -z "${BUILD_GUEST_TYPE}" ]; then
fi

case "${BUILD_GUEST_TYPE}" in
-realview-eb-mpcore)
- if [ "${BUILD_ARM_FAMILY}" != "v6" ]; then
- echo "ARM family has to be v6 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- BUILD_XVISOR_TESTS_DIR=arm32
- BUILD_XVISOR_GUEST_DTS_BASENAME=realview-eb-mpcore-guest
- BUILD_LINUX_DEFCONFIG=realview_defconfig
- BUILD_LINUX_DEFCONFIG_EXTRA=${BUILD_XVISOR_SOURCE_PATH}/tests/arm32/realview-eb-mpcore/linux/linux_extra.config
- BUILD_LINUX_DTB_NAME=arm-realview-eb-11mp-ctrevb.dtb
- ;;
-realview-pb-a8)
- if [ "${BUILD_ARM_FAMILY}" == "v5" ]; then
- echo "ARM family cannot be v5 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v6" ]; then
- echo "ARM family cannot be v6 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- BUILD_XVISOR_TESTS_DIR=arm32
- BUILD_XVISOR_GUEST_DTS_BASENAME=realview-pb-a8-guest
- BUILD_LINUX_DEFCONFIG=realview_defconfig
- BUILD_LINUX_DEFCONFIG_EXTRA=${BUILD_XVISOR_SOURCE_PATH}/tests/arm32/realview-pb-a8/linux/linux_extra.config
- BUILD_LINUX_DTB_NAME=arm-realview-pba8.dtb
- ;;
-versatilepb)
- if [ "${BUILD_ARM_FAMILY}" != "v5" ]; then
- echo "ARM family has to be v5 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- BUILD_XVISOR_TESTS_DIR=arm32
- BUILD_XVISOR_GUEST_DTS_BASENAME=versatilepb-guest
- BUILD_LINUX_DEFCONFIG=versatile_defconfig
- BUILD_LINUX_DEFCONFIG_EXTRA=${BUILD_XVISOR_SOURCE_PATH}/tests/arm32/versatilepb/linux/linux_extra.config
- BUILD_LINUX_DTB_NAME=versatile-pb.dtb
- ;;
-vexpress-a9)
- if [ "${BUILD_ARM_FAMILY}" == "v5" ]; then
- echo "ARM family cannot be v5 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v6" ]; then
- echo "ARM family cannot be v6 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- BUILD_XVISOR_TESTS_DIR=arm32
- BUILD_XVISOR_GUEST_DTS_BASENAME=vexpress-a9-guest
- BUILD_LINUX_DEFCONFIG=vexpress_defconfig
- BUILD_LINUX_DEFCONFIG_EXTRA=${BUILD_XVISOR_SOURCE_PATH}/tests/arm32/vexpress-a9/linux/linux_extra.config
- BUILD_LINUX_DTB_NAME=vexpress-v2p-ca9.dtb
- ;;
vexpress-a15)
- if [ "${BUILD_ARM_FAMILY}" == "v5" ]; then
- echo "ARM family cannot be v5 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v6" ]; then
- echo "ARM family cannot be v6 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v7" ]; then
- echo "ARM family cannot be v7 for ${BUILD_GUEST_TYPE}"
- usage
- fi
BUILD_XVISOR_TESTS_DIR=arm32
BUILD_XVISOR_GUEST_DTS_BASENAME=vexpress-a15-guest
BUILD_LINUX_DEFCONFIG=vexpress_defconfig
@@ -286,18 +191,6 @@ vexpress-a15)
BUILD_LINUX_DTB_NAME=vexpress-v2p-ca15-tc1.dtb
;;
virt-v7)
- if [ "${BUILD_ARM_FAMILY}" == "v5" ]; then
- echo "ARM family cannot be v5 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v6" ]; then
- echo "ARM family cannot be v6 for ${BUILD_GUEST_TYPE}"
- usage
- fi
- if [ "${BUILD_ARM_FAMILY}" == "v7" ]; then
- echo "ARM family cannot be v7 for ${BUILD_GUEST_TYPE}"
- usage
- fi
BUILD_XVISOR_TESTS_DIR=arm32
BUILD_XVISOR_GUEST_DTS_BASENAME=virt-v7-guest
BUILD_LINUX_DEFCONFIG=vexpress_defconfig
@@ -419,7 +312,6 @@ echo "xvisor_disk_linux_ext2_path = ${BUILD_XVISOR_DISK_LINUX_EXT2_PATH}"
echo "xvisor_basic_firmware_source_path = ${BUILD_XVISOR_BASIC_FIRMWARE_SOURCE_PATH}"
echo "xvisor_only = ${BUILD_XVISOR_ONLY}"
echo "linux_version = ${BUILD_LINUX_VERSION}"
-echo "linux_cpatch = ${BUILD_LINUX_CPATCH}"
echo "linux_arch = ${BUILD_LINUX_ARCH}"
echo "linux_cross_compile = ${BUILD_LINUX_CROSS_COMPILE}"
echo "linux_tarball = ${BUILD_LINUX_TARBALL}"
@@ -469,12 +361,7 @@ if [ ! -d ${BUILD_XVISOR_DISK_BASIC_PATH} ]; then
cp -f ${BUILD_XVISOR_SOURCE_PATH}/docs/logo/xvisor_logo_name.ppm ${BUILD_XVISOR_DISK_BASIC_PATH}/system/logo.ppm
mkdir -p ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}
dtc -q -I dts -O dtb -o ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_XVISOR_GUEST_DTS_BASENAME}.dtb ${BUILD_XVISOR_GUEST_DTS_PATH}
- if [ "${BUILD_LINUX_CPATCH}" == "yes" ]; then
- cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin.patched ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
- fi
- if [ "${BUILD_LINUX_CPATCH}" != "yes" ]; then
- cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
- fi
+ cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
cp -f ${BUILD_XVISOR_SOURCE_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/nor_flash.list ${BUILD_XVISOR_DISK_BASIC_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/nor_flash.list
cp -f ${BUILD_XVISOR_SOURCE_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/xscript/${BUILD_GUEST_XSCRIPT}.xscript ${BUILD_XVISOR_DISK_BASIC_PATH}/boot.xscript
fi
@@ -512,21 +399,12 @@ export ARCH=${BUILD_LINUX_ARCH}
export CROSS_COMPILE=${BUILD_LINUX_CROSS_COMPILE}
mkdir -p ${BUILD_LINUX_OUTPUT_PATH}
if [ ! -f ${BUILD_LINUX_OUTPUT_PATH}/.config ]; then
- if [ "${BUILD_LINUX_CPATCH}" == "yes" ]; then
- sed -i 's/0xff800000UL/0xff000000UL/' ${BUILD_LINUX_SOURCE_PATH}/arch/arm/include/asm/pgtable.h
- fi
cp -f ${BUILD_LINUX_SOURCE_PATH}/arch/${BUILD_LINUX_ARCH}/configs/${BUILD_LINUX_DEFCONFIG} ${BUILD_LINUX_SOURCE_PATH}/arch/${BUILD_LINUX_ARCH}/configs/tmp-${BUILD_GUEST_TYPE}_defconfig
${BUILD_XVISOR_SOURCE_PATH}/tests/common/scripts/update-linux-defconfig.sh -p ${BUILD_LINUX_SOURCE_PATH}/arch/${BUILD_LINUX_ARCH}/configs/tmp-${BUILD_GUEST_TYPE}_defconfig -f ${BUILD_LINUX_DEFCONFIG_EXTRA}
make ARCH=${BUILD_LINUX_ARCH} -C ${BUILD_LINUX_SOURCE_PATH} O=${BUILD_LINUX_OUTPUT_PATH} tmp-${BUILD_GUEST_TYPE}_defconfig
fi
if [ ! -f ${BUILD_LINUX_OUTPUT_PATH}/vmlinux ]; then
make ARCH=${BUILD_LINUX_ARCH} -C ${BUILD_LINUX_SOURCE_PATH} O=${BUILD_LINUX_OUTPUT_PATH} -j ${BUILD_NUM_THREADS} Image dtbs
- if [ "${BUILD_LINUX_CPATCH}" == "yes" ]; then
- cp -f ${BUILD_LINUX_OUTPUT_PATH}/arch/${BUILD_LINUX_ARCH}/boot/Image ${BUILD_LINUX_OUTPUT_PATH}/arch/${BUILD_LINUX_ARCH}/boot/Image.orig
- cp -f ${BUILD_LINUX_OUTPUT_PATH}/vmlinux ${BUILD_LINUX_OUTPUT_PATH}/vmlinux.orig
- ${BUILD_XVISOR_SOURCE_PATH}/arch/arm/cpu/arm32/elf2cpatch.py -f ${BUILD_LINUX_OUTPUT_PATH}/vmlinux | ${BUILD_XVISOR_OUTPUT_PATH}/tools/cpatch/cpatch32 ${BUILD_LINUX_OUTPUT_PATH}/vmlinux 0
- ${CROSS_COMPILE}objcopy -O binary ${BUILD_LINUX_OUTPUT_PATH}/vmlinux ${BUILD_LINUX_OUTPUT_PATH}/arch/${BUILD_LINUX_ARCH}/boot/Image
- fi
fi

echo "=== Configure and Build Busybox ==="
@@ -565,12 +443,7 @@ if [ ! -d ${BUILD_XVISOR_DISK_LINUX_PATH} ]; then
cp -f ${BUILD_XVISOR_SOURCE_PATH}/docs/logo/xvisor_logo_name.ppm ${BUILD_XVISOR_DISK_LINUX_PATH}/system/logo.ppm
mkdir -p ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}
dtc -q -I dts -O dtb -o ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_XVISOR_GUEST_DTS_BASENAME}.dtb ${BUILD_XVISOR_GUEST_DTS_PATH}
- if [ "${BUILD_LINUX_CPATCH}" == "yes" ]; then
- cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin.patched ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
- fi
- if [ "${BUILD_LINUX_CPATCH}" != "yes" ]; then
- cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
- fi
+ cp -f ${BUILD_XVISOR_OUTPUT_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/basic/firmware.bin ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/firmware.bin
cp -f ${BUILD_XVISOR_SOURCE_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/linux/nor_flash.list ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/nor_flash.list
cp -f ${BUILD_XVISOR_SOURCE_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/linux/cmdlist ${BUILD_XVISOR_DISK_LINUX_PATH}/images/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/cmdlist
cp -f ${BUILD_XVISOR_SOURCE_PATH}/tests/${BUILD_XVISOR_TESTS_DIR}/${BUILD_GUEST_TYPE}/xscript/${BUILD_GUEST_XSCRIPT}.xscript ${BUILD_XVISOR_DISK_LINUX_PATH}/boot.xscript
diff --git a/tests/common/scripts/build-images.sh b/tests/common/scripts/build-images.sh
index 2f293e42..10adb51b 100755
--- a/tests/common/scripts/build-images.sh
+++ b/tests/common/scripts/build-images.sh
@@ -83,24 +83,6 @@ BUILD_SCRIPTS_PATH=`dirname $0`

mkdir -p ${BUILD_OUTPUT_PATH}/arm

-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v5 -g versatilepb -s one_guest_versatilepb -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v5 -i ${BUILD_INSTALL_PATH}/arm/v5 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v5 -g versatilepb -s two_guest_versatilepb -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v5 -i ${BUILD_INSTALL_PATH}/arm/v5 -j ${BUILD_NUM_THREADS}
-rm -rf ${BUILD_OUTPUT_PATH}/arm/v5
-
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v6 -g realview-eb-mpcore -s one_guest_ebmp -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v6 -i ${BUILD_INSTALL_PATH}/arm/v6 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v6 -g realview-eb-mpcore -s two_guest_ebmp -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v6 -i ${BUILD_INSTALL_PATH}/arm/v6 -j ${BUILD_NUM_THREADS}
-rm -rf ${BUILD_OUTPUT_PATH}/arm/v6
-
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7 -g realview-pb-a8 -s one_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7 -i ${BUILD_INSTALL_PATH}/arm/v7 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7 -g realview-pb-a8 -s two_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7 -i ${BUILD_INSTALL_PATH}/arm/v7 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7 -g vexpress-a9 -s one_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7 -i ${BUILD_INSTALL_PATH}/arm/v7 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7 -g vexpress-a9 -s two_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7 -i ${BUILD_INSTALL_PATH}/arm/v7 -j ${BUILD_NUM_THREADS}
-rm -rf ${BUILD_OUTPUT_PATH}/arm/v7
-
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g realview-pb-a8 -s one_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g realview-pb-a8 -s two_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g vexpress-a9 -s one_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g vexpress-a9 -s two_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g vexpress-a15 -s one_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g vexpress-a15 -s one_novgic_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g vexpress-a15 -s two_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
@@ -112,10 +94,6 @@ ${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g virt-v7 -s two_guest_virt-
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v7-ve -g virt-v7 -s two_novgic_guest_virt-v7 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v7-ve -i ${BUILD_INSTALL_PATH}/arm/v7-ve -j ${BUILD_NUM_THREADS}
rm -rf ${BUILD_OUTPUT_PATH}/arm/v7-ve

-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g realview-pb-a8 -s one_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g realview-pb-a8 -s two_guest_pb-a8 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g vexpress-a9 -s one_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
-${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g vexpress-a9 -s two_guest_vexpress-a9 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g vexpress-a15 -s one_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g vexpress-a15 -s one_novgic_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
${BUILD_SCRIPTS_PATH}/build-arm-images.sh -a v8 -g vexpress-a15 -s two_guest_vexpress-a15 -d ${BUILD_TARBALL_PATH} -l ${BUILD_LINUX_VERSION} -b ${BUILD_BUSYBOX_VERSION} -p ${BUILD_XVISOR_SOURCE_PATH} -o ${BUILD_OUTPUT_PATH}/arm/v8 -i ${BUILD_INSTALL_PATH}/arm/v8 -j ${BUILD_NUM_THREADS}
--
2.25.1

[Anup Patel]

[Anup Patel]

Applied this patch to the xvisor-next repo.

Regards,
Anup

[Anup Patel]

Applied this patch to the xvisor-next repo.

Regards,
Anup