[GIT PULL] Changes for v0.3.2 release
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Anup Patel
Jan 1, 2023, 8:02:30 AM1/1/23
to Xvisor Devel
The following changes since commit 9be2fdd7f89b669130b19ee70f25b1dcf81f272c:
DOCS: Update commit tag in v0.3.1 release notes (2021-12-20 10:37:28 +0530)
are available in the Git repository at:
https://github.com/avpatel/xvisor-next.git
for you to fetch changes up to 0ff131498a26bd1c97a867ef3ccfbc23873209f1:
TOP: Bump-up version to 0.3.2 (2023-01-01 17:12:42 +0530)
----------------------------------------------------------------
Anup Patel (107):
RISC-V: Sync-up CSR and instruction encoding defines with OpenSBI v1.0
RISC-V: Add AIA related CSR defines
RISC-V: Add feature flag for AIA support on all CPUs
CORE: vmm_host_irq: Improve sanity check in vmm_host_irqdomain_add()
RISC-V: Fix base host irq used for IPI irqdomain
DRIVERS: irqchip/riscv-intc: Add support for RISC-V AIA
CORE: vmm_host_irq: Provide previous interrupt in active_irq() callback
CORE: vmm_host_irqdomain: Add common xlate() to translate two cells
DRIVERS: irqchip/sifive-plic: Implement irqdomain map() callback
CORE: vmm_smp: Add vmm_smp_map_cpuid() API
DRIVERS: irqchip/sifive-plic: Simplify contexts setup in plic_init()
CORE: vmm_devtree: Add declaration of vmm_devtree_irqdomain_find() API
CORE: vmm_platform: Probe interrupt controller before other devices
CORE: vmm_devtree_irq: Fix vmm_devtree_irq_create_mapping() domain check
DRIVERS: irqchip: Add RISC-V Advancded PLIC driver
RISC-V: Enable RISC-V APLIC in RV32 and RV64 defconfigs
RISC-V: Use hfence.vvma in arch_mmu_test_nested_pgtbl()
RISC-V: Fix usage of hfence.gvma instruction
TESTS: riscv: Disable DRM drivers for Linux guests
TESTS: riscv: Update ramdisk size in autoexec command list
RISC-V: Make CY, TM, and IR counters accessible in VU mode
RISC-V: Add linux style flat image header
TESTS: riscv: Enable HUGETLBFS for Linux guest
TESTS: riscv: Enable SBI based earlycon for guest linux
TESTS: riscv: Add letter h to guest ISA string
TESTS: riscv: Improve SBI support in basic firmware
RISC-V: Add Xvisor specific SBI extension
TESTS: riscv: Generate VCPU isa string using Xvisor SBI extension
RISC-V: Fix typo in __sbi_rfence_v02() call to host
RISC-V: Treat Guest SBI HFENCE calls as NOPs
RISC-V: Add nested virtualization state in VCPU private context
RISC-V: Add more indentation in VCPU register dump prints
RISC-V: Improve H-extension CSR defines for emulation
RISC-V: Add helper functions for nested virtualization
RISC-V: Initial support for nested virtualization
ARCH: generic_mmu: Add mechanism to get guest page table mapping
RISC-V: Emulate HLV and HSV instructions for guest hypervisor
ARCH: generic_mmu: Add attributes and hardware tag for each page table
RISC-V: Emulate guest G-stage page table and guest HFENCE instructions
DRIVERS: riscv_timer: Ensure timer interrupt is not pending at boot time
TESTS: common: Enable conspy in busybox-1.33.1 defconfig
RISC-V: Add Sv57 support for Host
RISC-V: Add Sv57x4 support for Guest/VM
TESTS: riscv: Enable earlycon=sbi for Linux Guest/VM
RISC-V: Use shadow_page for nested_swtlb_lookup()
CORE: vmm_stdio: Improve defterm polling in vmm_scanchars()
RISC-V: Use timer event to ensure interrupt delivery to virtual-VS mode
RISC-V: Setup interrupt delegation for both Orphan and Normal VCPUs
DRIVERS: irqchip/riscv-aplic: Align priority and threshold with Linux
CORE: vmm_host_irqdomain: Add alloc() and free() domain operations
CORE: vmm_msi: Move compose_msi_msg() from MSI domain to irqchip
CORE: vmm_msi: Use desc->msg in vmm_msi_domain_alloc/free_irqs()
CORE: vmm_msi: Add vmm_msi_domain_write_msg() API
CORE: vmm_msi: Provide complete set of default ops
CORE: vmm_msi: Add common msi_index for both PCIe and Platform MSIs
CORE: vmm_host_irq: Allow irqchip drivers to mark chained interrupts
CORE: vmm_devres: Add custom action APIs
CORE: vmm_host_irqext: Fix extended IRQ allocations
LIBS: bitops: Improve get_count_order() implementation
DRIVERS: irqchip: Add RISC-V incoming MSI controller driver
DRIVERS: irqchip/riscv-aplic: Add support for MSI-mode
RISC-V: Enable RISC-V IMSIC in RV32 and RV64 defconfigs
COMMANDS: host: Add sub-command to poke a host CPU
RISC-V: Fix compile error for latest binutils 2.38
ARCH: generic_mmu: Check child pointer before use in mmu_pgtbl_get_child()
RISC-V: Print shadow page input address when panic
ARCH: generic_mmu: Fix typo in mmu_pgtbl_nonpool_alloc()
COMMANDS: memory: Add iodump8, iodump16, and iodump32 sub-commands
ARCH: generic_mmu: Initialize attributes of hypervisor page table
RISC-V: Emulate dummy henvcfg[h] CSR for the guest hypervisor
TESTS: Don't disable CONFIG_PROFILING in update-linux-defconfig.sh
EMULATORS: plic: Fix number of irq lines
RISC-V: Extend ISA string parsing for multi-letter extension names
RISC-V: Remove riscv_aia_available feature flag
DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
RISC-V: Gather and prints stats for normal VCPU
CORE: Add vmm_scheduler_irq_regs() function
CORE: Add endianness helper macros for long
RISC-V: Improve SRET based nested world-switch
RISC-V: Make function to emulate SRET instruction as global
RISC-V: Combine SBI extension handler output parameters into a struct
RISC-V: Add regs_updated flag in struct cpu_vcpu_sbi_return
RISC-V: Add cpu_vcpu_sbi_xlate_error() helper function
RISC-V: Change the SBI specification version to v1.0 for guest
RISC-V: Extend ISA parsing to detect Sstc extension
RISC-V: Add CSR defines for Sstc extension
DRIVERS: riscv_timer: Use Sstc extension when available
RISC-V: Rename VCPU timer handling functions for consistency
RISC-V: Move time delta update function to cpu_vcpu_timer.c
RISC-V: Introduce VCPU timer save/restore functions
RISC-V: VCPU ISA bitmap should only have extensions available on Host
RISC-V: Use Sstc virtualization in VCPU timer implement
TESTS: riscv: Add sstc to ISA string whenever Xvisor support it
RISC-V: Take nested interrupts after vmm_scheduler_irq_exit()
RISC-V: Add nested virtualization support for Sstc extension
RISC-V: Fix compile error for RV32 systems.
TESTS: arm32/arm64/riscv: Suppress linker warning
TESTS: arm32/arm64/riscv: Clean spaces and alignment in linker scripts
Makefile: Suppress linker warning
CORE: Fix compile warning seen with GCC 12 (or higher)
DRIVERS: input/mouse: Use "static inline" instead of "inline"
ARM: arm32ve: Fix linker warning seen with binutils 2.39
ARCH: generic_mmu: Don't print if attach fails in mmu_pgtbl_get_child()
TESTS: common: Update default linux version in scripts
DOCS: Add Xvisor v0.3.2 release notes
TOP: Bump-up version to 0.3.2
Himanshu Chauhan (20):
x86: program the flags before writing to ICR
x86: Facing facility for timer programming and IRQs
x86: Add locks for accessing LAPIC area
x86: Add EPT tracepoints
x86: Information on how to add Qemu monitor on telnet
x86: Add framebuffer support for early prints
x86: Fix compilation warnings in guest address translation
drivers: Outsmarted by compilers. IDE detection with latest
compiler fails.
x86: Remove static linking of guest fdt in Xvisor binary
x86: Add support for direct ljmp instruction decoding
x86: Handle reset in better way
x86: Add support for PAM registers and boot from single copy of BIOS
doc: x86: updated the reponame
x86: Separate out the EPT logs from general VM logs
emulators: Fix the ordering of class and prog_if registers
emulators: Add class code in i440FX emulator
tests: Disable and Enable virtio block and LAPIC emulation respectively
x86: Make guest be CR0 owner
x86: Add sub-system level loggin facility for x86 architecture
x86: Move the logging to subsystem level logging
Makefile | 9 +-
arch/arm/cpu/arm32ve/cpu_vcpu_helper.c | 10 +-
arch/arm/cpu/arm32ve/objects.mk | 3 +-
arch/arm/cpu/arm64/cpu_vcpu_helper.c | 10 +-
arch/arm/cpu/common/include/mmu_lpae.h | 7 +-
arch/arm/cpu/common/mmu_lpae.c | 7 +-
arch/common/generic_mmu.c | 128 +-
arch/common/include/generic_mmu.h | 49 +-
arch/riscv/configs/generic-32b-defconfig | 2 +
arch/riscv/configs/generic-64b-defconfig | 2 +
arch/riscv/cpu/generic/cpu_entry.S | 56 +
arch/riscv/cpu/generic/cpu_exception.c | 60 +-
arch/riscv/cpu/generic/cpu_init.c | 107 +-
arch/riscv/cpu/generic/cpu_mmu.c | 60 +-
arch/riscv/cpu/generic/cpu_mmu_initial_pgtbl.c | 67 +
arch/riscv/cpu/generic/cpu_sbi.c | 2 +-
arch/riscv/cpu/generic/cpu_sbi_ipi.c | 2 +-
arch/riscv/cpu/generic/cpu_vcpu_csr.c | 54 -
arch/riscv/cpu/generic/cpu_vcpu_fp.c | 60 +-
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 311 +++-
arch/riscv/cpu/generic/cpu_vcpu_nested.c | 1799 ++++++++++++++++++++
arch/riscv/cpu/generic/cpu_vcpu_sbi.c | 58 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_base.c | 25 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_hsm.c | 11 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_legacy.c | 21 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_replace.c | 90 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_xvisor.c | 63 +
arch/riscv/cpu/generic/cpu_vcpu_timer.c | 306 +++-
arch/riscv/cpu/generic/cpu_vcpu_trap.c | 963 ++++++++++-
arch/riscv/cpu/generic/include/arch_mmu.h | 13 +-
arch/riscv/cpu/generic/include/arch_regs.h | 60 +
arch/riscv/cpu/generic/include/cpu_hwcap.h | 47 +-
arch/riscv/cpu/generic/include/cpu_tlb.h | 8 +-
arch/riscv/cpu/generic/include/cpu_vcpu_csr.h | 37 -
arch/riscv/cpu/generic/include/cpu_vcpu_fp.h | 4 +-
arch/riscv/cpu/generic/include/cpu_vcpu_helper.h | 9 +
arch/riscv/cpu/generic/include/cpu_vcpu_nested.h | 114 ++
arch/riscv/cpu/generic/include/cpu_vcpu_sbi.h | 19 +-
arch/riscv/cpu/generic/include/cpu_vcpu_timer.h | 20 +-
arch/riscv/cpu/generic/include/cpu_vcpu_trap.h | 26 +-
arch/riscv/cpu/generic/include/riscv_encoding.h | 671 ++++++--
arch/riscv/cpu/generic/objects.mk | 16 +-
.../board/common/devices/video/fb_early_console.c | 228 +++
arch/x86/board/common/devices/video/objects.mk | 1 +
arch/x86/board/common/include/video/ter-i16b.h | 3 +-
arch/x86/board/common/include/video/ter-i16n.h | 4 +-
arch/x86/board/common/include/x86_debug_log.h | 59 +
arch/x86/board/x86_64_generic/brd_defterm.c | 5 +
arch/x86/board/x86_64_generic/brd_pic.c | 2 +-
arch/x86/board/x86_64_generic/dts/defconfig.dts | 2 -
arch/x86/cpu/common/cpu_apic.c | 127 +-
arch/x86/cpu/common/include/cpu_apic.h | 2 +
arch/x86/cpu/common/include/cpu_inst_decode.h | 10 +
arch/x86/cpu/common/include/cpu_vm.h | 22 -
arch/x86/cpu/common/vm/arch_guest_helper.c | 7 +-
arch/x86/cpu/common/vm/cpu_inst_decode.c | 15 +
arch/x86/cpu/common/vm/svm/intercept.c | 115 +-
arch/x86/cpu/common/vm/svm/svm.c | 21 +-
arch/x86/cpu/common/vm/vm.c | 37 +-
arch/x86/cpu/common/vm/vtx/ept.c | 173 +-
arch/x86/cpu/common/vm/vtx/intercept.c | 148 +-
arch/x86/cpu/common/vm/vtx/vmcs.c | 24 +-
arch/x86/cpu/common/vm/vtx/vmx.c | 31 +-
arch/x86/cpu/x86_64/cpu_main.c | 9 +-
arch/x86/cpu/x86_64/cpu_mmu.c | 93 +-
arch/x86/cpu/x86_64/cpu_vcpu_helper.c | 15 +-
arch/x86/cpu/x86_64/include/cpu_mmu.h | 4 +
arch/x86/cpu/x86_64/start.S | 5 +
.../guests/{x86_64_guest.dtsi => amd_guest.dts} | 0
commands/cmd_host.c | 61 +-
commands/cmd_memory.c | 152 +-
core/include/vmm_devres.h | 8 +
core/include/vmm_devtree.h | 10 +
core/include/vmm_host_io.h | 8 +
core/include/vmm_host_irq.h | 30 +-
core/include/vmm_host_irqdomain.h | 16 +-
core/include/vmm_msi.h | 17 +-
core/include/vmm_scheduler.h | 3 +
core/include/vmm_smp.h | 13 +
core/vmm_devres.c | 54 +
core/vmm_devtree.c | 5 +-
core/vmm_devtree_irq.c | 19 +-
core/vmm_host_irq.c | 62 +-
core/vmm_host_irqdomain.c | 93 +-
core/vmm_host_irqext.c | 3 +-
core/vmm_msi.c | 123 +-
core/vmm_platform.c | 29 +-
core/vmm_platform_msi.c | 4 +-
core/vmm_scheduler.c | 7 +
core/vmm_smp.c | 23 +
core/vmm_stdio.c | 12 +-
core/vmm_workqueue.c | 2 +-
docs/releases/v0.3.2 | 62 +
docs/x86/x86_64_generic.txt | 7 +-
drivers/clocksource/riscv_timer.c | 39 +-
drivers/ide/host/piix3_ide.c | 4 +-
drivers/include/drv/irqchip/riscv-aplic.h | 115 ++
drivers/include/drv/irqchip/riscv-imsic.h | 87 +
drivers/input/mouse/alps.h | 4 +-
drivers/input/mouse/lifebook.h | 6 +-
drivers/input/mouse/logips2pp.h | 2 +-
drivers/input/mouse/sentelic.h | 4 +-
drivers/input/mouse/trackpoint.h | 2 +-
drivers/irqchip/irq-avic.c | 2 +-
drivers/irqchip/irq-bcm2835.c | 4 +-
drivers/irqchip/irq-bcm2836.c | 2 +-
drivers/irqchip/irq-gic-v3.c | 2 +-
drivers/irqchip/irq-gic.c | 2 +-
drivers/irqchip/irq-omap-intc.c | 2 +-
drivers/irqchip/irq-riscv-aclint-swi.c | 2 +-
drivers/irqchip/irq-riscv-aplic.c | 664 ++++++++
drivers/irqchip/irq-riscv-imsic.c | 1147 +++++++++++++
drivers/irqchip/irq-riscv-intc.c | 45 +-
drivers/irqchip/irq-sifive-plic.c | 93 +-
drivers/irqchip/irq-sun4i.c | 2 +-
drivers/irqchip/irq-versatile-fpga.c | 2 +-
drivers/irqchip/irq-vic.c | 2 +-
drivers/irqchip/objects.mk | 2 +
drivers/irqchip/openconf.cfg | 22 +
emulators/include/emu/pci/pci_emu_core.h | 4 +-
emulators/pci/host/i440fx.c | 63 +-
emulators/pic/plic.c | 3 +-
libs/include/libs/bitops.h | 31 +-
libs/wboxtest/nested_mmu/nested_mmu_test.h | 3 +-
tests/arm32/common/basic/Makefile.inc | 2 +-
tests/arm32/common/basic/firmware.ld | 108 +-
tests/arm32/vexpress-a15/linux/linux_extra.config | 1 +
tests/arm32/virt-v7/linux/linux_extra.config | 1 +
tests/arm64/common/basic/firmware.ld | 53 +-
tests/arm64/virt-v8/linux/linux_extra.config | 1 +
tests/common/basic/Makefile.inc | 7 +
tests/common/busybox/busybox-1.33.1_defconfig | 4 +-
tests/common/scripts/build-arm-images.sh | 2 +-
tests/common/scripts/build-images.sh | 2 +-
tests/common/scripts/build-riscv-images.sh | 2 +-
tests/common/scripts/update-linux-defconfig.sh | 1 -
tests/riscv/common/basic/Makefile.inc | 1 +
tests/riscv/common/basic/arch_sbi.c | 302 ++++
tests/riscv/common/basic/arch_sbi.h | 359 +++-
tests/riscv/common/basic/firmware.ld | 5 +-
tests/riscv/virt32/basic/arch_board.c | 10 +-
tests/riscv/virt32/linux/cmdlist | 4 +-
tests/riscv/virt32/linux/linux_extra.config | 5 +
tests/riscv/virt32/linux/virt32.dts | 2 +-
tests/riscv/virt32/virt32-guest.dts | 4 +-
tests/riscv/virt64/basic/arch_board.c | 10 +-
tests/riscv/virt64/linux/cmdlist | 4 +-
tests/riscv/virt64/linux/linux_extra.config | 5 +
tests/riscv/virt64/linux/virt64.dts | 2 +-
tests/riscv/virt64/virt64-guest.dts | 4 +-
tests/x86/README | 25 +
tests/x86/create_hdd_partitions.expt | 36 -
tests/x86/guest_init.cmd | 13 -
tests/x86/hdd.layout | 7 -
tests/x86/intel-guest.dts | 203 +++
tests/x86/lomount.c | 435 -----
.../guest_init.cmd => xscripts/one_guest.xscript} | 7 +-
157 files changed, 9594 insertions(+), 1766 deletions(-)
delete mode 100644 arch/riscv/cpu/generic/cpu_vcpu_csr.c
create mode 100644 arch/riscv/cpu/generic/cpu_vcpu_nested.c
create mode 100644 arch/riscv/cpu/generic/cpu_vcpu_sbi_xvisor.c
delete mode 100644 arch/riscv/cpu/generic/include/cpu_vcpu_csr.h
create mode 100644 arch/riscv/cpu/generic/include/cpu_vcpu_nested.h
create mode 100644 arch/x86/board/common/devices/video/fb_early_console.c
create mode 100644 arch/x86/board/common/include/x86_debug_log.h
rename arch/x86/guests/{x86_64_guest.dtsi => amd_guest.dts} (100%)
create mode 100644 docs/releases/v0.3.2
create mode 100644 drivers/include/drv/irqchip/riscv-aplic.h
create mode 100644 drivers/include/drv/irqchip/riscv-imsic.h
create mode 100644 drivers/irqchip/irq-riscv-aplic.c
create mode 100644 drivers/irqchip/irq-riscv-imsic.c
create mode 100644 tests/riscv/common/basic/arch_sbi.c
create mode 100644 tests/x86/README
delete mode 100755 tests/x86/create_hdd_partitions.expt
delete mode 100644 tests/x86/guest_init.cmd
delete mode 100644 tests/x86/hdd.layout
create mode 100644 tests/x86/intel-guest.dts
delete mode 100644 tests/x86/lomount.c
rename tests/x86/{scripts/guest_init.cmd => xscripts/one_guest.xscript} (56%)
Regards,
Anup
DOCS: Update commit tag in v0.3.1 release notes (2021-12-20 10:37:28 +0530)
are available in the Git repository at:
https://github.com/avpatel/xvisor-next.git
for you to fetch changes up to 0ff131498a26bd1c97a867ef3ccfbc23873209f1:
TOP: Bump-up version to 0.3.2 (2023-01-01 17:12:42 +0530)
----------------------------------------------------------------
Anup Patel (107):
RISC-V: Sync-up CSR and instruction encoding defines with OpenSBI v1.0
RISC-V: Add AIA related CSR defines
RISC-V: Add feature flag for AIA support on all CPUs
CORE: vmm_host_irq: Improve sanity check in vmm_host_irqdomain_add()
RISC-V: Fix base host irq used for IPI irqdomain
DRIVERS: irqchip/riscv-intc: Add support for RISC-V AIA
CORE: vmm_host_irq: Provide previous interrupt in active_irq() callback
CORE: vmm_host_irqdomain: Add common xlate() to translate two cells
DRIVERS: irqchip/sifive-plic: Implement irqdomain map() callback
CORE: vmm_smp: Add vmm_smp_map_cpuid() API
DRIVERS: irqchip/sifive-plic: Simplify contexts setup in plic_init()
CORE: vmm_devtree: Add declaration of vmm_devtree_irqdomain_find() API
CORE: vmm_platform: Probe interrupt controller before other devices
CORE: vmm_devtree_irq: Fix vmm_devtree_irq_create_mapping() domain check
DRIVERS: irqchip: Add RISC-V Advancded PLIC driver
RISC-V: Enable RISC-V APLIC in RV32 and RV64 defconfigs
RISC-V: Use hfence.vvma in arch_mmu_test_nested_pgtbl()
RISC-V: Fix usage of hfence.gvma instruction
TESTS: riscv: Disable DRM drivers for Linux guests
TESTS: riscv: Update ramdisk size in autoexec command list
RISC-V: Make CY, TM, and IR counters accessible in VU mode
RISC-V: Add linux style flat image header
TESTS: riscv: Enable HUGETLBFS for Linux guest
TESTS: riscv: Enable SBI based earlycon for guest linux
TESTS: riscv: Add letter h to guest ISA string
TESTS: riscv: Improve SBI support in basic firmware
RISC-V: Add Xvisor specific SBI extension
TESTS: riscv: Generate VCPU isa string using Xvisor SBI extension
RISC-V: Fix typo in __sbi_rfence_v02() call to host
RISC-V: Treat Guest SBI HFENCE calls as NOPs
RISC-V: Add nested virtualization state in VCPU private context
RISC-V: Add more indentation in VCPU register dump prints
RISC-V: Improve H-extension CSR defines for emulation
RISC-V: Add helper functions for nested virtualization
RISC-V: Initial support for nested virtualization
ARCH: generic_mmu: Add mechanism to get guest page table mapping
RISC-V: Emulate HLV and HSV instructions for guest hypervisor
ARCH: generic_mmu: Add attributes and hardware tag for each page table
RISC-V: Emulate guest G-stage page table and guest HFENCE instructions
DRIVERS: riscv_timer: Ensure timer interrupt is not pending at boot time
TESTS: common: Enable conspy in busybox-1.33.1 defconfig
RISC-V: Add Sv57 support for Host
RISC-V: Add Sv57x4 support for Guest/VM
TESTS: riscv: Enable earlycon=sbi for Linux Guest/VM
RISC-V: Use shadow_page for nested_swtlb_lookup()
CORE: vmm_stdio: Improve defterm polling in vmm_scanchars()
RISC-V: Use timer event to ensure interrupt delivery to virtual-VS mode
RISC-V: Setup interrupt delegation for both Orphan and Normal VCPUs
DRIVERS: irqchip/riscv-aplic: Align priority and threshold with Linux
CORE: vmm_host_irqdomain: Add alloc() and free() domain operations
CORE: vmm_msi: Move compose_msi_msg() from MSI domain to irqchip
CORE: vmm_msi: Use desc->msg in vmm_msi_domain_alloc/free_irqs()
CORE: vmm_msi: Add vmm_msi_domain_write_msg() API
CORE: vmm_msi: Provide complete set of default ops
CORE: vmm_msi: Add common msi_index for both PCIe and Platform MSIs
CORE: vmm_host_irq: Allow irqchip drivers to mark chained interrupts
CORE: vmm_devres: Add custom action APIs
CORE: vmm_host_irqext: Fix extended IRQ allocations
LIBS: bitops: Improve get_count_order() implementation
DRIVERS: irqchip: Add RISC-V incoming MSI controller driver
DRIVERS: irqchip/riscv-aplic: Add support for MSI-mode
RISC-V: Enable RISC-V IMSIC in RV32 and RV64 defconfigs
COMMANDS: host: Add sub-command to poke a host CPU
RISC-V: Fix compile error for latest binutils 2.38
ARCH: generic_mmu: Check child pointer before use in mmu_pgtbl_get_child()
RISC-V: Print shadow page input address when panic
ARCH: generic_mmu: Fix typo in mmu_pgtbl_nonpool_alloc()
COMMANDS: memory: Add iodump8, iodump16, and iodump32 sub-commands
ARCH: generic_mmu: Initialize attributes of hypervisor page table
RISC-V: Emulate dummy henvcfg[h] CSR for the guest hypervisor
TESTS: Don't disable CONFIG_PROFILING in update-linux-defconfig.sh
EMULATORS: plic: Fix number of irq lines
RISC-V: Extend ISA string parsing for multi-letter extension names
RISC-V: Remove riscv_aia_available feature flag
DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
RISC-V: Gather and prints stats for normal VCPU
CORE: Add vmm_scheduler_irq_regs() function
CORE: Add endianness helper macros for long
RISC-V: Improve SRET based nested world-switch
RISC-V: Make function to emulate SRET instruction as global
RISC-V: Combine SBI extension handler output parameters into a struct
RISC-V: Add regs_updated flag in struct cpu_vcpu_sbi_return
RISC-V: Add cpu_vcpu_sbi_xlate_error() helper function
RISC-V: Change the SBI specification version to v1.0 for guest
RISC-V: Extend ISA parsing to detect Sstc extension
RISC-V: Add CSR defines for Sstc extension
DRIVERS: riscv_timer: Use Sstc extension when available
RISC-V: Rename VCPU timer handling functions for consistency
RISC-V: Move time delta update function to cpu_vcpu_timer.c
RISC-V: Introduce VCPU timer save/restore functions
RISC-V: VCPU ISA bitmap should only have extensions available on Host
RISC-V: Use Sstc virtualization in VCPU timer implement
TESTS: riscv: Add sstc to ISA string whenever Xvisor support it
RISC-V: Take nested interrupts after vmm_scheduler_irq_exit()
RISC-V: Add nested virtualization support for Sstc extension
RISC-V: Fix compile error for RV32 systems.
TESTS: arm32/arm64/riscv: Suppress linker warning
TESTS: arm32/arm64/riscv: Clean spaces and alignment in linker scripts
Makefile: Suppress linker warning
CORE: Fix compile warning seen with GCC 12 (or higher)
DRIVERS: input/mouse: Use "static inline" instead of "inline"
ARM: arm32ve: Fix linker warning seen with binutils 2.39
ARCH: generic_mmu: Don't print if attach fails in mmu_pgtbl_get_child()
TESTS: common: Update default linux version in scripts
DOCS: Add Xvisor v0.3.2 release notes
TOP: Bump-up version to 0.3.2
Himanshu Chauhan (20):
x86: program the flags before writing to ICR
x86: Facing facility for timer programming and IRQs
x86: Add locks for accessing LAPIC area
x86: Add EPT tracepoints
x86: Information on how to add Qemu monitor on telnet
x86: Add framebuffer support for early prints
x86: Fix compilation warnings in guest address translation
drivers: Outsmarted by compilers. IDE detection with latest
compiler fails.
x86: Remove static linking of guest fdt in Xvisor binary
x86: Add support for direct ljmp instruction decoding
x86: Handle reset in better way
x86: Add support for PAM registers and boot from single copy of BIOS
doc: x86: updated the reponame
x86: Separate out the EPT logs from general VM logs
emulators: Fix the ordering of class and prog_if registers
emulators: Add class code in i440FX emulator
tests: Disable and Enable virtio block and LAPIC emulation respectively
x86: Make guest be CR0 owner
x86: Add sub-system level loggin facility for x86 architecture
x86: Move the logging to subsystem level logging
Makefile | 9 +-
arch/arm/cpu/arm32ve/cpu_vcpu_helper.c | 10 +-
arch/arm/cpu/arm32ve/objects.mk | 3 +-
arch/arm/cpu/arm64/cpu_vcpu_helper.c | 10 +-
arch/arm/cpu/common/include/mmu_lpae.h | 7 +-
arch/arm/cpu/common/mmu_lpae.c | 7 +-
arch/common/generic_mmu.c | 128 +-
arch/common/include/generic_mmu.h | 49 +-
arch/riscv/configs/generic-32b-defconfig | 2 +
arch/riscv/configs/generic-64b-defconfig | 2 +
arch/riscv/cpu/generic/cpu_entry.S | 56 +
arch/riscv/cpu/generic/cpu_exception.c | 60 +-
arch/riscv/cpu/generic/cpu_init.c | 107 +-
arch/riscv/cpu/generic/cpu_mmu.c | 60 +-
arch/riscv/cpu/generic/cpu_mmu_initial_pgtbl.c | 67 +
arch/riscv/cpu/generic/cpu_sbi.c | 2 +-
arch/riscv/cpu/generic/cpu_sbi_ipi.c | 2 +-
arch/riscv/cpu/generic/cpu_vcpu_csr.c | 54 -
arch/riscv/cpu/generic/cpu_vcpu_fp.c | 60 +-
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 311 +++-
arch/riscv/cpu/generic/cpu_vcpu_nested.c | 1799 ++++++++++++++++++++
arch/riscv/cpu/generic/cpu_vcpu_sbi.c | 58 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_base.c | 25 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_hsm.c | 11 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_legacy.c | 21 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_replace.c | 90 +-
arch/riscv/cpu/generic/cpu_vcpu_sbi_xvisor.c | 63 +
arch/riscv/cpu/generic/cpu_vcpu_timer.c | 306 +++-
arch/riscv/cpu/generic/cpu_vcpu_trap.c | 963 ++++++++++-
arch/riscv/cpu/generic/include/arch_mmu.h | 13 +-
arch/riscv/cpu/generic/include/arch_regs.h | 60 +
arch/riscv/cpu/generic/include/cpu_hwcap.h | 47 +-
arch/riscv/cpu/generic/include/cpu_tlb.h | 8 +-
arch/riscv/cpu/generic/include/cpu_vcpu_csr.h | 37 -
arch/riscv/cpu/generic/include/cpu_vcpu_fp.h | 4 +-
arch/riscv/cpu/generic/include/cpu_vcpu_helper.h | 9 +
arch/riscv/cpu/generic/include/cpu_vcpu_nested.h | 114 ++
arch/riscv/cpu/generic/include/cpu_vcpu_sbi.h | 19 +-
arch/riscv/cpu/generic/include/cpu_vcpu_timer.h | 20 +-
arch/riscv/cpu/generic/include/cpu_vcpu_trap.h | 26 +-
arch/riscv/cpu/generic/include/riscv_encoding.h | 671 ++++++--
arch/riscv/cpu/generic/objects.mk | 16 +-
.../board/common/devices/video/fb_early_console.c | 228 +++
arch/x86/board/common/devices/video/objects.mk | 1 +
arch/x86/board/common/include/video/ter-i16b.h | 3 +-
arch/x86/board/common/include/video/ter-i16n.h | 4 +-
arch/x86/board/common/include/x86_debug_log.h | 59 +
arch/x86/board/x86_64_generic/brd_defterm.c | 5 +
arch/x86/board/x86_64_generic/brd_pic.c | 2 +-
arch/x86/board/x86_64_generic/dts/defconfig.dts | 2 -
arch/x86/cpu/common/cpu_apic.c | 127 +-
arch/x86/cpu/common/include/cpu_apic.h | 2 +
arch/x86/cpu/common/include/cpu_inst_decode.h | 10 +
arch/x86/cpu/common/include/cpu_vm.h | 22 -
arch/x86/cpu/common/vm/arch_guest_helper.c | 7 +-
arch/x86/cpu/common/vm/cpu_inst_decode.c | 15 +
arch/x86/cpu/common/vm/svm/intercept.c | 115 +-
arch/x86/cpu/common/vm/svm/svm.c | 21 +-
arch/x86/cpu/common/vm/vm.c | 37 +-
arch/x86/cpu/common/vm/vtx/ept.c | 173 +-
arch/x86/cpu/common/vm/vtx/intercept.c | 148 +-
arch/x86/cpu/common/vm/vtx/vmcs.c | 24 +-
arch/x86/cpu/common/vm/vtx/vmx.c | 31 +-
arch/x86/cpu/x86_64/cpu_main.c | 9 +-
arch/x86/cpu/x86_64/cpu_mmu.c | 93 +-
arch/x86/cpu/x86_64/cpu_vcpu_helper.c | 15 +-
arch/x86/cpu/x86_64/include/cpu_mmu.h | 4 +
arch/x86/cpu/x86_64/start.S | 5 +
.../guests/{x86_64_guest.dtsi => amd_guest.dts} | 0
commands/cmd_host.c | 61 +-
commands/cmd_memory.c | 152 +-
core/include/vmm_devres.h | 8 +
core/include/vmm_devtree.h | 10 +
core/include/vmm_host_io.h | 8 +
core/include/vmm_host_irq.h | 30 +-
core/include/vmm_host_irqdomain.h | 16 +-
core/include/vmm_msi.h | 17 +-
core/include/vmm_scheduler.h | 3 +
core/include/vmm_smp.h | 13 +
core/vmm_devres.c | 54 +
core/vmm_devtree.c | 5 +-
core/vmm_devtree_irq.c | 19 +-
core/vmm_host_irq.c | 62 +-
core/vmm_host_irqdomain.c | 93 +-
core/vmm_host_irqext.c | 3 +-
core/vmm_msi.c | 123 +-
core/vmm_platform.c | 29 +-
core/vmm_platform_msi.c | 4 +-
core/vmm_scheduler.c | 7 +
core/vmm_smp.c | 23 +
core/vmm_stdio.c | 12 +-
core/vmm_workqueue.c | 2 +-
docs/releases/v0.3.2 | 62 +
docs/x86/x86_64_generic.txt | 7 +-
drivers/clocksource/riscv_timer.c | 39 +-
drivers/ide/host/piix3_ide.c | 4 +-
drivers/include/drv/irqchip/riscv-aplic.h | 115 ++
drivers/include/drv/irqchip/riscv-imsic.h | 87 +
drivers/input/mouse/alps.h | 4 +-
drivers/input/mouse/lifebook.h | 6 +-
drivers/input/mouse/logips2pp.h | 2 +-
drivers/input/mouse/sentelic.h | 4 +-
drivers/input/mouse/trackpoint.h | 2 +-
drivers/irqchip/irq-avic.c | 2 +-
drivers/irqchip/irq-bcm2835.c | 4 +-
drivers/irqchip/irq-bcm2836.c | 2 +-
drivers/irqchip/irq-gic-v3.c | 2 +-
drivers/irqchip/irq-gic.c | 2 +-
drivers/irqchip/irq-omap-intc.c | 2 +-
drivers/irqchip/irq-riscv-aclint-swi.c | 2 +-
drivers/irqchip/irq-riscv-aplic.c | 664 ++++++++
drivers/irqchip/irq-riscv-imsic.c | 1147 +++++++++++++
drivers/irqchip/irq-riscv-intc.c | 45 +-
drivers/irqchip/irq-sifive-plic.c | 93 +-
drivers/irqchip/irq-sun4i.c | 2 +-
drivers/irqchip/irq-versatile-fpga.c | 2 +-
drivers/irqchip/irq-vic.c | 2 +-
drivers/irqchip/objects.mk | 2 +
drivers/irqchip/openconf.cfg | 22 +
emulators/include/emu/pci/pci_emu_core.h | 4 +-
emulators/pci/host/i440fx.c | 63 +-
emulators/pic/plic.c | 3 +-
libs/include/libs/bitops.h | 31 +-
libs/wboxtest/nested_mmu/nested_mmu_test.h | 3 +-
tests/arm32/common/basic/Makefile.inc | 2 +-
tests/arm32/common/basic/firmware.ld | 108 +-
tests/arm32/vexpress-a15/linux/linux_extra.config | 1 +
tests/arm32/virt-v7/linux/linux_extra.config | 1 +
tests/arm64/common/basic/firmware.ld | 53 +-
tests/arm64/virt-v8/linux/linux_extra.config | 1 +
tests/common/basic/Makefile.inc | 7 +
tests/common/busybox/busybox-1.33.1_defconfig | 4 +-
tests/common/scripts/build-arm-images.sh | 2 +-
tests/common/scripts/build-images.sh | 2 +-
tests/common/scripts/build-riscv-images.sh | 2 +-
tests/common/scripts/update-linux-defconfig.sh | 1 -
tests/riscv/common/basic/Makefile.inc | 1 +
tests/riscv/common/basic/arch_sbi.c | 302 ++++
tests/riscv/common/basic/arch_sbi.h | 359 +++-
tests/riscv/common/basic/firmware.ld | 5 +-
tests/riscv/virt32/basic/arch_board.c | 10 +-
tests/riscv/virt32/linux/cmdlist | 4 +-
tests/riscv/virt32/linux/linux_extra.config | 5 +
tests/riscv/virt32/linux/virt32.dts | 2 +-
tests/riscv/virt32/virt32-guest.dts | 4 +-
tests/riscv/virt64/basic/arch_board.c | 10 +-
tests/riscv/virt64/linux/cmdlist | 4 +-
tests/riscv/virt64/linux/linux_extra.config | 5 +
tests/riscv/virt64/linux/virt64.dts | 2 +-
tests/riscv/virt64/virt64-guest.dts | 4 +-
tests/x86/README | 25 +
tests/x86/create_hdd_partitions.expt | 36 -
tests/x86/guest_init.cmd | 13 -
tests/x86/hdd.layout | 7 -
tests/x86/intel-guest.dts | 203 +++
tests/x86/lomount.c | 435 -----
.../guest_init.cmd => xscripts/one_guest.xscript} | 7 +-
157 files changed, 9594 insertions(+), 1766 deletions(-)
delete mode 100644 arch/riscv/cpu/generic/cpu_vcpu_csr.c
create mode 100644 arch/riscv/cpu/generic/cpu_vcpu_nested.c
create mode 100644 arch/riscv/cpu/generic/cpu_vcpu_sbi_xvisor.c
delete mode 100644 arch/riscv/cpu/generic/include/cpu_vcpu_csr.h
create mode 100644 arch/riscv/cpu/generic/include/cpu_vcpu_nested.h
create mode 100644 arch/x86/board/common/devices/video/fb_early_console.c
create mode 100644 arch/x86/board/common/include/x86_debug_log.h
rename arch/x86/guests/{x86_64_guest.dtsi => amd_guest.dts} (100%)
create mode 100644 docs/releases/v0.3.2
create mode 100644 drivers/include/drv/irqchip/riscv-aplic.h
create mode 100644 drivers/include/drv/irqchip/riscv-imsic.h
create mode 100644 drivers/irqchip/irq-riscv-aplic.c
create mode 100644 drivers/irqchip/irq-riscv-imsic.c
create mode 100644 tests/riscv/common/basic/arch_sbi.c
create mode 100644 tests/x86/README
delete mode 100755 tests/x86/create_hdd_partitions.expt
delete mode 100644 tests/x86/guest_init.cmd
delete mode 100644 tests/x86/hdd.layout
create mode 100644 tests/x86/intel-guest.dts
delete mode 100644 tests/x86/lomount.c
rename tests/x86/{scripts/guest_init.cmd => xscripts/one_guest.xscript} (56%)
Regards,
Anup
Anup Patel
Jan 1, 2023, 8:05:16 AM1/1/23
to Xvisor Devel
Thanks,
Anup
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