How to create a design with memory

[Olivier Faure]

Hi,

I'm learning hardware design and so far XLS has felt very approachable, especially the DSLX language.

I'd like to build a RISC-V design as a learning experience. For that, I need load and store instructions. I'm guessing I could implement them with a huge internal array, but I'd like something more modular.

As an example, let's say I want to write a DSLX program that reads a value from an hardcoded address (say 0x42) and then writes "value + 1" to the same address. How do I write it the program and all the testing pipeline?

[Johan Euphrosine]

Bonjour Olivier,

There is a minimal example of integration with "external" RAM at: https://github.com/google/xls/blob/main/xls/examples/delay.x

Another contributor has also made a tentative integration in a bigger block here:

https://github.com/google/xls/pull/1092

The documentation is still lacking around the feature so I created https://github.com/google/xls/issues/1152 to track improvement around this.

You're more than welcome to contribute your ideas and suggestions by commenting on it!

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[Olivier Faure]

Hi,

It took me a while to parse what was going on in the ram.x example (the functional-like syntax may be elegant, but it's not very noob-friendly when you're trying to figure out which code does what!) and it looks like the "core" of the ram function is a big array of bytes being passed to each proc as state and returned as updated state?

How does work with synthesis? Wouldn't that generate an absurd number of flip-flops? Or is that ram module only intended for testing in-simulation?

Olivier.

[Paul Rigge]

Hello,

Yeah, the idea is that the ram proc models a ram for simulation, but when you go to generate RTL you generate the block without the ram. It's sort of an implicit assumption in XLS that we stitch leaf level blocks externally, although this issue is our tracker for a feature we call multi-proc codegen where we'd like to do more of the stitching in XLS. RAMs are parallel leafs to the leaf-level blocks we generate, i.e. they are expected to be instantiated externally and then stitched together to your block. The BUILD file for the delay example shows some codegen options (see here for more info) that will cause the channels to/from a RAM to be codegen'd specially, i.e. instead of ready/valid/data, it's flat addr, rd_data, wr_data, we, re, etc. ports.

My suggestion is to figure out what sort of RAMs you want to use (e.g. openram, FPGA block RAM, or whatever), use the ram model for XLS simulation, but use the ram codegen flags + a top-level block (handwritten is probably fine if you're only managing a handful of RAMs) that stitches the chosen RAM and XLS block together.

Note that the user interface is kind of clunky and annoying, ideally I'd like to have something that fills the same role of an SDC as part of the XLS flow to make specifying these sorts of metadata easier than passing a bunch of flags around. For now it's manageable if you have a small number of RAMs.

Thanks,

Paul

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