Executing xls generated verilog code using iverilog

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Debobroto Das

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Jan 3, 2024, 8:13:23 PM1/3/24
to xls-dev
Hello everyone,

I am totally new in the area. 

I was trying the XLS introductory tutorial from this link https://google.github.io/xls/tutorials/xlscc_overview/
I have followed the steps, and the generated RTL codes are stored in a file. The contents of the file is the following 

module xls_test(
  input wire [31:0] input,
  output wire [31:0] out
);
  wire [31:0] add_6;
  assign add_6 = input + 32'h0000_0003;
  assign out = add_6;

endmodule


Then, in the next step, I tried to run this RTL code using iVerilog simulator using the following command 

$ iverilog  test.v

It shows the following errors

test.v:2: syntax error
test.v:1: Errors in port declarations.
test.v:6: syntax error
test.v:6: error: Syntax error in continuous assignment



Can someone give me hints about how to use the XLS generated for simulation in iVerilog? 

Maximilien Dagois

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Jan 4, 2024, 8:54:41 PM1/4/24
to Debobroto Das, xls-dev
I am not an expert by any means, but input is a reserved keyword in verilog.
All the reported errors point to lines with that word in it.
Maybe try changing it to in and see if that works.
If that is the issue, I guess we'll need to change the tutorial to use non-problematic variable names.

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Paul Rigge

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Jan 4, 2024, 9:02:51 PM1/4/24
to Maximilien Dagois, Debobroto Das, xls-dev
+1 can confirm that the syntax error is from the input being named 'input'. Changing the problematic line to `input wire [31:0] in,` gets me past the error.

I don't think XLS does much to protect you from identifiers that are reserved verilog keywords. An identifier that's legal in the frontend language (e.g. C++) may not be a legal verilog identifier. This issue discusses a bit more.

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