Hello everyone,
I am totally new in the area.
I have followed the steps, and the generated RTL codes are stored in a file. The contents of the file is the following
module xls_test(
input wire [31:0] input,
output wire [31:0] out
);
wire [31:0] add_6;
assign add_6 = input + 32'h0000_0003;
assign out = add_6;
endmodule
Then, in the next step, I tried to run this RTL code using iVerilog simulator using the following command
$ iverilog test.v
It shows the following errors
test.v:2: syntax error
test.v:1: Errors in port declarations.
test.v:6: syntax error
test.v:6: error: Syntax error in continuous assignment
Can someone give me hints about how to use the XLS generated for simulation in iVerilog?