Targeting CPLDs like Atmel ATF1500?

[Rick Mann]

I'm working on a little hobby project and wanted to use a CPLD like the Atmel ATF1502. This is normally done using WinCUPL (or Atmel's version of it), but that app is old and clunky.

Looking around for open-source options, is XLS something that could target a CPLD? I'd be willing to do some work on the source code in this regard (I’m and expert software developer).

[Leary, Chris]

Hi Rick,

Thanks for reaching out -- XLS generates Verilog and SystemVerilog RTL (selectable by a flag), so conceptually the output can be fed to any tool that accepts Verilog constructs. We've done some cool demos on FPGAs "for fun" even though we don't generally target them right now for what we think of as mission-mode-supported flows.

At a technical level, for the purposes of producing Verilog, the main thing that changes from target to target right now (traditionally known as the "tech mapping") is the "delay model". The delay model really is a pile of data in protobuf form that we use as a basis for scheduling operations into pipe stages.

We have an example one for the open sky130 PDK here: https://github.com/google/xls/blob/0bc672dea2618ea947a97cd221a1bd30bf6ec6ab/xls/delay_model/models/sky130.textproto

As for the way we characterize a new target... I think we don't have full documentation for that yet... but there's basically a driver program that makes calls to a service that wraps a backend tool flow, and it jots down what delays it sees for operations -- it squeezes the ops until they fail to close timing, and notes down the number of picoseconds before it went "pop":

https://github.com/google/xls/blob/0bc672dea2618ea947a97cd221a1bd30bf6ec6ab/xls/synthesis/timing_characterization_client_main.py

It does it that way because some synthesis tools can be "lazy" until they run up against a timing budget, so you can get things that are quite suboptimal before it's up against that limit.

Example service using an open toolflow (yosys): https://github.com/google/xls/blob/0bc672dea2618ea947a97cd221a1bd30bf6ec6ab/xls/synthesis/yosys/yosys_server_main.cc#L63

Probably the most challenging bit will be hooking up your backend tool flow behind the service API to characterize the delays. That yosys one would serve as a good example though even if there's a new binary flow. Feel free to generalize the yosys one to support different tool invocations if you decide to take that on and it seems natural.

You could also use the delay model from something else, and presumably just get a bad fmax. If you're just trying to get something going that's often not the end of the world.

Notably XLS hasn't focused on FPGA specific nuances like effective DSP mapping, or being particularly friendly to a discrete-routed substrate with span wires, or methodologies for squeezing LUTs out. Just a fair warning in case you're hoping those are "in the box" already.

Let me know if that makes sense. I'd been meaning to write up the characterization flow for the open PDKs so this might be a good opportunity to do so or explain parts that aren't so clear.

- Chris Leary

On Mon, Nov 28, 2022 at 2:13 PM Rick Mann <jetf...@gmail.com> wrote:

I'm working on a little hobby project and wanted to use a CPLD like the Atmel ATF1502. This is normally done using WinCUPL (or Atmel's version of it), but that app is old and clunky.

Looking around for open-source options, is XLS something that could target a CPLD? I'd be willing to do some work on the source code in this regard (I’m and expert software developer).

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[Rick Mann]

Thanks for that thorough explanation. This may be more work than I want to take on right now. I guess XLS is probably much higher-level than what I need, which is really something that can take Verilog in and program the CPLD. I may just have to suffer through learning CUPL and using WinCUPL.

[Leary, Chris]

Ah, yes you're right -- my mistake, I thought you were already using some verilog to bitstream tooling. +Tim Ansell may have more helpful pointers relating to https://f4pga.org/ toolchain and whether that device has been a target device for those tools in any experimental capacity.

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[Tim 'mithro' Ansell]

(Sending again now I'm on the xls-dev mailing list...)

I would recommend looking at the iCE40 series of FPGAs from Lattice. They are "CPLD like" and have a fully open source verilog to bitstream toolchain.

You could also explore the QuickLogic PolarPro 3E series of devices. They are "CPLD like" and have a fully open source verilog to bitstream toolchain that the vendor actually supports.

There was a group working on support for the Lattice Mach XO2 series in the open source toolchain but I don't know the current state, or if it is usable. A long while ago there was support for the Silego GreenPak series of programmable devices but I also don't know the current state of the toolchain for them.

In theory you could use something like XLS for here, but given how small these devices are, probably working in straight Verilog is going to be more productive? Not a lot of people have looked at using XLS on these very small devices but Johan Euphrosine <pro...@google.com> and Rob Springer <rspr...@google.com> did present something at WOSET 2021 about using XLS on my little Fomu FPGA dev board (which is an iCE40UP5K based solution) -- see https://woset-workshop.github.io/WOSET2021.html#article-5

Hope that helps!

Tim 'mithro' Ansell

[Rick]

Ah, those are much bigger than I want for my particular purpose. Of course they would be better (in terms of replacing a lot more discrete logic), but that’s not what I’m going for here.

It’s okay, I can use WinCUPL, I was just hoping for a more modern toolchain.

-- Rick

On Nov 28, 2022, at 18:26, Tim 'mithro' Ansell <tan...@google.com> wrote: