Fwd: Best Paper Award at the 29th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) | VAST lab

[Robert Hundt]

FYI...

---------- Forwarded message ---------
From: co...@cs.ucla.edu <co...@cs.ucla.edu>
Date: Sun, Mar 7, 2021 at 12:18 PM
Subject: Best Paper Award at the 29th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) | VAST lab
To: <rhu...@google.com>

Hi, Robert, 

I hope that all is going well in the new year.

I’d like to share with you this news with you and your team — we had good success in coupling HLS with floor planning which boosts clock frequency of a wide range of design by 2X on average (esp. those large designs that across multiple dies).  

https://vast.cs.ucla.edu/news/2021-03/best-paper-award-29th-acmsigda-international-symposium-field-programmable-gate-arrays

Maybe it’s something to consider in XLS.

Best,

-Jason

Jason Cong, PhD

Volgenau Chair for Engineering Excellence

UCLA Department of Computer Science (with joint appointment in Electrical Engineering)

http://cadlab.cs.ucla.edu/~cong

Director, VAST Laboratory https://vast.cs.ucla.edu 

Director, Center for Domain-Specific Computing www.cdsc.ucla.edu

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Robert Hundt | Platforms | rhu...@google.com | 650-253-7680