Thanks for your interest in XLS! Right now the scheduling and verilog generation is fused into one tool ("codegen_main"). This consumes optimized, unscheduled IR and does the following:
(1) schedules the IR
(2) lowers the IR into a
block. A block is an RTL-level representation of the design. it includes constructs like ports and registers.
(3) generates (System)Verilog from the block
Ideally, these would be broken into different tools to enable observation and manipulation of the IR at each stage like what you're looking to do. However, this is now monolithic.
You can access intermediate artifacts programmatically, though. For example, at this
point in the compilation process you have the optimized IR (`main`) and the schedule (`schedule`). You could transform the IR and schedule then feed it on to ToPipelinedModule to generate Verilog.
Mark