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Thanos Papadimitriou

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Dec 16, 2022, 6:23:29 AM12/16/22
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Hi, we are trying to use XLS to develop a tool to manipulate the IR but we would also like to read and manipulate the design after scheduling and right before printing out the verilog code.

Is this possible and in which format can we get the design at this stage of the flow?

Ideally we would like to get the info and work outside XLS to manipulate the deign and then
feed it back to the codegen to get the verilog design.

Thank you a lot in advance,
Thanos

Mark Heffernan

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Dec 16, 2022, 1:16:56 PM12/16/22
to Thanos Papadimitriou, xls-dev
Thanks for your interest in XLS! Right now the scheduling and verilog generation is fused into one tool ("codegen_main"). This consumes optimized, unscheduled IR and does the following:

(1) schedules the IR
(2) lowers the IR into a block. A block is an RTL-level representation of the design. it includes constructs like ports and registers.
(3) generates (System)Verilog from the block

Ideally, these would be broken into different tools to enable observation and manipulation of the IR at each stage like what you're looking to do. However, this is now monolithic.

You can access intermediate artifacts programmatically, though. For example, at this point in the compilation process you have the optimized IR (`main`) and the schedule (`schedule`). You could transform the IR and schedule then feed it on to ToPipelinedModule to generate Verilog.

Mark

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Johan Euphrosine

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Dec 22, 2022, 9:03:06 AM12/22/22
to Mark Heffernan, Thanos Papadimitriou, xls-dev
Linking those two related issues for context:

`codegen_main` also seem to have an option to dump the schedule in a separate file:
the notebook below shows what the output looks like (in proto text format):

Hope that helps.





Mark Heffernan

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Dec 22, 2022, 1:22:21 PM12/22/22
to Johan Euphrosine, Thanos Papadimitriou, xls-dev
Thanks, Johan. I realized I did not reply-all to my earlier response to Thanos so it didn't make it to xls-dev. Here it is for posterity:

FYI, I filed https://github.com/google/xls/issues/813 for this issue of splitting up the codegen process.

Also, passing in `--logtostderr --vmodule=pipeline_generator=2` should dump the schedule and the optimized IR to stderr for you to scrape. You'll need to modify codegen_main to feed the transformed IR/schedule back in, however.

- Mark

 

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