Quadmode init
folknology
concerned with its initial concepts and issues.
Here are some initial things we need to answer
1) First of all Quadmode is an extension to SPI, and thus needs SPI
underneath. we could perhaps reuse the example Xmos SPI code or start
our own from scratch ?
2) Do we implement Quadmode using only 1 bit ports, or perhaps create
a more optimised port mapping using a 1bit port and the LSB of port 8D
(my preference).
3) Which devices should we aim to support first Flash, ADCs or some
other chip.
I'm sure their are other questions..
Let the discussion begin..
Jonathan May
> a more optimised port mapping using a 1bit port and the LSB of port 8D
> (my preference).
This is going to crop up quite commonly as a variable in interface
implementations. You are going to need to create separate versions of
the code for separate port maps/availability/clarity/speed.
Some people wishing to use the code may only have certain ports available.
Even in the XMOS-distributed code there is often more than one different
implementation of the same interface, and moreover different
implementations of different variants of the interface.
My opinion is that the first implementation should always be one
optimised for clarity alone.
Jonathan
--
Jonathan May, Managing Director
Silicon Futures Limited
T: +44(0)7767 847278
F: +44(0)1173 270277
E: jona...@siliconfutures.com
Al Wood
>> 2) Do we implement Quadmode using only 1 bit ports, or perhaps create
>> a more optimised port mapping using a 1bit port and the LSB of port 8D
>> (my preference).
>
> This is going to crop up quite commonly as a variable in interface
> implementations. You are going to need to create separate versions of the
> code for separate port maps/availability/clarity/speed.
>
Well the 1 bit version is more flexible when it comes to pin shuffling
I guess, even though the use of 8D maybe more elegant.
> Some people wishing to use the code may only have certain ports available.
>
> Even in the XMOS-distributed code there is often more than one different
> implementation of the same interface, and moreover different implementations
> of different variants of the interface.
>
> My opinion is that the first implementation should always be one optimised
> for clarity alone.
That would probably be made from 1 bit ports, as the 8bit port will be
more knarly due to switching port modes, although the later becomes
more elegant potentially (less bit masking required).
>
> Jonathan
>
> --
> Jonathan May, Managing Director
> Silicon Futures Limited
> T: +44(0)7767 847278
> F: +44(0)1173 270277
> E: jona...@siliconfutures.com
>
>
Al Wood
(3) I would love to use Quadmode SRAM but haven't been able to locate
any, is anyone else aware of QM SRAM in the pipe or already shipping
as it would be rather handy?
regards
Al
Russ Ferriday
"Quad-mode has emerged over last 18 months," said Lees. "After the initial handshake, the pins of the SPI interface are re-purposed into four data lanes that each support 80Mbit/s which is a total of 40Mbyte/s. So on a cold re-start you can transfer entire SPI flash in 1/3 to 1/100 seconds into on-chip SRAM or exterior RAM."
He claims NXP has tested quad-mode operation with 80 different flash chips from six supplier.
http://www.electronicsweekly.com/Articles/2010/09/23/49506/NXP-reveals-more-on-150MHz-Cortex-M3.htm
Russ Ferriday -- Systems Architect & Entrepreneur
Al Wood
> "Quad-mode has emerged over last 18 months," said Lees. "After the initial
> handshake, the pins of the SPI interface are re-purposed into four data
> lanes that each support 80Mbit/s which is a total of 40Mbyte/s. So on a cold
> re-start you can transfer entire SPI flash in 1/3 to 1/100 seconds into
> on-chip SRAM or exterior RAM."
>
> He claims NXP has tested quad-mode operation with 80 different flash chips
> from six supplier.
>
> http://www.electronicsweekly.com/Articles/2010/09/23/49506/NXP-reveals-more-on-150MHz-Cortex-M3.htm
>
> So they must be out there.
Yeah that's External Flash he's talking about and it is available, But
I am also interested in external QM SRAM, thats what I cannot find.
Russ Ferriday
led me to
and the cypress prod code got me here:
Al Wood
> Then this may do it for you...
> wikipedia
>
> http://en.wikipedia.org/wiki/Quad_Data_Rate_SRAM
>
> led me to
>
> http://electronicdesign.com/article/digital/quad-data-rate-sram-subsystems-maximize-system-per.aspx
>
> and the cypress prod code got me here:
>
> http://www.cypress.com/?app=search&searchType=part&keywords=CY7C1302
>
> Is this what you were looking for?
> --r
Alas no thats pipelined Quad Data Rate (QDR) SRAM which uses parallel
address and databuses
I'm looking for QuadMode SPI S/RAM