[RFC][PATCH] APX: Add R_X86_64_CODE_4_GOTPC32_TLSDESC

[H.J. Lu]

For TLS instruction:

lea foo@tlsdesc(%rip), %reg

add

#define R_X86_64_CODE_4_GOTPC32_TLSDESC 45

if the instruction starts at 4 bytes before the relocation offset. This
should be used if reg is one of the additional general-purpose registers,
r16-r31, in Intel APX. It is similar to R_X86_64_GOTPC32_TLSDESC and
linker optimization must take the different instruction encoding into
account.
---
x86-64-ABI/object-files.tex | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/x86-64-ABI/object-files.tex b/x86-64-ABI/object-files.tex
index 8acdb78..3cc6a4f 100644
--- a/x86-64-ABI/object-files.tex
+++ b/x86-64-ABI/object-files.tex
@@ -488,6 +488,7 @@ or \texttt{Elf32_Rel} relocation entries.
\texttt{R_X86_64_REX_GOTPCRELX} & 42 & \textit{word32} & \texttt{G + GOT + A - P} \\
\texttt{R_X86_64_CODE_4_GOTPCRELX} & 43 & \textit{word32} & \texttt{G + GOT + A - P} \\
\texttt{R_X86_64_CODE_4_GOTTPOFF} & 44 & \textit{word32} & \\
+ \texttt{R_X86_64_CODE_4_GOTPC32_TLSDESC} & 45 & \textit{word32} & \\
\cline{1-4}
\multicolumn{4}{l}{\small $^\dagger$ This relocation is used only for LP64.}\\
\multicolumn{4}{l}{\small $^{\dagger\dagger}$ This relocation only
@@ -586,6 +587,10 @@ writing. A description can be found in the document ``Thread-Local
Storage Descriptors for IA32 and AMD64/EM64T''\footnote{This document
is currently available via
\raggedright\url{http://www.fsfla.org/~lxoliva/writeups/TLS/RFC-TLSDESC-x86.txt}}.
+\texttt{R_X86_64_CODE_4_GOTPC32_TLSDESC} should be generated, instead of
+\texttt{R_X86_64_GOTPC32_TLSDESC}, if the instruction starts at 4 bytes
+before the relocation offset and linker optimization must take the
+different instruction encoding into account.
\end{sloppypar}

In order to make this document self-contained, a description of the
--
2.41.0

[Michael Matz]

Hey,

On Fri, 8 Sep 2023, H.J. Lu wrote:

> For TLS instruction:
>
> lea foo@tlsdesc(%rip), %reg
>
> add
>
> #define R_X86_64_CODE_4_GOTPC32_TLSDESC 45
>
> if the instruction starts at 4 bytes before the relocation offset. This
> should be used if reg is one of the additional general-purpose registers,
> r16-r31, in Intel APX. It is similar to R_X86_64_GOTPC32_TLSDESC and
> linker optimization must take the different instruction encoding into
> account.

I wish we had thought about all that much earlier and made the numbering
of the relocs more intelligent, so that e.g. the number of bytes to look
back would be a bitfield in that number. Alas, that ship has sailed
decades ago, so: the above makes sense IMHO.


Ciao,
Michael.

[H.J. Lu]

On Mon, Sep 11, 2023 at 5:45 AM Michael Matz <ma...@suse.de> wrote:
>
> Hey,
>
> On Fri, 8 Sep 2023, H.J. Lu wrote:
>
> > For TLS instruction:
> >
> > lea foo@tlsdesc(%rip), %reg
> >
> > add
> >
> > #define R_X86_64_CODE_4_GOTPC32_TLSDESC 45
> >
> > if the instruction starts at 4 bytes before the relocation offset. This
> > should be used if reg is one of the additional general-purpose registers,
> > r16-r31, in Intel APX. It is similar to R_X86_64_GOTPC32_TLSDESC and
> > linker optimization must take the different instruction encoding into
> > account.
>
> I wish we had thought about all that much earlier and made the numbering
> of the relocs more intelligent, so that e.g. the number of bytes to look
> back would be a bitfield in that number. Alas, that ship has sailed
> decades ago, so: the above makes sense IMHO.
>

Here is the merge request:

https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/49

Thanks.

H.J.