[PATCH] Add GNU_PROPERTY_X86_FEATURE_2_CODE16

[H.J. Lu]

An 32-bit or 64-bit object may be used as a container for 16-bit mode
instructions. Update GNU_PROPERTY_X86_FEATURE_2_USED with

#define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)

to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions. This should
address

https://sourceware.org/bugzilla/show_bug.cgi?id=27905
---
x86-64-ABI/dl.tex | 3 +++
1 file changed, 3 insertions(+)

diff --git a/x86-64-ABI/dl.tex b/x86-64-ABI/dl.tex
index 75e1e40..77db4a7 100644
--- a/x86-64-ABI/dl.tex
+++ b/x86-64-ABI/dl.tex
@@ -572,6 +572,7 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
\texttt{GNU_PROPERTY_X86_FEATURE_2_XSAVEC} & \texttt{1U << 9} \\
\texttt{GNU_PROPERTY_X86_FEATURE_2_TMM} & \texttt{1U << 10} \\
\texttt{GNU_PROPERTY_X86_FEATURE_2_MASK} & \texttt{1U << 11} \\
+ \texttt{GNU_PROPERTY_X86_FEATURE_2_CODE16} & \texttt{1U << 12} \\
\cline{1-2}
\multicolumn{2}{p{13cm}}{\small $^\dagger$ This bit should always
be set when \texttt{GNU_PROPERTY_X86_FEATURE_2_USED} is used.}\\
@@ -602,6 +603,8 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
feature is used.
\item[GNU_PROPERTY_X86_FEATURE_2_MASK] This indicates that mask register
feature is used.
+ \item[GNU_PROPERTY_X86_FEATURE_2_CODE16] This indicates that 16-bit mode
+ instructions are used.
\end{description}

%%% Local Variables:
--
2.31.1

[H.J. Lu]

An 32-bit or 64-bit object may be used as a container for 16-bit mode
instructions. Update GNU_PROPERTY_X86_FEATURE_2_USED with

#define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)

to indicate that only 16-bit mode instructions are used in the object to

allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions. This should
address:

https://sourceware.org/bugzilla/show_bug.cgi?id=27905
---
x86-64-ABI/dl.tex | 3 +++
1 file changed, 3 insertions(+)

diff --git a/x86-64-ABI/dl.tex b/x86-64-ABI/dl.tex

index 75e1e40..f694e11 100644

--- a/x86-64-ABI/dl.tex
+++ b/x86-64-ABI/dl.tex
@@ -572,6 +572,7 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
\texttt{GNU_PROPERTY_X86_FEATURE_2_XSAVEC} & \texttt{1U << 9} \\
\texttt{GNU_PROPERTY_X86_FEATURE_2_TMM} & \texttt{1U << 10} \\
\texttt{GNU_PROPERTY_X86_FEATURE_2_MASK} & \texttt{1U << 11} \\
+ \texttt{GNU_PROPERTY_X86_FEATURE_2_CODE16} & \texttt{1U << 12} \\
\cline{1-2}
\multicolumn{2}{p{13cm}}{\small $^\dagger$ This bit should always
be set when \texttt{GNU_PROPERTY_X86_FEATURE_2_USED} is used.}\\
@@ -602,6 +603,8 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
feature is used.
\item[GNU_PROPERTY_X86_FEATURE_2_MASK] This indicates that mask register
feature is used.

+ \item[GNU_PROPERTY_X86_FEATURE_2_CODE16] This indicates that only 16-bit
+ mode instructions are used.

[Jan Beulich]

On 25.05.2021 14:56, H.J. Lu wrote:
> --- a/x86-64-ABI/dl.tex
> +++ b/x86-64-ABI/dl.tex
> @@ -572,6 +572,7 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
> \texttt{GNU_PROPERTY_X86_FEATURE_2_XSAVEC} & \texttt{1U << 9} \\
> \texttt{GNU_PROPERTY_X86_FEATURE_2_TMM} & \texttt{1U << 10} \\
> \texttt{GNU_PROPERTY_X86_FEATURE_2_MASK} & \texttt{1U << 11} \\
> + \texttt{GNU_PROPERTY_X86_FEATURE_2_CODE16} & \texttt{1U << 12} \\
> \cline{1-2}
> \multicolumn{2}{p{13cm}}{\small $^\dagger$ This bit should always
> be set when \texttt{GNU_PROPERTY_X86_FEATURE_2_USED} is used.}\\
> @@ -602,6 +603,8 @@ and \code{GNU_PROPERTY_X86_FEATURE_2_NEEDED}:
> feature is used.
> \item[GNU_PROPERTY_X86_FEATURE_2_MASK] This indicates that mask register
> feature is used.
> + \item[GNU_PROPERTY_X86_FEATURE_2_CODE16] This indicates that only 16-bit
> + mode instructions are used.

Is "only" really correct here, considering the grouping with items
where individual objects' values get ORed together (whereas for "only"
they would need to be ANDed)?

Jan

[H.J. Lu]

You are right. I withdrew the v2 patch. The original one is correct.
16-bit SeaBIOS
has

.code32
1:calll *%edi
movl $2f, %edx
jmp transition16big
.code16gcc
2:movl %ebx, %ds
movl %ebx, %ss
movl %ebp, %esp


--
H.J.