[x-loader][PATCH v2] OMAP4: Select DPLL PER Clock as source for SGX FCLK

[Sebastien Jan]

From: Rajeev Kulkarni <raj...@ti.com>

The correct frequency for SGX is 307.2 Mhz. If DPLL_PER
is set 1536 Mhz, There is no need to change dividers, just
parent clock need to change. And DPLL PER is set at 1536.

Signed-off-by: Rajeev Kulkarni <raj...@ti.com>
Signed-off-by: Ricardo Salveti de Araujo <ricardo...@canonical.com>
Signed-off-by: Sebastien Jan <s-...@ti.com>
---
board/omap4430panda/clock.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index 4ccceca..27f7d92 100644
--- a/board/omap4430panda/clock.c
+++ b/board/omap4430panda/clock.c
@@ -715,6 +715,8 @@ static void enable_all_clocks(void)
/* Enable SGX clocks */
sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
+ /* Select DPLL PER CLOCK as source for SGX FCLK */
+ sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
/* Check for SGX FCLK and ICLK */
while (__raw_readl(0x4A009200) != 0x302)
;
--
1.7.1

[Anand Gadiyar]

> From: Rajeev Kulkarni <raj...@ti.com>
>
> The correct frequency for SGX is 307.2 Mhz. If DPLL_PER
> is set 1536 Mhz, There is no need to change dividers, just
> parent clock need to change. And DPLL PER is set at 1536.
>
> Signed-off-by: Rajeev Kulkarni <raj...@ti.com>
> Signed-off-by: Ricardo Salveti de Araujo <ricardo...@canonical.com>
> Signed-off-by: Sebastien Jan <s-...@ti.com>

Applied, thanks!