[x-loader][RFC PATCH 0/4] Remove unmaintained code
Enric Balletbo i Serra
As discussed in this thread
seems ha no sense maintain the support for OMAP2 boards, this patch series
tries to remove this unmaintained code.
Cheers,
Enric Balletbo i Serra (4):
omap2420h4: Remove this board because is not being maintained
omap2420sdp: Remove this board because is not being maintained
cpu/arm1136: Remove arm1136 support
arch-arm926ejs/sizes.h: Remove this files as is not being used.
Makefile | 6 -
README | 12 +-
board/omap2420h4/Makefile | 51 ---
board/omap2420h4/config.mk | 26 --
board/omap2420h4/omap2420h4.c | 598 --------------------------
board/omap2420h4/platform.S | 218 ----------
board/omap2420h4/x-load.lds | 54 ---
board/omap2430sdp/Makefile | 51 ---
board/omap2430sdp/config.mk | 28 --
board/omap2430sdp/omap2430sdp.c | 746 ---------------------------------
board/omap2430sdp/platform.S | 198 ---------
board/omap2430sdp/x-load.lds | 54 ---
cpu/arm1136/Makefile | 47 --
cpu/arm1136/config.mk | 33 --
cpu/arm1136/cpu.c | 65 ---
cpu/arm1136/start.S | 218 ----------
drivers/Makefile | 8 -
include/asm/arch-arm1136/bits.h | 49 ---
include/asm/arch-arm1136/clocks.h | 51 ---
include/asm/arch-arm1136/clocks242x.h | 147 -------
include/asm/arch-arm1136/clocks243x.h | 223 ----------
include/asm/arch-arm1136/mem.h | 383 -----------------
include/asm/arch-arm1136/omap2420.h | 223 ----------
include/asm/arch-arm1136/omap2430.h | 255 -----------
include/asm/arch-arm1136/sizes.h | 50 ---
include/asm/arch-arm1136/sys_info.h | 139 ------
include/asm/arch-arm926ejs/sizes.h | 51 ---
include/configs/omap2420h4.h | 140 ------
include/configs/omap2430sdp.h | 178 --------
29 files changed, 1 insertions(+), 4301 deletions(-)
delete mode 100644 board/omap2420h4/Makefile
delete mode 100644 board/omap2420h4/config.mk
delete mode 100644 board/omap2420h4/omap2420h4.c
delete mode 100644 board/omap2420h4/platform.S
delete mode 100644 board/omap2420h4/x-load.lds
delete mode 100644 board/omap2430sdp/Makefile
delete mode 100644 board/omap2430sdp/config.mk
delete mode 100644 board/omap2430sdp/omap2430sdp.c
delete mode 100644 board/omap2430sdp/platform.S
delete mode 100644 board/omap2430sdp/x-load.lds
delete mode 100644 cpu/arm1136/Makefile
delete mode 100644 cpu/arm1136/config.mk
delete mode 100644 cpu/arm1136/cpu.c
delete mode 100644 cpu/arm1136/start.S
delete mode 100644 include/asm/arch-arm1136/bits.h
delete mode 100644 include/asm/arch-arm1136/clocks.h
delete mode 100644 include/asm/arch-arm1136/clocks242x.h
delete mode 100644 include/asm/arch-arm1136/clocks243x.h
delete mode 100644 include/asm/arch-arm1136/mem.h
delete mode 100644 include/asm/arch-arm1136/omap2420.h
delete mode 100644 include/asm/arch-arm1136/omap2430.h
delete mode 100644 include/asm/arch-arm1136/sizes.h
delete mode 100644 include/asm/arch-arm1136/sys_info.h
delete mode 100644 include/asm/arch-arm926ejs/sizes.h
delete mode 100644 include/configs/omap2420h4.h
delete mode 100644 include/configs/omap2430sdp.h
Enric Balletbo i Serra
Signed-off-by: Enric Balletbo i Serra <ebal...@gmail.com>
---
Makefile | 3 -
board/omap2420h4/Makefile | 51 ----
board/omap2420h4/config.mk | 26 --
board/omap2420h4/omap2420h4.c | 598 -----------------------------------------
board/omap2420h4/platform.S | 218 ---------------
board/omap2420h4/x-load.lds | 54 ----
drivers/Makefile | 4 -
include/configs/omap2420h4.h | 140 ----------
8 files changed, 0 insertions(+), 1094 deletions(-)
delete mode 100644 board/omap2420h4/Makefile
delete mode 100644 board/omap2420h4/config.mk
delete mode 100644 board/omap2420h4/omap2420h4.c
delete mode 100644 board/omap2420h4/platform.S
delete mode 100644 board/omap2420h4/x-load.lds
delete mode 100644 include/configs/omap2420h4.h
diff --git a/Makefile b/Makefile
index 7f836e2..f378923 100644
--- a/Makefile
+++ b/Makefile
@@ -201,9 +201,6 @@ unconfig:
## OMAP2 (ARM1136) Systems
#########################################################################
-omap2420h4_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
-
omap2430sdp_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp
diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile
deleted file mode 100644
index e6f7629..0000000
--- a/board/omap2420h4/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap2420h4.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk
deleted file mode 100644
index 1c770f3..0000000
--- a/board/omap2420h4/config.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-# CONFIG_PARTIAL_SRAM must be defined to use this.
-TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
-#
-#TEXT_BASE = 0x40280000
-
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
deleted file mode 100644
index ef81b49..0000000
--- a/board/omap2420h4/omap2420h4.c
+++ /dev/null
@@ -1,598 +0,0 @@
-/*
- * Copyright (C) 2005 Texas Instruments.
- * Jian Zhang <jzh...@ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/bits.h>
-
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-
-static void wait_for_command_complete(unsigned int wd_base);
-static void watchdog_init(void);
-static void peripheral_enable(void);
-static void muxSetupUART1(void);
-static u32 get_cpu_rev(void);
-
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-#ifdef CFG_SDRAM_DDR
-void
-config_sdram_ddr(u32 rev)
-{
- /* ball D11, mode 0 */
- __raw_writeb(0x08, 0x48000032);
-
- /* SDRC_CS0 Configuration */
- if (rev == CPU_2420_2422_ES1) {
- __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- } else {
- __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
- }
-
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
-
- /*
- * CS0 SDRC Mode Register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- __raw_writel(0x00000032, SDRC_MR_0);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000002, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000002, SDRC_DLLB_CTRL);
- } else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
- }
-
-}
-#endif // CFG_SDRAM_DDR
-
-
-#ifdef CFG_SDRAM_COMBO
-void
-config_sdram_combo(u32 rev)
-{
-
- u32 dllctrl=0;
-
- /* ball C12, mode 0 */
- __raw_writeb(0x00, 0x480000a1);
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
- /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
- __raw_writeb(0x00, 0x480000a3);
-
- /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG);
-
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* CS1 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_1);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- /* CS1 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- }
-}
-
-#endif // CFG_SDRAM_COMBO
-
-#ifdef CFG_SDRAM_SDR
-void
-config_sdram_sdr(u32 rev)
-{
- u32 dllctrl=0;
-
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
-
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG);
-
- /* Chip-level shared interface management */
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
- if (rev == CPU_2420_2422_ES1)
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- else
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX14: 32Mbx32 */
- __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 2 - SDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */
-
- /* SDRC DLLA control register */
- /* Enable DLL, Load counter with 115 (middle of range) */
- /* Delay is 90 degrees */
-
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- }
-
-}
-#endif // CFG_SDRAM_SDR
-
-#ifdef CFG_SDRAM_STACKED
-void
-config_sdram_stacked(u32 rev)
-{
-
- /* Pin Muxing for SDRC */
- __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
- __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
- __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
- __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
-
- /* configure sdrc 32 bit for COMBO ddr sdram */
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */
-
- /* SDRC_SHARING */
- /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
- //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- __raw_writel(0x00004900, SDRC_SHARING);
-
- /* SDRC_CS0 Configuration */
- /* None for ES2.1 */
-
- /* SDRC_CS1 Configuration */
- __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */
-
- /* Disable power down of CKE */
- __raw_writel(0x00000085, SDRC_POWER);
-
- __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */
- __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */
- __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */
- __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */
-
- /*Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_1);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(0x00000032, SDRC_MR_1);
- __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL);
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-#endif // CFG_SDRAM_STACKED
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-int s_init(int skip)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
- watchdog_init();
- muxSetupUART1();
- delay(100);
-
- /*DPLL out = 2x DPLL --> core clock */
- __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);
-
- /*DPLL into low power bypass (others off) */
- __raw_writel(0x00000001, CM_CLKEN_PLL);
-
- /*MPU core clock = Core /2 = 300 */
- __raw_writel(MPU_DIV, CM_CLKSEL_MPU);
-
- /*DSPif=200, DSPif=100, IVA=200 */
- __raw_writel(DSP_DIV, CM_CLKSEL_DSP);
-
- /*GFX clock (L3/2) 50MHz */
- __raw_writel(GFX_DIV, CM_CLKSEL_GFX);
-
- /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */
- __raw_writel(BUS_DIV, CM_CLKSEL1_CORE);
-
- /*12MHz apll src, 12/(1+1)*50=300 */
- __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
-
- /*Valid the configuration */
- __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
- delay(1000);
-
- /*Enable DPLL=300, 96MHz APLL locked. */
- __raw_writel(0x0000000F, CM_CLKEN_PLL);
- delay(200000);
-
-#ifdef CFG_SDRAM_DDR
- config_sdram_ddr(rev);
-#elif defined(CFG_SDRAM_COMBO)
- config_sdram_combo(rev);
-#elif defined(CFG_SDRAM_SDR)
- config_sdram_sdr(rev);
-#elif defined(CFG_SDRAM_STACKED)
- config_sdram_stacked(rev);
-#else
-#error SDRAM type not supported
-#endif
-
- delay(20000);
- peripheral_enable();
- return(0);
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-static void watchdog_init(void)
-{
-#define GP (BIT8|BIT9)
-
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * I would expect that the ROM takes care of the secure one,
- * but we will try also. Of the 3 GP ones, 1 can reset us
- * directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
- __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
- wait_for_command_complete(WD3_BASE);
- __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
-
- __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
- wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
-#endif
-
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-static void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base+WWPS);
- } while (pending);
-}
-
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-static void peripheral_enable(void)
-{
- unsigned int v, if_clks=0, func_clks=0;
-
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CFG_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- delay(1000);
-
-#ifndef KERNEL_UPDATED
- {
-#define V1 0xffffffff
-#define V2 0x00000007
-
- __raw_writel(V1, CM_FCLKEN1_CORE);
- __raw_writel(V2, CM_FCLKEN2_CORE);
- __raw_writel(V1, CM_ICLKEN1_CORE);
- __raw_writel(V1, CM_ICLKEN2_CORE);
- }
-#endif
-
-}
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-static void muxSetupUART1(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* UART1_CTS pin configuration, PIN = D21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RTS pin configuration, PIN = H21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_TX pin configuration, PIN = L20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RX pin configuration, PIN = T21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-int nand_init(void)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
-
- /* GPMC pin muxing */
- (*(volatile int*)0x48000070) &= 0x000000FF;
- (*(volatile int*)0x48000074) &= 0x00000000;
- (*(volatile int*)0x48000078) &= 0x00000000;
- (*(volatile int*)0x4800007C) &= 0x00000000;
- (*(volatile int*)0x48000080) &= 0xFF000000;
-
- /* GPMC_IO_DIR */
- (*(volatile int*)0x4800008C) = 0x19000000;
-
- /* GPMC Configuration */
- (*(volatile int*)0x6800A010) = 0x0000000A;
- while (((*(volatile int *)0x6800A014) & 0x00000001) == 0);
-
- (*(volatile int*)0x6800A050) = 0x00000001;
- (*(volatile int*)0x6800A060) = 0x00001800;
- (*(volatile int*)0x6800A064) = 0x00141400;
- (*(volatile int*)0x6800A068) = 0x00141400;
- (*(volatile int*)0x6800A06C) = 0x0F010F01;
- (*(volatile int*)0x6800A070) = 0x010C1414;
- (*(volatile int*)0x6800A074) = 0x00000A80;
- (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000
-
- (*(volatile int*)0x6800A0A8) = 0x00000000;
- delay(1000);
-#ifdef CFG_SDRAM_STACKED
- (*(volatile int*)0x6800A090) = 0x00011000;
-#else
- (*(volatile int*)0x6800A090) = 0x00011200;
-#endif
- (*(volatile int*)0x6800A094) = 0x001f1f00;
- (*(volatile int*)0x6800A098) = 0x00080802;
- (*(volatile int*)0x6800A09C) = 0x1C091C09;
- (*(volatile int*)0x6800A0A0) = 0x031A1F1F;
- (*(volatile int*)0x6800A0A4) = 0x000003C2;
- (*(volatile int*)0x6800A0A8) = 0x00000F48;
-
- if (rev != CPU_2420_2422_ES1)
- (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x
-
- if (nand_chip()){
- printf("Unsupported Chip!\n");
- return 1;
- }
- return 0;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return(v+1); /* currently 2422 and 2420 match up */
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{}
-
-
-
diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S
deleted file mode 100644
index 5cc37e5..0000000
--- a/board/omap2420h4/platform.S
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#ifdef CONFIG_PARTIAL_SRAM
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- * R2 = dpll value
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- sub sp, sp, #0x4 /* get some stack space */
- str r4, [sp] /* save r4's value */
-
- /* move into fast relock bypass */
- ldr r8, pll_ctl_add
- mov r4, #0x2
- str r4, [r8]
- ldr r4, pll_stat
-block:
- ldr r8, [r4] /* wait for bypass to take effect */
- and r8, r8, #0x3
- cmp r8, #0x1
- bne block
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div_add
- ldr r8, pll_div_val
- str r8, [r4]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r4, cfg3_0_addr
- ldr r8, cfg3_0_val
- str r8, [r4]
- ldr r4, cfg4_0_addr
- ldr r8, cfg4_0_val
- str r8, [r4]
- ldr r4, cfg1_0_addr
- ldr r8, [r4]
- orr r8, r8, #0x3 /* up gpmc divider */
- str r8, [r4]
-
- /* setup to 2x loop though code. The first loop pre-loads the
- * icache, the 2nd commits the prcm config, and locks the dpll
- */
- mov r4, #0x1000 /* spin spin spin */
- mov r8, #0x4 /* first pass condition & set registers */
- cmp r8, #0x4
-2:
- ldrne r8, [r3] /* DPLL lock check */
- and r8, r8, #0x7
- cmp r8, #0x2
- beq 4f
-3:
- subeq r8, r8, #0x1
- streq r8, [r0] /* commit dividers (2nd time) */
- nop
-lloop1:
- sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop1
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- streq r2, [r1] /* lock dpll (2nd time) */
- nop
-lloop2:
- sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop2
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- ldreq r8, [r3] /* get lock condition for dpll */
- cmp r8, #0x4 /* first time though? */
- bne 2b
- moveq r8, #0x2 /* set to dpll check condition. */
- beq 3b /* if condition not true branch */
-4:
- ldr r4, [sp]
- add sp, sp, #0x4 /* return stack space */
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
- .word GPMC_CONFIG3_0
-cfg3_0_val:
- .word SMNAND_GPMC_CONFIG3
-cfg4_0_addr:
- .word GPMC_CONFIG4_0
-cfg4_0_val:
- .word SMNAND_GPMC_CONFIG4
-cfg1_0_addr:
- .word GPMC_CONFIG1_0
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_stat:
- .word CM_IDLEST_CKGEN
-pll_div_add:
- .word CM_CLKSEL1_PLL
-pll_div_val:
- .word DPLL_VAL /* DPLL setting (300MHz default) */
-#endif
-
-.globl platformsetup
-platformsetup:
- mov r3, r0 /* save skip information */
-#ifdef CONFIG_APTIX
- ldr r0, REG_SDRC_MCFG_0
- ldr r1, VAL_SDRC_MCFG_0
- str r1, [r0]
- ldr r0, REG_SDRC_MR_0
- ldr r1, VAL_SDRC_MR_0
- str r1, [r0]
- /* a ddr needs emr1 set here */
- ldr r0, REG_SDRC_SHARING
- ldr r1, VAL_SDRC_SHARING
- str r1, [r0]
- ldr r0, REG_SDRC_RFR_CTRL_0
- ldr r1, VAL_SDRC_RFR_CTRL_0
- str r1, [r0]
-
- /* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
-#endif
-#ifdef CONFIG_PARTIAL_SRAM
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- mov r0, r3 /* pass skip info to s_init */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-#endif
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-
-
-
-
-
diff --git a/board/omap2420h4/x-load.lds b/board/omap2420h4/x-load.lds
deleted file mode 100644
index f664ca7..0000000
--- a/board/omap2420h4/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <g...@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/arm1136/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/drivers/Makefile b/drivers/Makefile
index 25c5735..9fc61f6 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -48,10 +48,6 @@ ifeq ($(BOARD), overo)
COBJS += k9f1g08r0a.o
endif
-ifeq ($(BOARD), omap2420h4)
-COBJS += k9k1216.o
-endif
-
ifeq ($(BOARD), omap2430sdp)
COBJS += k9k1216.o
endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
deleted file mode 100644
index 7495d7f..0000000
--- a/include/configs/omap2420h4.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2004 - 2005 Texas Instruments.
- *
- * X-Loader Configuation settings for the TI OMAP H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF
-//#undef CFG_PRINTF
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP2420 1 /* which is in a 2420 */
-#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
-
-#define CONFIG_OMAP242X
-
-#define PRCM_CONFIG_II 1
-//#define PRCM_CONFIG_III 1
-#define CONFIG_PARTIAL_SRAM 1
-
-//#define CFG_SDRAM_DDR 1
-#define CFG_SDRAM_COMBO 2
-//#define CFG_SDRAM_SDR 3
-//#define CFG_SDRAM_STACKED 4
-
-/* Chipselect and NAND information :
- Since we share the mem.h from u-boot, we define few macros here
- so as to pick the right gpmc values from there for the macros in mem.h
-*/
-/* NAND fixed at CS5 */
-#define OMAP24XX_GPMC_CS0 SMNAND
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M
-#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE
-#define CFG_NAND_BOOT
-#define NAND_LEGACY
-
-#include <asm/arch/omap2420.h> /* get chip and board defs */
-
-#define V_SCLK 12000000
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ V_SCLK
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE (-4)
-#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1 OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* UART1 on H4 */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CFG_PBSIZE 256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR 0x80000000
-
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */
-
-#define NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
-
-/* H4 NAND is partitioned:
- * 0x0000000 - 0x0010000 Booting Image
- * 0x0010000 - 0x0050000 U-Boot Image
- * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care)
- * 0x0080000 - 0x4000000 depends on application
- */
-#define NAND_UBOOT_START 0x0040000
-#define NAND_UBOOT_END 0x0080000
-#define NAND_BLOCK_SIZE 0x4000
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-
-#define NAND_WAIT_READY()
-
-#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(adr)
-#define NAND_CTL_SETALE(adr)
-#define NAND_CTL_CLRCLE(adr)
-#define NAND_CTL_SETCLE(adr)
-#define NAND_DISABLE_CE()
-#define NAND_ENABLE_CE()
-
-
-#endif /* __CONFIG_H */
--
1.7.0.4
Enric Balletbo i Serra
Signed-off-by: Enric Balletbo i Serra <ebal...@gmail.com>
---
Makefile | 3 -
board/omap2430sdp/Makefile | 51 ---
board/omap2430sdp/config.mk | 28 --
board/omap2430sdp/omap2430sdp.c | 746 ---------------------------------------
board/omap2430sdp/platform.S | 198 -----------
board/omap2430sdp/x-load.lds | 54 ---
drivers/Makefile | 4 -
include/configs/omap2430sdp.h | 178 ----------
8 files changed, 0 insertions(+), 1262 deletions(-)
delete mode 100644 board/omap2430sdp/Makefile
delete mode 100644 board/omap2430sdp/config.mk
delete mode 100644 board/omap2430sdp/omap2430sdp.c
delete mode 100644 board/omap2430sdp/platform.S
delete mode 100644 board/omap2430sdp/x-load.lds
delete mode 100644 include/configs/omap2430sdp.h
diff --git a/Makefile b/Makefile
index f378923..a4ea69e 100644
--- a/Makefile
+++ b/Makefile
@@ -201,9 +201,6 @@ unconfig:
## OMAP2 (ARM1136) Systems
#########################################################################
-omap2430sdp_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp
-
#########################################################################
## OMAP3 (ARM-CortexA8) Systems
#########################################################################
diff --git a/board/omap2430sdp/Makefile b/board/omap2430sdp/Makefile
deleted file mode 100644
index b6c984c..0000000
--- a/board/omap2430sdp/Makefile
-COBJS := omap2430sdp.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap2430sdp/config.mk b/board/omap2430sdp/config.mk
deleted file mode 100644
index 7bc5078..0000000
--- a/board/omap2430sdp/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# 2430 h4 has same mem configuration as h4.
-
-# For use with external or internal boots.
-# CONFIG_PARTIAL_SRAM must be defined to use this.
-TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
-#
-#TEXT_BASE = 0x40280000
-
diff --git a/board/omap2430sdp/omap2430sdp.c b/board/omap2430sdp/omap2430sdp.c
deleted file mode 100644
index f2a7b42..0000000
--- a/board/omap2430sdp/omap2430sdp.c
+++ /dev/null
@@ -1,746 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzh...@ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/omap2430.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-
-static void wait_for_command_complete(unsigned int wd_base);
-static void watchdog_init(void);
-static void peripheral_enable(void);
-static void muxSetupAll(void);
-static u32 get_cpu_rev(void);
-static u32 get_device_type(void);
-static void prcm_init(void);
-
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return(v+1); /* currently 2422 and 2420 match up */
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return(mode >>= 8);
-}
-
-/*************************************************************
- * Helper function to wait for the status of a register
- *************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return(1);
- if (i==bound)
- return(0);
- } while (1);
-}
-
-/*************************************************************
- * Support for multiple type of memory types
- *************************************************************/
-#ifdef CFG_SDRAM_DDR
-void
-config_sdram_ddr(u32 rev)
-{
- /* ball D11, mode 0 */
- __raw_writeb(0x08, 0x48000032);
-
- /* SDRC_CS0 Configuration */
- __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
-
- /*
- * CS0 SDRC Mode Register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- __raw_writel(0x00000032, SDRC_MR_0);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
-
-}
-#endif // CFG_SDRAM_DDR
-
-#ifdef CFG_SDRAM_COMBO
-void
-config_sdram_combo(u32 rev)
-{
-
- u32 dllctrl=0;
-
- /* ball C12, mode 0 */
- __raw_writeb(0x00, 0x480000a1);
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
- /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
- __raw_writeb(0x00, 0x480000a3);
-
- /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
- __raw_writel(0x00000000, SDRC_SYSCONFIG);
-
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- if (rev == CPU_2420_2422_ES1)
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- else
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
-
- /* This is reqd only for ES1 */
- if (rev == CPU_242X_ES1)
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* CS1 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
- /* This is reqd only for ES1 */
- if (rev == CPU_242X_ES1)
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, 0x680090d8);
- __raw_writel(CMD_PRECHARGE, 0x680090d8);
- __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
- __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
-
- /* CS1 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
-
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-
-#endif // CFG_SDRAM_COMBO
-
-#ifdef CFG_2430SDRAM_DDR
-void
-config_2430sdram_ddr(u32 rev)
-{
- u32 dllstat, dllctrl;
-
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
- __raw_writel(0x00000000, SDRC_SYSCONFIG);
-
- /* Chip-level shared interface management */
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX14: 32Mbx32 */
- __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
-
- __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 2 - SDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* Set up SDRC DLL values for 2430 DDR */
- dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */
- __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */
- __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */
- delay(0x1000); /* time to track to center */
- dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */
- dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */
- __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */
- __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */
-}
-#endif // CFG_2430SDRAM_DDR
- __raw_writel(0x00000000, 0x680090D8);
- __raw_writel(0x00000001, 0x680090D8);
- __raw_writel(0x00000002, 0x680090D8);
- __raw_writel(0x00000002, 0x680090D8);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(0x00000032, 0x680090B4);
- __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL);
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-#endif // CFG_SDRAM_STACKED
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(u32 *shift)
-{
-#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
-#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */
- u32 start, cstart, cend, cdiff, val;
- unsigned int v, if_clks=0, func_clks=0 ;
-
-
-
- if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */
- *shift = 1;
- }else{
- *shift = 0;
- }
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */
- __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */
- __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */
- __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */
- /* enable 32kHz source */ /* enabled out of reset */
- /* determine sys_clk via gauging */
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/
- while(__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */
- while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */
- cend = __raw_readl(GPT_CTR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
- /* based on number of ticks assign speed */
- if(cdiff > (19000 >> *shift))
- return(S38_4M);
- else if (cdiff > (15200 >> *shift))
- return(S26M);
- else if (cdiff > (13000 >> *shift))
- return(S24M);
- else if (cdiff > (9000 >> *shift))
- return(S19_2M);
- else if (cdiff > (7600 >> *shift))
- return(S13M);
- else
- return(S12M);
-}
-
-/*********************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
- * -- called from SRAM
- *********************************************************************************/
-void
-prcm_init()
-{
- u32 div, speed, val, div_by_2;
-
- val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0);
-#if defined(OMAP2430_SQUARE_CLOCK_INPUT)
- __raw_writel(val, PRCM_CLKSRC_CTRL);
-#else
- __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL);
-#endif
- speed = get_osc_clk_speed(&div_by_2);
- if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */
- val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL);
- val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */
- __raw_writel(val, PRCM_CLKSRC_CTRL);
- }
-
- __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
- __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
- __raw_writel(0, CM_ICLKEN1_CORE);
- __raw_writel(0, CM_ICLKEN2_CORE);
-
- /*DPLL into low power bypass (others off) */
- __raw_writel(0x00000001, CM_CLKEN_PLL);
-
- __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
- __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
- __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
- __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
- __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */
-
- div = BUS_DIV;
- __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */
- delay(1000);
-
- /*13MHz apll src, PRCM 'x' DPLL rate */
- __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
-
- /*Valid the configuration */
- __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
- delay(1000);
-
- /* set up APLLS_CLKIN per crystal */
- if (speed > S19_2M)
- speed >>= 1; /* if fast shift to /2 range */
- val = (0x2 << 23); /* default to 13Mhz for 2430c */
- if (speed == S12M)
- val = (0x3 << 23);
- else if (speed == S19_2M)
- val = (0x0 << 23);
- val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL));
- __raw_writel(val, CM_CLKSEL1_PLL);
-
- __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
- wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */
-
- delay(200000);
-}
-
-void SEC_generic(void)
-{
-/* Permission values for registers -Full fledged permissions to all */
-#define UNLOCK_1 0xFFFFFFFF
-#define UNLOCK_2 0x00000000
-#define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
- __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/
-
-
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
-
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
- __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- mode = get_device_type();
-
- if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE)
- || (mode == TST_DEVICE)) {
- /* Secure or Emulation device - HS/E/T */
- SEC_generic();
- }
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-int s_init(int skip)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
- watchdog_init();
- try_unlock_sram();
- muxSetupAll();
- delay(100);
- prcm_init();
-
-#ifdef CFG_SDRAM_DDR
- config_sdram_ddr(rev);
-#elif defined(CFG_SDRAM_COMBO)
- config_sdram_combo(rev);
-#elif defined(CFG_2430SDRAM_DDR)
- config_2430sdram_ddr(rev);
- unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0;
-
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CFG_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */
- __raw_writel(v, CM_ICLKEN2_CORE);
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN2_CORE);
- delay(1000);
-
-}
-
-/* Do pin muxing for all the devices used in X-Loader */
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET);
-static void muxSetupAll(void)
-{
- /* UART 1*/
- MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */
- MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */
- MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */
- MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */
- MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */
- MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */
- MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */
- MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */
-
- /* Mux settings for SDRC */
- MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */
- MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */
- MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */
- MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */
- MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */
- /* GPMC */
- MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */
- MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */
- MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */
- MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */
- MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */
- MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */
- MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */
- MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */
- MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */
- MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */
- MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */
- MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */
-}
-
-int nand_init(void)
-{
- u32 rev;
-
- /* GPMC Configuration */
- rev = get_cpu_rev();
-
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CFG_NAND
- __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
-#endif
-
- /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0
- * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0.
- * We configure only GPMC CS0 with required values. Configiring other devices
- * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
- */
- __raw_writel(0, GPMC_CONFIG7_0);
- sdelay(1000);
-
-#ifdef CFG_NAND
- __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
- __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
- __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
- __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
- __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
- __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
-
-#else /* CFG_ONENAND */
- __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
- __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
- __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
- __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
- __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
- __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
-#endif
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) |
- (1<<6) ), GPMC_CONFIG7_0);
- sdelay(2000);
-#ifdef CFG_NAND
- if (nand_chip()){
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
-#else
- if (onenand_chip()){
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
-
-#endif
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
diff --git a/board/omap2430sdp/platform.S b/board/omap2430sdp/platform.S
deleted file mode 100644
index f221d7e..0000000
--- a/board/omap2430sdp/platform.S
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/omap2430.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
- ldr r4, flash_cfg3_addr
- ldr r8, flash_cfg3_val
- str r8, [r4]
- ldr r4, flash_cfg4_addr
- ldr r8, flash_cfg4_val
- str r8, [r4]
- ldr r4, flash_cfg1_addr
-#ifdef CFG_ONENAND
-flash_cfg3_addr:
- .word GPMC_CONFIG3_0
-flash_cfg3_val:
- .word ONENAND_GPMC_CONFIG3
-flash_cfg4_addr:
- .word GPMC_CONFIG4_0
-flash_cfg4_val:
- .word ONENAND_GPMC_CONFIG4
-flash_cfg1_addr:
- .word GPMC_CONFIG1_0
-#else
-flash_cfg3_addr:
- .word GPMC_CONFIG3_0
-flash_cfg3_val:
- .word SMNAND_GPMC_CONFIG3
-flash_cfg4_addr:
- .word GPMC_CONFIG4_0
-flash_cfg4_val:
- .word SMNAND_GPMC_CONFIG4
-flash_cfg1_addr:
- .word GPMC_CONFIG1_0
-#endif
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_stat:
- .word CM_IDLEST_CKGEN
-pll_div_add:
- .word CM_CLKSEL1_PLL
-pll_div_val:
- .word DPLL_VAL /* DPLL setting (300MHz default) */
-
-.globl platformsetup
-platformsetup:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
diff --git a/board/omap2430sdp/x-load.lds b/board/omap2430sdp/x-load.lds
deleted file mode 100644
index f12e8f8..0000000
--- a/board/omap2430sdp/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2005 Texas Instruments
index 9fc61f6..bd620c2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -48,10 +48,6 @@ ifeq ($(BOARD), overo)
COBJS += k9f1g08r0a.o
endif
-ifeq ($(BOARD), omap2430sdp)
-COBJS += k9k1216.o
-endif
-
ifeq ($(BOARD), igep00x0)
COBJS += onenand.o
endif
diff --git a/include/configs/omap2430sdp.h b/include/configs/omap2430sdp.h
deleted file mode 100644
index 3fda61f..0000000
--- a/include/configs/omap2430sdp.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Instruments.
-#define CONFIG_OMAP2430H4 1 /* and on a H4 board */
-
-#define CONFIG_OMAP243X 1
-
-//#define PRCM_CONFIG_5A 1
-#define PRCM_CONFIG_2 1 /* 2430 ES2+330ARM+DDR-165-PISMO */
-
-#define OMAP2430_SQUARE_CLOCK_INPUT 1
-
-/* Memory type */
-//#define CFG_SDRAM_DDR 1 /* not tested */
-//#define CFG_SDRAM_COMBO 2 /* not tested */
-#define CFG_2430SDRAM_DDR 3
-//#define CFG_SDRAM_STACKED 4 /* not tested */
-
-/* The actual register values are defined in u-boot- mem.h */
-/* SDRAM Bank Allocation method */
-//#define SDRC_B_R_C 1
-//#define SDRC_B1_R_B0_C 1
-#define SDRC_R_B_C 1
-
-/* Boot type */
-//#define CFG_NAND 1
-#define CFG_ONENAND 1
-
-# define NAND_BASE 0x0C000000 /* NAND flash */
-# define ONENAND_BASE 0x20000000 /* OneNand flash */
-
-#ifdef CFG_NAND
-#define NAND_LEGACY
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M
-#define OMAP24XX_GPMC_CS0_MAP NAND_BASE
-#else
-#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_128M
-#define OMAP24XX_GPMC_CS0_MAP ONENAND_BASE
-#define ONENAND_ADDR ONENAND_BASE /* physical address to access OneNAND at CS0*/
-#endif
-
-/* Another dependency on u-boot */
-#define sdelay delay
-
-#include <asm/arch/omap2430.h> /* get chip and board defs */
-
-#define V_SCLK 13000000
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ V_SCLK
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE (-4)
-#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1 OMAP2430_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* UART1 on 2430SDP */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CFG_PBSIZE 256
-
-#endif /* CFG_PRINTF */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LOADADDR 0x80008000
-
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-#ifdef CFG_NAND
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */
-
-/* NAND is partitioned:
- * 0x0000000 - 0x0010000 Booting Image
- * 0x0010000 - 0x0050000 U-Boot Image
- * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care)
- * 0x0080000 - 0x00B0000 Kernel Image
- * 0x00B0000 - 0x4000000 depends on application
- */
-#define NAND_UBOOT_START 0x0040000
-#define NAND_UBOOT_END 0x0080000
-#define NAND_BLOCK_SIZE 0x4000
-
-#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50)
-#define GPMC_NAND_COMMAND_0 (OMAP24XX_GPMC_BASE+0x7C)
-#define GPMC_NAND_ADDRESS_0 (OMAP24XX_GPMC_BASE+0x80)
-#define GPMC_NAND_DATA_0 (OMAP24XX_GPMC_BASE+0x84)
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0)
-#define NAND_WAIT_READY()
-#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
-#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(adr)
-#define NAND_CTL_SETALE(adr)
-#define NAND_CTL_CLRCLE(adr)
-#define NAND_CTL_SETCLE(adr)
-#define NAND_DISABLE_CE()
-#define NAND_ENABLE_CE()
-
-#else
-/*-----------------------------------------------------------------------
- * Board oneNAND Info.
- */
-#define CFG_SYNC_BURST_READ 1
-
-/* OneNAND is partitioned:
- * 0x0000000 - 0x0080000 X-Loader
- * 0x0080000 - 0x00c0000 U-boot Image
- * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care)
- * 0x00e0000 - 0x0120000 Kernel Image
- * 0x0120000 - 0x4000000 depends on application
- */
-
-#define ONENAND_START_BLOCK 4
-#define ONENAND_END_BLOCK 6
-#define ONENAND_PAGE_SIZE 2048 /* 2KB */
-#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */
-
-#endif // oneNAND
Enric Balletbo i Serra
cpu/arm1136 and include/asm/arch-arm1136 directories are not being
used so we can remove it.
Signed-off-by: Enric Balletbo i Serra <ebal...@gmail.com>
---
README | 12 +-
cpu/arm1136/Makefile | 47 ----
cpu/arm1136/config.mk | 33 ---
cpu/arm1136/cpu.c | 65 ------
cpu/arm1136/start.S | 218 -------------------
include/asm/arch-arm1136/bits.h | 49 -----
include/asm/arch-arm1136/clocks.h | 51 -----
include/asm/arch-arm1136/clocks242x.h | 147 -------------
include/asm/arch-arm1136/clocks243x.h | 223 -------------------
include/asm/arch-arm1136/mem.h | 383 ---------------------------------
include/asm/arch-arm1136/omap2420.h | 223 -------------------
include/asm/arch-arm1136/omap2430.h | 255 ----------------------
include/asm/arch-arm1136/sizes.h | 50 -----
include/asm/arch-arm1136/sys_info.h | 139 ------------
14 files changed, 1 insertions(+), 1894 deletions(-)
delete mode 100644 cpu/arm1136/Makefile
delete mode 100644 cpu/arm1136/config.mk
delete mode 100644 cpu/arm1136/cpu.c
delete mode 100644 cpu/arm1136/start.S
delete mode 100644 include/asm/arch-arm1136/bits.h
delete mode 100644 include/asm/arch-arm1136/clocks.h
delete mode 100644 include/asm/arch-arm1136/clocks242x.h
delete mode 100644 include/asm/arch-arm1136/clocks243x.h
delete mode 100644 include/asm/arch-arm1136/mem.h
delete mode 100644 include/asm/arch-arm1136/omap2420.h
delete mode 100644 include/asm/arch-arm1136/omap2430.h
delete mode 100644 include/asm/arch-arm1136/sizes.h
delete mode 100644 include/asm/arch-arm1136/sys_info.h
diff --git a/README b/README
index d7b16dd..2ca51eb 100644
--- a/README
+++ b/README
@@ -36,10 +36,6 @@ Nand booting.
Status:
=======
-The support for Texas Instruments H4 board (OMAP2420) has been implemented
-and tested. (Nov 2004)
-The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented
-and tested. (Jul 2006)
The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented
and tested. (Dec 2006)
@@ -55,15 +51,10 @@ Directory Hierarchy:
- drivers Commonly used device drivers
- lib Libraries
-- cpu/arm926ejs Files specific to ARM 926 CPUs
- cpu/arm1136 Files specific to ARM 1136 CPUs
- cpu/omap3 Files specific to ARM CortexA8 CPU
-- board/omap2420h4
- Files specific to OMAP 2420 H4 boards
-- board/omap2430sdp
- Files specific to OMAP 2430 2430sdp boards
- board/omap3430sdp
Files specific to OMAP 3420sdp boards
@@ -116,8 +107,7 @@ You can't use FlashWriterNand because it uses ROM code ECC style.
Implemenation notes:
====================
-H4 support NAND flash booting
-2430sdp & 3430sdp support OneNAND booting
+3430sdp support OneNAND booting
diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile
deleted file mode 100644
index b556419..0000000
--- a/cpu/arm1136/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(CPU).a
-
-START = start.o
-COBJS = cpu.o
-
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START := $(addprefix $(obj),$(START))
-
-all: $(obj).depend $(START) $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk
deleted file mode 100644
index 3106824..0000000
--- a/cpu/arm1136/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <g...@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8
-
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-#
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
deleted file mode 100644
index 1168fb9..0000000
--- a/cpu/arm1136/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Insturments
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * udelay() is CPU specific code
- */
-
-#include <common.h>
-
-/* See also ARM Ref. Man. */
-#define C1_MMU (1<<0) /* mmu off/on */
-#define C1_ALIGN (1<<1) /* alignment faults off/on */
-#define C1_DC (1<<2) /* dcache off/on */
-#define C1_WB (1<<3) /* merging write buffer on/off */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
-#define C1_SYS_PROT (1<<8) /* system protection */
-#define C1_ROM_PROT (1<<9) /* ROM protection */
-#define C1_IC (1<<12) /* icache off/on */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
-
-int cpu_init (void)
-{
- int i;
-
- /* turn off I/D-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(C1_DC | C1_IC);
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
- /* flush I/D-cache */
- i = 0;
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); // invalidate both caches and flush btb
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); // mem barrier to sync things
-
- return 0;
-}
-
-
-
-
-
-
-
-
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
deleted file mode 100644
index 16108d0..0000000
--- a/cpu/arm1136/start.S
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * armboot - Startup Code for OMP2420/ARM1136 CPU-core
- *
- * Copyright (c) 2004 Texas Instruments
- *
- * Copyright (c) 2001 Marius Gr�ger <m...@sysgo.de>
- * Copyright (c) 2002 Alex Z�pke <a...@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <g...@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woo...@ti.com>
- * Copyright (c) 2003 Kshitij <ksh...@ti.com>
- * Copyright (c) 2004 Jian Zhang <jzh...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-
-.globl _start
-_start:
- b reset
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
-
-_hang:
- .word do_hang
-
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678
- .word 0x12345678 /* now 16*4=64 */
-
-.global _end_vect
-_end_vect:
-
- .balignl 16,0xdeadbeef
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
- .word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start /* r0 <- current position of code */
- add r0, r0, #4 /* skip reset vector */
- mov r2, #64 /* r2 <- size to copy */
- add r2, r0, r2 /* r2 <- source end address */
- mov r1, #0x40000000 /* build vect addr */
- mov r3, #0x00200000
- add r1, r1, r3
- mov r3, #0xf800
- add r1, r1, r3
-next:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next /* loop until equal */
-
- bl cpy_clk_code /* put dpll adjust code behind vectors */
-
- /* the mask ROM code should have PLL and others stable */
- bl cpu_init_crit
-
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- /* beq stack_setup */
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-//clbss_l:str r2, [r0] /* clear loop... */
-// add r0, r0, #4
-// cmp r0, r1
-// bne clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot: .word start_armboot
-
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-cpu_init_crit:
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
-#ifndef CONFIG_ICACHE_OFF
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
-#endif
- mcr p15, 0, r0, c1, c0, 0
-
- /*
- * Jump to board specific initialization... The Mask ROM will have already initialized
- * basic memory. Go here to bump up clock rate and handle wake up conditions.
- */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* pass on info about skipping some init portions */
- moveq r0,#0x1 /* flag to skip prcm and sdrc setup */
- movne r0,#0x0
-
-//mov r0, #1 /* this skip memory init */
-
- mov ip, lr /* persevere link reg across call */
- bl platformsetup /* go setup pll,mux,memory */
-
- mov lr, ip /* restore link */
- mov pc, lr /* back to my caller */
-
-
-/*
- * exception handler
- */
- .align 5
-do_hang:
- ldr sp, _TEXT_BASE /* use 32 words abort stack */
- bl hang /* hang and never return */
-
diff --git a/include/asm/arch-arm1136/bits.h b/include/asm/arch-arm1136/bits.h
deleted file mode 100644
index dc3273e..0000000
--- a/include/asm/arch-arm1136/bits.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software; you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0 (1<<0)
-#define BIT1 (1<<1)
-#define BIT2 (1<<2)
-#define BIT3 (1<<3)
-#define BIT4 (1<<4)
-#define BIT5 (1<<5)
-#define BIT6 (1<<6)
-#define BIT7 (1<<7)
-#define BIT8 (1<<8)
-#define BIT9 (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
-
diff --git a/include/asm/arch-arm1136/clocks.h b/include/asm/arch-arm1136/clocks.h
deleted file mode 100644
index 8e00d2e..0000000
--- a/include/asm/arch-arm1136/clocks.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS 0x1
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK 0xc
-#define DPLL_LOCK 0x3 /* DPLL lock */
-#define LDELAY 12000000
-
-#if defined(CONFIG_OMAP242X)
-#include <asm/arch/clocks242x.h>
-#elif defined(CONFIG_OMAP243X)
-#include <asm/arch/clocks243x.h>
-#endif
-
-#define S12M 12000000
-#define S13M 13000000
-#define S19_2M 19200000
-#define S24M 24000000
-#define S26M 26000000
-#define S38_4M 38400000
-
-#endif
-
-
-
-
-
-
-
-
diff --git a/include/asm/arch-arm1136/clocks242x.h b/include/asm/arch-arm1136/clocks242x.h
deleted file mode 100644
index 0ae1c4e..0000000
--- a/include/asm/arch-arm1136/clocks242x.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP242X_CLOCKS_H_
-#define _OMAP242X_CLOCKS_H_
-
-/****************************************************************************;
-; PRCM Scheme I
-;
-; Enable clocks and DPLL for:
-; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55
-; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
-; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
-; DSPI=110 6 CM_CLKSEL_DSP[6:5]
-; DSP_S activated CM_CLKSEL_DSP[7]
-; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8]
-; IVAF=82.5 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S bypass CM_CLKSEL_DSP[13]
-; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0]
-; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=110 auto
-; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0]
-; L4=82.5Mhz 8
-; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define I_DPLL_OUT_X2 0x2 /* x2 core out */
-#define I_MPU_DIV 0x2 /* mpu = core/2 */
-#define I_DSP_DIV 0x3c3 /* dsp & iva divider */
-#define I_GFX_DIV 0x2
-#define I_BUS_DIV 0x04601044
-#ifdef INPUT_CLK_13MHZ
-#define I_DPLL_330 0x0114AC00 /* 13MHz */
-#else
-#define I_DPLL_330 0x01837100 /* 12MHz */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II <tested>
-;
-; Enable clocks and DPLL for:
-; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
-; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
-; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
-; DSPI=100 6 CM_CLKSEL_DSP[6:5]
-; DSP_S bypass CM_CLKSEL_DSP[7]
-; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
-; IVAF=100 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S bypass CM_CLKSEL_DSP[13]
-; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
-; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=100 auto
-; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
-; L4=100Mhz 6
-; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2 0x2 /* x2 core out */
-#define II_MPU_DIV 0x2 /* mpu = core/2 */
-#define II_DSP_DIV 0x343 /* dsp & iva divider */
-#define II_GFX_DIV 0x2
-#define II_BUS_DIV 0x04601026
-#ifdef INPUT_CLK_13MHZ
-#define II_DPLL_300 0x0112CC00 /* 13MHz */
-#else
-#define II_DPLL_300 0x01832100 /* 12MHz */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme III <tested>
-;
-; Enable clocks and DPLL for:
-; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
-; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
-; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
-; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
-; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
-; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
-; IVAF=88.67 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
-; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
-; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=88.67 auto
-; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
-; L4=66.5Mhz /8
-; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2 0x2 /* x2 core out */
-#define III_MPU_DIV 0x2 /* mpu = core/2 */
-#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV 0x2
-#define III_BUS_DIV 0x08301044
-#ifdef INPUT_CLK_13MHZ
-#define III_DPLL_266 0x0110AC00 /* 13MHz */
-#else
-#define III_DPLL_266 0x01885500 /* 12MHz */
-#endif
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_I
-# define DPLL_OUT I_DPLL_OUT_X2
-# define MPU_DIV I_MPU_DIV
-# define DSP_DIV I_DSP_DIV
-# define GFX_DIV I_GFX_DIV
-# define BUS_DIV I_BUS_DIV
-# define DPLL_VAL I_DPLL_266
-#elif PRCM_CONFIG_II
-# define DPLL_OUT II_DPLL_OUT_X2
-# define MPU_DIV II_MPU_DIV
-# define DSP_DIV II_DSP_DIV
-# define GFX_DIV II_GFX_DIV
-# define BUS_DIV II_BUS_DIV
-# define DPLL_VAL II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT III_DPLL_OUT_X2
-# define MPU_DIV III_MPU_DIV
-# define DSP_DIV III_DSP_DIV
-# define GFX_DIV III_GFX_DIV
-# define BUS_DIV III_BUS_DIV
-# define DPLL_VAL III_DPLL_266
-#endif
-
-#endif
diff --git a/include/asm/arch-arm1136/clocks243x.h b/include/asm/arch-arm1136/clocks243x.h
deleted file mode 100644
index 18d2e46..0000000
--- a/include/asm/arch-arm1136/clocks243x.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP243X_CLOCKS_H_
-#define _OMAP243X_CLOCKS_H_
-
-/* cm_clksel core fields not ratio governed */
-#define RX_CLKSEL_DSS1 (0x10 << 8)
-#define RX_CLKSEL_DSS2 (0x0 << 13)
-#define RX_CLKSEL_SSI (0x5 << 20)
-
-/* 2430 Ratio's */
-/* 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3 (4 << 0)
-#define R1_CLKSEL_L4 (2 << 5)
-#define R1_CLKSEL_USB (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
- | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP (2 << 0)
-#define R1_CLKSEL_DSP_IF (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3 (6 << 0)
-#define R2_CLKSEL_L4 (2 << 5)
-#define R2_CLKSEL_USB (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
- | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP (2 << 0)
-#define R2_CLKSEL_DSP_IF (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
-
-/* 2430-Ratio Boot */
-#define RB_CLKSEL_L3 (1 << 0)
-#define RB_CLKSEL_L4 (1 << 5)
-#define RB_CLKSEL_USB (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \
- | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP (1 << 0)
-#define RB_CLKSEL_DSP_IF (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
-
-/* 2430 Target modes: Along with each configuration the CPU has several modes
- * which goes along with them. Modes mainly are the addition of descrite DPLL
- * combinations to go along with a ratio.
- */
-/* hardware goverend */
-#define MX_48M_SRC (0 << 3)
-#define MX_54M_SRC (0 << 5)
-#define MX_APLLS_CLIKIN_12 (3 << 23)
-#define MX_APLLS_CLIKIN_13 (2 << 23)
-#define MX_APLLS_CLIKIN_19_2 (0 << 23)
-
-/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */
-
-/* boot (boot) */
-#define MB_DPLL_MULT (1 << 12)
-#define MB_DPLL_DIV (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
- | MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
- | MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \
- | MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */
-
-#define M2_DPLL_MULT_12 (55 << 12)
-#define M2_DPLL_DIV_12 (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \
- | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */
-#define M2_DPLL_MULT_13 (330 << 12)
-#define M2_DPLL_DIV_13 (12 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \
- | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M2_DPLL_MULT_19 (275 << 12)
-#define M2_DPLL_DIV_19 (15 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \
- | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */
-#define M3_DPLL_MULT_12 (55 << 12)
-#define M3_DPLL_DIV_12 (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \
- | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13 (330 << 12)
-#define M3_DPLL_DIV_13 (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \
- | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19 (275 << 12)
-#define M3_DPLL_DIV_19 (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \
- | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/
-#define M4_DPLL_MULT_12 (133 << 12)
-#define M4_DPLL_DIV_12 (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \
- | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M4_DPLL_MULT_13 (399 << 12)
-#define M4_DPLL_DIV_13 (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \
- | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M4_DPLL_MULT_19 (145 << 12)
-#define M4_DPLL_DIV_19 (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \
- | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */
-#define M5A_DPLL_MULT_12 (133 << 12)
-#define M5A_DPLL_DIV_12 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \
- | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13 (266 << 12)
-#define M5A_DPLL_DIV_13 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \
- | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19 (180 << 12)
-#define M5A_DPLL_DIV_19 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \
- | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */
-#define M5B_DPLL_MULT_12 (50 << 12)
-#define M5B_DPLL_DIV_12 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \
- | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13 (200 << 12)
-#define M5B_DPLL_DIV_13 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \
- | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19 (125 << 12)
-#define M5B_DPLL_DIV_19 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \
- | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2
-
-/* 2430 - chassis (sedna) */
- /* 165 (ratio1) same as above #2 */
- /* 150 (ratio1)*/
- /* 133 (ratio2) same as above #4 */
- /* 110 (ratio2) same as above #3*/
- /* 104 (ratio2)*/
- /* boot (boot) */
-
-/* high and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
-
-/* set defaults for boot up */
-#if defined(PRCM_CONFIG_2) /* ARM-330MHz IVA2-330MHz L3-165MHz */
-# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV R1_CLKSEL_MPU
-# define DSP_DIV R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */
-# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV R2_CLKSEL_MPU
-# define DSP_DIV R2_CM_CLKSEL_DSP_VAL
-# define GFX_DIV R2_CM_CLKSEL_GFX_VAL
-# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */
-# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV R1_CLKSEL_MPU
-# define DSP_DIV R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV R2_CM_CLKSEL_MDM_VAL
-#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */
-# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL
-# define MPU_DIV R1_CLKSEL_MPU
-# define DSP_DIV R1_CM_CLKSEL_DSP_VAL
-# define GFX_DIV R1_CM_CLKSEL_GFX_VAL
-# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL
-# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL
-# define MDM_DIV R1_CM_CLKSEL_MDM_VAL
-#endif
-
-#endif
diff --git a/include/asm/arch-arm1136/mem.h b/include/asm/arch-arm1136/mem.h
deleted file mode 100644
index 2a3da73..0000000
--- a/include/asm/arch-arm1136/mem.h
+++ /dev/null
@@ -1,383 +0,0 @@
-
-/*
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET 0x0
-#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
- early in init when NO global access are there */
-struct sdrc_data_s {
- u32 sdrc_sharing;
- u32 sdrc_mdcfg_0_ddr;
- u32 sdrc_mdcfg_0_sdr;
- u32 sdrc_actim_ctrla_0;
- u32 sdrc_actim_ctrlb_0;
- u32 sdrc_rfr_ctrl;
- u32 sdrc_mr_0_ddr;
- u32 sdrc_mr_0_sdr;
- u32 sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
- STACKED = 0,
- IP_DDR = 1,
- COMBO_DDR = 2,
- IP_SDR = 3,
-} mem_t;
-
-#endif
-
-/* set the 243x-SDRC incoming address convention */
-#if defined(SDRC_B_R_C)
-#define B_ALL (0 << 6) /* bank-row-column */
-#elif defined(SDRC_B1_R_B0_C)
-#define B_ALL (1 << 6) /* bank1-row-bank0-column */
-#elif defined(SDRC_R_B_C)
-#define B_ALL (2 << 6) /* row-bank-column */
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING 0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR 0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
-#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR 0x00000032
-
-#define H4_2422_SDRC_SHARING 0x00004b00
-#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */
-#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR 0x00000032
-
-#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */
-#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */
-#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */
-#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */
-#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/
-#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */
-#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */
-
-/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns
- * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5
- * TDPL = 15/7.5 = 2
- * TRRD = 15/2.5 = 2
- * TRCD = 22.5/7.5 = 3
- * TRP = 22.5/7.5 = 3
- * TRAS = 45/7.5 = 6
- * TRC = 65/7.5 = 8.6->9
- * TRFC = 75/7.5 = 10
- * ACTIMB
- * TCKE = 2 <new in 2430>
- * XSR = 120/7.5 = 16
- */
-#define TDAL_133 5
-#define TDPL_133 2
-#define TRRD_133 2
-#define TRCD_133 3
-#define TRP_133 3
-#define TRAS_133 6
-#define TRC_133 9
-#define TRFC_133 10
-#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \
- (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133))
-
-#define TCKE_133 2
-#define XSR_133 16
-#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0))
-
-/* Infineon part of 2430SDP (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 18/6 = 3
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 72/6 = 12
- * ACTIMB
- * TCKE = 2 <new in 2430>
- * XSR = 120/6 = 20
- */
-#define TDAL_165 6
-#define TDPL_165 3
-#define TRRD_165 2
-#define TRCD_165 3
-#define TRP_165 3
-#define TRAS_165 7
-#define TRC_165 10
-#define TRFC_165 12
-#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \
- (TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165))
-
-#define TCKE_165 2
-#define XSR_165 20
-#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0))
-
-#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz
-# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz
-#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3)
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz
-# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz
-#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2)
-# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz
-# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
-# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
-# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz
-# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz
-#endif
-
-/*
- * GPMC settings -
- * Definitions is as per the following format
- * # define <PART>_GPMC_CONFIG<x> <value>
- * Where:
- * PART is the part name e.g. STNOR - Intel Strata Flash
- * x is GPMC config registers from 1 to 6 (there will be 6 macros)
- * Value is corresponding value
- *
- * For every valid PRCM configuration there should be only one definition of the same.
- * if values are independent of the board, this definition will be present in this file
- * if values are dependent on the board, then this should go into corresponding mem-boardName.h file
- *
- * Currently valid part Names are (PART):
- * STNOR - Intel Strata Flash
- * SMNAND - Samsung NAND
- * MPDB - H4 MPDB board
- * SBNOR - Sibley NOR
- * ONNAND - Samsung One NAND
- *
- * include/configs/file.h contains the following defn - for all CS we are interested
- * #define OMAP24XX_GPMC_CSx PART
- * #define OMAP24XX_GPMC_CSx_SIZE Size
- * #define OMAP24XX_GPMC_CSx_MAP Map
- * Where:
- * x - CS number
- * PART - Part Name as defined above
- * SIZE - how big is the mapping to be
- * GPMC_SIZE_128M - 0x8
- * GPMC_SIZE_64M - 0xC
- * GPMC_SIZE_32M - 0xE
- * GPMC_SIZE_16M - 0xF
- * MAP - Map this CS to which address(GPMC address space)- Absolute address
- * >>24 before being used.
- */
-
-#define GPMC_SIZE_256M 0x0
-#define GPMC_SIZE_128M 0x8
-#define GPMC_SIZE_64M 0xC
-#define GPMC_SIZE_32M 0xE
-#define GPMC_SIZE_16M 0xF
-
-#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */
-# define SMNAND_GPMC_CONFIG1 0x0
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define STNOR_GPMC_CONFIG1 0x3
-# define STNOR_GPMC_CONFIG2 0x000f0f01
-# define STNOR_GPMC_CONFIG3 0x00050502
-# define STNOR_GPMC_CONFIG4 0x0C060C06
-# define STNOR_GPMC_CONFIG5 0x01131F1F
-# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */
-# define MPDB_GPMC_CONFIG1 0x00011000
-# define MPDB_GPMC_CONFIG2 0x001F1F00
-# define MPDB_GPMC_CONFIG3 0x00080802
-# define MPDB_GPMC_CONFIG4 0x1C091C09
-# define MPDB_GPMC_CONFIG5 0x031A1F1F
-# define MPDB_GPMC_CONFIG6 0x000003C2
-#endif
-
-#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */
-# define SMNAND_GPMC_CONFIG1 0x00001800
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define SMNAND_GPMC_CONFIG7 0x00000C44
-
-# define STNOR_GPMC_CONFIG1 0x3
-# define STNOR_GPMC_CONFIG2 0x00151501
-# define STNOR_GPMC_CONFIG3 0x00060602
-# define STNOR_GPMC_CONFIG4 0x10081008
-# define STNOR_GPMC_CONFIG5 0x01131F1F
-# define STNOR_GPMC_CONFIG6 0x000004c4
-
-# define MPDB_GPMC_CONFIG1 0x00011000
-# define MPDB_GPMC_CONFIG2 0x001f1f01
-# define MPDB_GPMC_CONFIG3 0x00080803
-# define MPDB_GPMC_CONFIG4 0x1C091C09
-# define MPDB_GPMC_CONFIG5 0x041f1F1F
-# define MPDB_GPMC_CONFIG6 0x000004C4
-
-# define SIBNOR_GPMC_CONFIG1 0x3
-# define SIBNOR_GPMC_CONFIG2 0x00151501
-# define SIBNOR_GPMC_CONFIG3 0x00060602
-# define SIBNOR_GPMC_CONFIG4 0x10081008
-# define SIBNOR_GPMC_CONFIG5 0x01131F1F
-# define SIBNOR_GPMC_CONFIG6 0x00000000
-
-# define ONENAND_GPMC_CONFIG1 0x00001200
-# define ONENAND_GPMC_CONFIG2 0x000c0c01
-# define ONENAND_GPMC_CONFIG3 0x00030301
-# define ONENAND_GPMC_CONFIG4 0x0c040c04
-# define ONENAND_GPMC_CONFIG5 0x010C1010
-# define ONENAND_GPMC_CONFIG6 0x00000000
-
-# define PCMCIA_GPMC_CONFIG1 0x01E91200
-# define PCMCIA_GPMC_CONFIG2 0x001E1E01
-# define PCMCIA_GPMC_CONFIG3 0x00020203
-# define PCMCIA_GPMC_CONFIG4 0x1D041D04
-# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
-# define PCMCIA_GPMC_CONFIG6 0x000004C4
-#endif /* endif CFG_PRCM_III */
-
-#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */
-# define SMNAND_GPMC_CONFIG1 0x00001800
-# define SMNAND_GPMC_CONFIG2 0x00141400
-# define SMNAND_GPMC_CONFIG3 0x00141400
-# define SMNAND_GPMC_CONFIG4 0x0F010F01
-# define SMNAND_GPMC_CONFIG5 0x010C1414
-# define SMNAND_GPMC_CONFIG6 0x00000A80
-# define SMNAND_GPMC_CONFIG7 0x00000C44
-
-# define STNOR_GPMC_CONFIG1 0x3
-# define STNOR_GPMC_CONFIG2 0x00151501
-# define STNOR_GPMC_CONFIG3 0x00060602
-# define STNOR_GPMC_CONFIG4 0x11091109
-# define STNOR_GPMC_CONFIG5 0x01141F1F
-# define STNOR_GPMC_CONFIG6 0x000004c4
-
-# define MPDB_GPMC_CONFIG1 0x00011000
-# define MPDB_GPMC_CONFIG2 0x001f1f01
-# define MPDB_GPMC_CONFIG3 0x00080803
-# define MPDB_GPMC_CONFIG4 0x1c0b1c0a
-# define MPDB_GPMC_CONFIG5 0x041f1F1F
-# define MPDB_GPMC_CONFIG6 0x000004C4
-
-# define SIBNOR_GPMC_CONFIG1 0x3
-# define SIBNOR_GPMC_CONFIG2 0x00151501
-# define SIBNOR_GPMC_CONFIG3 0x00060602
-# define SIBNOR_GPMC_CONFIG4 0x11091109
-# define SIBNOR_GPMC_CONFIG5 0x01141F1F
-# define SIBNOR_GPMC_CONFIG6 0x00000000
-
-# define ONENAND_GPMC_CONFIG1 0x00001200
-# define ONENAND_GPMC_CONFIG2 0x000F0F01
-# define ONENAND_GPMC_CONFIG3 0x00030301
-# define ONENAND_GPMC_CONFIG4 0x0F040F04
-# define ONENAND_GPMC_CONFIG5 0x010F1010
-# define ONENAND_GPMC_CONFIG6 0x00000000
-
-# define PCMCIA_GPMC_CONFIG1 0x01E91200
-# define PCMCIA_GPMC_CONFIG2 0x001E1E01
-# define PCMCIA_GPMC_CONFIG3 0x00020203
-# define PCMCIA_GPMC_CONFIG4 0x1D041D04
-# define PCMCIA_GPMC_CONFIG5 0x031D1F1F
-# define PCMCIA_GPMC_CONFIG6 0x000004C4
-
-#endif
-
-#if 0
-/* Board Specific Settings for each of the configurations for chips
- * whose values change as per platform. - None currently
- */
-#if CONFIG_OMAP24XXH4
-#include <asm/arch/mem-h4.h>
-#endif
-
-#if CONFIG_2430SDP
-#include <asm/arch/mem-sdp2430.h>
-#endif
-
-#endif /* if 0 */
-
-/* max number of GPMC Chip Selects */
-#define GPMC_MAX_CS 8
-/* max number of GPMC regs */
-#define GPMC_MAX_REG 7
-
-#define PROC_NOR 1
-#define PROC_NAND 2
-#define PISMO_SIBLEY0 3
-#define PISMO_SIBLEY1 4
-#define PISMO_ONENAND 5
-#define DBG_MPDB 6
-#define PISMO_PCMCIA 7
-
-/* make it readable for the gpmc_init */
-#define PROC_NOR_BASE FLASH_BASE
-#define PROC_NAND_BASE NAND_BASE
-#define PISMO_SIB0_BASE SIBLEY_MAP1
-#define PISMO_SIB1_BASE SIBLEY_MAP2
-#define PISMO_ONEN_BASE ONENAND_MAP
-#define DBG_MPDB_BASE DEBUG_BASE
-#define PISMO_PCMCIA_BASE PCMCIA_BASE
-
-#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/include/asm/arch-arm1136/omap2420.h b/include/asm/arch-arm1136/omap2420.h
deleted file mode 100644
index 2164b68..0000000
--- a/include/asm/arch-arm1136/omap2420.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2005 Texas Instruments, <www.ti.com>
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/arch/sizes.h>
-
-
-#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-
-#define __raw_readb(a) (*(volatile unsigned char *)(a))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-
-
-/*
- * 2420 specific Section
- */
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE (0x48000000)
-#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* TAP information */
-#define OMAP2420_TAP_BASE (0x48014000)
-#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE (0x6800A000)
-#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14)
-#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64)
-#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0)
-#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4)
-#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
-#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4)
-#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8)
-
-#define OMAP2420_SDRC_CS0 0x80000000
-#define OMAP2420_SDRC_CS1 0xA0000000
-
-#define LOADDLL BIT2
-#define CMD_NOP 0x0
-#define CMD_PRECHARGE 0x1
-#define CMD_AUTOREFRESH 0x2
-#define CMD_ENTR_PWRDOWN 0x3
-#define CMD_EXIT_PWRDOWN 0x4
-#define CMD_ENTR_SRFRSH 0x5
-#define CMD_CKE_HIGH 0x6
-#define CMD_CKE_LOW 0x7
-#define SOFTRESET BIT1
-#define SMART_IDLE (0x2 << 3)
-#define REF_ON_IDLE (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1 0x4806A000
-#define OMAP2420_UART2 0x4806C000
-#define OMAP2420_UART3 0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1 0x48028000
-#define OMAP2420_GPT2 0x4802A000
-#define OMAP2420_GPT3 0x48078000
-#define OMAP2420_GPT4 0x4807A000
-#define OMAP2420_GPT5 0x4807C000
-#define OMAP2420_GPT6 0x4807E000
-#define OMAP2420_GPT7 0x48080000
-#define OMAP2420_GPT8 0x48082000
-#define OMAP2420_GPT9 0x48084000
-#define OMAP2420_GPT10 0x48086000
-#define OMAP2420_GPT11 0x48088000
-#define OMAP2420_GPT12 0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR 0x0 /* r */
-#define TIOCP_CFG 0x10 /* rw */
-#define TISTAT 0x14 /* r */
-#define TISR 0x18 /* rw */
-#define TIER 0x1C /* rw */
-#define TWER 0x20 /* rw */
-#define TCLR 0x24 /* rw */
-#define TCRR 0x28 /* rw */
-#define TLDR 0x2C /* rw */
-#define TTGR 0x30 /* rw */
-#define TWPS 0x34 /* r */
-#define TMAR 0x38 /* rw */
-#define TCAR1 0x3c /* r */
-#define TSICR 0x40 /* rw */
-#define TCAR2 0x44 /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE 0x48020000
-#define WD2_BASE 0x48022000
-#define WD3_BASE 0x48024000
-#define WD4_BASE 0x48026000
-#define WWPS 0x34 /* r */
-#define WSPR 0x48 /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- * The 2420's chip selects are programmable. The mask ROM
- * does configure CS0 to 0x08000000 before dispatch. So, if
- * you want your code to live below that address, you have to
- * be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A /* Pre version B */
-# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x04000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
-#else
-# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x08000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0 0x40000000
-#define SRAM_OFFSET1 0x00200000
-#define SRAM_OFFSET2 0x0000F800
-#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-#define PERIFERAL_PORT_BASE 0x480FE003
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
-#endif /* endif CONFIG_2420H4 */
-
-#endif
-
diff --git a/include/asm/arch-arm1136/omap2430.h b/include/asm/arch-arm1136/omap2430.h
deleted file mode 100644
index cf2b0f9..0000000
--- a/include/asm/arch-arm1136/omap2430.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2430_SYS_H_
-#define _OMAP2430_SYS_H_
-
-#include <asm/arch/sizes.h>
-
-
-#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-
-#define __raw_readb(a) (*(volatile unsigned char *)(a))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-
-/* device type */
-#define DEVICE_MASK (BIT8|BIT9|BIT10)
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
-
-/*
- * 2430 specific Section
- */
-#define OMAP243X_CORE_L4_IO_BASE 0x48000000
-#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000
-#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE
-
-
-/* CONTROL */
-#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000)
-#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8)
-
-/* TAP information */
-#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000)
-#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204)
-
-/*
- GPMC : In 2430 NOR and NAND can coexist.
- During NAND booting , NAND is at CS0 and NOR at CS1
- and Debug FPGA is GPMC_CS5
-*/
-#define OMAP24XX_GPMC_BASE (0x6E000000)
-
-#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10)
-#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14)
-#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40)
-#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150)
-#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154)
-#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158)
-#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C)
-#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160)
-#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164)
-#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168)
-
-
-/* SMS */
-#define OMAP24XX_SMS_BASE 0x6C000000
-#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10)
-
-/* SDRC */
-#define OMAP24XX_SDRC_BASE 0x6D000000
-#define OMAP24XX_SDRC_CS0 0x80000000
-#define OMAP24XX_SDRC_CS1 0xA0000000
-#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10)
-#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14)
-#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60)
-#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64)
-#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68)
-#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70)
-#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80)
-#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0)
-#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8)
-#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4)
-
-#define LOADDLL BIT2
-#define CMD_NOP 0x0
-#define CMD_PRECHARGE 0x1
-#define CMD_AUTOREFRESH 0x2
-#define CMD_ENTR_PWRDOWN 0x3
-#define CMD_EXIT_PWRDOWN 0x4
-#define CMD_ENTR_SRFRSH 0x5
-#define CMD_CKE_HIGH 0x6
-#define CMD_CKE_LOW 0x7
-#define SOFTRESET BIT1
-#define SMART_IDLE (0x2 << 3)
-#define REF_ON_IDLE (0x1 << 6)
-
-
-/* UART */
-#define OMAP2430_UART1 0x4806A000
-#define OMAP2430_UART2 0x4806C000
-#define OMAP2430_UART3 0x4806E000
-
-/* General Purpose Timers */
-#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000)
-#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
-#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
-#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
-#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
-#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
-#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
-#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
-#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
-#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
-#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
-#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR 0x0 /* r */
-#define TIOCP_CFG 0x10 /* rw */
-#define TISTAT 0x14 /* r */
-#define TISR 0x18 /* rw */
-#define TIER 0x1C /* rw */
-#define TWER 0x20 /* rw */
-#define TCLR 0x24 /* rw */
-#define TCRR 0x28 /* rw */
-#define TLDR 0x2C /* rw */
-#define TTGR 0x30 /* rw */
-#define TWPS 0x34 /* r */
-#define TMAR 0x38 /* rw */
-#define TCAR1 0x3c /* r */
-#define TSICR 0x40 /* rw */
-#define TCAR2 0x44 /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000)
-#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000)
-#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */
-#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000)
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000)
-#define S32K_CR (SYNC_32KTIMER_BASE+0x10)
-
-#define WWPS 0x34 /* r */
-#define WSPR 0x48 /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000)
-
-#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060)
-#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070)
-#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078)
-#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080)
-#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084)
-#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244)
-#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300)
-#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310)
-#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340)
-#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350)
-#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400)
-#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410)
-#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450)
-#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544)
-#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840)
-#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40)
-
-/* SMX-APE */
-#define SMX_APE_BASE 0x68000000
-#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
-#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
-#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
-#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00)
-
-/* IVA2 */
-#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
-
-/*
- * The 2430's chip selects are programmable. The mask ROM
- * does configure CS0 to 0x08000000 before dispatch. So, if
- * you want your code to live below that address, you have to
- * be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP243X)
-
-/* GPMC */
-/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */
-# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */
-#define CFG_FLASH_BASE H4_CS1_BASE
-#define DEBUG_BASE 0x08000000
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0 0x40000000
-#define SRAM_OFFSET1 0x00200000
-#define SRAM_OFFSET2 0x0000F800
-#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-#define PERIFERAL_PORT_BASE 0x480FE003
-
-#endif /* endif CONFIG_2430SDP */
-
-#endif
-
diff --git a/include/asm/arch-arm1136/sizes.h b/include/asm/arch-arm1136/sizes.h
deleted file mode 100644
index 3dddd8e..0000000
--- a/include/asm/arch-arm1136/sizes.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
-
diff --git a/include/asm/arch-arm1136/sys_info.h b/include/asm/arch-arm1136/sys_info.h
deleted file mode 100644
index 94a09cd..0000000
--- a/include/asm/arch-arm1136/sys_info.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright 2005 (C) Texas Instruments, <www.ti.com>
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woo...@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-#if 0
-typedef struct h4_system_data {
- /* base board info */
- u32 base_b_rev; /* rev from base board i2c */
- /* cpu board info */
- u32 cpu_b_rev; /* rev from cpu board i2c */
- u32 cpu_b_mux; /* mux type on daughter board */
- u32 cpu_b_ddr_type; /* mem type */
- u32 cpu_b_ddr_speed; /* ddr speed rating */
- u32 cpu_b_switches; /* boot ctrl switch settings */
- /* cpu info */
- u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
- u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#endif
-
-#define XDR_POP 5 /* package on package part */
-#define SDR_DISCRETE 4 /* 128M memory SDR module*/
-#define DDR_STACKED 3 /* stacked part on 2422 */
-#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
-
-#define DDR_100 100 /* type found on most mem d-boards */
-#define DDR_111 111 /* some combo parts */
-#define DDR_133 133 /* most combo, some mem d-boards */
-#define DDR_165 165 /* future parts */
-
-#define CPU_2420 0x2420
-#define CPU_2422 0x2422 /* 2420 + 64M stacked */
-#define CPU_2423 0x2423 /* 2420 + 96M stacked */
-#define CPU_2430 0x2430
-
-/* 242x real hardware:
- * ES1 = rev 0
- * ES2 = rev 1
- * ES2.05 = rev 2
- * ES2.1 = rev 3
- * ES2.1.1 = rev 4
- */
-
-/* 242x code defines:
- * ES1 = 0+1 = 1
- * ES2 = 1+1 = 2
- * ES2.05 = 2+1 = 3
- * ES2.1 = 3+1 = 4
- * Es2.1.1 = 4+1 = 5
- */
-#define CPU_2422_ES1 1
-#define CPU_2422_ES2 2
-#define CPU_2422_ES2_05 3
-#define CPU_2422_ES2_1 4
-#define CPU_2422_ES2_1_1 5
-
-#define CPU_2420_ES1 1
-#define CPU_2420_ES2 2
-#define CPU_2420_ES2_05 3
-#define CPU_2420_ES2_1 4
-#define CPU_2420_ES2_1_1 5
-
-#define CPU_242X_ES1 1
-#define CPU_242X_ES2 2
-#define CPU_242X_ES2_05 3
-#define CPU_242X_ES2_1 4
-#define CPU_242X_ES2_1_1 5
-
-#define CPU_2420_2422_ES1 1
-#define CPU_2420_2422_ES2_1 4
-
-/* 243x real hardware:
- * ES1 = rev 0
- * ES2 = rev 1
- *
- * 243x code defines:
- * ES1 = 0+1 = 1
- * ES2 = 1+1 = 2
- */
-#define CPU_2430_ES1 1
-#define CPU_2430_ES2 2
-
-#ifdef VPOM2430
-# define CPU_2430_VIRTIO 3
-#else
-# define CPU_2430_VIRTIO 1
-#endif
-#define CPU_2430_ZEBU 0xD
-
-#define CPU_2420_CHIPID 0x0B5D9000
-#define CPU_2430_CHIPID 0x0B68A000
-#define CPU_24XX_ID_MASK 0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS 1
-#define BOARD_H4_SDP 2
-#define BOARD_H4_MENELAUS_HRP 3
-#define BOARD_SDP_2430 4
-
-#define GPMC_MUXED 1
-#define GPMC_NONMUXED 0
-
-#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
-#define TYPE_NOR 0x000
-#define TYPE_ONENAND 0x800
-
-#define WIDTH_8BIT 0x0000
-#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
-
-#endif
--
1.7.0.4
Enric Balletbo i Serra
1 files changed, 0 insertions(+), 51 deletions(-)
delete mode 100644 include/asm/arch-arm926ejs/sizes.h
diff --git a/include/asm/arch-arm926ejs/sizes.h b/include/asm/arch-arm926ejs/sizes.h
deleted file mode 100644
index ef0b99b..0000000
--- a/include/asm/arch-arm926ejs/sizes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
- * USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
--
1.7.0.4
Gadiyar, Anand
> Hello,
>
> As discussed in this thread
>
>
> http://groups.google.com/group/x-loader/browse_thread/thread/42ee3aa6df45a896/ea7296ba34155bad#ea7296ba34155bad
>
> seems ha no sense maintain the support for OMAP2 boards, this patch series
> tries to remove this unmaintained code.
>
> Cheers,
Doesn't look like anyone cares about these boards.
All applied and pushed out, thanks!
- Anand