[PATCH 0/6] pandora support series for x-loader
Grazvydas Ignotas
NAND parameter page (this allows to identify POP parts from
the same manufacturer), and finally adds support for pandora
board, see http://www.openpandora.org/ .
This can also be pulled from:
git://git.openpandora.org/pandora-x-loader.git for_upstream
Grazvydas Ignotas (6):
Drop I2C dependency on MMC
Do i2c init before serial init
Add some missing function prototypes
k9f1g08r0a: fix various warnings
k9f1g08r0a: add support for reading parameter page
Add support for pandora board
MAINTAINERS | 3 +
Makefile | 5 +-
board/pandora/Makefile | 51 +++
board/pandora/config.mk | 1 +
board/pandora/pandora.c | 785 ++++++++++++++++++++++++++++++++++++
board/pandora/platform.S | 359 ++++++++++++++++
board/pandora/x-load.lds | 54 +++
drivers/Makefile | 4 +
drivers/k9f1g08r0a.c | 43 ++-
include/asm/arch-omap3/sys_proto.h | 3 +
include/common.h | 3 +
include/configs/pandora.h | 179 ++++++++
lib/board.c | 12 +-
13 files changed, 1484 insertions(+), 18 deletions(-)
create mode 100644 board/pandora/Makefile
create mode 100644 board/pandora/config.mk
create mode 100644 board/pandora/pandora.c
create mode 100644 board/pandora/platform.S
create mode 100644 board/pandora/x-load.lds
create mode 100644 include/configs/pandora.h
Grazvydas Ignotas
without it.
Signed-off-by: Grazvydas Ignotas <not...@gmail.com>
---
lib/board.c | 6 ------
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/lib/board.c b/lib/board.c
index 0f6b960..a5b45b8 100644
--- a/lib/board.c
+++ b/lib/board.c
@@ -47,9 +47,6 @@ int print_info(void)
return 0;
}
-/* !!! why is I2C dependent on MMC? */
-
-#ifdef CONFIG_MMC
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
static int init_func_i2c (void)
{
@@ -57,7 +54,6 @@ static int init_func_i2c (void)
return 0;
}
#endif
-#endif
typedef int (init_fnc_t) (void);
@@ -69,11 +65,9 @@ init_fnc_t *init_sequence[] = {
#endif
print_info,
nand_init, /* board specific nand init */
-#ifdef CONFIG_MMC
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
init_func_i2c,
#endif
-#endif
NULL,
};
--
1.7.0.4
Grazvydas Ignotas
serial output can be seen.
Signed-off-by: Grazvydas Ignotas <not...@gmail.com>
---
lib/board.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/board.c b/lib/board.c
index a5b45b8..1c79d58 100644
--- a/lib/board.c
+++ b/lib/board.c
@@ -59,15 +59,15 @@ typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ init_func_i2c,
+#endif
board_init, /* basic board dependent setup */
#ifdef CFG_NS16550_SERIAL
serial_init, /* serial communications setup */
#endif
print_info,
nand_init, /* board specific nand init */
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- init_func_i2c,
-#endif
NULL,
};
--
1.7.0.4
Grazvydas Ignotas
Signed-off-by: Grazvydas Ignotas <not...@gmail.com>
---
include/asm/arch-omap3/sys_proto.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/asm/arch-omap3/sys_proto.h b/include/asm/arch-omap3/sys_proto.h
index 8622d9f..e295cad 100644
--- a/include/asm/arch-omap3/sys_proto.h
+++ b/include/asm/arch-omap3/sys_proto.h
@@ -51,6 +51,9 @@ u32 running_in_sram(void);
u32 running_in_flash(void);
u32 running_from_internal_boot(void);
u32 get_device_type(void);
+u32 get_cpu_family(void);
+
+int print_cpuinfo(void);
void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel);
--
1.7.0.4
Grazvydas Ignotas
Signed-off-by: Grazvydas Ignotas <not...@gmail.com>
---
drivers/k9f1g08r0a.c | 14 ++++++--------
1 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
index 988533c..b039b50 100644
--- a/drivers/k9f1g08r0a.c
+++ b/drivers/k9f1g08r0a.c
@@ -82,7 +82,6 @@ static u_char ecc_pos[] =
{40, 41, 42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63};
-static u_char eccvalid_pos = 4;
static unsigned long chipsize = (256 << 20);
@@ -235,7 +234,7 @@ int nand_read_block(unsigned char *buf, ulong block_addr)
/* check bad block */
/* 0th word in spare area needs be 0xff */
- if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){
+ if (nand_read_oob((u_char *)oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){
printf("Skipped bad block at 0x%x\n", block_addr);
return 1; /* skip bad block */
}
@@ -249,7 +248,7 @@ int nand_read_block(unsigned char *buf, ulong block_addr)
return 0;
}
-static count = 0;
+
/* read a page with ECC */
static int nand_read_page(u_char *buf, ulong page_addr)
{
@@ -257,6 +256,7 @@ static int nand_read_page(u_char *buf, ulong page_addr)
u_char ecc_code[ECC_SIZE];
u_char ecc_calc[ECC_STEPS];
u_char oob_buf[OOB_SIZE];
+ int count;
#endif
u16 val;
int cntr;
@@ -277,20 +277,19 @@ static int nand_read_page(u_char *buf, ulong page_addr)
/* A delay seems to be helping here. needs more investigation */
delay(10000);
len = (bus_width == 16) ? PAGE_SIZE >> 1 : PAGE_SIZE;
- p = buf;
+ p = (void *)buf;
for (cntr = 0; cntr < len; cntr++){
*p++ = READ_NAND(NAND_ADDR);
delay(10);
}
#ifdef ECC_CHECK_ENABLE
- p = oob_buf;
+ p = (void *)oob_buf;
len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
for (cntr = 0; cntr < len; cntr++){
*p++ = READ_NAND(NAND_ADDR);
delay(10);
}
- count = 0;
NAND_DISABLE_CE(); /* set pin high */
/* Pick the ECC bytes out of the oob data */
@@ -318,7 +317,6 @@ static int nand_read_page(u_char *buf, ulong page_addr)
*/
static int nand_read_oob(u_char *buf, ulong page_addr)
{
- u16 val;
int cntr;
int len;
@@ -327,7 +325,7 @@ static int nand_read_oob(u_char *buf, ulong page_addr)
#else
u_char *p;
#endif
- p = buf;
+ p = (void *)buf;
len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
NAND_ENABLE_CE(); /* set pin low */
--
1.7.0.4
Grazvydas Ignotas
distinguish between POP parts that both have the same manufacturer/device
id, but different RAM.
Signed-off-by: Grazvydas Ignotas <not...@gmail.com>
---
drivers/k9f1g08r0a.c | 29 +++++++++++++++++++++++++++++
include/common.h | 3 +++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
index b039b50..eeb17c1 100644
--- a/drivers/k9f1g08r0a.c
+++ b/drivers/k9f1g08r0a.c
@@ -177,6 +177,35 @@ int nand_readid(int *mfr, int *id)
return 0;
}
+/* reads parameter page */
+int nand_read_param_page(unsigned char *data, unsigned int size)
+{
+ unsigned int i;
+
+ NAND_ENABLE_CE();
+
+ if (NanD_Command(NAND_CMD_RESET)) {
+ NAND_DISABLE_CE();
+ return 1;
+ }
+
+ if (NanD_Command(NAND_CMD_READPARAM)) {
+ NAND_DISABLE_CE();
+ return 1;
+ }
+
+ NanD_Address(ADDR_COLUMN, 0);
+ delay(10000);
+
+ for (i = 0; i < size; i++) {
+ data[i] = READ_NAND(NAND_ADDR);
+ delay(10);
+ }
+
+ NAND_DISABLE_CE();
+ return 0;
+}
+
/* read chip mfr and id
* return 0 if they match board config
* return 1 if not
diff --git a/include/common.h b/include/common.h
index a3c5092..9cf3f3a 100644
--- a/include/common.h
+++ b/include/common.h
@@ -75,6 +75,7 @@ void udelay (unsigned long usec);
#define NAND_CMD_READOOB 0x50
#define NAND_CMD_STATUS 0x70
#define NAND_CMD_READID 0x90
+#define NAND_CMD_READPARAM 0xec
#define NAND_CMD_RESET 0xff
/* Extended Commands for Large page devices */
@@ -82,6 +83,8 @@ void udelay (unsigned long usec);
int nand_chip(void);
int nand_read_block(uchar *buf, ulong block_addr);
+int nand_readid(int *mfr, int *id);
+int nand_read_param_page(unsigned char *data, unsigned int size);
int onenand_chip(void);
int onenand_read_block(unsigned char *buf, ulong block);
--
1.7.0.4
Grazvydas Ignotas
board/pandora/platform.S | 359 +++++++++++++++++++++
board/pandora/x-load.lds | 54 +++
drivers/Makefile | 4 +
9 files changed, 1440 insertions(+), 1 deletions(-)
create mode 100644 board/pandora/Makefile
create mode 100644 board/pandora/config.mk
create mode 100644 board/pandora/pandora.c
create mode 100644 board/pandora/platform.S
create mode 100644 board/pandora/x-load.lds
create mode 100644 include/configs/pandora.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 12f1521..3bbc893 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18,6 +18,9 @@
Enric Balletbo i Serra, <ebal...@iseebcn.com>
igep00x0 ARM ARMV7 (OMAP3xx SoC)
+GraÅžvydas Ignotas <not...@gmail.com>
+ pandora ARM ARMV7 (OMAP3xx SoC)
+
Tapani Utriainen, <tap...@technexion.com>
tam3517 ARM ARMV7 (Sitara AM3517 SoM)
tao3530 ARM ARMV7 (OMAP3530 SoM)
diff --git a/Makefile b/Makefile
index a54dcb3..0916bd8 100644
--- a/Makefile
+++ b/Makefile
@@ -230,7 +230,10 @@ tao3530_config : unconfig
tdm3730_config : unconfig
@$(MKCONFIG) $(@:_config=) arm omap3 tdm3730
-
+
+pandora_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm omap3 pandora
+
#########################################################################
## OMAP4 (ARM-CortexA9) Systems
#########################################################################
diff --git a/board/pandora/Makefile b/board/pandora/Makefile
new file mode 100644
index 0000000..074dc1b
--- /dev/null
+++ b/board/pandora/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := pandora.o
+SOBJS := platform.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/pandora/config.mk b/board/pandora/config.mk
new file mode 100644
index 0000000..2596adc
--- /dev/null
+++ b/board/pandora/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x40200800
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
new file mode 100644
index 0000000..9086733
--- /dev/null
+++ b/board/pandora/pandora.c
@@ -0,0 +1,785 @@
+/*
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzh...@ti.com>
+ * Richard Woodruff <r-woo...@ti.com>
+ *
+ * Modified for the Pandora
+ * John Willis <sou...@distant-earth.com>
+ * GraÅžvydas Ignotas <not...@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+#include <part.h>
+#include <fat.h>
+#include <i2c.h>
+
+/* params for 37XX */
+#define CORE_DPLL_PARAM_M2 0x09
+#define CORE_DPLL_PARAM_M 0x360
+#define CORE_DPLL_PARAM_N 0xC
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+typedef struct dpll_param dpll_param;
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
+#define __raw_readw(a) (*(volatile unsigned short *)(a))
+#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
+
+/* slight RAM timing differencer,
+ * tCKE differs from beagle's Micron part */
+#define MICRON_V_ACTIMB_200_2 (((MICRON_V_ACTIMB_200) & ~(7 << 12)) | (1 << 12))
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+void udelay (unsigned long usecs) {
+ delay(usecs);
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+#if defined(CFG_PRINTF) && defined(CONFIG_DRIVER_OMAP34XX_I2C)
+ unsigned char byte;
+
+ /* do additional init to prevent trash being output on startup */
+ serial_init();
+
+ /* restore GPBR1 for charging to work -
+ * boot ROM or something clears it before us */
+ byte = 0x90;
+ i2c_write(0x49, 0x91, 1, &byte, 1);
+
+ /* VAUX3 = 2.8V (AV connector) */
+ byte = 0x20;
+ i2c_write(0x4B, 0x7A, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x7D, 1, &byte, 1);
+#endif
+
+ return 0;
+}
+
+/*************************************************************
+ * Routine: get_mem_type(void) - returns the kind of memory connected
+ * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+ u32 mem_type = get_sysboot_value();
+ switch (mem_type) {
+ case 0:
+ case 2:
+ case 4:
+ case 16:
+ case 22:
+ return GPMC_ONENAND;
+
+ case 1:
+ case 12:
+ case 15:
+ case 21:
+ case 27:
+ return GPMC_NAND;
+
+ case 3:
+ case 6:
+ return MMC_ONENAND;
+
+ case 8:
+ case 11:
+ case 14:
+ case 20:
+ case 26:
+ return GPMC_MDOC;
+
+ case 17:
+ case 18:
+ case 24:
+ return MMC_NAND;
+
+ case 7:
+ case 10:
+ case 13:
+ case 19:
+ case 25:
+ default:
+ return GPMC_NOR;
+ }
+}
+
+static void early_nand_init(void)
+{
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */
+
+ /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
+ * We configure only GPMC CS0 with required values. Configiring other devices
+ * at other CS is done in u-boot. So we don't have to bother doing it here.
+ */
+ __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ delay(1000);
+
+ __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+ /* Enable the GPMC Mapping */
+ __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((NAND_BASE_ADR>>24) & 0x3F) |
+ (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+ delay(2000);
+}
+
+#ifdef CFG_3430SDRAM_DDR
+static int strncmp(const char *s1, const char *s2, int n)
+{
+ int i;
+ for (i = 0; i < n; i++)
+ if (s1[i] != s2[i])
+ return s1[i] - s2[i];
+ return 0;
+}
+
+#define MICRON_128MB_166MHZ 0
+#define MICRON_256MB_200MHZ 1
+
+/*********************************************************************
+ * config_sdram_ddr() - Init DDR SDRAM
+ *********************************************************************/
+static void config_sdram_ddr(void)
+{
+ unsigned char buf[64];
+ int ram_type = MICRON_128MB_166MHZ;
+ int ret;
+
+ /* reset sdrc controller */
+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+ __raw_writel(0, SDRC_SYSCONFIG);
+
+ /* setup sdrc to ball mux */
+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+
+ /* read NAND id to guess what RAM is attached */
+ early_nand_init();
+ ret = nand_read_param_page(buf, sizeof(buf));
+ if (ret == 0) {
+ if (strncmp((char *)buf + 44, "MT29F4G16ABBDA", 14) == 0)
+ ram_type = MICRON_256MB_200MHZ;
+ }
+
+ if (ram_type == MICRON_256MB_200MHZ) {
+ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
+ } else {
+ __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
+ }
+
+ if (get_cpu_family() == CPU_OMAP36XX && ram_type == MICRON_256MB_200MHZ) {
+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(MICRON_V_ACTIMB_200_2, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
+ __raw_writel(MICRON_V_ACTIMB_200_2, SDRC_ACTIM_CTRLB_1);
+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
+ } else {
+ __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
+ __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
+ }
+
+ __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
+
+ /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ __raw_writel(CMD_NOP, SDRC_MANUAL_1);
+
+ delay(5000);
+
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
+
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+
+ /* set mr0 */
+ __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
+ __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
+
+ /* set up dll */
+ __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
+ delay(0x2000); /* give time to lock */
+}
+#endif /* CFG_3430SDRAM_DDR */
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, cdiv, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+
+ if (val & SYSCLKDIV_2)
+ cdiv = 2;
+ else
+ cdiv = 1;
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source */
+ /* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+ cdiff *= cdiv;
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return S38_4M;
+ else if (cdiff > 15200)
+ return S26M;
+ else if (cdiff > 13000)
+ return S24M;
+ else if (cdiff > 9000)
+ return S19_2M;
+ else if (cdiff > 7600)
+ return S13M;
+ else
+ return S12M;
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ u32 osc_clk = 0, sys_clkin_sel;
+ dpll_param *dpll_param_p;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if (sys_clkin_sel > 2) {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
+ clk_index = sys_clkin_sel / 2;
+ } else {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
+ clk_index = sys_clkin_sel;
+ }
+
+ sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ sil_index = !(get_cpu_rev() == CPU_3XX_ES10);
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address of Core DPLL param table */
+ dpll_param_p = (dpll_param *) get_core_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ /* CORE DPLL */
+ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
+ work. write another value and then default value. */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
+ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to PER DPLL param table */
+ dpll_param_p = (dpll_param *) get_per_dpll_param();
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+ /* PER DPLL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
+ sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
+ } else {
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
+ }
+
+ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table */
+ dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address to IVA DPLL param table */
+ dpll_param_p = (dpll_param *) get_iva_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ /* IVA DPLL (set to 12*20=240MHz) */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+
+void s_init(void)
+{
+ watchdog_init();
+ try_unlock_memory();
+ set_muxconf_regs();
+ delay(100);
+ per_clocks_enable();
+ prcm_init();
+ config_sdram_ddr();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ ********************************************************/
+int misc_init_r(void)
+{
+#ifdef CFG_PRINTF
+ unsigned char buf[64];
+ char nand_model[20];
+ int i, ret;
+
+ printf("OpenPandora System\n");
+ print_cpuinfo();
+
+ /* log NAND model */
+ ret = nand_read_param_page(buf, sizeof(buf));
+ if (ret == 0) {
+ for (i = 0; i < sizeof(nand_model) - 1; i++) {
+ if (buf[i + 44] == ' ')
+ break;
+ nand_model[i] = buf[i + 44];
+ }
+ nand_model[i] = 0;
+ printf("NAND: %s\n", nand_model);
+ }
+#endif
+
+ return 0;
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init(void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+ /* UART 3 Clocks */
+ sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+ sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+#endif
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ /* Turn on all 3 I2C clocks */
+ sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
+ sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
+#endif
+
+ /* Enable the ICLK for 32K Sync Timer as its used in udelay */
+ sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
+
+ sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
+ sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
+ sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
+ sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
+ sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
+ sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
+ sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
+ sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
+ sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
+ sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
+ sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
+ sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
+
+ /* Enable GPIO5 clocks for blinky LEDs */
+ sr32(CM_FCLKEN_PER, 16, 1, 0x1); /* FCKen GPIO5 */
+ sr32(CM_ICLKEN_PER, 16, 1, 0x1); /* ICKen GPIO5 */
+
+ delay(1000);
+}
+
+/* Set MUX for UART, GPMC, SDRC, GPIO */
+
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define CP(x) (CONTROL_PADCONF_##x)
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /*Serial Interface (Peripheral boot, Linux console)*/\
+ MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
+ MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+ /*I2C Ports*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ /*LEDs (Controlled by OMAP)*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
+ MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+/**********************************************************
+ * Routine: nand+_init
+ * Description: Set up nand for nand and jffs2 commands
+ *********************************************************/
+int nand_init(void)
+{
+ /* init already done in early_nand_init */
+
+ if (get_mem_type() != GPMC_NAND && get_mem_type() != MMC_NAND) {
+#ifdef CFG_PRINTF
+ printf("Unsupported flash chip!\n");
+#endif
+ return 1;
+ }
+
+ if (nand_chip()) {
+#ifdef CFG_PRINTF
+ printf("Unsupported NAND Chip!\n");
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+#define DEBUG_LED1 128 /* gpio - SD Slot 1 */
+#define DEBUG_LED2 129 /* gpio - SD Slot 2 */
+
+static void blinkLEDs(void)
+{
+ void *p;
+
+ /* Alternately turn the LEDs on and off */
+ p = (unsigned long *)OMAP34XX_GPIO5_BASE;
+ while (1) {
+ /* turn LED1 on and LED2 off */
+ *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
+ *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
+
+ /* delay for a while */
+ delay(1000);
+
+ /* turn LED1 off and LED2 on */
+ *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
+ *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
+
+ /* delay for a while */
+ delay(1000);
+ }
+}
+
+/* optionally do something like blinking LED */
+void board_hang(void)
+{
+ while (1)
+ blinkLEDs();
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void raise(void)
+{
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void abort(void)
+{
+}
diff --git a/board/pandora/platform.S b/board/pandora/platform.S
new file mode 100644
index 0000000..7b1fa7b
--- /dev/null
+++ b/board/pandora/platform.S
@@ -0,0 +1,359 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woo...@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
diff --git a/board/pandora/x-load.lds b/board/pandora/x-load.lds
new file mode 100644
index 0000000..5f352d3
--- /dev/null
+++ b/board/pandora/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <g...@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/drivers/Makefile b/drivers/Makefile
index c0acdf5..209b082 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -64,6 +64,10 @@ ifeq ($(BOARD), tdm3730)
COBJS += k9f1g08r0a.o
endif
+ifeq ($(BOARD), pandora)
+COBJS += k9f1g08r0a.o
+endif
+
## Disabled for now:
## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \
## lan91c96.o mw_eeprom.o natsemi.o \
diff --git a/include/configs/pandora.h b/include/configs/pandora.h
new file mode 100644
index 0000000..24e18b0
--- /dev/null
+++ b/include/configs/pandora.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2006
+ * Texas Instruments <www.ti.com>
+ * Richard Woodruff <r-woo...@ti.com>
+ *
+ * X-Loader Configuation settings for the Pandora board.
+ *
+ * Derived from /include/configs/omap3evm.h
+ * John Willis <sou...@distant-earth.com>
+ * GraÅžvydas Ignotas <not...@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* serial printf facility takes about 3.5K */
+#define CFG_PRINTF
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_PANDORA 1 /* working with a Pandora */
+
+/* Enable the below macro if MMC boot support is required */
+#define CONFIG_MMC 1
+#define CFG_CMD_MMC 1
+#define CFG_CMD_FAT 1
+
+/* Enable I2C stuff */
+/* I2C to power serial shifter */
+
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 1
+#define CFG_I2C_BUS 0
+#define CFG_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+
+#if (V_OSCK > 19200000)
+#define V_SCLK (V_OSCK >> 1)
+#else
+#define V_SCLK V_OSCK
+#endif
+
+#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
+#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */
+
+/* Memory type */
+#define CFG_3430SDRAM_DDR 1
+
+/* The actual register values are defined in u-boot- mem.h */
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define NAND_BASE_ADR NAND_BASE
+
+#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
+
+#ifdef CFG_PRINTF
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE -4
+#define CFG_NS16550_CLK 48000000
+#define CFG_NS16550_COM3 OMAP34XX_UART3
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 3 /* UART3 for Serial, Thanks */
+#define CONFIG_CONS_INDEX 3
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_PBSIZE 256
+
+#endif /* CFG_PRINTF */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LOADADDR 0x80008000
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Board NAND Info.
+ */
+
+#define CFG_NAND_K9F1G08R0A /* Micron 16-bit 256MB chip large page NAND chip */
+#define NAND_16BIT
+
+/* NAND is partitioned:
+ * 0x00000000 - 0x0007FFFF Booting Image
+ * 0x00080000 - 0x0025FFFF U-Boot Image
+ * 0x00260000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care)
+ * 0x00280000 - ... depends on application
+ */
+#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */
+#define NAND_UBOOT_END 0x0160000 /* Only read part for faster boot */
+#define NAND_BLOCK_SIZE 0x20000
+
+#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
+#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C)
+#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80)
+#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84)
+
+#ifdef NAND_16BIT
+#define WRITE_NAND_COMMAND(d, adr) \
+ do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+ do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+ do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+ (*(volatile u16 *)GPMC_NAND_DATA_0)
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF() \
+ do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON() \
+ do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#else /* to support 8-bit NAND devices */
+#define WRITE_NAND_COMMAND(d, adr) \
+ do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+ do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+ do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+ (*(volatile u8 *)GPMC_NAND_DATA_0);
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF() \
+ do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON() \
+ do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#endif
+
+#define NAND_CTL_CLRALE(adr)
+#define NAND_CTL_SETALE(adr)
+#define NAND_CTL_CLRCLE(adr)
+#define NAND_CTL_SETCLE(adr)
+#define NAND_DISABLE_CE()
+#define NAND_ENABLE_CE()
+
+#endif /* __CONFIG_H */
--
1.7.0.4