I m new to this topic " Channel estimation in RAKE receiver" as i know
only that the estimation is done on the basis of Pilot channel. But can
anybody tell me how can i develope an algorithm as i need to design a
sythesiable Verilog Code for it.
If the algorithm can be explained in the form of digital logics,it
would be good for me to understand the design.
If needed,some type of assumption can be made in the algorithm that
could be fine.
If we dont do channel estmation it is kind of Blind Reception? Is it?
Means am i right or having wrong concepts.
Please friends help me out in this problems.
Estimation of channel is a signal processing element, where you need
all floating point operations and that too on complex numbers. This is
done on a DSP processor. Synthesis of fixed point/floating point ALU in
verilog itself is a major design problem.
Its possible that directly the IF is sampled and converted to digital
data, the matched filtering itself would be digital filter and the
samples are fed to DSP block which does signal processing on it.
Hope you are getting the picture clear..
regrds
Wirelessman