Hi,
We are trying to design a daughter board for Warp with audio in/out. For this, we are using SGTL5000 via I2S interface for audio out and microphone application. For I2S, apart from the DOUT(AUD_RXD), DIN(AUD_TXD), LRCLK(AUD_TXFS) and SCLK(AUD_TXC), we need an additional clock signal (10 to 27 MHz) for SYS_MCLK of SGTL5000 PLL.
Can any of the pins (in the 3 Warp ports) provide these signals ?
Cheers
Rams
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Hey Rams,GPIO4_IO23 (pin 30 of Warp P2 connector) can be used as the audio clock output. I believe this is what you're looking for:MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT
Jacob Postman, Ph.D.Address: 1215 NW Alder Creek Drive Corvallis, OR 97330
On Sun, Apr 9, 2017 at 2:09 PM, Romsub <ramy...@gmail.com> wrote:
Hi,
We are trying to design a daughter board for Warp with audio in/out. For this, we are using SGTL5000 via I2S interface for audio out and microphone application. For I2S, apart from the DOUT(AUD_RXD), DIN(AUD_TXD), LRCLK(AUD_TXFS) and SCLK(AUD_TXC), we need an additional clock signal (10 to 27 MHz) for SYS_MCLK of SGTL5000 PLL.
Can any of the pins (in the 3 Warp ports) provide these signals ?
Cheers
Rams
--
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