How to pass on the file list to the VTR tool

[Waseem Saify Kraipak]

HI Vaughn,

 

I want to know how to give the file list to the vtr tool.

The File list has all the RTL files which needs to be synthesized using the vtr tool.

Whats the command  to pass the file list ?

 

Thanks,

Waseem

 

[Aman Arora]

Waseem,

You might wanna try out the includes_dir and include_list_add feature in the VTR task file. See this: https://docs.verilogtorouting.org/en/latest/vtr/tasks/#optional-fields

Here's an example: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin/config/config.txt

Thanks,

Aman

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[Waseem Saify Kraipak]

Hi Aman,

 

Could you provide a run command with config option as an example

The current command which we are using to compile a single rtl file using  VTR is as below :

 

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py $SRC_RTL/RTL/addr.v  $SRC_RTL/RTL/k6_frac_N10_frac_chain_mem32K_40nm_dpram.xml -temp_dir .  -route_chan_width 40

 

$SRC_RTL is the directory where we keep our rtl files and architectural file of our design

Now what we are trying to do is compile a bigger design which has couple of more RTL files.

Inside the RTL folder there is include directory which has .vh files which

$SRC_RTL/RTL/include

RTL files

$SRC_RTL/RTL/top.v

$SRC_RTL/RTL/m1.v

$SRC_RTL/RTL/m2.v

$SRC_RTL/RTL/m3.v

 

Do we have to keep the config.txt in the RTL folder ?

We have created the config.txt the snapshot is as below:

 

*******************************************************************************************************************

# Path to directory of circuits to use
circuits_dir=$SRC_RTL/RTL/

# Path to directory of includes circuits to use
includes_dir=$SRC_RTL/RTL/include

# Path to directory of architectures to use
archs_dir=$SRC_RTL/RTL/

# Add circuits to list to sweep
circuit_list_add=top.v

# Add circuits to includes list to sweep
include_list_add=common1.vh
include_list_add= common2.vh
include_list_add=m1.v
include_list_add=m2.v
include_list_add=m3.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm_mult9x9.xml

# Parse info and how to parse
#parse_file=vpr_no_timing.txt

# How to parse QoR info
#qor_parse_file=qor_no_timing.txt

# Script parameters
script_params_common=-track_memory_usage --timing_analysis off

 

*******************************************************************************************************************

 

Could you confirm if the config.txt is ok

 

What’s the command line where we can pass the config.txt

 

$VTR_ROOT/vtr_flow/scripts/run_vtr_flow.py $SRC_RTL/RTL/config.txt  ????

 

Thanks and Regards,

Waseem

[Aman Arora]

To use the config file, you need to use run_vtr_task.py instead of run_vtr_flow.py. See these pages:

https://docs.verilogtorouting.org/en/latest/vtr/tasks/#vtr-tasks

https://docs.verilogtorouting.org/en/latest/vtr/run_vtr_task/

The config file you've shown looks okay to me. 

I should mention that the includes_dir and include_list_add variables in the config file are a relatively new feature. 

The common method earlier was to preprocess the Verilog files to concatenate them into one Verilog file and then give that to VTR.

This is all done using Python scripts in the vtr_flow/scripts folder. You're welcome to add features to these and submit pull requests. 

[Waseem Saify Kraipak]

Hi Aman,

 

$VTR_ROOT/vtr_flow/scripts/run_vtr_task.py  -$SRC_RTL/RTL/config.txt 

Is this the correct command.

 

Wasim

[Aman Arora]

The usage is:

run_vtr_task.py <task_name> 

Please see how to create tasks at:

https://docs.verilogtorouting.org/en/latest/vtr/tasks/#vtr-tasks

And how to use run_vtr_task.py at:

https://docs.verilogtorouting.org/en/latest/vtr/run_vtr_task/