Issue with Multibit Adder in VTR Architecture

[Cheng-Chieh Liao]

Hi VTR Team,

I’ve encountered an issue while working with the multibit adder in my research project. I created a simple 8-bit adder benchmark (see Figure 1), but when I ran it using the flagship VTR architecture (vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32k_40nm.xml), I ran into an error. When I investigated the error, I saw that in the BLIF file generated by ABC (see Figure 2), the outputs are not connected. Hence, when VPR runs, it optimizes all the logic out and says there are no blocks to place/route in the benchmark and errors out. There are no errors in the ABC log file. However, when I modified the benchmark to use a sequential adder (see Figure 3), the run was successful.

Fig.1

 

Fig.2

 

Fig.3

Has anyone experienced this before? Any guidance on what might be causing this issue would be greatly appreciated.

Best regards,
Cheng-Chieh Liao

[Cheng-Chieh Liao]

Fig1:


Fig2:


Fig3:

Cheng-Chieh Liao 在 2024年8月12日 星期一凌晨12:09:27 [UTC-7] 的信中寫道：