Difficulty with for-loops

[Bryan Arguello]

I am trying to run odin on the two attached modules. I run it as :

>>odin_ii -V subBytes.v sbox.v 

and get the following error:

std::Logic_error basic_string::_M_construct null not valid

If I unroll the for-loop manually, ODIN is able to generate a netlist with no problem.

I have a few other modules with for-loops that ODIN cannot process, but I am hoping that I can transfer what I learn from this issue to those modules as well.

Please let me know if you can share some guidance or provide additional details.

Thanks,

-Bryan

[Vaughn Betz]

Odin-II has quite a few limitations in verilog language features. I recommend using vtr 9 or the master branch (which is even more recent) and using the default yosys+parmys synthesis engine.

Vaughn

On May 20, 2025, at 7:07 AM, Bryan Arguello <brome...@gmail.com> wrote:



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<sbox.v>

<subBytes.v>

[Bryan Arguello]

Thanks Vaughn,

You are recommending that I use yosys+parmys synthesis engine instead of odin_II in the master branch?  Can you point me to documentation that can guide me in using these tools to generate a netlist from the Verilog modules?

-Bryan

[Vaughn Betz]

See this paper (Section 7) for an overview https://dl.acm.org/doi/epdf/10.1145/3734798 .

See https://docs.verilogtorouting.org/en/latest/quickstart/ for a walkthrough of how to run the flow, and pointers of what to read next.

Vaughn

To view this discussion visit https://groups.google.com/d/msgid/vtr-users/f402724a-9114-43d4-897d-8f2c01aeb41cn%40googlegroups.com.

[Bryan Arguello]

I have built VTR v9, and I am trying to apply  run_vtr_flow.py to a package of Verilog scripts in a single folder.  I am passing it the top Verilog script (hoping that the flow automatically brings in the others as needed).  It errors out with an error message in parmys.out of "Duplicate definition of module DFF!".  I am not sure what this means as I have no DFF modules anywhere in my Verilog package.  I have also tried using the -yosys_script argument to supply all the Verilog scripts to yosys.  This yields the same error.

In case it helps, I am trying to obtain a netlist for the Verilog package in the following repo: https://github.com/michaelehab/AES-Verilog/tree/main

Thanks,

-Bryan