Find error in creating clock using sdc file.

[Frank Franklin]

Hi VTR Team,

 

I try to run vpr with .sdc file whose content is:

create_clock -period 20 {v}

 

The command seems right according to the VTR document.

create_clock -period <float> <netlist clock list or regexes>

 

And finally, I get the error provided by vpr_stdout.log:

Error 1:

Type: SDC file

File: ../condition_program_test6.sdc

Line: 1

Message: Clock name or pattern 'v' does not correspond to any nets. To create a virtual clock, use the '-name' option.

 

However, 'v' is indeed one of the inputs in module passed in.

I also try other commands like:

create_clock -period 20 v

create_clock -period 20 condition_program_test6^v

create_clock -period 20 {condition_program_test6^v}

 

And none of these commands worked.

 

I wonder if I made some mistakes, but from the VTR documentation it seems that there are no errors? I’ll appreciate it if you could help me find the mistakes in commands.

Thank you!

The operating system is Ubuntu 20.04.

The version of VTR is FCCM 2023, and the whole command is:

/home/frank/Desktop/Software/reload-vtr-verilog-to-routing-vFCCM_2023_NoC_Placement/vtr_flow/scripts/run_vtr_flow.py condition_program_test6.v /home/frank/Desktop/Software/vscode/Vgenerator-beta-1.0.2-202405071327/exploration/EArch_fixed_40_40.xml -temp_dir temp -start odin --device fixed --route_chan_width 100 --sdc_file ../condition_program_test6.sdc --timing_report_detail detailed --timing_report_npaths 100000

The verilog RTL code is:

module condition_program_test6(s, qNf10, wA, v, R);
output s;
output [9:0] qNf10;
output wA;
input v;
input [8:0] R;
reg u;
reg i;
reg A7h;
reg [1:0] M;
always @ (R) begin
i = 3;
u = 229;
if (v) begin
i = ~(~(R[7]) - ((~(u & R[0]))) * ~(~((v - (8 & 4)))) - ~(120) - 8);
end
if ((((~(~((v))) & v))) != (~(~((40 + 37 * 2) & ~(R[4:3]) * i)))) begin
M = (4);
end
else begin
M = 425 + R[6:5];
end
end
always @ (posedge v) begin
A7h <= R[0] + 1;
end
assign s = (~(64));
assign qNf10 = 65 - M[0] & A7h * 2 - ((~(234)));
assign wA = (M[1]);
endmodule

[Vaughn Betz]

I suggest looking at the .blif file to make sure the net name you expect is there; if it is, try setting a clock on that exact net name.

[Adding Kevin in case he can provide any syntax insight].

Vaughn

--
You received this message because you are subscribed to the Google Groups "VTR-Users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to vtr-users+...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/vtr-users/c77e1629-3338-47d4-b3e7-6e1b8301adc6n%40googlegroups.com.

[Frank Franklin]

Thank you, Professor. Part of the .blif content about clock ‘v’ is shown as follow:

.inputs condition_program_test6^v condition_program_test6^R~0 condition_program_test6^R~1 condition_program_test6^R~2 \

 condition_program_test6^R~3 condition_program_test6^R~4 condition_program_test6^R~5 condition_program_test6^R~6 \

 condition_program_test6^R~7 condition_program_test6^R~8

 

.outputs condition_program_test6^s condition_program_test6^qNf10~0 condition_program_test6^qNf10~1 \

 condition_program_test6^qNf10~2 condition_program_test6^qNf10~3 condition_program_test6^qNf10~4 \

 condition_program_test6^qNf10~5 condition_program_test6^qNf10~6 condition_program_test6^qNf10~7 \

 condition_program_test6^qNf10~8 condition_program_test6^qNf10~9 condition_program_test6^wA

 

.latch n160 condition_program_test6^A7h_FF re condition_program_test6^v 0

 

.names condition_program_test6^v condition_program_test6^ADD~24-2[1] condition_program_test6^wA

01 1

 

.names condition_program_test6^v condition_program_test6^ADD~24-1[1] lNOT~56

01 0

 

The .pre-vpr.blif file is generated by odin_ii and ABC. So, maybe the net name isn’t wrong. The clock name of v is condition_program_test6^v. The command is

‘create_clock -period 20 condition_program_test6^v’

 

However, vpr seems cannot match ‘condition_program_test6^v’ by using the net name. The crash info like the previous one is thrown.

 

I also try to use other names (e.g. condition_program_test6^A7h_FF, lNOT~56, condition_program_test6^R~1) in case I make a name mistake. Unfortunately, it still isn’t work.

 

Could you please help me check it again? I'm really overwhelmed by the situation. 

Thank you.

[Vaughn Betz]

It seems like this one should work then:

create_clock -period 20 condition_program_test6^v

You could also try 

create_clock -period 20 * 

to constrain all netlist clocks.

Vaughn

To view this discussion on the web visit https://groups.google.com/d/msgid/vtr-users/1c858c76-2720-4e84-bcc7-2681f9fbfca0n%40googlegroups.com.