NoC-Enhanced FPGAs

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li_yo...@zju.edu.cn

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Oct 15, 2024, 4:03:47 AM10/15/24
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Hello VTR developers! I am a user of the VTR project, but recently I have encountered a troubling problem, and I need your help. In the paper "Placement Optimization for NoC-Enhanced FPGAs", you mentioned that the synthesis tool for NoC-Enhanced FPGAs is done using Quartus, and then using vqm2blif to get the blif netlists required by VPR. Compared to VTR, the largest limitation of Quartus is the inability to add support for new primitive types (new hard blocks like logical routers). However, you mention you modify the Titan flow to support custom hard blocks. I was wondering how I could use titan flow to add new primitive types and match the new primitive types in the architecture file in VPR. In other words, how do you use quartus' synthesis tool to synthesize RTL code and leave custom primitives unsynthesized to map VPR custom primitive. Looking forward to your reply!  

Vaughn Betz

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Oct 17, 2024, 12:15:13 PM10/17/24
to li_yo...@zju.edu.cn, Soheil Shahrouz, vtr-...@googlegroups.com
You don't have to use Quartus to generate benchmarks with NoCs in them -- we did that in that paper, but you should also be able to add hard routers to designs and synthesize them through yosys/parmys.  Soheil, which flow are you using for your recent NoC benchmarks, and can you give any pointers?

We can also pass new hard blocks through Quartus by black boxing them, and then using scripts to recover the connectivity / to from them and inserting the proper block before vpr.  See the section of the attached thesis starting at page 21.

Hope this helps,

Vaughn

On Tue, Oct 15, 2024 at 4:03 AM <li_yo...@zju.edu.cn> wrote:
Hello VTR developers! I am a user of the VTR project, but recently I have encountered a troubling problem, and I need your help. In the paper "Placement Optimization for NoC-Enhanced FPGAs", you mentioned that the synthesis tool for NoC-Enhanced FPGAs is done using Quartus, and then using vqm2blif to get the blif netlists required by VPR. Compared to VTR, the largest limitation of Quartus is the inability to add support for new primitive types (new hard blocks like logical routers). However, you mention you modify the Titan flow to support custom hard blocks. I was wondering how I could use titan flow to add new primitive types and match the new primitive types in the architecture file in VPR. In other words, how do you use quartus' synthesis tool to synthesize RTL code and leave custom primitives unsynthesized to map VPR custom primitive. Looking forward to your reply!  

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Srivatsan_MASc_Thesis.pdf

Soheil Shahrouz

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Oct 18, 2024, 10:37:12 AM10/18/24
to Vaughn Betz, li_yo...@zju.edu.cn, vtr-...@googlegroups.com
I used the modified titan flow for new benchmarks. There is a CI test that pushes a NoC design through Odin-II and VPR. You can find it under the following path: vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_noc_mlp_odin_ii.

li_yo...@zju.edu.cn

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Oct 19, 2024, 10:28:06 AM10/19/24
to Soheil Shahrouz, Vaughn Betz, vtr-...@googlegroups.com

Thank you for your reply. Is the modified titan flow you are referring to titan_release_2.0.0?  I still prefer to use Quartus for black box new hard blocks like "noc_router_adapter_block" because Quartus has more verilog support. I have read the paper "Design Mapping and Optimization for Field Programmable Gate Arrays with Embedded Networks on Chip ", you say "By partitioning the hard blocks we prevent Quartus from synthesizing them out of the netlist. We have automated this compilation process with a script." in page 24. Where can I get this script you mentioned? Is it q2_flow.tcl in titan_release_2.0.0? I have tried to use Quartus to synthesize simple_four_noc_1D_chain under Synthetic_Designs, run Quartus with q2_flow.tcl, generate VQM files, and then convert vqm2blif into blif files. Unfortunately, eventually the "noc_router_adapter_block" primitive was optimized out and could not be generated. I look forward to your reply, if possible, can you tell me where I can find the latest modified titan flow. I download titan_release_2.0.0 in https://www.eecg.utoronto.ca/~vaughn/titan/ download titan_release_2. 0.0. 




-----原始邮件-----
发件人: "Soheil Shahrouz" <sohe...@gmail.com>
发送时间: 2024-10-18 22:36:57 (星期五)
收件人: "Vaughn Betz" <vau...@ece.utoronto.ca>
抄送: li_yo...@zju.edu.cn, vtr-...@googlegroups.com
主题: Re: [vtr-users] NoC-Enhanced FPGAs

Vaughn Betz

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Oct 19, 2024, 2:05:53 PM10/19/24
to li_yo...@zju.edu.cn, Srivatsan Srinivasan, Srivatsan Srinivasan, Soheil Shahrouz, vtr-...@googlegroups.com
Hi Srivatsan,

I hope you're doing well.  Could you point us at the script that automates the protection / extraction of hard blocks (e.g. NoC routers) in Quartus to blif flows?

Vaughn

Vaughn Betz

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Oct 19, 2024, 2:26:20 PM10/19/24
to li_yo...@zju.edu.cn, Srivatsan Srinivasan, Srivatsan Srinivasan, Soheil Shahrouz, vtr-...@googlegroups.com
Soheil, perhaps you have been using this script and know where it is too?

Vaughn
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