Problem with VPR support routing constraint

[feng yu]

Hi VTR Team, sorry to bother you.

VPR document on website only show"Global Routing Constraints", i wonder if VPR support other routing constraint just like Xilinx fixed routing.

For example, i want output of LUT_a and LUT_b connect to input of LUT_c and output of LUT_d and LUT_e connect to input of LUT_f and so on.

if VPR support this type of routing constraint ? How can i know how to write this type of constraint.

Thank you  sincerely

[vaugh...@gmail.com]

VTR only supports constraints on the routing of global signals at this point.

Vaughn

On Aug 16, 2024, at 12:46 AM, feng yu <keroro...@gmail.com> wrote:



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