How synthesis tools know the functionality of user-specified blocks and map RTL design to them?

[WanZheng Weng]

Hi VTR team,

I am trying to learn how to define my own FPGA architecture using VTR Architecture Description Language and test its performance through VTR flow. But I have doubt about how synthesis tools handle user-defined netlist block?

Through reading online document, I have learn that synthesis tools already know some basic primitive blocks defined in .blif format, like IO(.inputs/.outputs), flipflop(.latch), LUT(.names), and they can be related with complex blocks through "blif_model" field in the "pb_type" tag. But for other non-primitive/user-defined blocks with complex functionality, like "multiply", "adder" and "dual_port_ram" defined in EArch.xml, the architecture file only defines the io pins and internal interconnection information of these block. So I wonder how synthesis tools know about the detailed functionality of these blocks and map RTL design to it. And If I want to define a new netlist block in my architecture, like DSP48E in Xilinx FPGA, where should I add the functionality information about it so that synthesis tools knows how to map designs to it.

[Vaughn Betz]

Adding Amir, Navid and Alireza, who might be good candidates to answer this.

Vaughn

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