Hello,
I have a question regarding the graphical representation of the routing architecture.
The channel width is set to a fixed value of 20, which corresponds to the number of channels highlighted in yellow. However, in other areas, such as the section highlighted in orange, the number of channels decreases to 10.
Why does this happen? Shouldn't the channel width remain constant across the FPGA, resulting in 20 channels throughout?
I would appreciate your assistance.