TILE Based FPGA support in VTR tool

[Waseem Saify Kraipak]

 

 

Hi Vaughn,

 

We were going through with one of the OpenSource Tile based FPGA architecture.

In this they are describing the architecture as shown in the Diagram Below :

Does the VPR tool support the Tileable architecture in which a tile is described in the architecture file.

Do we have an example architecture file which describes all the components within a tile(CLB,SB and Connection Box) ?

When the VPR is invoked in Gui mode, will it show tile or it will still show the traditional CLB,SB and connection Box spread across .

 

 

Waseem

[Vaughn Betz]

Is this from the OpenFPGA web site or paper?  If so the best people to contact are the OpenFPGA team.

I believe their current flow is to export the entire rr-graph and read it into vpr, although they have talked about integrating the modified rr-graph generator directly in the master branch of vtr.

Vaughn

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