[verilog-to-routing/vtr-verilog-to-routing] 62279e: Modified detailed routing to support different cha...
16 views
Skip to first unread message
Paula Perdomo
Aug 16, 2021, 11:01:06 AM8/16/21
to vtr-c...@googlegroups.com
Branch: refs/heads/manual_moves
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: 62279ec3855172b75f7e1b0a57f3e9de0efddc71
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/62279ec3855172b75f7e1b0a57f3e9de0efddc71
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M doc/src/arch/reference.rst
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
Log Message:
-----------
Modified detailed routing to support different channel widths
Commit: 0129d821c1f75977bda39b08dc2997ea2745822a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0129d821c1f75977bda39b08dc2997ea2745822a
Author: Brandon Heiner <77360779...@users.noreply.github.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M .github/gha/install_dependencies.sh
M .github/kokoro/continuous/nightly.cfg
A .github/kokoro/continuous/odin_strong.cfg
M .github/kokoro/continuous/strong.cfg
M .github/kokoro/continuous/strong_sanitized.cfg
M .github/kokoro/continuous/weekly.cfg
R .github/kokoro/presubmit/nightly.cfg
A .github/kokoro/presubmit/nightly_test1.cfg
A .github/kokoro/presubmit/nightly_test2.cfg
A .github/kokoro/presubmit/nightly_test3.cfg
A .github/kokoro/presubmit/nightly_test4.cfg
A .github/kokoro/presubmit/odin_strong.cfg
M .github/kokoro/run-vtr.sh
M .github/kokoro/steps/vtr-full-setup.sh
M .github/kokoro/steps/vtr-test.sh
M .github/travis/build.sh
R .github/travis/setup.sh
M .github/workflows/test.yml
A .gitpod.Dockerfile
A .gitpod.yml
M BUILDING.md
M Dockerfile
M Makefile
M ODIN_II/CMakeLists.txt
M ODIN_II/SRC/ast_elaborate.cpp
M ODIN_II/SRC/include/odin_error.h
M ODIN_II/SRC/netlist_create_from_ast.cpp
M ODIN_II/SRC/odin_error.cpp
M ODIN_II/SRC/subtractions.cpp
M ODIN_II/regression_test/benchmark/suite/heavy_suite/task_list.conf
M ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf
A ODIN_II/regression_test/benchmark/suite/vtr_multiclock_suite/task_list.conf
A ODIN_II/regression_test/benchmark/task/koios/synthesis_result.json
A ODIN_II/regression_test/benchmark/task/koios/task.conf
M ODIN_II/regression_test/benchmark/task/large/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports.v
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports_input
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports_output
M ODIN_II/verify_odin.sh
M README.developers.md
M README.md
M blifexplorer/CMakeLists.txt
M dev/pylint_check.py
M dev/upgrade_vtr_archs.sh
M doc/src/api/vpr/netlist.rst
M doc/src/arch/reference.rst
M doc/src/tutorials/arch/fracturable_multiplier_bus.rst
M doc/src/tutorials/flow/basic_flow.rst
M doc/src/vpr/debug_aids.rst
M doc/src/vtr/benchmarks.rst
M doc/src/vtr/tasks.rst
M doc/src/z_references.bib
M libs/EXTERNAL/libargparse/src/argparse.cpp
M libs/EXTERNAL/libblifparse/CMakeLists.txt
M libs/EXTERNAL/libsdcparse/CMakeLists.txt
M libs/libarchfpga/CMakeLists.txt
M libs/liblog/CMakeLists.txt
M libs/librtlnumber/src/include/internal_bits.hpp
M libs/libvtrcapnproto/CMakeLists.txt
M libs/libvtrutil/src/vtr_memory.h
M libs/libvtrutil/src/vtr_vector_map.h
M requirements.txt
M run_reg_test.py
M utils/fasm/CMakeLists.txt
M utils/fasm/src/main.cpp
M utils/fasm/test/test_fasm.cpp
M utils/fasm/test/test_fasm_arch.xml
M utils/route_diag/CMakeLists.txt
M utils/route_diag/src/main.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/SetupVPR.h
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist_utils.cpp
M vpr/src/base/clustered_netlist_utils.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_route.cpp
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/stats.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints_serializer.h
A vpr/src/base/vpr_constraints_writer.cpp
A vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
A vpr/src/device/rr_graph_builder.cpp
A vpr/src/device/rr_graph_builder.h
A vpr/src/device/rr_graph_view.cpp
A vpr/src/device/rr_graph_view.h
A vpr/src/device/rr_spatial_lookup.cpp
A vpr/src/device/rr_spatial_lookup.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/search_bar.cpp
M vpr/src/pack/cluster.cpp
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/critical_uniform_move_generator.cpp
M vpr/src/place/feasible_region_move_generator.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_transactions.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/uniform_move_generator.cpp
M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp
M vpr/src/power/power.cpp
M vpr/src/route/annotate_routing.cpp
M vpr/src/route/check_route.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/overuse_report.cpp
M vpr/src/route/route_breadth_first.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h
M vpr/src/route/route_timing.cpp
M vpr/src/route/route_tree_timing.cpp
M vpr/src/route/route_util.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_sampling.cpp
A vpr/src/route/rr_edge.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph2.h
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_graph_indexed_data.cpp
M vpr/src/route/rr_graph_reader.cpp
M vpr/src/route/rr_graph_storage.h
M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_util.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_graph_writer.cpp
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
M vpr/src/route/segment_stats.cpp
M vpr/src/timing/VprTimingGraphResolver.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml
M vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml
M vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v
R vtr_flow/benchmarks/blif/multiclock/cascading_ff.blif
R vtr_flow/benchmarks/blif/multiclock/iir1.blif
R vtr_flow/benchmarks/blif/multiclock/multi_clock_reader_writer.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_output_and_latch.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_reader_writer.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_separate_and_latch.blif
R vtr_flow/benchmarks/blif/multiclock/simple_multiclock.blif
R vtr_flow/benchmarks/blif/multiclock/stereovision3.blif
R vtr_flow/benchmarks/blif/multiclock/sv_chip3_hierarchy_no_mem.blif
A vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v
A vtr_flow/benchmarks/hdl_include/include/README.md
A vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh
A vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh
A vtr_flow/benchmarks/hdl_include/include/memory_controller.v
M vtr_flow/benchmarks/titan_blif/README.rst
M vtr_flow/benchmarks/titan_other_blif/README.rst
A vtr_flow/benchmarks/verilog/koios/README.md
A vtr_flow/benchmarks/verilog/koios/attention_layer.v
A vtr_flow/benchmarks/verilog/koios/bnn.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.large.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.medium.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.small.v
A vtr_flow/benchmarks/verilog/koios/conv_layer.v
A vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v
A vtr_flow/benchmarks/verilog/koios/dla_like.medium.v
A vtr_flow/benchmarks/verilog/koios/dla_like.small.v
A vtr_flow/benchmarks/verilog/koios/eltwise_layer.v
A vtr_flow/benchmarks/verilog/koios/gemm_layer.v
A vtr_flow/benchmarks/verilog/koios/lstm.v
A vtr_flow/benchmarks/verilog/koios/reduction_layer.v
A vtr_flow/benchmarks/verilog/koios/robot_rl.v
A vtr_flow/benchmarks/verilog/koios/softmax.v
A vtr_flow/benchmarks/verilog/koios/spmv.v
A vtr_flow/benchmarks/verilog/koios/test.v
A vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.medium.v
A vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.small.v
R vtr_flow/benchmarks/verilog/matmul_8x8_fp16.v
M vtr_flow/benchmarks/verilog/raygentop.v
R vtr_flow/benchmarks/verilog/tpu.16x16.int8.v
R vtr_flow/benchmarks/verilog/tpu.32x32.int8.v
M vtr_flow/primitives.v
M vtr_flow/scripts/flow_script_template.txt
M vtr_flow/scripts/python_libs/vtr/flow.py
M vtr_flow/scripts/python_libs/vtr/log_parse.py
M vtr_flow/scripts/python_libs/vtr/odin/odin.py
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py
M vtr_flow/scripts/python_libs/vtr/task.py
M vtr_flow/scripts/python_libs/vtr/util.py
M vtr_flow/scripts/run_vtr_flow.py
M vtr_flow/scripts/run_vtr_task.py
A vtr_flow/scripts/slurm/README.md
A vtr_flow/scripts/slurm/submission_template.sh
R vtr_flow/tasks/arithmetic_tasks/FIR_filters/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/FIR_filters_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/adder_trees/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/cmu_DFT/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/cmu_DFT_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/figure_8/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/multless_consts/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/open_cores/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/open_cores_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/table_X/config/config.txt
R vtr_flow/tasks/basic_flow/config/config.txt
R vtr_flow/tasks/basic_flow/config/golden_results.txt
R vtr_flow/tasks/checkin_reg/config/config.txt
R vtr_flow/tasks/checkin_reg/config/golden_results.txt
A vtr_flow/tasks/cmu_DFT/config/config.txt
A vtr_flow/tasks/cmu_DFT/config/golden_results.txt
A vtr_flow/tasks/cmu_DFT_frac/config/config.txt
A vtr_flow/tasks/cmu_DFT_frac/config/golden_results.txt
R vtr_flow/tasks/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/func_multiclock/once/config/config.txt
R vtr_flow/tasks/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/multiclock_mcnc/config/config.txt
M vtr_flow/tasks/power/power_frac_sweep/config/config.txt
A vtr_flow/tasks/power/power_frac_sweep/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac/config/config.txt
A vtr_flow/tasks/power/power_nofrac/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt
A vtr_flow/tasks/power/power_nofrac_130nm/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt
A vtr_flow/tasks/power/power_nofrac_22nm/config/golden_results.txt
M vtr_flow/tasks/power/power_quick/config/config.txt
A vtr_flow/tasks/power/power_quick/config/golden_results.txt
M vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt
A vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/golden_results.txt
M vtr_flow/tasks/power/power_std/config/config.txt
A vtr_flow/tasks/power/power_std/config/golden_results.txt
R vtr_flow/tasks/regression_bidir/config/config.txt
R vtr_flow/tasks/regression_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_fpu_hard_block_arch/config/config.txt
R vtr_flow/tasks/regression_fpu_hard_block_arch/config/golden_results.txt
R vtr_flow/tasks/regression_fpu_soft_logic_arch/config/config.txt
R vtr_flow/tasks/regression_fpu_soft_logic_arch/config/golden_results.txt
R vtr_flow/tasks/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/symbiflow/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/symbiflow/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/golden_results.txt
R vtr_flow/tasks/timing/config/config.txt
R vtr_flow/tasks/timing/config/golden_results.txt
R vtr_flow/tasks/timing_chain/config/config.txt
R vtr_flow/tasks/timing_chain/config/golden_results.txt
R vtr_flow/tasks/timing_small/config/config.txt
R vtr_flow/tasks/timing_small/config/golden_results.txt
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into vtr_new_routing
Commit: 5d3c43d18bb5ad223e1a28a772d387ee2df01a88
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d3c43d18bb5ad223e1a28a772d387ee2df01a88
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-22 (Tue, 22 Jun 2021)
Changed paths:
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/route/route_common.cpp
M vpr/test/test_connection_router.cpp
Log Message:
-----------
Added requested changes and fixed to pass all tests
Commit: 5021128e81b1804b83a2ad5f7ed027af55e6b2af
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5021128e81b1804b83a2ad5f7ed027af55e6b2af
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-22 (Tue, 22 Jun 2021)
Changed paths:
M vpr/src/base/place_and_route.cpp
Log Message:
-----------
Enhanced description of cfactor parameter
Commit: 5d8755a48f8a16d18da599c3d4960570be9699e1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d8755a48f8a16d18da599c3d4960570be9699e1
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
Log Message:
-----------
Implementation of RRGraphView::node_fan_in()
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 04c3d8aa5804d358d3c9c049beddc5e9c353f909
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/04c3d8aa5804d358d3c9c049beddc5e9c353f909
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-05 (Mon, 05 Jul 2021)
Changed paths:
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Add comment for attraction group gain in clusterer
Commit: d2c23495543d4c8239c23c7fdcddb6821929f379
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d2c23495543d4c8239c23c7fdcddb6821929f379
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-06 (Tue, 06 Jul 2021)
Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/prepack.cpp
M vpr/src/pack/prepack.h
Log Message:
-----------
Load attraction groups during prepacking
Commit: 181b2d028198c7fb992da15dffa86d8a3385057a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/181b2d028198c7fb992da15dffa86d8a3385057a
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/base/vpr_types.h
M vpr/src/device/rr_graph_obj.cpp
M vpr/src/device/rr_graph_obj.h
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/route/build_switchblocks.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/clock_network_builders.h
M vpr/src/route/overuse_report.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph_storage.cpp
M vpr/src/route/rr_graph_storage.h
M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h
M vpr/src/timing/VprTimingGraphResolver.cpp
Log Message:
-----------
Merge branch 'rr_graph_node_direction' into rr_graph_node_fan_in
Commit: 4e326d2b1b2bbc41d51d2ee922e2726fcc6af427
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4e326d2b1b2bbc41d51d2ee922e2726fcc6af427
Author: ethanroj23 <55202333+...@users.noreply.github.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into rr_graph_node_fan_in
Commit: 967d2575a999de204fb48f903208528fd9e73640
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/967d2575a999de204fb48f903208528fd9e73640
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Formatting changes
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: fa3f5244e7fe49527fbdf8c39af1d600536ef968
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fa3f5244e7fe49527fbdf8c39af1d600536ef968
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/power/power.cpp
Log Message:
-----------
Fixed a few Warnings due to variables not in use
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 18966b5fdbb9aa0f297bad3613aaba68c776c52a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/18966b5fdbb9aa0f297bad3613aaba68c776c52a
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Return highest gain molecule that also matches cluster's attraction group (if the cluster has one)
Commit: c0801630068dd971f97828f2bbff03041a21bb05
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c0801630068dd971f97828f2bbff03041a21bb05
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Added attraction gain to relevent atoms in update_total_gain during clustering
Commit: ad5421f1730fc96075351a80aa45b2f8cbc10a75
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ad5421f1730fc96075351a80aa45b2f8cbc10a75
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
Log Message:
-----------
Ran make format and added a routine to add cluster molecule candidates by attraction group
Commit: 56535988c31222ed1051f794d344a9420c00288f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56535988c31222ed1051f794d344a9420c00288f
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comment to routine for adding cluster molecule candidates by attraction group
Commit: 4fa0b627a2e3cfc3a894b2aedcac8f33f4dac48b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4fa0b627a2e3cfc3a894b2aedcac8f33f4dac48b
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-15 (Thu, 15 Jul 2021)
Changed paths:
M vpr/src/power/power.cpp
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Changed a few data types so that int casting could be removed.
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: e5b296438ceb742c7d1fdb81bd4255b09624f3d6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e5b296438ceb742c7d1fdb81bd4255b09624f3d6
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-15 (Thu, 15 Jul 2021)
Changed paths:
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Formatting fixes
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 36ac4387979c887df727ceda8f3a062e6f6d440b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/36ac4387979c887df727ceda8f3a062e6f6d440b
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
R .github/gha/install_dependencies.sh
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
Log Message:
-----------
ci: move scripts from '.github/gha' and '.github/travis' into '.github/scripts'
Commit: dc1ca82758d0b1496a3cbf87f4b78d6ca08ddc12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dc1ca82758d0b1496a3cbf87f4b78d6ca08ddc12
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
M .github/labeler.yml
M .github/scripts/build.sh
M .github/scripts/common.sh
M .github/scripts/cron_build.sh
M .github/scripts/unittest.sh
M .github/workflows/test.yml
M dev/check-format-py.sh
M dev/check-format.sh
Log Message:
-----------
ci: cleanup
Commit: 54402b0ef2bebbf43929cc13ec05066d2dff530a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/54402b0ef2bebbf43929cc13ec05066d2dff530a
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
M .github/scripts/install_dependencies.sh
M .github/workflows/test.yml
Log Message:
-----------
ci: install pip dependencies in 'install_dependencies.sh', cleanup accordingly
Commit: 9f6a3248a31c090bc36fc69ae8b8f733ad4b588e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9f6a3248a31c090bc36fc69ae8b8f733ad4b588e
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
M vpr/src/pack/prepack.h
Log Message:
-----------
Used attraction groups class constructor to create attraction groups instead of initializing them in another function. Also removed attraction groups from the clustering context, and instead passed them by reference where needed
Commit: 95cdf5604854192e5ce46e3539941f39b4e571cb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/95cdf5604854192e5ce46e3539941f39b4e571cb
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Added changes to attraction groups class - made some functions inline, made parameters const references where possible
Commit: 683a3a9f70ddf2e64c0e833d7107be0de7685207
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/683a3a9f70ddf2e64c0e833d7107be0de7685207
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Added comments to attraction groups class
Commit: f17da200e3f2aa238b5f7c84b98f1f5641eba120
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f17da200e3f2aa238b5f7c84b98f1f5641eba120
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Got rid of unnecssary variables such as has_attraction_group in t_pb_stats and the no attraction group sentinel value in the attraction groups class
Commit: 59afa1c4c528cc958f0d766b00d9a994d42d3dd6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/59afa1c4c528cc958f0d766b00d9a994d42d3dd6
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Made a couple of fixes to get rid of warnings about variables being used uninitialized
Commit: b6217bedc15692fe57506c8274cba07ca30638df
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b6217bedc15692fe57506c8274cba07ca30638df
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Refactored the functions that add cluster molecule candidates by moving repetitive code into a helper function
Commit: 1ae7dc31a9c5bd0197b6618fec2a20c33d5873fb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1ae7dc31a9c5bd0197b6618fec2a20c33d5873fb
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Removed an unused variable to fix compiler warning
Commit: aacd4a885cced2b76cdcd5804fbb9808c5010cf2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aacd4a885cced2b76cdcd5804fbb9808c5010cf2
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
Log Message:
-----------
fixing typos in task_list and adding to CI
Commit: 06e15bec76f4a084dd156ab8e8413bc8fa433fc1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/06e15bec76f4a084dd156ab8e8413bc8fa433fc1
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
Log Message:
-----------
adding regression_mcnc to CI
Commit: 46970ef99f9ceebb3c4ce62a202feab0ed72f300
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/46970ef99f9ceebb3c4ce62a202feab0ed72f300
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
Log Message:
-----------
adding qor_parser file to regression_mcnc config
Commit: f262a978376a000e6a172b3cc1f815e4e4454ce1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f262a978376a000e6a172b3cc1f815e4e4454ce1
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-26 (Mon, 26 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comments to clarify attraction groups-related code
Commit: 4dc0fe43aa3356c6e7c54ad92ee386821614fa6f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4dc0fe43aa3356c6e7c54ad92ee386821614fa6f
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-26 (Mon, 26 Jul 2021)
Changed paths:
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_types.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/pack.cpp
Log Message:
-----------
Added command line option to turn attraction groups on or off
Commit: 926f64980927082591686d43f9b1a47c7b68cc28
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/926f64980927082591686d43f9b1a47c7b68cc28
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
Log Message:
-----------
Adding README.md's and comments
Commit: d82d908f245c28fd9e7a53c2aabb875d767ac718
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d82d908f245c28fd9e7a53c2aabb875d767ac718
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
Log Message:
-----------
Adding README.md's and comments (fixing previous commit)
Commit: 02a76968c48e19527e2a96fd2fc0147f3f570464
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/02a76968c48e19527e2a96fd2fc0147f3f570464
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
Log Message:
-----------
Renaming regression_mcnc in task_list.txt
Commit: aef1ad0fad6b553342073d87a3769b7d6d7dbeec
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aef1ad0fad6b553342073d87a3769b7d6d7dbeec
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/golden_results.txt
Log Message:
-----------
fixing folder name for vpr_reg_mcnc_equiv
Commit: 339142705224c49d0292dd25d414e76ce0ad37e0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/339142705224c49d0292dd25d414e76ce0ad37e0
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
Log Message:
-----------
moving func_multiclock
Commit: a5f4b39ce4a32f043f9c6ae338db64f3e5aa22f0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a5f4b39ce4a32f043f9c6ae338db64f3e5aa22f0
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
Log Message:
-----------
removing func_multiclock from suite
Commit: c928ade556522b897b82f9cdb0b0703c075db1b7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c928ade556522b897b82f9cdb0b0703c075db1b7
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
Log Message:
-----------
Added comment to attraction groups constructor to explain how it will differ based on packer option
Commit: 9033cfb4c97ac52ba45cdb1612e5a59ea168beea
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9033cfb4c97ac52ba45cdb1612e5a59ea168beea
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Added sanitizer suppression file info, and mention of valgrind.
Commit: 364a22f6165338c9e9f477766ef152f1eb32b881
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/364a22f6165338c9e9f477766ef152f1eb32b881
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Added a bit more info to the valgrind and sanitizers.
Commit: 31fa0fed161d59bd4484339f0d4d327be2b884fc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31fa0fed161d59bd4484339f0d4d327be2b884fc
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
Log Message:
-----------
[Odin]: verify_odin fails if run_vtr_reg failed
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 5013c76dfee2b577b0948e3e319bcb55ef2d9fb0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5013c76dfee2b577b0948e3e319bcb55ef2d9fb0
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Small wording changes to valgrind/sanitizers.
Commit: fbb933722206d969d726d4463ed5b1f8c30c5e7c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fbb933722206d969d726d4463ed5b1f8c30c5e7c
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Changed attraction group default gain
Commit: ba2ef9bb81aaf7eaa9275d8bf44534c552633d12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ba2ef9bb81aaf7eaa9275d8bf44534c552633d12
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
Log Message:
-----------
temporarily updating golden_results with 14x actual values for vpr_max_mem due Issue#1808
Commit: 070651bbd8243cff02f4e392286b4e1bb13bb6cf
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/070651bbd8243cff02f4e392286b4e1bb13bb6cf
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
Log Message:
-----------
Merge branch 'Issue1806' of https://github.com/ArashAhmadian/vtr-verilog-to-routing into Issue1806
Commit: 3206d439ba961a48aa29e1f8b701f63045ff8eeb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3206d439ba961a48aa29e1f8b701f63045ff8eeb
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/regression_test/parse_result/parse_result.py
Log Message:
-----------
[Odin]: show expected failure status in verify odin script
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 66e4f83538c64771503655c8ec6f1bb7798d2f59
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/66e4f83538c64771503655c8ec6f1bb7798d2f59
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
Log Message:
-----------
Adjusted a comment in rr_graph_view.h
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: f536a13e88b5d81dac2fe868bd0d687e015e85e6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f536a13e88b5d81dac2fe868bd0d687e015e85e6
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Merge pull request #1809 from verilog-to-routing/vaughnbetz-valgrind-sanitizer_doc
Update README.developers.md : Added sanitizer suppression file info, and mention of valgrind.
Commit: 966d0e13e2c2d43023a2bbc56f6f4470736533d4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/966d0e13e2c2d43023a2bbc56f6f4470736533d4
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/regression_test/parse_result/parse_result.py
Log Message:
-----------
Merge pull request #1810 from verilog-to-routing/odin_verification_script
[Odin]: show expected failure status in verify odin script
Commit: 07127de99bcdc41ade184ec897b54c20a592beee
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/07127de99bcdc41ade184ec897b54c20a592beee
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comments for functions related to adding cluster molecule candidates
Commit: e0c16b6272597d6689c26f854487288fbe2ba193
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e0c16b6272597d6689c26f854487288fbe2ba193
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
Log Message:
-----------
Merge pull request #1799 from ethanroj23/rr_graph_node_fan_in
RRGraphView::node_fan_in() Implementation
Commit: b05b77c22b72a1fb275091288788cc066cb8d5df
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b05b77c22b72a1fb275091288788cc066cb8d5df
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
Log Message:
-----------
Merge pull request #1807 from ArashAhmadian/Issue1806
Adding regression_mcnc & vtr_reg_multiclock to CI
Commit: c43fdbcacad7c2104c427217f823644f31954cee
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c43fdbcacad7c2104c427217f823644f31954cee
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
R .github/gha/install_dependencies.sh
M .github/labeler.yml
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
M dev/check-format-py.sh
M dev/check-format.sh
Log Message:
-----------
Merge pull request #1804 from umarcor/ci-scripts
ci: move scripts from '.github/gha' and '.github/travis' into '.github/scripts'
Commit: 8d5eda91927039071aff956bd47fdc6ed98669dc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d5eda91927039071aff956bd47fdc6ed98669dc
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
Log Message:
-----------
[Odin]: fix arch name type for mixing optimization tasks in Odin regtest
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: c4279ddec361b5e308dd4179fb94fe2634e82942
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c4279ddec361b5e308dd4179fb94fe2634e82942
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/vpr_api.cpp
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/route/route_common.cpp
M vpr/test/test_connection_router.cpp
Log Message:
-----------
Merge pull request #1786 from byuccl/vtr_new_routing
Added the ability to perform detailed routing with different channel widths
Commit: 110bae4ae127ed1a67fcf6c1b38f8a6ff9e24e46
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/110bae4ae127ed1a67fcf6c1b38f8a6ff9e24e46
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_types.h
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
Log Message:
-----------
Merge pull request #1802 from verilog-to-routing/cluster_attraction_groups
Cluster attraction groups
Commit: 9ad12216889f2f0e0d4e7518b43a5d4b11948550
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ad12216889f2f0e0d4e7518b43a5d4b11948550
Author: Steve Kelly <kd2...@gmail.com>
Date: 2021-07-31 (Sat, 31 Jul 2021)
Changed paths:
M dev/nix/shell.nix
Log Message:
-----------
[nix] drop python 2.7
Commit: 79e784dbcbb1f994fba1059d4b132de51d86136a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/79e784dbcbb1f994fba1059d4b132de51d86136a
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-08-04 (Wed, 04 Aug 2021)
Changed paths:
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
fixing regex issue with fixed_chan_width parse file
Commit: 66f547892f9065c6911f1e91f97350a17cf1d2ce
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/66f547892f9065c6911f1e91f97350a17cf1d2ce
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-08-05 (Thu, 05 Aug 2021)
Changed paths:
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
[Infra]: fix run_vtr_task lint error
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 5e59252522f8f2431bcd558c878042d2b906a568
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5e59252522f8f2431bcd558c878042d2b906a568
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-08-05 (Thu, 05 Aug 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
Log Message:
-----------
updating golden_results for titan tests
Commit: 2e0bafe202e3f8cb4e1f099002f7272f4705068d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2e0bafe202e3f8cb4e1f099002f7272f4705068d
Author: Tim Ansell <m...@mith.ro>
Date: 2021-08-08 (Sun, 08 Aug 2021)
Changed paths:
M dev/nix/shell.nix
Log Message:
-----------
Merge pull request #1793 from sjkelly/sjk/nixpin1
[nix] drop python 2.7
Commit: dd7fd42f9e0ed8c78f4ff50768a70cb8a93ef1ab
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dd7fd42f9e0ed8c78f4ff50768a70cb8a93ef1ab
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
Merge pull request #1821 from verilog-to-routing/run_task_lint
[Infra]: fix run_vtr_task lint error
Commit: 223e8b607b3653e44770c1ce6c6186e02bfebb30
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/223e8b607b3653e44770c1ce6c6186e02bfebb30
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M dev/nix/shell.nix
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into fixed_chan_width_bug
Commit: 8b2d0ed106d17933b760ecb33a9e5bddac964e84
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8b2d0ed106d17933b760ecb33a9e5bddac964e84
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
Log Message:
-----------
Merge pull request #1812 from verilog-to-routing/mixing_optimization_typo
[Odin]: fix arch name type for mixing optimization tasks in Odin regtest
Commit: 06317d042ba3c0c2dea3680a1b55d61279d34a35
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/06317d042ba3c0c2dea3680a1b55d61279d34a35
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
Merge pull request #1820 from ArashAhmadian/fixed_chan_width_bug
fixing regex issue with fixed_chan_width parse file
Commit: 8d7bafddf426a44f9c628acc56e017bd72a95818
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d7bafddf426a44f9c628acc56e017bd72a95818
Author: Paula <perd...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2021-08-13 (Fri, 13 Aug 2021)
Changed paths:
R .github/gha/install_dependencies.sh
M .github/labeler.yml
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
M ODIN_II/regression_test/parse_result/parse_result.py
M ODIN_II/verify_odin.sh
M README.developers.md
M dev/check-format-py.sh
M dev/check-format.sh
M dev/nix/shell.nix
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_types.h
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
M vpr/test/test_connection_router.cpp
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/scripts/run_vtr_task.py
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
Merge branch 'master' into manual_moves
Commit: df73c467b943a78d6dde1642074f01f1ba85c344
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/df73c467b943a78d6dde1642074f01f1ba85c344
Author: Paula <perd...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2021-08-16 (Mon, 16 Aug 2021)
Changed paths:
M vpr/src/place/manual_move_generator.cpp
M vpr/src/place/place.cpp
Log Message:
-----------
Changed placement of manual move move type in place.cpp, in case the user selects manual move accidentally
Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/d421ed7a0af5...df73c467b943
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: 62279ec3855172b75f7e1b0a57f3e9de0efddc71
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/62279ec3855172b75f7e1b0a57f3e9de0efddc71
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M doc/src/arch/reference.rst
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
Log Message:
-----------
Modified detailed routing to support different channel widths
Commit: 0129d821c1f75977bda39b08dc2997ea2745822a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0129d821c1f75977bda39b08dc2997ea2745822a
Author: Brandon Heiner <77360779...@users.noreply.github.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M .github/gha/install_dependencies.sh
M .github/kokoro/continuous/nightly.cfg
A .github/kokoro/continuous/odin_strong.cfg
M .github/kokoro/continuous/strong.cfg
M .github/kokoro/continuous/strong_sanitized.cfg
M .github/kokoro/continuous/weekly.cfg
R .github/kokoro/presubmit/nightly.cfg
A .github/kokoro/presubmit/nightly_test1.cfg
A .github/kokoro/presubmit/nightly_test2.cfg
A .github/kokoro/presubmit/nightly_test3.cfg
A .github/kokoro/presubmit/nightly_test4.cfg
A .github/kokoro/presubmit/odin_strong.cfg
M .github/kokoro/run-vtr.sh
M .github/kokoro/steps/vtr-full-setup.sh
M .github/kokoro/steps/vtr-test.sh
M .github/travis/build.sh
R .github/travis/setup.sh
M .github/workflows/test.yml
A .gitpod.Dockerfile
A .gitpod.yml
M BUILDING.md
M Dockerfile
M Makefile
M ODIN_II/CMakeLists.txt
M ODIN_II/SRC/ast_elaborate.cpp
M ODIN_II/SRC/include/odin_error.h
M ODIN_II/SRC/netlist_create_from_ast.cpp
M ODIN_II/SRC/odin_error.cpp
M ODIN_II/SRC/subtractions.cpp
M ODIN_II/regression_test/benchmark/suite/heavy_suite/task_list.conf
M ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf
A ODIN_II/regression_test/benchmark/suite/vtr_multiclock_suite/task_list.conf
A ODIN_II/regression_test/benchmark/task/koios/synthesis_result.json
A ODIN_II/regression_test/benchmark/task/koios/task.conf
M ODIN_II/regression_test/benchmark/task/large/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports.v
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports_input
A ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports_output
M ODIN_II/verify_odin.sh
M README.developers.md
M README.md
M blifexplorer/CMakeLists.txt
M dev/pylint_check.py
M dev/upgrade_vtr_archs.sh
M doc/src/api/vpr/netlist.rst
M doc/src/arch/reference.rst
M doc/src/tutorials/arch/fracturable_multiplier_bus.rst
M doc/src/tutorials/flow/basic_flow.rst
M doc/src/vpr/debug_aids.rst
M doc/src/vtr/benchmarks.rst
M doc/src/vtr/tasks.rst
M doc/src/z_references.bib
M libs/EXTERNAL/libargparse/src/argparse.cpp
M libs/EXTERNAL/libblifparse/CMakeLists.txt
M libs/EXTERNAL/libsdcparse/CMakeLists.txt
M libs/libarchfpga/CMakeLists.txt
M libs/liblog/CMakeLists.txt
M libs/librtlnumber/src/include/internal_bits.hpp
M libs/libvtrcapnproto/CMakeLists.txt
M libs/libvtrutil/src/vtr_memory.h
M libs/libvtrutil/src/vtr_vector_map.h
M requirements.txt
M run_reg_test.py
M utils/fasm/CMakeLists.txt
M utils/fasm/src/main.cpp
M utils/fasm/test/test_fasm.cpp
M utils/fasm/test/test_fasm_arch.xml
M utils/route_diag/CMakeLists.txt
M utils/route_diag/src/main.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/SetupVPR.h
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist_utils.cpp
M vpr/src/base/clustered_netlist_utils.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_route.cpp
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/stats.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints_serializer.h
A vpr/src/base/vpr_constraints_writer.cpp
A vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
A vpr/src/device/rr_graph_builder.cpp
A vpr/src/device/rr_graph_builder.h
A vpr/src/device/rr_graph_view.cpp
A vpr/src/device/rr_graph_view.h
A vpr/src/device/rr_spatial_lookup.cpp
A vpr/src/device/rr_spatial_lookup.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/search_bar.cpp
M vpr/src/pack/cluster.cpp
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/critical_uniform_move_generator.cpp
M vpr/src/place/feasible_region_move_generator.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_transactions.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/uniform_move_generator.cpp
M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp
M vpr/src/power/power.cpp
M vpr/src/route/annotate_routing.cpp
M vpr/src/route/check_route.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/overuse_report.cpp
M vpr/src/route/route_breadth_first.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h
M vpr/src/route/route_timing.cpp
M vpr/src/route/route_tree_timing.cpp
M vpr/src/route/route_util.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_sampling.cpp
A vpr/src/route/rr_edge.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph2.h
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_graph_indexed_data.cpp
M vpr/src/route/rr_graph_reader.cpp
M vpr/src/route/rr_graph_storage.h
M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_util.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_graph_writer.cpp
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
M vpr/src/route/segment_stats.cpp
M vpr/src/timing/VprTimingGraphResolver.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.denser.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.densest.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml
A vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fixed_size/fixed_nointerclb_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2ripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_2uripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_ripple_N8_22nm.xml
M vtr_flow/arch/timing/fraclut_carrychain/k6_frac_uripple_N8_22nm.xml
M vtr_flow/arch/timing/k6_N10_mem32K_40nm.xml
M vtr_flow/benchmarks/arithmetic/FIR_filters/verilog/generate_fir.c++
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_10.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_11.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_14.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_19.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_23.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_27.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_29.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_33.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_34.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_35.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_36.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_40.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_42.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_44.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_45.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_46.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_48.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_49.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_50.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_10.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_11.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_13.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_14.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_15.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_16.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_18.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_22.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_23.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_24.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_25.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_26.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_27.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_29.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_32.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_33.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_34.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_36.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_37.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_39.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_40.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_42.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_44.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_45.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_47.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_48.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_52.v
M vtr_flow/benchmarks/arithmetic/generated_circuits/cmu_DFT/verilog/64-16bit-fixed-JACM.v
R vtr_flow/benchmarks/blif/multiclock/cascading_ff.blif
R vtr_flow/benchmarks/blif/multiclock/iir1.blif
R vtr_flow/benchmarks/blif/multiclock/multi_clock_reader_writer.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_output_and_latch.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_reader_writer.blif
R vtr_flow/benchmarks/blif/multiclock/multiclock_separate_and_latch.blif
R vtr_flow/benchmarks/blif/multiclock/simple_multiclock.blif
R vtr_flow/benchmarks/blif/multiclock/stereovision3.blif
R vtr_flow/benchmarks/blif/multiclock/sv_chip3_hierarchy_no_mem.blif
A vtr_flow/benchmarks/hdl_include/ch_intrinsics_modified.v
A vtr_flow/benchmarks/hdl_include/include/README.md
A vtr_flow/benchmarks/hdl_include/include/generic_definitions1.vh
A vtr_flow/benchmarks/hdl_include/include/generic_definitions2.vh
A vtr_flow/benchmarks/hdl_include/include/memory_controller.v
M vtr_flow/benchmarks/titan_blif/README.rst
M vtr_flow/benchmarks/titan_other_blif/README.rst
A vtr_flow/benchmarks/verilog/koios/README.md
A vtr_flow/benchmarks/verilog/koios/attention_layer.v
A vtr_flow/benchmarks/verilog/koios/bnn.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.large.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.medium.v
A vtr_flow/benchmarks/verilog/koios/clstm_like.small.v
A vtr_flow/benchmarks/verilog/koios/conv_layer.v
A vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v
A vtr_flow/benchmarks/verilog/koios/dla_like.medium.v
A vtr_flow/benchmarks/verilog/koios/dla_like.small.v
A vtr_flow/benchmarks/verilog/koios/eltwise_layer.v
A vtr_flow/benchmarks/verilog/koios/gemm_layer.v
A vtr_flow/benchmarks/verilog/koios/lstm.v
A vtr_flow/benchmarks/verilog/koios/reduction_layer.v
A vtr_flow/benchmarks/verilog/koios/robot_rl.v
A vtr_flow/benchmarks/verilog/koios/softmax.v
A vtr_flow/benchmarks/verilog/koios/spmv.v
A vtr_flow/benchmarks/verilog/koios/test.v
A vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.medium.v
A vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.small.v
R vtr_flow/benchmarks/verilog/matmul_8x8_fp16.v
M vtr_flow/benchmarks/verilog/raygentop.v
R vtr_flow/benchmarks/verilog/tpu.16x16.int8.v
R vtr_flow/benchmarks/verilog/tpu.32x32.int8.v
M vtr_flow/primitives.v
M vtr_flow/scripts/flow_script_template.txt
M vtr_flow/scripts/python_libs/vtr/flow.py
M vtr_flow/scripts/python_libs/vtr/log_parse.py
M vtr_flow/scripts/python_libs/vtr/odin/odin.py
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py
M vtr_flow/scripts/python_libs/vtr/task.py
M vtr_flow/scripts/python_libs/vtr/util.py
M vtr_flow/scripts/run_vtr_flow.py
M vtr_flow/scripts/run_vtr_task.py
A vtr_flow/scripts/slurm/README.md
A vtr_flow/scripts/slurm/submission_template.sh
R vtr_flow/tasks/arithmetic_tasks/FIR_filters/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/FIR_filters_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/adder_trees/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/cmu_DFT/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/cmu_DFT_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/figure_8/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/multless_consts/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/open_cores/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/open_cores_frac/config/config.txt
R vtr_flow/tasks/arithmetic_tasks/table_X/config/config.txt
R vtr_flow/tasks/basic_flow/config/config.txt
R vtr_flow/tasks/basic_flow/config/golden_results.txt
R vtr_flow/tasks/checkin_reg/config/config.txt
R vtr_flow/tasks/checkin_reg/config/golden_results.txt
A vtr_flow/tasks/cmu_DFT/config/config.txt
A vtr_flow/tasks/cmu_DFT/config/golden_results.txt
A vtr_flow/tasks/cmu_DFT_frac/config/config.txt
A vtr_flow/tasks/cmu_DFT_frac/config/golden_results.txt
R vtr_flow/tasks/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/func_multiclock/once/config/config.txt
R vtr_flow/tasks/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/multiclock_mcnc/config/config.txt
M vtr_flow/tasks/power/power_frac_sweep/config/config.txt
A vtr_flow/tasks/power/power_frac_sweep/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac/config/config.txt
A vtr_flow/tasks/power/power_nofrac/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac_130nm/config/config.txt
A vtr_flow/tasks/power/power_nofrac_130nm/config/golden_results.txt
M vtr_flow/tasks/power/power_nofrac_22nm/config/config.txt
A vtr_flow/tasks/power/power_nofrac_22nm/config/golden_results.txt
M vtr_flow/tasks/power/power_quick/config/config.txt
A vtr_flow/tasks/power/power_quick/config/golden_results.txt
M vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/config.txt
A vtr_flow/tasks/power/power_sparse_crossbar_sweep/config/golden_results.txt
M vtr_flow/tasks/power/power_std/config/config.txt
A vtr_flow/tasks/power/power_std/config/golden_results.txt
R vtr_flow/tasks/regression_bidir/config/config.txt
R vtr_flow/tasks/regression_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_fpu_hard_block_arch/config/config.txt
R vtr_flow/tasks/regression_fpu_hard_block_arch/config/golden_results.txt
R vtr_flow/tasks/regression_fpu_soft_logic_arch/config/config.txt
R vtr_flow/tasks/regression_fpu_soft_logic_arch/config/golden_results.txt
R vtr_flow/tasks/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/symbiflow/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_bidir/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_coffe/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_depop/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain_large/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/symbiflow/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_error_check/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_func_formal/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_netlist_writer/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/complex_switch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_large/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/config/golden_results.txt
R vtr_flow/tasks/timing/config/config.txt
R vtr_flow/tasks/timing/config/golden_results.txt
R vtr_flow/tasks/timing_chain/config/config.txt
R vtr_flow/tasks/timing_chain/config/golden_results.txt
R vtr_flow/tasks/timing_small/config/config.txt
R vtr_flow/tasks/timing_small/config/golden_results.txt
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into vtr_new_routing
Commit: 5d3c43d18bb5ad223e1a28a772d387ee2df01a88
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d3c43d18bb5ad223e1a28a772d387ee2df01a88
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-22 (Tue, 22 Jun 2021)
Changed paths:
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/route/route_common.cpp
M vpr/test/test_connection_router.cpp
Log Message:
-----------
Added requested changes and fixed to pass all tests
Commit: 5021128e81b1804b83a2ad5f7ed027af55e6b2af
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5021128e81b1804b83a2ad5f7ed027af55e6b2af
Author: Brandon Heiner <hein...@byu.edu>
Date: 2021-06-22 (Tue, 22 Jun 2021)
Changed paths:
M vpr/src/base/place_and_route.cpp
Log Message:
-----------
Enhanced description of cfactor parameter
Commit: 5d8755a48f8a16d18da599c3d4960570be9699e1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d8755a48f8a16d18da599c3d4960570be9699e1
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-06-29 (Tue, 29 Jun 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
Log Message:
-----------
Implementation of RRGraphView::node_fan_in()
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 04c3d8aa5804d358d3c9c049beddc5e9c353f909
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/04c3d8aa5804d358d3c9c049beddc5e9c353f909
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-05 (Mon, 05 Jul 2021)
Changed paths:
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Add comment for attraction group gain in clusterer
Commit: d2c23495543d4c8239c23c7fdcddb6821929f379
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d2c23495543d4c8239c23c7fdcddb6821929f379
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-06 (Tue, 06 Jul 2021)
Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/prepack.cpp
M vpr/src/pack/prepack.h
Log Message:
-----------
Load attraction groups during prepacking
Commit: 181b2d028198c7fb992da15dffa86d8a3385057a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/181b2d028198c7fb992da15dffa86d8a3385057a
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/base/vpr_types.h
M vpr/src/device/rr_graph_obj.cpp
M vpr/src/device/rr_graph_obj.h
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/route/build_switchblocks.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/clock_network_builders.h
M vpr/src/route/overuse_report.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph_storage.cpp
M vpr/src/route/rr_graph_storage.h
M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h
M vpr/src/timing/VprTimingGraphResolver.cpp
Log Message:
-----------
Merge branch 'rr_graph_node_direction' into rr_graph_node_fan_in
Commit: 4e326d2b1b2bbc41d51d2ee922e2726fcc6af427
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4e326d2b1b2bbc41d51d2ee922e2726fcc6af427
Author: ethanroj23 <55202333+...@users.noreply.github.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into rr_graph_node_fan_in
Commit: 967d2575a999de204fb48f903208528fd9e73640
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/967d2575a999de204fb48f903208528fd9e73640
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Formatting changes
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: fa3f5244e7fe49527fbdf8c39af1d600536ef968
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fa3f5244e7fe49527fbdf8c39af1d600536ef968
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-12 (Mon, 12 Jul 2021)
Changed paths:
M vpr/src/power/power.cpp
Log Message:
-----------
Fixed a few Warnings due to variables not in use
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 18966b5fdbb9aa0f297bad3613aaba68c776c52a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/18966b5fdbb9aa0f297bad3613aaba68c776c52a
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Return highest gain molecule that also matches cluster's attraction group (if the cluster has one)
Commit: c0801630068dd971f97828f2bbff03041a21bb05
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c0801630068dd971f97828f2bbff03041a21bb05
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Added attraction gain to relevent atoms in update_total_gain during clustering
Commit: ad5421f1730fc96075351a80aa45b2f8cbc10a75
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ad5421f1730fc96075351a80aa45b2f8cbc10a75
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
Log Message:
-----------
Ran make format and added a routine to add cluster molecule candidates by attraction group
Commit: 56535988c31222ed1051f794d344a9420c00288f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56535988c31222ed1051f794d344a9420c00288f
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-14 (Wed, 14 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comment to routine for adding cluster molecule candidates by attraction group
Commit: 4fa0b627a2e3cfc3a894b2aedcac8f33f4dac48b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4fa0b627a2e3cfc3a894b2aedcac8f33f4dac48b
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-15 (Thu, 15 Jul 2021)
Changed paths:
M vpr/src/power/power.cpp
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Changed a few data types so that int casting could be removed.
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: e5b296438ceb742c7d1fdb81bd4255b09624f3d6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e5b296438ceb742c7d1fdb81bd4255b09624f3d6
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-15 (Thu, 15 Jul 2021)
Changed paths:
M vpr/src/route/rr_graph.cpp
Log Message:
-----------
Formatting fixes
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: 36ac4387979c887df727ceda8f3a062e6f6d440b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/36ac4387979c887df727ceda8f3a062e6f6d440b
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
R .github/gha/install_dependencies.sh
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
Log Message:
-----------
ci: move scripts from '.github/gha' and '.github/travis' into '.github/scripts'
Commit: dc1ca82758d0b1496a3cbf87f4b78d6ca08ddc12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dc1ca82758d0b1496a3cbf87f4b78d6ca08ddc12
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
M .github/labeler.yml
M .github/scripts/build.sh
M .github/scripts/common.sh
M .github/scripts/cron_build.sh
M .github/scripts/unittest.sh
M .github/workflows/test.yml
M dev/check-format-py.sh
M dev/check-format.sh
Log Message:
-----------
ci: cleanup
Commit: 54402b0ef2bebbf43929cc13ec05066d2dff530a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/54402b0ef2bebbf43929cc13ec05066d2dff530a
Author: umarcor <unai.mart...@ehu.eus>
Date: 2021-07-18 (Sun, 18 Jul 2021)
Changed paths:
M .github/scripts/install_dependencies.sh
M .github/workflows/test.yml
Log Message:
-----------
ci: install pip dependencies in 'install_dependencies.sh', cleanup accordingly
Commit: 9f6a3248a31c090bc36fc69ae8b8f733ad4b588e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9f6a3248a31c090bc36fc69ae8b8f733ad4b588e
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
M vpr/src/pack/prepack.h
Log Message:
-----------
Used attraction groups class constructor to create attraction groups instead of initializing them in another function. Also removed attraction groups from the clustering context, and instead passed them by reference where needed
Commit: 95cdf5604854192e5ce46e3539941f39b4e571cb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/95cdf5604854192e5ce46e3539941f39b4e571cb
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Added changes to attraction groups class - made some functions inline, made parameters const references where possible
Commit: 683a3a9f70ddf2e64c0e833d7107be0de7685207
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/683a3a9f70ddf2e64c0e833d7107be0de7685207
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Added comments to attraction groups class
Commit: f17da200e3f2aa238b5f7c84b98f1f5641eba120
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f17da200e3f2aa238b5f7c84b98f1f5641eba120
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/pack_types.h
Log Message:
-----------
Got rid of unnecssary variables such as has_attraction_group in t_pb_stats and the no attraction group sentinel value in the attraction groups class
Commit: 59afa1c4c528cc958f0d766b00d9a994d42d3dd6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/59afa1c4c528cc958f0d766b00d9a994d42d3dd6
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Made a couple of fixes to get rid of warnings about variables being used uninitialized
Commit: b6217bedc15692fe57506c8274cba07ca30638df
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b6217bedc15692fe57506c8274cba07ca30638df
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Refactored the functions that add cluster molecule candidates by moving repetitive code into a helper function
Commit: 1ae7dc31a9c5bd0197b6618fec2a20c33d5873fb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1ae7dc31a9c5bd0197b6618fec2a20c33d5873fb
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-21 (Wed, 21 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Removed an unused variable to fix compiler warning
Commit: aacd4a885cced2b76cdcd5804fbb9808c5010cf2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aacd4a885cced2b76cdcd5804fbb9808c5010cf2
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
Log Message:
-----------
fixing typos in task_list and adding to CI
Commit: 06e15bec76f4a084dd156ab8e8413bc8fa433fc1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/06e15bec76f4a084dd156ab8e8413bc8fa433fc1
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
Log Message:
-----------
adding regression_mcnc to CI
Commit: 46970ef99f9ceebb3c4ce62a202feab0ed72f300
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/46970ef99f9ceebb3c4ce62a202feab0ed72f300
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-22 (Thu, 22 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
Log Message:
-----------
adding qor_parser file to regression_mcnc config
Commit: f262a978376a000e6a172b3cc1f815e4e4454ce1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f262a978376a000e6a172b3cc1f815e4e4454ce1
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-26 (Mon, 26 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comments to clarify attraction groups-related code
Commit: 4dc0fe43aa3356c6e7c54ad92ee386821614fa6f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4dc0fe43aa3356c6e7c54ad92ee386821614fa6f
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-26 (Mon, 26 Jul 2021)
Changed paths:
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_types.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/pack.cpp
Log Message:
-----------
Added command line option to turn attraction groups on or off
Commit: 926f64980927082591686d43f9b1a47c7b68cc28
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/926f64980927082591686d43f9b1a47c7b68cc28
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
Log Message:
-----------
Adding README.md's and comments
Commit: d82d908f245c28fd9e7a53c2aabb875d767ac718
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d82d908f245c28fd9e7a53c2aabb875d767ac718
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
Log Message:
-----------
Adding README.md's and comments (fixing previous commit)
Commit: 02a76968c48e19527e2a96fd2fc0147f3f570464
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/02a76968c48e19527e2a96fd2fc0147f3f570464
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
Log Message:
-----------
Renaming regression_mcnc in task_list.txt
Commit: aef1ad0fad6b553342073d87a3769b7d6d7dbeec
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aef1ad0fad6b553342073d87a3769b7d6d7dbeec
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_mcnc_equiv/config/golden_results.txt
Log Message:
-----------
fixing folder name for vpr_reg_mcnc_equiv
Commit: 339142705224c49d0292dd25d414e76ce0ad37e0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/339142705224c49d0292dd25d414e76ce0ad37e0
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
Log Message:
-----------
moving func_multiclock
Commit: a5f4b39ce4a32f043f9c6ae338db64f3e5aa22f0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a5f4b39ce4a32f043f9c6ae338db64f3e5aa22f0
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/README.md
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
Log Message:
-----------
removing func_multiclock from suite
Commit: c928ade556522b897b82f9cdb0b0703c075db1b7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c928ade556522b897b82f9cdb0b0703c075db1b7
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.cpp
Log Message:
-----------
Added comment to attraction groups constructor to explain how it will differ based on packer option
Commit: 9033cfb4c97ac52ba45cdb1612e5a59ea168beea
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9033cfb4c97ac52ba45cdb1612e5a59ea168beea
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Added sanitizer suppression file info, and mention of valgrind.
Commit: 364a22f6165338c9e9f477766ef152f1eb32b881
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/364a22f6165338c9e9f477766ef152f1eb32b881
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-28 (Wed, 28 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Added a bit more info to the valgrind and sanitizers.
Commit: 31fa0fed161d59bd4484339f0d4d327be2b884fc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31fa0fed161d59bd4484339f0d4d327be2b884fc
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
Log Message:
-----------
[Odin]: verify_odin fails if run_vtr_reg failed
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 5013c76dfee2b577b0948e3e319bcb55ef2d9fb0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5013c76dfee2b577b0948e3e319bcb55ef2d9fb0
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Update README.developers.md
Small wording changes to valgrind/sanitizers.
Commit: fbb933722206d969d726d4463ed5b1f8c30c5e7c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fbb933722206d969d726d4463ed5b1f8c30c5e7c
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vpr/src/pack/attraction_groups.h
Log Message:
-----------
Changed attraction group default gain
Commit: ba2ef9bb81aaf7eaa9275d8bf44534c552633d12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ba2ef9bb81aaf7eaa9275d8bf44534c552633d12
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
Log Message:
-----------
temporarily updating golden_results with 14x actual values for vpr_max_mem due Issue#1808
Commit: 070651bbd8243cff02f4e392286b4e1bb13bb6cf
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/070651bbd8243cff02f4e392286b4e1bb13bb6cf
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
Log Message:
-----------
Merge branch 'Issue1806' of https://github.com/ArashAhmadian/vtr-verilog-to-routing into Issue1806
Commit: 3206d439ba961a48aa29e1f8b701f63045ff8eeb
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3206d439ba961a48aa29e1f8b701f63045ff8eeb
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/regression_test/parse_result/parse_result.py
Log Message:
-----------
[Odin]: show expected failure status in verify odin script
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 66e4f83538c64771503655c8ec6f1bb7798d2f59
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/66e4f83538c64771503655c8ec6f1bb7798d2f59
Author: Ethan Rogers <ethanro...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
Log Message:
-----------
Adjusted a comment in rr_graph_view.h
Signed-off-by: Ethan Rogers <ethanro...@gmail.com>
Commit: f536a13e88b5d81dac2fe868bd0d687e015e85e6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f536a13e88b5d81dac2fe868bd0d687e015e85e6
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M README.developers.md
Log Message:
-----------
Merge pull request #1809 from verilog-to-routing/vaughnbetz-valgrind-sanitizer_doc
Update README.developers.md : Added sanitizer suppression file info, and mention of valgrind.
Commit: 966d0e13e2c2d43023a2bbc56f6f4470736533d4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/966d0e13e2c2d43023a2bbc56f6f4470736533d4
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-29 (Thu, 29 Jul 2021)
Changed paths:
M ODIN_II/regression_test/parse_result/parse_result.py
Log Message:
-----------
Merge pull request #1810 from verilog-to-routing/odin_verification_script
[Odin]: show expected failure status in verify odin script
Commit: 07127de99bcdc41ade184ec897b54c20a592beee
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/07127de99bcdc41ade184ec897b54c20a592beee
Author: Sarah Khalid <srhkh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/pack/cluster.cpp
Log Message:
-----------
Added comments for functions related to adding cluster molecule candidates
Commit: e0c16b6272597d6689c26f854487288fbe2ba193
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e0c16b6272597d6689c26f854487288fbe2ba193
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
Log Message:
-----------
Merge pull request #1799 from ethanroj23/rr_graph_node_fan_in
RRGraphView::node_fan_in() Implementation
Commit: b05b77c22b72a1fb275091288788cc066cb8d5df
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b05b77c22b72a1fb275091288788cc066cb8d5df
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M ODIN_II/verify_odin.sh
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
Log Message:
-----------
Merge pull request #1807 from ArashAhmadian/Issue1806
Adding regression_mcnc & vtr_reg_multiclock to CI
Commit: c43fdbcacad7c2104c427217f823644f31954cee
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c43fdbcacad7c2104c427217f823644f31954cee
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
R .github/gha/install_dependencies.sh
M .github/labeler.yml
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
M dev/check-format-py.sh
M dev/check-format.sh
Log Message:
-----------
Merge pull request #1804 from umarcor/ci-scripts
ci: move scripts from '.github/gha' and '.github/travis' into '.github/scripts'
Commit: 8d5eda91927039071aff956bd47fdc6ed98669dc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d5eda91927039071aff956bd47fdc6ed98669dc
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
Log Message:
-----------
[Odin]: fix arch name type for mixing optimization tasks in Odin regtest
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: c4279ddec361b5e308dd4179fb94fe2634e82942
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c4279ddec361b5e308dd4179fb94fe2634e82942
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/vpr_api.cpp
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/route/route_common.cpp
M vpr/test/test_connection_router.cpp
Log Message:
-----------
Merge pull request #1786 from byuccl/vtr_new_routing
Added the ability to perform detailed routing with different channel widths
Commit: 110bae4ae127ed1a67fcf6c1b38f8a6ff9e24e46
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/110bae4ae127ed1a67fcf6c1b38f8a6ff9e24e46
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-07-30 (Fri, 30 Jul 2021)
Changed paths:
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_types.h
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
Log Message:
-----------
Merge pull request #1802 from verilog-to-routing/cluster_attraction_groups
Cluster attraction groups
Commit: 9ad12216889f2f0e0d4e7518b43a5d4b11948550
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ad12216889f2f0e0d4e7518b43a5d4b11948550
Author: Steve Kelly <kd2...@gmail.com>
Date: 2021-07-31 (Sat, 31 Jul 2021)
Changed paths:
M dev/nix/shell.nix
Log Message:
-----------
[nix] drop python 2.7
Commit: 79e784dbcbb1f994fba1059d4b132de51d86136a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/79e784dbcbb1f994fba1059d4b132de51d86136a
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-08-04 (Wed, 04 Aug 2021)
Changed paths:
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
fixing regex issue with fixed_chan_width parse file
Commit: 66f547892f9065c6911f1e91f97350a17cf1d2ce
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/66f547892f9065c6911f1e91f97350a17cf1d2ce
Author: Seyed Alireza Damghani <sdam...@unb.ca>
Date: 2021-08-05 (Thu, 05 Aug 2021)
Changed paths:
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
[Infra]: fix run_vtr_task lint error
Signed-off-by: Seyed Alireza Damghani <sdam...@unb.ca>
Commit: 5e59252522f8f2431bcd558c878042d2b906a568
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5e59252522f8f2431bcd558c878042d2b906a568
Author: Arash Ahmadian <arash.a...@mail.utoronto.ca>
Date: 2021-08-05 (Thu, 05 Aug 2021)
Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff_titan/config/golden_results.txt
Log Message:
-----------
updating golden_results for titan tests
Commit: 2e0bafe202e3f8cb4e1f099002f7272f4705068d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2e0bafe202e3f8cb4e1f099002f7272f4705068d
Author: Tim Ansell <m...@mith.ro>
Date: 2021-08-08 (Sun, 08 Aug 2021)
Changed paths:
M dev/nix/shell.nix
Log Message:
-----------
Merge pull request #1793 from sjkelly/sjk/nixpin1
[nix] drop python 2.7
Commit: dd7fd42f9e0ed8c78f4ff50768a70cb8a93ef1ab
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dd7fd42f9e0ed8c78f4ff50768a70cb8a93ef1ab
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
Merge pull request #1821 from verilog-to-routing/run_task_lint
[Infra]: fix run_vtr_task lint error
Commit: 223e8b607b3653e44770c1ce6c6186e02bfebb30
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/223e8b607b3653e44770c1ce6c6186e02bfebb30
Author: ArashAhmadian <70601261+Ar...@users.noreply.github.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M dev/nix/shell.nix
M vtr_flow/scripts/run_vtr_task.py
Log Message:
-----------
Merge branch 'verilog-to-routing:master' into fixed_chan_width_bug
Commit: 8b2d0ed106d17933b760ecb33a9e5bddac964e84
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8b2d0ed106d17933b760ecb33a9e5bddac964e84
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
Log Message:
-----------
Merge pull request #1812 from verilog-to-routing/mixing_optimization_typo
[Odin]: fix arch name type for mixing optimization tasks in Odin regtest
Commit: 06317d042ba3c0c2dea3680a1b55d61279d34a35
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/06317d042ba3c0c2dea3680a1b55d61279d34a35
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2021-08-12 (Thu, 12 Aug 2021)
Changed paths:
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
Merge pull request #1820 from ArashAhmadian/fixed_chan_width_bug
fixing regex issue with fixed_chan_width parse file
Commit: 8d7bafddf426a44f9c628acc56e017bd72a95818
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d7bafddf426a44f9c628acc56e017bd72a95818
Author: Paula <perd...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2021-08-13 (Fri, 13 Aug 2021)
Changed paths:
R .github/gha/install_dependencies.sh
M .github/labeler.yml
A .github/scripts/build.sh
A .github/scripts/common.sh
A .github/scripts/cron_build.sh
A .github/scripts/install_dependencies.sh
A .github/scripts/unittest.sh
R .github/travis/build.sh
R .github/travis/common.sh
R .github/travis/cron_build.sh
R .github/travis/unittest.sh
M .github/workflows/test.yml
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/task.conf
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/task.conf
M ODIN_II/regression_test/parse_result/parse_result.py
M ODIN_II/verify_odin.sh
M README.developers.md
M dev/check-format-py.sh
M dev/check-format.sh
M dev/nix/shell.nix
M doc/src/arch/reference.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_types.h
M vpr/src/device/rr_graph_view.h
M vpr/src/draw/draw.cpp
A vpr/src/pack/attraction_groups.cpp
A vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack_types.h
M vpr/src/pack/prepack.cpp
M vpr/src/place/place.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/power/power.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_node.h
M vpr/src/route/rr_node_impl.h
M vpr/test/test_connection_router.cpp
M vtr_flow/parse/parse_config/common/vpr.route_fixed_chan_width.txt
M vtr_flow/scripts/run_vtr_task.py
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/regression_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/multiclock_mcnc/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/blanket/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/iterative/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/multiclock_mcnc/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/my_script1.sh
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/once/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_other/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/titan_quick_qor/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_reg_multiclock_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt
Log Message:
-----------
Merge branch 'master' into manual_moves
Commit: df73c467b943a78d6dde1642074f01f1ba85c344
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/df73c467b943a78d6dde1642074f01f1ba85c344
Author: Paula <perd...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2021-08-16 (Mon, 16 Aug 2021)
Changed paths:
M vpr/src/place/manual_move_generator.cpp
M vpr/src/place/place.cpp
Log Message:
-----------
Changed placement of manual move move type in place.cpp, in case the user selects manual move accidentally
Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/d421ed7a0af5...df73c467b943
Reply all
Reply to author
Forward
0 new messages