[verilog-to-routing/vtr-verilog-to-routing] bddc65: lint error solved

[Amir Arjomand]

Branch: refs/heads/vtr+synlig
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: bddc654b3e43cb2910f2ff338bc10e62f30056a7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/bddc654b3e43cb2910f2ff338bc10e62f30056a7
Author: Amir.A <amirarj...@gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)

Changed paths:
R vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py
M vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py
M vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py

Log Message:
-----------
lint error solved



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