[verilog-to-routing/vtr-verilog-to-routing] ff6dd8: f4pga systemverilog tests flattened

[Amir Arjomand]

Branch: refs/heads/vtr+synlig
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: ff6dd80b40ce394bc1bd5bf93796d20b111e08a6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ff6dd80b40ce394bc1bd5bf93796d20b111e08a6
Author: Amir.A <amirarj...@gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)

Changed paths:
M .github/workflows/nightly_test.yml
M libs/EXTERNAL/CMakeLists.txt
M vtr_flow/benchmarks/system_verilog/f4pga/README.md
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py
A vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv
A vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py
A vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv
A vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py
M vtr_flow/misc/yosys/synthesis.tcl
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt

Log Message:
-----------
f4pga systemverilog tests flattened



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