[verilog-to-routing/vtr-verilog-to-routing] 178aca: tcl update - error handling

[Amir Arjomand]

Branch: refs/heads/vtr+synlig
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: 178aca633f93fb3be9b2bffd987881427a97cee1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/178aca633f93fb3be9b2bffd987881427a97cee1
Author: Amir.A <amirarj...@gmail.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)

Changed paths:
M vtr_flow/misc/yosys/synthesis.tcl

Log Message:
-----------
tcl update - error handling



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