[verilog-to-routing/vtr-verilog-to-routing] 4beb0d: Adding api make_edges_as_rr_switch_ids to rr_graph...

[tangxifan]

Branch: refs/heads/master
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: 4beb0d50c6750f624125f6bc68cfc20054bbdb7e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4beb0d50c6750f624125f6bc68cfc20054bbdb7e
Author: Muhammad Haris Zafar <muhamma...@lampromellon.com>
Date: 2021-10-27 (Wed, 27 Oct 2021)

Changed paths:
M vpr/src/device/rr_graph_builder.h

Log Message:
-----------
Adding api make_edges_as_rr_switch_ids to rr_graph_builder.h


Commit: 44ac5d88b5044670c092aa26fd3c2cc996ba822d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/44ac5d88b5044670c092aa26fd3c2cc996ba822d
Author: Muhammad Haris Zafar <muhamma...@lampromellon.com>
Date: 2021-10-27 (Wed, 27 Oct 2021)

Changed paths:
M vpr/src/route/rr_graph_uxsdcxx_serializer.h

Log Message:
-----------
replacing mark_edges_as_rr_switch_ids from respective .cpp/.h files


Commit: f1fa182981a733324e4346d8930c282844e1aa1c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f1fa182981a733324e4346d8930c282844e1aa1c
Author: Muhammad Haris Zafar <muhamma...@lampromellon.com>
Date: 2021-10-29 (Fri, 29 Oct 2021)

Changed paths:
M .github/workflows/test.yml
M doc/requirements.txt
M vpr/src/base/read_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/device/rr_graph_builder.h
M vpr/src/device/rr_graph_fwd.h
M vpr/src/device/rr_graph_view.h
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/overuse_report.cpp
M vpr/src/route/overuse_report.h
M vpr/src/route/route_common.cpp
M vpr/src/route/route_tree_timing.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_indexed_data.cpp
M vpr/src/route/rr_graph_storage.cpp
M vpr/src/route/rr_graph_storage.h
M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h
M vpr/src/util/vpr_utils.cpp

Log Message:
-----------
Merge branch 'verilog-to-routing:master' into api_make_edges_switch_ids


Commit: 3a59e0f86c90bb88b4740908df03afcc73aa8574
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3a59e0f86c90bb88b4740908df03afcc73aa8574
Author: Muhammad Haris Zafar <muhamma...@lampromellon.com>
Date: 2021-11-01 (Mon, 01 Nov 2021)

Changed paths:
M dev/subtree_config.xml
A libs/EXTERNAL/libinterchange/.github/workflows/ci.yml
A libs/EXTERNAL/libinterchange/.gitignore
A libs/EXTERNAL/libinterchange/.readthedocs.yml
A libs/EXTERNAL/libinterchange/LICENSE
A libs/EXTERNAL/libinterchange/README.md
A libs/EXTERNAL/libinterchange/cmake/cxx_static/CMakeLists.txt
A libs/EXTERNAL/libinterchange/docs/Makefile
A libs/EXTERNAL/libinterchange/docs/_static/.keepme
A libs/EXTERNAL/libinterchange/docs/bel_and_site_design.md
A libs/EXTERNAL/libinterchange/docs/conf.py
A libs/EXTERNAL/libinterchange/docs/device_resources.md
A libs/EXTERNAL/libinterchange/docs/environment.yml
A libs/EXTERNAL/libinterchange/docs/eos_slice.png
A libs/EXTERNAL/libinterchange/docs/eos_slice.png-057.png
A libs/EXTERNAL/libinterchange/docs/eos_slice_mux4x2.png
A libs/EXTERNAL/libinterchange/docs/eos_slice_mux8x3.png
A libs/EXTERNAL/libinterchange/docs/frac_lut4.png
A libs/EXTERNAL/libinterchange/docs/frac_lut4_a.png
A libs/EXTERNAL/libinterchange/docs/frac_lut4_b.png
A libs/EXTERNAL/libinterchange/docs/highlight_bottom_lut6.png
A libs/EXTERNAL/libinterchange/docs/highlight_muxf5.png
A libs/EXTERNAL/libinterchange/docs/highlight_muxf5_muxf6.png
A libs/EXTERNAL/libinterchange/docs/highlight_top_lut6.png
A libs/EXTERNAL/libinterchange/docs/index.rst
A libs/EXTERNAL/libinterchange/docs/pseudo_cells.md
A libs/EXTERNAL/libinterchange/docs/requirements.txt
A libs/EXTERNAL/libinterchange/docs/site_pip_usage.svg
A libs/EXTERNAL/libinterchange/docs/stratix10_highlight_lut5.png
A libs/EXTERNAL/libinterchange/docs/stratix10_highlight_lut6.png
A libs/EXTERNAL/libinterchange/docs/stratix10_highlight_muxf5_muxf6.png
A libs/EXTERNAL/libinterchange/docs/stratix10_slice.png-11.png
A libs/EXTERNAL/libinterchange/docs/stratix2_slice.png-026.png
A libs/EXTERNAL/libinterchange/docs/stratix2_slice.png-026_rotate.png
A libs/EXTERNAL/libinterchange/docs/versal_lut4.png
A libs/EXTERNAL/libinterchange/docs/versal_lut5.png
A libs/EXTERNAL/libinterchange/docs/versal_lut6.png
A libs/EXTERNAL/libinterchange/docs/versal_luts.png
A libs/EXTERNAL/libinterchange/docs/versal_row.png
A libs/EXTERNAL/libinterchange/docs/versal_slice.png-12.png
A libs/EXTERNAL/libinterchange/interchange/DeviceResources.capnp
A libs/EXTERNAL/libinterchange/interchange/LogicalNetlist.capnp
A libs/EXTERNAL/libinterchange/interchange/PhysicalNetlist.capnp
A libs/EXTERNAL/libinterchange/interchange/References.capnp
M vpr/src/device/rr_graph_builder.h
M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_node.cpp
M vpr/src/route/rr_node.h

Log Message:
-----------
Merge branch 'master' into api_make_edges_switch_ids


Commit: 1fc8b8a16a4077a79df9c8be672cc9a8d13e3a6c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1fc8b8a16a4077a79df9c8be672cc9a8d13e3a6c
Author: Muhammad Haris Zafar <muhamma...@lampromellon.com>
Date: 2021-11-02 (Tue, 02 Nov 2021)

Changed paths:
M vpr/src/device/rr_graph_builder.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph_uxsdcxx_serializer.h

Log Message:
-----------
Merge branch 'master' into api_make_edges_switch_ids


Commit: 89dffd5286cdd234b4cda32bb0a5877de66f980a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/89dffd5286cdd234b4cda32bb0a5877de66f980a
Author: tangxifan <tang...@gmail.com>
Date: 2021-11-02 (Tue, 02 Nov 2021)

Changed paths:
M vpr/src/device/rr_graph_builder.h
M vpr/src/route/rr_graph_uxsdcxx_serializer.h

Log Message:
-----------
Merge pull request #1902 from RapidSilicon/api_make_edges_switch_ids

Add a new API make_edges_as_rr_switch_ids() to RRGraphBuilder


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/efbad52e9d8a...89dffd5286cd