[verilog-to-routing/vtr-verilog-to-routing] d2b306: Correcting typo of abosrb to absorb

[vaughnbetz]

Branch: refs/heads/master
Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: d2b306bddb986fdb76469190e60d71a847ba7b4a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d2b306bddb986fdb76469190e60d71a847ba7b4a
Author: Nicholas Strong <nichola...@gmail.com>
Date: 2021-11-18 (Thu, 18 Nov 2021)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------
Correcting typo of abosrb to absorb


Commit: ff4f91d55e47087fdb41657985bf38a74d9cf116
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ff4f91d55e47087fdb41657985bf38a74d9cf116
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2022-07-08 (Fri, 08 Jul 2022)

Changed paths:
M .github/kokoro/continuous/strong_sanitized.cfg
M .github/kokoro/presubmit/strong_sanitized.cfg
M .github/kokoro/steps/hostsetup.sh
A .github/scripts/hostsetup.sh
M .github/scripts/install_dependencies.sh
A .github/scripts/run-vtr.sh
A .github/scripts/vtr-build.sh
A .github/scripts/vtr-full-setup.sh
A .github/scripts/vtr-test.sh
A .github/workflows/containers.yml
M .github/workflows/test.yml
M .gitignore
M BUILDING.md
M CMakeLists.txt
M CONTRIBUTING.md
M Dockerfile
M ODIN_II/Makefile
M ODIN_II/SRC/BLIFElaborate.cpp
M ODIN_II/SRC/BLIFReader.cpp
M ODIN_II/SRC/BLIFWriter.cpp
M ODIN_II/SRC/Division.cpp
M ODIN_II/SRC/GenericIO.cpp
M ODIN_II/SRC/GenericWriter.cpp
A ODIN_II/SRC/VerilogWriter.cpp
M ODIN_II/SRC/YYosys.cpp
M ODIN_II/SRC/hard_blocks.cpp
M ODIN_II/SRC/include/BLIF.hpp
M ODIN_II/SRC/include/GenericIO.hpp
M ODIN_II/SRC/include/GenericWriter.hpp
M ODIN_II/SRC/include/Verilog.hpp
M ODIN_II/SRC/include/YYosys.hpp
M ODIN_II/SRC/include/config_t.h
M ODIN_II/SRC/include/multipliers.h
M ODIN_II/SRC/include/odin_error.h
M ODIN_II/SRC/include/odin_globals.h
M ODIN_II/SRC/include/odin_util.h
M ODIN_II/SRC/multipliers.cpp
M ODIN_II/SRC/netlist_cleanup.cpp
M ODIN_II/SRC/netlist_statistic.cpp
M ODIN_II/SRC/odin_ii.cpp
M ODIN_II/SRC/odin_util.cpp
M ODIN_II/SRC/partial_map.cpp
M ODIN_II/regression_test/benchmark/task/fpu/hard_logic/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/if/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/initial/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json
M ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json
M ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/common/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/common/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/full/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/and/simulation_result.json
A ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/input/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/input/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/integer/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/integer/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/nand/simulation_result.json
A ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/output/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/output/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/reg/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/reg/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/signed_unsigned/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/signed_unsigned/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/koios/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/micro/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/micro/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/syntax/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json
A ODIN_II/regression_test/benchmark/verilog/common/shiftx.v
M ODIN_II/regression_test/benchmark/verilog/full/stereovision1_yosys_output
M ODIN_II/regression_test/benchmark/verilog/keywords/input/multiple_declarations_yosys_input
M ODIN_II/regression_test/benchmark/verilog/keywords/input/multiple_declarations_yosys_output
M ODIN_II/regression_test/benchmark/verilog/keywords/integer/integer_port_yosys_output
M ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_input
M ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match2_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match3_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match5_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match6_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/syntax/expression_in_chain_modules_yosys_output
M ODIN_II/regression_test/benchmark/verilog/syntax/unordered_ports_yosys_output
M ODIN_II/regression_test/tools/run_yosys.sh
M ODIN_II/regression_test/tools/synth.tcl
M README.developers.md
M README.md
A cmake/modules/PyEnv.cmake
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A doc/src/LICENSE.md
A doc/src/README.developers.md
A doc/src/SUPPORT.md
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M doc/src/api/vpr/rr_graph.rst
M doc/src/arch/reference.rst
R doc/src/building/building.md
R doc/src/building/index.rst
M doc/src/conf.py
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R doc/src/dev/license.md
R doc/src/dev/support.md
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M doc/src/odin/dev_guide/contributing.md
M doc/src/odin/dev_guide/regression_test.md
M doc/src/odin/dev_guide/testing.md
M doc/src/quickstart/index.rst
M doc/src/tutorials/arch/classic_soft_logic.rst
M doc/src/tutorials/arch/configurable_memory.rst
M doc/src/tutorials/arch/configurable_memory_bus.rst
M doc/src/tutorials/arch/fracturable_multiplier.rst
M doc/src/tutorials/arch/fracturable_multiplier_bus.rst
M doc/src/vpr/command_line_usage.rst
M doc/src/vpr/file_formats.rst
M doc/src/vpr/index.rst
A doc/src/vpr/placement_constraints.rst
M doc/src/vtr/get_vtr.rst
M doc/src/vtr/index.rst
R doc/src/vtr/install_vtr.rst
A doc/src/vtr/optional_build_info.md
M doc/src/vtr/power_estimation/index.rst
A doc/src/yosys+odin/dev_guide/YosysOdinFlow.png
A doc/src/yosys+odin/dev_guide/contributing.rst
A doc/src/yosys+odin/dev_guide/index.rst
A doc/src/yosys+odin/dev_guide/regression_test.rst
A doc/src/yosys+odin/dev_guide/testing.rst
A doc/src/yosys+odin/index.rst
A doc/src/yosys+odin/quickstart.rst
A doc/src/yosys+odin/user_guide.rst
A doc/src/yosys/dev_guide.rst
A doc/src/yosys/index.rst
A doc/src/yosys/quickstart.rst
A doc/src/yosys/structure.rst
A doc/src/yosys/verilog_support.rst
M doc/src/z_references.bib
A install_apt_packages.sh
M libs/CMakeLists.txt
M libs/EXTERNAL/CMakeLists.txt
A libs/EXTERNAL/capnproto/.github/workflows/quick-test.yml
A libs/EXTERNAL/capnproto/.github/workflows/release-test.yml
R libs/EXTERNAL/capnproto/.travis.yml
M libs/EXTERNAL/capnproto/CMakeLists.txt
M libs/EXTERNAL/capnproto/README.md
R libs/EXTERNAL/capnproto/appveyor.yml
M libs/EXTERNAL/capnproto/c++/CMakeLists.txt
M libs/EXTERNAL/capnproto/c++/Makefile.am
M libs/EXTERNAL/capnproto/c++/cmake/CapnProtoConfig.cmake.in
M libs/EXTERNAL/capnproto/c++/cmake/CapnProtoMacros.cmake
M libs/EXTERNAL/capnproto/c++/configure.ac
A libs/EXTERNAL/capnproto/c++/pkgconfig/capnp-websocket.pc.in
A libs/EXTERNAL/capnproto/c++/pkgconfig/capnpc.pc.in
M libs/EXTERNAL/capnproto/c++/pkgconfig/kj-async.pc.in
A libs/EXTERNAL/capnproto/c++/pkgconfig/kj-gzip.pc.in
A libs/EXTERNAL/capnproto/c++/pkgconfig/kj-tls.pc.in
M libs/EXTERNAL/capnproto/c++/regenerate-bootstraps.sh
M libs/EXTERNAL/capnproto/c++/src/CMakeLists.txt
M libs/EXTERNAL/capnproto/c++/src/capnp/CMakeLists.txt
M libs/EXTERNAL/capnproto/c++/src/capnp/any-test.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/any.h
M libs/EXTERNAL/capnproto/c++/src/capnp/arena.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/arena.h
M libs/EXTERNAL/capnproto/c++/src/capnp/blob.h
M libs/EXTERNAL/capnproto/c++/src/capnp/bootstrap-test.ekam-rule
M libs/EXTERNAL/capnproto/c++/src/capnp/c++.capnp.h
M libs/EXTERNAL/capnproto/c++/src/capnp/capability-test.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/capability.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/capability.h
M libs/EXTERNAL/capnproto/c++/src/capnp/capnpc.ekam-rule
M libs/EXTERNAL/capnproto/c++/src/capnp/common.h
A libs/EXTERNAL/capnproto/c++/src/capnp/compat/byte-stream-test.c++
A libs/EXTERNAL/capnproto/c++/src/capnp/compat/byte-stream.c++
A libs/EXTERNAL/capnproto/c++/src/capnp/compat/byte-stream.capnp
A libs/EXTERNAL/capnproto/c++/src/capnp/compat/byte-stream.h
A libs/EXTERNAL/capnproto/c++/src/capnp/compat/http-over-capnp-test.c++
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A libs/EXTERNAL/capnproto/c++/src/capnp/compat/http-over-capnp.capnp
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M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/compiler.h
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/error-reporter.h
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M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/lexer.capnp.h
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/lexer.h
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/module-loader.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/module-loader.h
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/node-translator.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/node-translator.h
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/parser.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/compiler/parser.h
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M libs/EXTERNAL/capnproto/c++/src/capnp/dynamic.c++
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M libs/EXTERNAL/capnproto/c++/src/capnp/encoding-test.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/endian.h
M libs/EXTERNAL/capnproto/c++/src/capnp/ez-rpc.h
M libs/EXTERNAL/capnproto/c++/src/capnp/generated-header-support.h
M libs/EXTERNAL/capnproto/c++/src/capnp/layout.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/layout.h
M libs/EXTERNAL/capnproto/c++/src/capnp/list.h
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M libs/EXTERNAL/capnproto/c++/src/capnp/membrane.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/membrane.h
M libs/EXTERNAL/capnproto/c++/src/capnp/message-test.c++
M libs/EXTERNAL/capnproto/c++/src/capnp/message.c++
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M libs/libvtrcapnproto/CMakeLists.txt
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M libs/libvtrutil/src/vtr_ndmatrix.h
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M vpr/src/base/vpr_context.h
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M vpr/src/draw/manual_moves.cpp
M vpr/src/draw/search_bar.cpp
M vpr/src/draw/search_bar.h
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M vpr/src/pack/pack_types.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/post_routing_pb_pin_fixup.cpp
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A vpr/src/pack/re_cluster_util.cpp
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M vpr/src/place/analytic_placer.cpp
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/critical_uniform_move_generator.cpp
M vpr/src/place/cut_spreader.cpp
M vpr/src/place/feasible_region_move_generator.cpp
M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/initial_placement.h
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_utils.cpp
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M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/uniform_move_generator.cpp
M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp
M vpr/src/power/power.cpp
M vpr/src/power/power_callibrate.cpp
M vpr/src/power/power_components.cpp
M vpr/src/power/power_sizing.cpp
M vpr/src/route/annotate_routing.cpp
M vpr/src/route/build_switchblocks.cpp
M vpr/src/route/check_route.cpp
M vpr/src/route/check_rr_graph.cpp
M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/clock_network_builders.h
M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h
M vpr/src/route/overuse_report.cpp
M vpr/src/route/overuse_report.h
M vpr/src/route/route_breadth_first.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/route_profiling.cpp
M vpr/src/route/route_timing.cpp
M vpr/src/route/route_tree_timing.cpp
M vpr/src/route/route_util.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_lookahead_extended_map.cpp
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M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_map_utils.h
M vpr/src/route/router_lookahead_sampling.cpp
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M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph.h
M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph2.h
M vpr/src/route/rr_graph_area.cpp
M vpr/src/route/rr_graph_clock.cpp
M vpr/src/route/rr_graph_clock.h
M vpr/src/route/rr_graph_indexed_data.cpp
M vpr/src/route/rr_graph_indexed_data.h
M vpr/src/route/rr_graph_reader.cpp
M vpr/src/route/rr_graph_sbox.cpp
M vpr/src/route/rr_graph_sbox.h
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M vpr/src/route/rr_graph_timing_params.cpp
M vpr/src/route/rr_graph_util.cpp
M vpr/src/route/rr_graph_util.h
M vpr/src/route/rr_graph_uxsdcxx_serializer.h
M vpr/src/route/rr_graph_writer.cpp
M vpr/src/route/rr_metadata.cpp
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R vpr/src/route/rr_node.h
R vpr/src/route/rr_node_fwd.h
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M vpr/src/route/rr_types.h
M vpr/src/route/segment_stats.cpp
M vpr/src/route/spatial_route_tree_lookup.cpp
M vpr/src/timing/timing_util.cpp
M vpr/src/timing/timing_util.h
M vpr/src/util/vpr_error.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
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A vpr/test/pre_pack.report_timing.setup.rpt
M vpr/test/test_connection_router.cpp
A vpr/test/test_interchange_device.cpp
A vpr/test/test_interchange_netlist.cpp
A vpr/test/test_noc_storage.cpp
A vpr/test/test_post_verilog.cpp
A vpr/test/test_post_verilog_arch.xml
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M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp
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M vtr_flow/scripts/python_libs/vtr/odin/odin.py
M vtr_flow/scripts/run_vtr_flow.py
M vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/vtr_benchmarks/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into absorb_buffer_typo


Commit: 196207dda9a4f26922270d2d4d2e5a35e889c806
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/196207dda9a4f26922270d2d4d2e5a35e889c806
Author: AlexandreSinger <49374526+Ale...@users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)

Changed paths:
M .gitattributes
A .github/dependabot.yml
R .github/kokoro/continuous/nightly_test1.cfg
R .github/kokoro/continuous/nightly_test2.cfg
R .github/kokoro/continuous/nightly_test3.cfg
R .github/kokoro/continuous/nightly_test4.cfg
R .github/kokoro/continuous/odin_strong.cfg
R .github/kokoro/continuous/odin_tech_strong.cfg
R .github/kokoro/continuous/strong.cfg
R .github/kokoro/continuous/strong_sanitized.cfg
R .github/kokoro/continuous/weekly.cfg
R .github/kokoro/continuous/yosys_odin_test.cfg
R .github/kokoro/continuous/yosys_test.cfg
R .github/kokoro/presubmit/nightly_test1.cfg
R .github/kokoro/presubmit/nightly_test2.cfg
R .github/kokoro/presubmit/nightly_test3.cfg
R .github/kokoro/presubmit/nightly_test4.cfg
R .github/kokoro/presubmit/odin_strong.cfg
R .github/kokoro/presubmit/odin_tech_strong.cfg
R .github/kokoro/presubmit/strong.cfg
R .github/kokoro/presubmit/strong_sanitized.cfg
R .github/kokoro/presubmit/yosys_odin_test.cfg
R .github/kokoro/presubmit/yosys_test.cfg
R .github/kokoro/run-vtr.sh
R .github/kokoro/steps/git.sh
R .github/kokoro/steps/hostinfo.sh
R .github/kokoro/steps/hostsetup.sh
R .github/kokoro/steps/vtr-build.sh
R .github/kokoro/steps/vtr-full-setup.sh
R .github/kokoro/steps/vtr-min-setup.sh
R .github/kokoro/steps/vtr-test.sh
M .github/labeler.yml
M .github/scripts/hostsetup.sh
M .github/scripts/install_dependencies.sh
A .github/scripts/install_noble_dependencies.sh
M .github/scripts/run-vtr.sh
M .github/workflows/containers.yml
M .github/workflows/labeler.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml
M .gitignore
A .gitmodules
M .readthedocs.yaml
M BUILDING.md
M CHANGELOG.md
M CMakeLists.txt
M CONTRIBUTING.md
M Dockerfile
M Makefile
R ODIN_II/.gitignore
R ODIN_II/CMakeLists.txt
R ODIN_II/Makefile
R ODIN_II/README.md
R ODIN_II/SRC/BLIF.cpp
R ODIN_II/SRC/BLIFElaborate.cpp
R ODIN_II/SRC/BLIFReader.cpp
R ODIN_II/SRC/BLIFWriter.cpp
R ODIN_II/SRC/BlockMemories.cpp
R ODIN_II/SRC/CaseEqual.cpp
R ODIN_II/SRC/Division.cpp
R ODIN_II/SRC/FlipFlop.cpp
R ODIN_II/SRC/GenericIO.cpp
R ODIN_II/SRC/GenericReader.cpp
R ODIN_II/SRC/GenericWriter.cpp
R ODIN_II/SRC/HardSoftLogicMixer.cpp
R ODIN_II/SRC/Hashtable.cpp
R ODIN_II/SRC/Latch.cpp
R ODIN_II/SRC/LogicalOps.cpp
R ODIN_II/SRC/MixingOptimization.cpp
R ODIN_II/SRC/Modulo.cpp
R ODIN_II/SRC/Multiplexer.cpp
R ODIN_II/SRC/Power.cpp
R ODIN_II/SRC/Shift.cpp
R ODIN_II/SRC/Verilog.cpp
R ODIN_II/SRC/VerilogReader.cpp
R ODIN_II/SRC/VerilogWriter.cpp
R ODIN_II/SRC/YYosys.cpp
R ODIN_II/SRC/enum_str.cpp
R ODIN_II/SRC/include/AtomicBuffer.hpp
R ODIN_II/SRC/include/BLIF.hpp
R ODIN_II/SRC/include/BLIFElaborate.hpp
R ODIN_II/SRC/include/BlockMemories.hpp
R ODIN_II/SRC/include/CaseEqual.hpp
R ODIN_II/SRC/include/Division.hpp
R ODIN_II/SRC/include/FlipFlop.hpp
R ODIN_II/SRC/include/GenericIO.hpp
R ODIN_II/SRC/include/GenericReader.hpp
R ODIN_II/SRC/include/GenericWriter.hpp
R ODIN_II/SRC/include/HardSoftLogicMixer.hpp
R ODIN_II/SRC/include/Hashtable.hpp
R ODIN_II/SRC/include/Latch.hpp
R ODIN_II/SRC/include/LogicalOps.hpp
R ODIN_II/SRC/include/MixingOptimization.hpp
R ODIN_II/SRC/include/Modulo.hpp
R ODIN_II/SRC/include/Multiplexer.hpp
R ODIN_II/SRC/include/Power.hpp
R ODIN_II/SRC/include/Shift.hpp
R ODIN_II/SRC/include/Verilog.hpp
R ODIN_II/SRC/include/YYosys.hpp
R ODIN_II/SRC/include/ast_loop_unroll.h
R ODIN_II/SRC/include/ast_util.h
R ODIN_II/SRC/include/config_t.h
R ODIN_II/SRC/include/hierarchy_util.h
R ODIN_II/SRC/include/netlist_check.h
R ODIN_II/SRC/include/netlist_cleanup.h
R ODIN_II/SRC/include/netlist_statistic.h
R ODIN_II/SRC/include/netlist_utils.h
R ODIN_II/SRC/include/netlist_visualizer.h
R ODIN_II/SRC/include/node_creation_library.h
R ODIN_II/SRC/include/odin_buffer.hpp
R ODIN_II/SRC/include/odin_error.h
R ODIN_II/SRC/include/odin_globals.h
R ODIN_II/SRC/include/odin_ii.h
R ODIN_II/SRC/include/odin_memory.hpp
R ODIN_II/SRC/include/odin_types.h
R ODIN_II/SRC/include/odin_util.h
R ODIN_II/SRC/include/partial_map.h
R ODIN_II/SRC/include/read_xml_config_file.h
R ODIN_II/SRC/include/scope_util.h
R ODIN_II/SRC/include/sim_block.h
R ODIN_II/SRC/include/string_cache.h
R ODIN_II/SRC/include/verilog_bison_user_defined.h
R ODIN_II/SRC/multipliers.cpp
R ODIN_II/SRC/netlist_check.cpp
R ODIN_II/SRC/netlist_utils.cpp
R ODIN_II/SRC/node_creation_library.cpp
R ODIN_II/SRC/odin_memory.cpp
R ODIN_II/SRC/scope_util.cpp
R ODIN_II/exec_wrapper.sh
R ODIN_II/main.cpp
R ODIN_II/odin_II
R ODIN_II/regression_test/.library/conf_generate.sh
R ODIN_II/regression_test/.library/handle_exit.sh
R ODIN_II/regression_test/.library/helper.sh
R ODIN_II/regression_test/.library/no_tool.conf
R ODIN_II/regression_test/.library/output_on_error.conf
R ODIN_II/regression_test/.library/regenerate_vectors.conf
R ODIN_II/regression_test/.library/threaded_sim.conf
R ODIN_II/regression_test/.library/time_format.sh
R ODIN_II/regression_test/.library/valgrind_simulation.conf
R ODIN_II/regression_test/.library/valgrind_synthesis.conf
R ODIN_II/regression_test/benchmark/suite/complex_synthesis_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/full_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/heavy_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/keyword_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/yosys+odin/techmap_heavysuite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/yosys+odin/techmap_keyword_suite/task_list.conf
R ODIN_II/regression_test/benchmark/suite/yosys+odin/techmap_lightsuite/task_list.conf
R ODIN_II/regression_test/benchmark/task/FIR/simulation_result.json
R ODIN_II/regression_test/benchmark/task/FIR/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/FIR/task.conf
R ODIN_II/regression_test/benchmark/task/arch_sweep/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/arch_sweep/task.conf
R ODIN_II/regression_test/benchmark/task/c_functions/clog2/simulation_result.json
R ODIN_II/regression_test/benchmark/task/c_functions/clog2/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/c_functions/clog2/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/simulation_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/simulation_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/simulation_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/graphviz_ast/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/graphviz_ast/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/graphviz_netlist/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/graphviz_netlist/task.conf
R ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/simulation_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/task.conf
R ODIN_II/regression_test/benchmark/task/fpu/hard_logic/simulation_result.json
R ODIN_II/regression_test/benchmark/task/fpu/hard_logic/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/fpu/hard_logic/task.conf
R ODIN_II/regression_test/benchmark/task/full/simulation_result.json
R ODIN_II/regression_test/benchmark/task/full/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/full/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/always/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/always/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/and/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/and/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/and/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/assign/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/assign/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/assign/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/automatic/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/automatic/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/begin_end/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/begin_end/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/begin_end/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/buf/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/buf/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/buf/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/case_endcase/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/case_endcase/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/case_endcase/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/default/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/default/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/default/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/defparam/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/defparam/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/else/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/else/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/else/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/for/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/for/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/for/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/function_endfunction/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/function_endfunction/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/function_endfunction/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/generate_endgenerate/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/generate_endgenerate/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/generate_endgenerate/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/genvar/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/genvar/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/genvar/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/if/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/if/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/if/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/initial/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/initial/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/initial/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/inout/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/inout/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/input/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/input/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/integer/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/integer/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/localparam/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/localparam/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/localparam/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/macromodule/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/macromodule/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/macromodule/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/module_endmodule/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/module_endmodule/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/module_endmodule/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/nand/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/nand/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/nand/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/negedge/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/negedge/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/negedge/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/nor/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/nor/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/nor/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/not/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/not/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/not/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/or/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/or/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/output/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/output/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/parameter/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/parameter/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/parameter/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/posedge/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/posedge/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/posedge/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/reg/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/reg/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/reg/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/specify_endspecify/synthesis_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/specparam/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/specparam/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/task_endtask/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/task_endtask/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/task_endtask/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/while/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/while/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/wire/simulation_result.json
R ODIN_II/regression_test/benchmark/task/keywords/wire/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/keywords/wire/task.conf
R ODIN_II/regression_test/benchmark/task/keywords/xnor/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/xor/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/keywords/xor/task.conf
R ODIN_II/regression_test/benchmark/task/koios/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/koios/task.conf
R ODIN_II/regression_test/benchmark/task/large/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/large/task.conf
R ODIN_II/regression_test/benchmark/task/micro/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
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R ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/operators/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/syntax/task.conf
R ODIN_II/regression_test/benchmark/task/vtr/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/vtr/task.conf
R ODIN_II/regression_test/benchmark/task/yosys+odin/FIR/simulation_result.json
R ODIN_II/regression_test/benchmark/task/yosys+odin/FIR/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/yosys+odin/FIR/task.conf
R ODIN_II/regression_test/benchmark/task/yosys+odin/arch_sweep/synthesis_result.json
R ODIN_II/regression_test/benchmark/task/yosys+odin/arch_sweep/task.conf
R ODIN_II/regression_test/benchmark/task/yosys+odin/c_functions/clog2/simulation_result.json
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R ODIN_II/regression_test/benchmark/task/yosys+odin/common/simulation_result.json
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R ODIN_II/regression_test/benchmark/verilog/keywords/inout/simple_inout.v
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R ODIN_II/regression_test/benchmark/verilog/syntax/README
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R ODIN_II/regression_test/benchmark/verilog/syntax/expression_in_chain_modules.v
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R ODIN_II/regression_test/parse_result/conf/synth.toml
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R ODIN_II/regression_test/tools/odin_config_maker.py
R ODIN_II/regression_test/tools/regression_test_arch.pl
R ODIN_II/regression_test/tools/regression_test_no_args.pl
R ODIN_II/regression_test/tools/run_yosys.sh
R ODIN_II/regression_test/tools/run_yosys_sample_task.ycfg
R ODIN_II/regression_test/tools/synth.tcl
R ODIN_II/regression_test/tools/synth_using_odin.py
R ODIN_II/techlib/bram_bb.v
R ODIN_II/techlib/mem_map.v
R ODIN_II/techlib/rom_bb.v
M README.developers.md
M README.md
M abc/CMakeLists.txt
M abc/Makefile
M abc/README.md
M abc/abc.rc
M abc/abclib.dsp
M abc/src/aig/aig/aig.h
M abc/src/aig/aig/aigCanon.c
M abc/src/aig/aig/aigDup.c
M abc/src/aig/aig/aigShow.c
M abc/src/aig/aig/aigUtil.c
M abc/src/aig/gia/gia.c
M abc/src/aig/gia/gia.h
M abc/src/aig/gia/giaAgi.c
M abc/src/aig/gia/giaAig.c
M abc/src/aig/gia/giaAiger.c
M abc/src/aig/gia/giaAigerExt.c
M abc/src/aig/gia/giaBalAig.c
M abc/src/aig/gia/giaBalLut.c
M abc/src/aig/gia/giaCSat.c
M abc/src/aig/gia/giaCSat2.c
A abc/src/aig/gia/giaCSat3.c
A abc/src/aig/gia/giaCSatP.c
A abc/src/aig/gia/giaCSatP.h
M abc/src/aig/gia/giaCTas.c
M abc/src/aig/gia/giaCex.c
M abc/src/aig/gia/giaCut.c
A abc/src/aig/gia/giaDecs.c
A abc/src/aig/gia/giaDeep.c
M abc/src/aig/gia/giaDfs.c
M abc/src/aig/gia/giaDup.c
M abc/src/aig/gia/giaEmbed.c
M abc/src/aig/gia/giaEquiv.c
M abc/src/aig/gia/giaFalse.c
M abc/src/aig/gia/giaFanout.c
M abc/src/aig/gia/giaFx.c
A abc/src/aig/gia/giaGen.c
M abc/src/aig/gia/giaHash.c
M abc/src/aig/gia/giaHcd.c
M abc/src/aig/gia/giaIf.c
M abc/src/aig/gia/giaIso.c
M abc/src/aig/gia/giaIso2.c
M abc/src/aig/gia/giaIso3.c
M abc/src/aig/gia/giaKf.c
M abc/src/aig/gia/giaLf.c
M abc/src/aig/gia/giaMan.c
M abc/src/aig/gia/giaMf.c
M abc/src/aig/gia/giaMfs.c
A abc/src/aig/gia/giaMinLut.c
A abc/src/aig/gia/giaMinLut2.c
M abc/src/aig/gia/giaMini.c
M abc/src/aig/gia/giaMuxes.c
A abc/src/aig/gia/giaNewBdd.h
A abc/src/aig/gia/giaNewTt.h
M abc/src/aig/gia/giaNf.c
A abc/src/aig/gia/giaPat2.c
M abc/src/aig/gia/giaPf.c
M abc/src/aig/gia/giaQbf.c
A abc/src/aig/gia/giaReshape1.c
A abc/src/aig/gia/giaReshape2.c
M abc/src/aig/gia/giaResub.c
A abc/src/aig/gia/giaResub2.c
A abc/src/aig/gia/giaResub3.c
A abc/src/aig/gia/giaResub6.c
M abc/src/aig/gia/giaRex.c
M abc/src/aig/gia/giaSatMap.c
A abc/src/aig/gia/giaSatSyn.c
M abc/src/aig/gia/giaScript.c
M abc/src/aig/gia/giaShow.c
A abc/src/aig/gia/giaSif.c
M abc/src/aig/gia/giaSim.c
A abc/src/aig/gia/giaSimBase.c
M abc/src/aig/gia/giaSort.c
M abc/src/aig/gia/giaSpeedup.c
M abc/src/aig/gia/giaStg.c
A abc/src/aig/gia/giaStoch.c
M abc/src/aig/gia/giaStr.c
A abc/src/aig/gia/giaSupps.c
M abc/src/aig/gia/giaSweep.c
M abc/src/aig/gia/giaSweeper.c
M abc/src/aig/gia/giaSwitch.c
M abc/src/aig/gia/giaTim.c
A abc/src/aig/gia/giaTranStoch.c
A abc/src/aig/gia/giaTransduction.cpp
A abc/src/aig/gia/giaTransduction.h
M abc/src/aig/gia/giaTruth.c
A abc/src/aig/gia/giaTtopt.cpp
M abc/src/aig/gia/giaUnate.c
M abc/src/aig/gia/giaUtil.c
M abc/src/aig/gia/module.make
M abc/src/aig/hop/hopBalance.c
M abc/src/aig/ioa/ioaReadAig.c
M abc/src/aig/ivy/ivyBalance.c
M abc/src/aig/ivy/ivyCheck.c
M abc/src/aig/ivy/ivyCutTrav.c
M abc/src/aig/ivy/ivyFraig.c
M abc/src/aig/ivy/ivyRwrAlg.c
M abc/src/aig/ivy/ivyShow.c
M abc/src/aig/miniaig/abcOper.h
M abc/src/aig/miniaig/miniaig.h
M abc/src/aig/miniaig/minilut.h
M abc/src/aig/miniaig/ndr.h
M abc/src/aig/saig/saigConstr.c
M abc/src/aig/saig/saigInd.c
M abc/src/aig/saig/saigIoa.c
M abc/src/aig/saig/saigIso.c
M abc/src/aig/saig/saigIsoFast.c
M abc/src/aig/saig/saigIsoSlow.c
M abc/src/aig/saig/saigMiter.c
M abc/src/aig/saig/saigSimMv.c
M abc/src/aig/saig/saigTrans.c
M abc/src/aig/saig/saigWnd.c
M abc/src/base/abc/abc.h
M abc/src/base/abc/abcAig.c
M abc/src/base/abc/abcCheck.c
M abc/src/base/abc/abcDfs.c
M abc/src/base/abc/abcFanOrder.c
M abc/src/base/abc/abcFanio.c
M abc/src/base/abc/abcFunc.c
M abc/src/base/abc/abcHie.c
M abc/src/base/abc/abcHieNew.c
M abc/src/base/abc/abcLatch.c
M abc/src/base/abc/abcMinBase.c
M abc/src/base/abc/abcNames.c
M abc/src/base/abc/abcNetlist.c
M abc/src/base/abc/abcNtk.c
M abc/src/base/abc/abcObj.c
M abc/src/base/abc/abcRefs.c
M abc/src/base/abc/abcShow.c
M abc/src/base/abc/abcSop.c
M abc/src/base/abc/abcUtil.c
M abc/src/base/abci/abc.c
M abc/src/base/abci/abcAuto.c
M abc/src/base/abci/abcBalance.c
M abc/src/base/abci/abcCas.c
M abc/src/base/abci/abcCascade.c
M abc/src/base/abci/abcCollapse.c
M abc/src/base/abci/abcCut.c
M abc/src/base/abci/abcDar.c
M abc/src/base/abci/abcDarUnfold2.c
M abc/src/base/abci/abcDec.c
M abc/src/base/abci/abcDetect.c
M abc/src/base/abci/abcDress2.c
M abc/src/base/abci/abcDsd.c
M abc/src/base/abci/abcEspresso.c
M abc/src/base/abci/abcExact.c
M abc/src/base/abci/abcExtract.c
M abc/src/base/abci/abcFx.c
M abc/src/base/abci/abcFxu.c
M abc/src/base/abci/abcGen.c
M abc/src/base/abci/abcIf.c
M abc/src/base/abci/abcIvy.c
M abc/src/base/abci/abcLog.c
M abc/src/base/abci/abcLut.c
M abc/src/base/abci/abcLutmin.c
M abc/src/base/abci/abcMap.c
M abc/src/base/abci/abcMffc.c
M abc/src/base/abci/abcMfs.c
M abc/src/base/abci/abcMiter.c
M abc/src/base/abci/abcNpn.c
M abc/src/base/abci/abcNpnSave.c
M abc/src/base/abci/abcNtbdd.c
M abc/src/base/abci/abcOdc.c
A abc/src/base/abci/abcOrchestration.c
M abc/src/base/abci/abcPrint.c
M abc/src/base/abci/abcProve.c
M abc/src/base/abci/abcQbf.c
M abc/src/base/abci/abcQuant.c
M abc/src/base/abci/abcReach.c
M abc/src/base/abci/abcRec3.c
M abc/src/base/abci/abcRefactor.c
M abc/src/base/abci/abcReorder.c
M abc/src/base/abci/abcRestruct.c
M abc/src/base/abci/abcResub.c
M abc/src/base/abci/abcRewrite.c
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M abc/src/bdd/cas/casCore.c
M abc/src/bdd/cudd/cuddAddIte.c
M abc/src/bdd/cudd/cuddAddNeg.c
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M abc/src/bdd/cudd/cuddLinear.c
M abc/src/bdd/cudd/cuddMatMult.c
M abc/src/bdd/cudd/cuddPriority.c
M abc/src/bdd/cudd/cuddReorder.c
M abc/src/bdd/cudd/cuddSat.c
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M abc/src/bdd/cudd/cuddSubsetSP.c
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M abc/src/bdd/cudd/cuddZddGroup.c
M abc/src/bdd/cudd/cuddZddIsop.c
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M abc/src/bdd/cudd/cuddZddSymm.c
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M abc/src/bdd/extrab/extraBddMisc.c
A abc/src/bdd/extrab/extraBddSet.c
M abc/src/bdd/extrab/extraBddUnate.c
M abc/src/bdd/extrab/module.make
M abc/src/bdd/llb/llb4Nonlin.c
M abc/src/bdd/reo/reo.h
M abc/src/bool/bdc/bdc.h
M abc/src/bool/bdc/bdcCore.c
M abc/src/bool/bdc/bdcSpfd.c
M abc/src/bool/dec/dec.h
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M abc/src/bool/kit/kitPla.c
M abc/src/bool/kit/kitTruth.c
M abc/src/bool/lucky/lucky.c
M abc/src/bool/lucky/luckyFast16.c
M abc/src/bool/lucky/luckySwap.c
M abc/src/bool/lucky/luckySwapIJ.c
M abc/src/demo.c
M abc/src/map/amap/amapInt.h
M abc/src/map/amap/amapLib.c
M abc/src/map/amap/amapLiberty.c
M abc/src/map/amap/amapMan.c
M abc/src/map/amap/amapMatch.c
M abc/src/map/amap/amapRead.c
M abc/src/map/amap/amapRule.c
M abc/src/map/amap/amapUniq.c
M abc/src/map/fpga/fpgaCut.c
M abc/src/map/fpga/fpgaUtils.c
M abc/src/map/fpga/fpgaVec.c
M abc/src/map/if/if.h
M abc/src/map/if/ifCore.c
M abc/src/map/if/ifCut.c
M abc/src/map/if/ifDec07.c
M abc/src/map/if/ifDsd.c
M abc/src/map/if/ifMan.c
M abc/src/map/if/ifMap.c
M abc/src/map/if/ifTruth.c
M abc/src/map/if/ifTune.c
M abc/src/map/mapper/mapperCut.c
M abc/src/map/mapper/mapperLib.c
M abc/src/map/mapper/mapperTable.c
M abc/src/map/mapper/mapperUtils.c
M abc/src/map/mapper/mapperVec.c
M abc/src/map/mio/mio.c
M abc/src/map/mio/mio.h
M abc/src/map/mio/mioRead.c
M abc/src/map/mio/mioUtils.c
M abc/src/map/mpm/mpmMan.c
M abc/src/map/scl/scl.c
M abc/src/map/scl/sclBufSize.c
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M abc/src/map/scl/sclLib.h
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M abc/src/map/scl/sclLibUtil.c
M abc/src/map/scl/sclLiberty.c
M abc/src/map/scl/sclSize.c
M abc/src/map/super/superAnd.c
M abc/src/map/super/superGate.c
M abc/src/misc/bar/bar.h
M abc/src/misc/bbl/bblif.c
M abc/src/misc/bzlib/compress.c
M abc/src/misc/bzlib/decompress.c
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M abc/src/misc/espresso/contain.c
M abc/src/misc/espresso/cvrm.c
M abc/src/misc/extra/extra.h
A abc/src/misc/extra/extraUtilCfs.c
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A abc/src/misc/extra/extraUtilGen.c
A abc/src/misc/extra/extraUtilMacc.c
A abc/src/misc/extra/extraUtilMaj.c
M abc/src/misc/extra/extraUtilMisc.c
A abc/src/misc/extra/extraUtilMult.c
A abc/src/misc/extra/extraUtilPath.c
M abc/src/misc/extra/extraUtilPerm.c
M abc/src/misc/extra/extraUtilPrime.c
M abc/src/misc/extra/extraUtilReader.c
M abc/src/misc/extra/extraUtilUtil.c
M abc/src/misc/extra/module.make
M abc/src/misc/mem/mem.c
M abc/src/misc/mem/mem.h
M abc/src/misc/tim/tim.h
M abc/src/misc/tim/timMan.c
M abc/src/misc/util/abc_global.h
M abc/src/misc/util/utilBridge.c
M abc/src/misc/util/utilCex.c
M abc/src/misc/util/utilMem.c
M abc/src/misc/util/utilNam.c
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M abc/src/misc/util/utilTruth.h
M abc/src/misc/vec/vecAtt.h
M abc/src/misc/vec/vecBit.h
M abc/src/misc/vec/vecFlt.h
M abc/src/misc/vec/vecHsh.h
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M abc/src/misc/vec/vecMem.h
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M abc/src/misc/vec/vecSet.h
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M abc/src/misc/vec/vecVec.h
M abc/src/misc/vec/vecWec.h
M abc/src/misc/vec/vecWrd.h
M abc/src/misc/zlib/crc32.c
M abc/src/misc/zlib/deflate.c
M abc/src/misc/zlib/gzwrite.c
M abc/src/misc/zlib/trees.c
M abc/src/misc/zlib/zutil.h
M abc/src/opt/cgt/cgtAig.c
M abc/src/opt/cut/cutCut.c
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M abc/src/opt/dar/darCore.c
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M abc/src/opt/fxu/fxuReduce.c
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M abc/src/opt/lpk/lpkAbcUtil.c
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M abc/src/opt/lpk/lpkInt.h
M abc/src/opt/lpk/lpkMan.c
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M abc/src/opt/mfs/mfsDiv.c
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M abc/src/opt/rwr/rwrTemp.c
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M abc/src/opt/sfm/sfm.h
M abc/src/opt/sfm/sfmCnf.c
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M abc/src/opt/sfm/sfmDec.c
M abc/src/opt/sfm/sfmInt.h
M abc/src/opt/sfm/sfmLib.c
M abc/src/opt/sfm/sfmNtk.c
M abc/src/opt/sfm/sfmSat.c
M abc/src/opt/sfm/sfmWin.c
M abc/src/opt/sim/simMan.c
M abc/src/opt/sim/simSupp.c
M abc/src/opt/sim/simUtils.c
M abc/src/phys/place/place_bin.c
M abc/src/phys/place/place_partition.c
M abc/src/proof/abs/absGla.c
M abc/src/proof/abs/absGlaOld.c
M abc/src/proof/abs/absRpmOld.c
M abc/src/proof/abs/absVta.c
M abc/src/proof/acec/acecBo.c
M abc/src/proof/acec/acecCore.c
M abc/src/proof/acec/acecFadds.c
M abc/src/proof/acec/acecMult.c
M abc/src/proof/acec/acecOrder.c
M abc/src/proof/acec/acecPo.c
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M abc/src/proof/acec/acecPool.c
M abc/src/proof/acec/acecRe.c
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M abc/src/proof/dch/dchCore.c
M abc/src/proof/dch/dchSimSat.c
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M abc/src/proof/fra/fraLcr.c
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M abc/src/proof/fraig/fraigInt.h
M abc/src/proof/fraig/fraigSat.c
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M abc/src/proof/fraig/fraigVec.c
M abc/src/proof/int/int.h
M abc/src/proof/live/ltl_parser.c
M abc/src/proof/pdr/pdr.h
M abc/src/proof/pdr/pdrCore.c
M abc/src/proof/pdr/pdrIncr.c
M abc/src/proof/pdr/pdrInv.c
M abc/src/proof/ssc/sscUtil.c
M abc/src/proof/ssw/ssw.h
M abc/src/proof/ssw/sswCore.c
M abc/src/proof/ssw/sswPart.c
M abc/src/proof/ssw/sswRarity.c
M abc/src/proof/ssw/sswSat.c
M abc/src/sat/bmc/bmc.h
M abc/src/sat/bmc/bmcBmc3.c
M abc/src/sat/bmc/bmcBmcAnd.c
M abc/src/sat/bmc/bmcBmcG.c
M abc/src/sat/bmc/bmcCexDepth.c
M abc/src/sat/bmc/bmcCexMin2.c
M abc/src/sat/bmc/bmcCexTools.c
M abc/src/sat/bmc/bmcEco.c
M abc/src/sat/bmc/bmcFault.c
M abc/src/sat/bmc/bmcMaj.c
M abc/src/sat/bmc/bmcMulti.c
M abc/src/sat/bmc/bmcUnroll.c
M abc/src/sat/bsat/satClause.h
M abc/src/sat/bsat/satSolver.c
M abc/src/sat/bsat/satSolver.h
M abc/src/sat/bsat2/Solver.cpp
M abc/src/sat/cnf/cnf.h
M abc/src/sat/cnf/cnfData.c
M abc/src/sat/cnf/cnfMan.c
M abc/src/sat/cnf/cnfUtil.c
M abc/src/sat/glucose/AbcGlucose.cpp
M abc/src/sat/glucose/AbcGlucose.h
M abc/src/sat/glucose/AbcGlucoseCmd.cpp
M abc/src/sat/glucose/Glucose.cpp
M abc/src/sat/glucose/Options.cpp
M abc/src/sat/glucose/Solver.h
M abc/src/sat/glucose/SolverTypes.h
M abc/src/sat/glucose/System.cpp
M abc/src/sat/glucose/Vec.h
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A abc/src/sat/glucose2/AbcGlucoseCmd2.cpp
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A abc/src/sat/glucose2/BoundedQueue.h
A abc/src/sat/glucose2/CGlucose.h
A abc/src/sat/glucose2/CGlucoseCore.h
A abc/src/sat/glucose2/Constants.h
A abc/src/sat/glucose2/Dimacs.h
A abc/src/sat/glucose2/Glucose2.cpp
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A abc/src/sat/glucose2/IntTypes.h
A abc/src/sat/glucose2/Map.h
A abc/src/sat/glucose2/Options.h
A abc/src/sat/glucose2/Options2.cpp
A abc/src/sat/glucose2/ParseUtils.h
A abc/src/sat/glucose2/Queue.h
A abc/src/sat/glucose2/SimpSolver.h
A abc/src/sat/glucose2/SimpSolver2.cpp
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A abc/src/sat/glucose2/SolverTypes.h
A abc/src/sat/glucose2/Sort.h
A abc/src/sat/glucose2/System.h
A abc/src/sat/glucose2/System2.cpp
A abc/src/sat/glucose2/Vec.h
A abc/src/sat/glucose2/XAlloc.h
A abc/src/sat/glucose2/license
A abc/src/sat/glucose2/module.make
A abc/src/sat/glucose2/pstdint.h
M abc/src/sat/msat/msatClause.c
M abc/src/sat/msat/msatSolverSearch.c
M abc/src/sat/msat/msatVec.c
M abc/src/sat/satoko/solver.c
M abc/src/sat/satoko/solver_api.c
M abc/src/sat/satoko/utils/sdbl.h
M abc/src/sat/satoko/utils/vec/vec_char.h
M abc/src/sat/satoko/utils/vec/vec_flt.h
M abc/src/sat/satoko/utils/vec/vec_int.h
M abc/src/sat/satoko/utils/vec/vec_sdbl.h
M abc/src/sat/satoko/utils/vec/vec_uint.h
M abc/src/sat/xsat/xsatSolver.c
M ace2/CMakeLists.txt
M blifexplorer/CMakeLists.txt
M blifexplorer/src/container.cpp
M blifexplorer/src/mainwindow.cpp
M blifexplorer/src/odininterface.cpp
M cmake/modules/AutoClangFormat.cmake
R cmake/modules/FindTBB.cmake
M dev/DOCKER_DEPLOY.md
M dev/odin2_helper/Makefile
M dev/pylint_check.py
M dev/subtree_config.xml
M dev/test_git_bisect.sh
A doc/.DS_Store
M doc/README
M doc/_doxygen/ODIN_II.dox
A doc/_exts/constraintsdomain/__init__.py
M doc/requirements.txt
A doc/src/.DS_Store
A doc/src/Images/.DS_Store
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A doc/src/api/vpr/server.rst
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R libs/EXTERNAL/libyosys/techlibs/xilinx/lut6_lutrams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc2v_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc2v_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc3sa_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc3sda_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc6s_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc6s_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc7_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc7_xcu_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcu_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcup_urams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcup_urams_map.v
R libs/EXTERNAL/libyosys/tests/arch/anlogic/lutram.ys
R libs/EXTERNAL/libyosys/tests/arch/anlogic/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/common/blockram.v
R libs/EXTERNAL/libyosys/tests/arch/common/shifter.v
R libs/EXTERNAL/libyosys/tests/arch/ecp5/memories.ys
R libs/EXTERNAL/libyosys/tests/arch/ecp5/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/efinix/lutram.ys
R libs/EXTERNAL/libyosys/tests/arch/gowin/lutram.ys
R libs/EXTERNAL/libyosys/tests/arch/gowin/tribuf.ys
R libs/EXTERNAL/libyosys/tests/arch/ice40/memories.ys
R libs/EXTERNAL/libyosys/tests/arch/intel_alm/blockram.ys
R libs/EXTERNAL/libyosys/tests/arch/intel_alm/counter.ys
R libs/EXTERNAL/libyosys/tests/arch/intel_alm/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/add_sub.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/dffs.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/fsm.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/logic.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/shifter.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/tribuf.ys
R libs/EXTERNAL/libyosys/tests/arch/nexus/blockram.ys
R libs/EXTERNAL/libyosys/tests/arch/nexus/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/blockram.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/dsp_abc9.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/fsm.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/lutram.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/tribuf.sh
R libs/EXTERNAL/libyosys/tests/memories/read_two_mux.v
R libs/EXTERNAL/libyosys/tests/memories/run-test.sh
R libs/EXTERNAL/libyosys/tests/opt/opt_merge_init.ys
R libs/EXTERNAL/libyosys/tests/sat/.gitignore
R libs/EXTERNAL/libyosys/tests/simple/arrays01.v
R libs/EXTERNAL/libyosys/tests/simple/attrib01_module.v
R libs/EXTERNAL/libyosys/tests/simple/attrib02_port_decl.v
R libs/EXTERNAL/libyosys/tests/simple/attrib03_parameter.v
R libs/EXTERNAL/libyosys/tests/simple/attrib05_port_conn.v.DISABLED
R libs/EXTERNAL/libyosys/tests/simple/attrib06_operator_suffix.v
R libs/EXTERNAL/libyosys/tests/simple/attrib07_func_call.v.DISABLED
R libs/EXTERNAL/libyosys/tests/simple/attrib08_mod_inst.v
R libs/EXTERNAL/libyosys/tests/simple/attrib09_case.v
R libs/EXTERNAL/libyosys/tests/simple/forgen02.v
R libs/EXTERNAL/libyosys/tests/simple/hierarchy.v
R libs/EXTERNAL/libyosys/tests/simple/hierdefparam.v
R libs/EXTERNAL/libyosys/tests/simple/module_scope.v
R libs/EXTERNAL/libyosys/tests/simple/module_scope_case.v
R libs/EXTERNAL/libyosys/tests/simple/wandwor.v
R libs/EXTERNAL/libyosys/tests/sva/.gitignore
R libs/EXTERNAL/libyosys/tests/sva/Makefile
R libs/EXTERNAL/libyosys/tests/svinterfaces/run-test.sh
R libs/EXTERNAL/libyosys/tests/svtypes/logic_rom.ys
R libs/EXTERNAL/libyosys/tests/svtypes/struct_array.sv
R libs/EXTERNAL/libyosys/tests/svtypes/typedef_memory.ys
R libs/EXTERNAL/libyosys/tests/svtypes/typedef_memory_2.ys
R libs/EXTERNAL/libyosys/tests/svtypes/typedef_scopes.sv
R libs/EXTERNAL/libyosys/tests/techmap/.gitignore
R libs/EXTERNAL/libyosys/tests/techmap/aigmap.ys
R libs/EXTERNAL/libyosys/tests/techmap/dfflegalize_dlatch.ys
R libs/EXTERNAL/libyosys/tests/techmap/dfflegalize_dlatch_init.ys
R libs/EXTERNAL/libyosys/tests/techmap/mem_simple_4x1_runtest.sh
R libs/EXTERNAL/libyosys/tests/techmap/recursive_runtest.sh
R libs/EXTERNAL/libyosys/tests/various/.gitignore
R libs/EXTERNAL/libyosys/tests/various/async.sh
R libs/EXTERNAL/libyosys/tests/various/help.ys
R libs/EXTERNAL/libyosys/tests/verilog/.gitignore
R libs/EXTERNAL/libyosys/tests/verilog/struct_access.sv
A libs/EXTERNAL/sockpp
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/cad_types.h
A libs/libarchfpga/src/device_grid.cpp
A libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/echo_arch.cpp
A libs/libarchfpga/src/histogram.cpp
A libs/libarchfpga/src/histogram.h
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/parse_switchblocks.cpp
M libs/libarchfpga/src/physical_types.h
M libs/libarchfpga/src/physical_types_util.cpp
M libs/libarchfpga/src/physical_types_util.h
M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h
A libs/libarchfpga/src/write_models_bb.cpp
A libs/libarchfpga/src/write_models_bb.h
M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/liblog/CMakeLists.txt
M libs/libpugiutil/CMakeLists.txt
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M libs/libpugiutil/src/pugixml_util.hpp
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A libs/librrgraph/src/base/SCHEMA_GENERATOR.md
A libs/librrgraph/src/base/check_rr_graph.cpp
A libs/librrgraph/src/base/check_rr_graph.h
A libs/librrgraph/src/base/get_parallel_segs.cpp
A libs/librrgraph/src/base/get_parallel_segs.h
M libs/librrgraph/src/base/rr_edge.h
M libs/librrgraph/src/base/rr_graph_builder.cpp
M libs/librrgraph/src/base/rr_graph_builder.h
A libs/librrgraph/src/base/rr_graph_cost.h
M libs/librrgraph/src/base/rr_graph_fwd.h
M libs/librrgraph/src/base/rr_graph_obj.cpp
M libs/librrgraph/src/base/rr_graph_storage.cpp
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A libs/librrgraph/src/base/rr_graph_storage_utils.h
A libs/librrgraph/src/base/rr_graph_type.h
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M libs/librrgraph/src/base/rr_graph_view.h
A libs/librrgraph/src/base/rr_metadata.cpp
A libs/librrgraph/src/base/rr_metadata.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h
A libs/librrgraph/src/base/rr_rc_data.cpp
A libs/librrgraph/src/base/rr_rc_data.h
M libs/librrgraph/src/base/rr_spatial_lookup.cpp
M libs/librrgraph/src/base/rr_spatial_lookup.h
A libs/librrgraph/src/io/gen/README.gen.md
A libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
A libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
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A libs/librrgraph/src/io/rr_graph.xsd
A libs/librrgraph/src/io/rr_graph_reader.cpp
A libs/librrgraph/src/io/rr_graph_reader.h
A libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
A libs/librrgraph/src/io/rr_graph_writer.cpp
A libs/librrgraph/src/io/rr_graph_writer.h
A libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp
A libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h
A libs/librrgraph/src/utils/describe_rr_node.cpp
A libs/librrgraph/src/utils/describe_rr_node.h
M libs/librtlnumber/CMakeLists.txt
M libs/librtlnumber/src/include/internal_bits.hpp
M libs/librtlnumber/src/include/rtl_utils.hpp
M libs/librtlnumber/src/rtl_int.cpp
M libs/libvqm/CMakeLists.txt
M libs/libvqm/vqm_common.c
M libs/libvqm/vqm_dll.cpp
M libs/libvqm/vqm_dll.h
M libs/libvqm/vqm_parser.y
M libs/libvtrcapnproto/extended_map_lookahead.capnp
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A libs/libvtrcapnproto/intra_cluster_serdes.h
M libs/libvtrcapnproto/map_lookahead.capnp
M libs/libvtrcapnproto/matrix.capnp
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M libs/libvtrutil/cmake/modules/configure_version.cmake
A libs/libvtrutil/src/specrand.cpp
A libs/libvtrutil/src/specrand.h
A libs/libvtrutil/src/tl_optional.hpp
A libs/libvtrutil/src/vpr_error.cpp
A libs/libvtrutil/src/vpr_error.h
M libs/libvtrutil/src/vtr_array_view.h
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_bimap.h
M libs/libvtrutil/src/vtr_cache.h
M libs/libvtrutil/src/vtr_dynamic_bitset.h
M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M libs/libvtrutil/src/vtr_list.cpp
M libs/libvtrutil/src/vtr_memory.cpp
M libs/libvtrutil/src/vtr_ndmatrix.h
A libs/libvtrutil/src/vtr_optional.h
M libs/libvtrutil/src/vtr_pair_util.h
M libs/libvtrutil/src/vtr_ragged_matrix.h
M libs/libvtrutil/src/vtr_random.cpp
M libs/libvtrutil/src/vtr_range.h
M libs/libvtrutil/src/vtr_string_interning.h
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M libs/libvtrutil/src/vtr_strong_id_range.h
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A odin_ii/Makefile
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A odin_ii/regression_test/benchmark/task/koios/koios_large/synthesis_result.json
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A odin_ii/regression_test/benchmark/task/koios/koios_large_no_hb/synthesis_result.json
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A odin_ii/regression_test/benchmark/task/mixing_optimization/config_file_half/config_file_half.xml
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A odin_ii/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json
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A odin_ii/regression_test/benchmark/task/vtr/synthesis_result.json
A odin_ii/regression_test/benchmark/task/vtr/task.conf
A odin_ii/regression_test/benchmark/third_party/.gitignore
A odin_ii/regression_test/benchmark/third_party/SymbiFlow/build.sh
A odin_ii/regression_test/benchmark/third_party/SymbiFlow/task.mk
A odin_ii/regression_test/benchmark/verilog/FIR/SOURCE.txt
A odin_ii/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20.v
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A odin_ii/regression_test/benchmark/verilog/common/div.v
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A odin_ii/regression_test/benchmark/verilog/common/dlatch.v
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A odin_ii/regression_test/benchmark/verilog/common/nr.v
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A odin_ii/regression_test/benchmark/verilog/common/sdff.v
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A odin_ii/regression_test/benchmark/verilog/common/shiftx.v
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A odin_ii/regression_test/benchmark/verilog/common/sr.v
A odin_ii/regression_test/benchmark/verilog/common/sub.v
A odin_ii/regression_test/benchmark/verilog/full/CRC33_D264.v
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A odin_ii/regression_test/benchmark/verilog/full/LU8PEEng.v
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A odin_ii/regression_test/benchmark/verilog/full/bm_DL_four_bit_adder_continuous_assign_using_vectors.v
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A odin_ii/regression_test/benchmark/verilog/full/bm_sfifo_rtl_odin_input
A odin_ii/regression_test/benchmark/verilog/full/bm_sfifo_rtl_odin_output
A odin_ii/regression_test/benchmark/verilog/full/bm_sfifo_rtl_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/bm_sfifo_rtl_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_18_18_18.v
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_18_18_18_odin_input
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_18_18_18_odin_output
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_18_18_18_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_18_18_18_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_8_8_8.v
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_8_8_8_odin_input
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_8_8_8_odin_output
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_8_8_8_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/cf_cordic_v_8_8_8_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fft_256_8.v
A odin_ii/regression_test/benchmark/verilog/full/cf_fft_256_8_odin_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fft_256_8_odin_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fft_256_8_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fft_256_8_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_24_16_16.v
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_24_16_16_odin_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_24_16_16_odin_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_24_16_16_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_24_16_16_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_3_8_8.v
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_3_8_8_odin_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_3_8_8_odin_output
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_3_8_8_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/cf_fir_3_8_8_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/ch_intrinsics.v
A odin_ii/regression_test/benchmark/verilog/full/ch_intrinsics_odin_input
A odin_ii/regression_test/benchmark/verilog/full/ch_intrinsics_odin_output
A odin_ii/regression_test/benchmark/verilog/full/ch_intrinsics_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/ch_intrinsics_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/diffeq1.v
A odin_ii/regression_test/benchmark/verilog/full/diffeq1_odin_input
A odin_ii/regression_test/benchmark/verilog/full/diffeq1_odin_output
A odin_ii/regression_test/benchmark/verilog/full/diffeq1_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/diffeq1_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/diffeq2.v
A odin_ii/regression_test/benchmark/verilog/full/diffeq2_odin_input
A odin_ii/regression_test/benchmark/verilog/full/diffeq2_odin_output
A odin_ii/regression_test/benchmark/verilog/full/diffeq2_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/diffeq2_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/fir_scu_rtl_restructured_for_cmm_exp.v
A odin_ii/regression_test/benchmark/verilog/full/fir_scu_rtl_restructured_for_cmm_exp_odin_input
A odin_ii/regression_test/benchmark/verilog/full/fir_scu_rtl_restructured_for_cmm_exp_odin_output
A odin_ii/regression_test/benchmark/verilog/full/fir_scu_rtl_restructured_for_cmm_exp_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/fir_scu_rtl_restructured_for_cmm_exp_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/iir1.v
A odin_ii/regression_test/benchmark/verilog/full/iir1_odin_input
A odin_ii/regression_test/benchmark/verilog/full/iir1_odin_output
A odin_ii/regression_test/benchmark/verilog/full/iir1_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/iir1_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/iir_no_combinational.v
A odin_ii/regression_test/benchmark/verilog/full/iir_no_combinational_odin_input
A odin_ii/regression_test/benchmark/verilog/full/iir_no_combinational_odin_output
A odin_ii/regression_test/benchmark/verilog/full/iir_no_combinational_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/iir_no_combinational_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/matmul.v
A odin_ii/regression_test/benchmark/verilog/full/matmul_odin_input
A odin_ii/regression_test/benchmark/verilog/full/matmul_odin_output
A odin_ii/regression_test/benchmark/verilog/full/matmul_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/matmul_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/mcml.v
A odin_ii/regression_test/benchmark/verilog/full/mcml_odin_input
A odin_ii/regression_test/benchmark/verilog/full/mcml_odin_output
A odin_ii/regression_test/benchmark/verilog/full/mcml_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/mcml_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/memory_controller.v
A odin_ii/regression_test/benchmark/verilog/full/memory_controller_odin_input
A odin_ii/regression_test/benchmark/verilog/full/memory_controller_odin_output
A odin_ii/regression_test/benchmark/verilog/full/memory_controller_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/memory_controller_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/mkPktMerge.v
A odin_ii/regression_test/benchmark/verilog/full/mkPktMerge_odin_input
A odin_ii/regression_test/benchmark/verilog/full/mkPktMerge_odin_output
A odin_ii/regression_test/benchmark/verilog/full/mkPktMerge_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/mkPktMerge_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/oc54_cpu.v
A odin_ii/regression_test/benchmark/verilog/full/oc54_cpu_odin_input
A odin_ii/regression_test/benchmark/verilog/full/oc54_cpu_odin_output
A odin_ii/regression_test/benchmark/verilog/full/oc54_cpu_yosys_input
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A odin_ii/regression_test/benchmark/verilog/full/paj_framebuftop_hierarchy_no_mem_no_combinational.v
A odin_ii/regression_test/benchmark/verilog/full/paj_framebuftop_hierarchy_no_mem_no_combinational_odin_input
A odin_ii/regression_test/benchmark/verilog/full/paj_framebuftop_hierarchy_no_mem_no_combinational_odin_output
A odin_ii/regression_test/benchmark/verilog/full/paj_framebuftop_hierarchy_no_mem_no_combinational_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/paj_framebuftop_hierarchy_no_mem_no_combinational_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/sha.v
A odin_ii/regression_test/benchmark/verilog/full/sha_odin_input
A odin_ii/regression_test/benchmark/verilog/full/sha_odin_output
A odin_ii/regression_test/benchmark/verilog/full/sha_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/sha_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision0.v
A odin_ii/regression_test/benchmark/verilog/full/stereovision0_odin_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision0_odin_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision0_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision0_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision1.v
A odin_ii/regression_test/benchmark/verilog/full/stereovision1_odin_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision1_odin_output
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A odin_ii/regression_test/benchmark/verilog/full/stereovision1_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision2.v
A odin_ii/regression_test/benchmark/verilog/full/stereovision2_odin_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision2_odin_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision2_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision2_yosys_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision3.v
A odin_ii/regression_test/benchmark/verilog/full/stereovision3_odin_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision3_odin_output
A odin_ii/regression_test/benchmark/verilog/full/stereovision3_yosys_input
A odin_ii/regression_test/benchmark/verilog/full/stereovision3_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/.generic/range_any_width_binary_test.v
A odin_ii/regression_test/benchmark/verilog/keywords/.generic/range_any_width_unary_test.v
A odin_ii/regression_test/benchmark/verilog/keywords/.generic/replicate_any_width_binary_test.v
A odin_ii/regression_test/benchmark/verilog/keywords/.generic/replicate_any_width_unary_test.v
A odin_ii/regression_test/benchmark/verilog/keywords/.generic/wire_test.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_asterisk_event.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_asterisk_event_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_asterisk_event_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_asterisk_event_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_asterisk_event_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_clk.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_clk_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_clk_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_clk_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_clk_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_lone_asterisk.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_lone_asterisk_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_lone_asterisk_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_lone_asterisk_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_lone_asterisk_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_or_event.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_or_event_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_or_event_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_or_event_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_or_event_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_posedge_negedge.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_posedge_negedge_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_posedge_negedge_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_posedge_negedge_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/always_posedge_negedge_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/case_default.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/case_default_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/case_default_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/case_default_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/case_default_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/posedge.v
A odin_ii/regression_test/benchmark/verilog/keywords/always/posedge_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/posedge_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/always/posedge_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/always/posedge_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_indexed_port.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_indexed_port_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_indexed_port_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_indexed_port_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_indexed_port_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_wire.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_wire_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_wire_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_wire_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/and_wire_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_int_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_int_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_int_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_int_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_int_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_ultra_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_ultra_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_ultra_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_ultra_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_ultra_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/range_and_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_int_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_int_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_int_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_int_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_int_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_ultra_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_ultra_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_ultra_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_ultra_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_ultra_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/and/replicate_and_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign.vh
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_int_wide.v
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A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_int_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_int_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_int_wide_yosys_output
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A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wide_yosys_output
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A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wire_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wire_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wire_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/assign/assign_wire_yosys_output
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A odin_ii/regression_test/benchmark/verilog/keywords/automatic/recursive_function_odin_input
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A odin_ii/regression_test/benchmark/verilog/keywords/begin_end/case_default.v
A odin_ii/regression_test/benchmark/verilog/keywords/begin_end/case_default_odin_input
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A odin_ii/regression_test/benchmark/verilog/keywords/begin_end/posedge_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/buf/buf_indexed_port.vh
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A odin_ii/regression_test/benchmark/verilog/keywords/localparam/parameter_define_localparam.v
A odin_ii/regression_test/benchmark/verilog/keywords/localparam/parameter_define_localparam_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/localparam/parameter_define_localparam_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/localparam/parameter_define_localparam_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/localparam/parameter_define_localparam_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/macromodule/macromodules_modules.v
A odin_ii/regression_test/benchmark/verilog/keywords/macromodule/macromodules_modules_odin_input
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A odin_ii/regression_test/benchmark/verilog/keywords/macromodule/macromodules_modules_yosys_input
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A odin_ii/regression_test/benchmark/verilog/keywords/macromodule/multiple_macromodules.v
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A odin_ii/regression_test/benchmark/verilog/keywords/macromodule/repeated_macromodule_failure.v
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A odin_ii/regression_test/benchmark/verilog/keywords/module_endmodule/repeated_module_failure.v
A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_indexed_port.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_indexed_port_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_indexed_port_odin_output
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A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_wire.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_wire_odin_input
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A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_wire_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/nand_wire_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_int_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_int_wide_odin_input
R vpr/src/route/SCHEMA_GENERATOR.md
R vpr/src/route/check_rr_graph.cpp
R vpr/src/route/gen/README.gen.md
R vpr/src/route/rr_graph.xsd
R vpr/src/route/rr_graph_uxsdcxx_serializer.h
R vpr/src/route/rr_rc_data.h
R vpr/src/util/histogram.cpp
R vpr/src/util/histogram.h
R vpr/src/util/vpr_error.cpp
R vpr/src/util/vpr_error.h

Log Message:
-----------
Merge branch 'master' into absorb_buffer_typo


Commit: 31f60a5fc9e3ce14e5a8a50ba9846b5500943902
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31f60a5fc9e3ce14e5a8a50ba9846b5500943902
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------
Merge pull request #1919 from nbstrong/absorb_buffer_typo

Corrected typo of abosrb to absorb


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/121a16c57183...31f60a5fc9e3

To unsubscribe from these emails, change your notification settings at https://github.com/verilog-to-routing/vtr-verilog-to-routing/settings/notifications

[sara_mahmoudi]

Branch: refs/heads/diff_switches_for_inc_dec_wires

Commit: 443c2c80ef98ed84714050acd7757e758cee57d9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/443c2c80ef98ed84714050acd7757e758cee57d9
Author: sara_mahmoudi <sin2...@gmail.com>

Date: 2024-07-18 (Thu, 18 Jul 2024)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------

Merge branch 'master' into diff_switches_for_inc_dec_wires


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/4cea89ff9448...443c2c80ef98

[Amir Arjomand]

Branch: refs/heads/Yosys42

Home: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Commit: d2b306bddb986fdb76469190e60d71a847ba7b4a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d2b306bddb986fdb76469190e60d71a847ba7b4a
Author: Nicholas Strong <nichola...@gmail.com>
Date: 2021-11-18 (Thu, 18 Nov 2021)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------
Correcting typo of abosrb to absorb

Commit: a8009b288823ba982656f8bc22a27a20360f9fff
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a8009b288823ba982656f8bc22a27a20360f9fff
Author: trick2011 <tric...@users.noreply.github.com>
Date: 2022-03-14 (Mon, 14 Mar 2022)

Changed paths:
M BUILDING.md

Log Message:
-----------
Fixed wrong path for current directory

Commit: a915cfef559052981368121bb33d4811b8c41bf3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a915cfef559052981368121bb33d4811b8c41bf3
Author: trick2011 <tric...@users.noreply.github.com>
Date: 2022-12-17 (Sat, 17 Dec 2022)

Changed paths:

M .github/scripts/hostsetup.sh
M .github/scripts/install_dependencies.sh
R .github/workflows/large-tests.yml
M .github/workflows/test.yml
M .gitignore
M .readthedocs.yaml
M CMakeLists.txt
M Dockerfile
M Makefile
M ODIN_II/CMakeLists.txt
M ODIN_II/README.md
M ODIN_II/SRC/BLIFElaborate.cpp
M ODIN_II/SRC/BLIFReader.cpp
A ODIN_II/SRC/BitwiseOps.cpp
M ODIN_II/SRC/BlockMemories.cpp
M ODIN_II/SRC/GenericReader.cpp
M ODIN_II/SRC/VerilogWriter.cpp
M ODIN_II/SRC/YYosys.cpp
M ODIN_II/SRC/adders.cpp
M ODIN_II/SRC/enum_str.cpp
M ODIN_II/SRC/hard_blocks.cpp
A ODIN_II/SRC/include/BitwiseOps.hpp
M ODIN_II/SRC/include/BlockMemories.hpp
M ODIN_II/SRC/include/GenericIO.hpp
M ODIN_II/SRC/include/GenericWriter.hpp
M ODIN_II/SRC/include/YYosys.hpp
M ODIN_II/SRC/include/config_t.h
M ODIN_II/SRC/include/odin_error.h
M ODIN_II/SRC/include/odin_globals.h
M ODIN_II/SRC/include/odin_types.h

M ODIN_II/SRC/include/odin_util.h
M ODIN_II/SRC/multipliers.cpp
M ODIN_II/SRC/netlist_cleanup.cpp
M ODIN_II/SRC/netlist_statistic.cpp
M ODIN_II/SRC/odin_ii.cpp
M ODIN_II/SRC/odin_util.cpp
M ODIN_II/SRC/partial_map.cpp

M ODIN_II/SRC/read_xml_config_file.cpp
M ODIN_II/main.cpp

M ODIN_II/regression_test/benchmark/task/fpu/hard_logic/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/if/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/initial/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/input/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/integer/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/output/simulation_result.json
M ODIN_II/regression_test/benchmark/task/keywords/signed_unsigned/simulation_result.json

M ODIN_II/regression_test/benchmark/task/koios/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/koios/task.conf

M ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json
M ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/common/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/common/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/full/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/full/synthesis_result.json

M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/always/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/and/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/and/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/automatic/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/buf/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/default/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/defparam/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/function_endfunction/synthesis_result.json
A ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/input/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/input/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/integer/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/macromodule/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/module_endmodule/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/nand/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/nand/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/nor/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/not/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/or/synthesis_result.json

A ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/output/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/output/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/reg/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/reg/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/signed_unsigned/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/signed_unsigned/synthesis_result.json

M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/specparam/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/while/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/xnor/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/keywords/xor/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/koios/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/koios/task.conf

M ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/micro/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/micro/synthesis_result.json

M ODIN_II/regression_test/benchmark/task/yosys+odin/operators/synthesis_result.json

M ODIN_II/regression_test/benchmark/task/yosys+odin/syntax/simulation_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/syntax/synthesis_result.json
M ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

M ODIN_II/regression_test/benchmark/verilog/keywords/input/multiple_declarations_yosys_input
M ODIN_II/regression_test/benchmark/verilog/keywords/input/multiple_declarations_yosys_output
M ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_input
M ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match1_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/micro/bm_match4_str_arch_yosys_output
M ODIN_II/regression_test/benchmark/verilog/syntax/expression_in_chain_modules.v
M ODIN_II/regression_test/benchmark/verilog/syntax/expression_in_chain_modules_yosys_output
M ODIN_II/regression_test/benchmark/verilog/syntax/mix_expression_in_module_port_nested.v
M ODIN_II/regression_test/parse_result/conf/synth.toml
M ODIN_II/regression_test/tools/run_yosys.sh
M ODIN_II/regression_test/tools/synth.tcl
A ODIN_II/techlib/aldff2dff.v
A ODIN_II/techlib/aldffe2dff.v
M ODIN_II/verify_odin.sh
M README.developers.md
M README.md
M abc/src/misc/util/abc_global.h
R cmake/modules/FindTBB.cmake
A comparison_output.xlsx
M dev/pylint_check.py
M dev/subtree_config.xml
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/mapping.rst

A doc/src/api/vprinternals/draw_files.rst
A doc/src/api/vprinternals/draw_structs.rst
A doc/src/api/vprinternals/index.rst

A doc/src/api/vprinternals/vpr_ui.rst
M doc/src/arch/reference.rst
M doc/src/conf.py

A doc/src/dev/eval_qor/action_button.png
A doc/src/dev/eval_qor/artifact.png
A doc/src/dev/eval_qor/cancel_workflow.png
A doc/src/dev/eval_qor/parse_result_dir.png
A doc/src/dev/eval_qor/re_run_tests.png
A doc/src/dev/eval_qor/test.png

A doc/src/dev/tutorials/edit_vpr_ui.rst
M doc/src/dev/tutorials/index.rst
M doc/src/index.rst
M doc/src/odin/quickstart.md
M doc/src/odin/user_guide.md
M doc/src/vpr/command_line_usage.rst
M doc/src/vpr/file_formats.rst
M doc/src/vpr/graphics.rst
M doc/src/vpr/index.rst
A doc/src/vpr/placement_constraints.rst
M doc/src/vtr/benchmarks.rst
M doc/src/vtr/parse_vtr_task.rst
M doc/src/vtr/run_vtr_flow.rst
M doc/src/vtr/run_vtr_task.rst
M doc/src/vtr/tasks.rst
M doc/src/yosys+odin/dev_guide/contributing.rst
M doc/src/yosys+odin/quickstart.rst
M doc/src/yosys+odin/user_guide.rst
M doc/src/yosys/dev_guide.rst
M doc/src/yosys/quickstart.rst
M doc/src/yosys/structure.rst
M install_apt_packages.sh

R libs/EXTERNAL/libtatum/cmake/modules/FindTBB.cmake
M libs/EXTERNAL/libtatum/libtatum/CMakeLists.txt
M libs/EXTERNAL/libyosys/.gitattributes
A libs/EXTERNAL/libyosys/.gitcommit
A libs/EXTERNAL/libyosys/.github/ISSUE_TEMPLATE/bug_report.yml
A libs/EXTERNAL/libyosys/.github/ISSUE_TEMPLATE/config.yml
A libs/EXTERNAL/libyosys/.github/ISSUE_TEMPLATE/feature_request.yml
R libs/EXTERNAL/libyosys/.github/issue_template.md
A libs/EXTERNAL/libyosys/.github/workflows/codeql.yml
A libs/EXTERNAL/libyosys/.github/workflows/deprecated.yml
A libs/EXTERNAL/libyosys/.github/workflows/emcc.yml
A libs/EXTERNAL/libyosys/.github/workflows/test-linux.yml
A libs/EXTERNAL/libyosys/.github/workflows/test-macos.yml
R libs/EXTERNAL/libyosys/.github/workflows/test.yml
M libs/EXTERNAL/libyosys/.github/workflows/version.yml
M libs/EXTERNAL/libyosys/.github/workflows/vs.yml
M libs/EXTERNAL/libyosys/.gitignore
M libs/EXTERNAL/libyosys/CHANGELOG
M libs/EXTERNAL/libyosys/CMakeLists.txt
M libs/EXTERNAL/libyosys/CODEOWNERS
M libs/EXTERNAL/libyosys/Makefile
M libs/EXTERNAL/libyosys/README.md
M libs/EXTERNAL/libyosys/backends/aiger/aiger.cc
M libs/EXTERNAL/libyosys/backends/aiger/xaiger.cc
M libs/EXTERNAL/libyosys/backends/blif/blif.cc
M libs/EXTERNAL/libyosys/backends/btor/btor.cc
M libs/EXTERNAL/libyosys/backends/cxxrtl/cxxrtl.h
M libs/EXTERNAL/libyosys/backends/cxxrtl/cxxrtl_backend.cc
M libs/EXTERNAL/libyosys/backends/edif/edif.cc
M libs/EXTERNAL/libyosys/backends/firrtl/firrtl.cc
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M libs/EXTERNAL/libyosys/backends/json/json.cc

R libs/EXTERNAL/libyosys/backends/protobuf/.gitignore
R libs/EXTERNAL/libyosys/backends/protobuf/Makefile.inc
R libs/EXTERNAL/libyosys/backends/protobuf/protobuf.cc

M libs/EXTERNAL/libyosys/backends/rtlil/rtlil_backend.cc
M libs/EXTERNAL/libyosys/backends/smt2/Makefile.inc
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M libs/EXTERNAL/libyosys/backends/smv/smv.cc
M libs/EXTERNAL/libyosys/backends/verilog/verilog_backend.cc
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A libs/EXTERNAL/libyosys/techlibs/xilinx/brams_xcv.txt
A libs/EXTERNAL/libyosys/techlibs/xilinx/brams_xcv_map.v
M libs/EXTERNAL/libyosys/techlibs/xilinx/cells_map.v
M libs/EXTERNAL/libyosys/techlibs/xilinx/cells_xtra.py
M libs/EXTERNAL/libyosys/techlibs/xilinx/cells_xtra.v

R libs/EXTERNAL/libyosys/techlibs/xilinx/lut4_lutrams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/lut6_lutrams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_map.v

A libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_xc5v.txt
A libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_xc5v_map.v
A libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_xcu.txt
A libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_xcv.txt
A libs/EXTERNAL/libyosys/techlibs/xilinx/lutrams_xcv_map.v
M libs/EXTERNAL/libyosys/techlibs/xilinx/synth_xilinx.cc
A libs/EXTERNAL/libyosys/techlibs/xilinx/urams.txt
A libs/EXTERNAL/libyosys/techlibs/xilinx/urams_map.v

R libs/EXTERNAL/libyosys/techlibs/xilinx/xc2v_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc2v_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc3sa_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc3sda_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc6s_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc6s_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc7_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xc7_xcu_brams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcu_brams_map.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcup_urams.txt
R libs/EXTERNAL/libyosys/techlibs/xilinx/xcup_urams_map.v

A libs/EXTERNAL/libyosys/tests/arch/anlogic/blockram.ys
M libs/EXTERNAL/libyosys/tests/arch/anlogic/lutram.ys
M libs/EXTERNAL/libyosys/tests/arch/common/adffs.v
M libs/EXTERNAL/libyosys/tests/arch/common/dffs.v
M libs/EXTERNAL/libyosys/tests/arch/common/shifter.v
A libs/EXTERNAL/libyosys/tests/arch/ecp5/bug2731.ys
M libs/EXTERNAL/libyosys/tests/arch/ecp5/memories.ys
M libs/EXTERNAL/libyosys/tests/arch/efinix/lutram.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/.gitignore
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A libs/EXTERNAL/libyosys/tests/arch/gatemate/dffs.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/fsm.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/gen_luttrees.py
A libs/EXTERNAL/libyosys/tests/arch/gatemate/latches.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/logic.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/luttrees.v
A libs/EXTERNAL/libyosys/tests/arch/gatemate/luttrees.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/memory.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/mul.v
A libs/EXTERNAL/libyosys/tests/arch/gatemate/mul.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/mux.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/run-test.sh
A libs/EXTERNAL/libyosys/tests/arch/gatemate/shifter.ys
A libs/EXTERNAL/libyosys/tests/arch/gatemate/tribuf.ys
M libs/EXTERNAL/libyosys/tests/arch/gowin/lutram.ys
M libs/EXTERNAL/libyosys/tests/arch/gowin/tribuf.ys
M libs/EXTERNAL/libyosys/tests/arch/ice40/.gitignore
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M libs/EXTERNAL/libyosys/tests/arch/ice40/ice40_opt.ys
M libs/EXTERNAL/libyosys/tests/arch/ice40/memories.ys
M libs/EXTERNAL/libyosys/tests/arch/intel_alm/blockram.ys
M libs/EXTERNAL/libyosys/tests/arch/intel_alm/counter.ys
M libs/EXTERNAL/libyosys/tests/arch/machxo2/mux.ys
M libs/EXTERNAL/libyosys/tests/arch/machxo2/tribuf.ys
M libs/EXTERNAL/libyosys/tests/arch/nexus/blockram.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/abc9_dff.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/attributes_test.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/blockram.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/fsm.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/lutram.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/opt_lut_ins.ys
M libs/EXTERNAL/libyosys/tests/arch/xilinx/tribuf.sh
M libs/EXTERNAL/libyosys/tests/arch/xilinx/xilinx_dffopt.ys
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A libs/EXTERNAL/libyosys/tests/blif/bug3385.ys
M libs/EXTERNAL/libyosys/tests/bram/run-single.sh
M libs/EXTERNAL/libyosys/tests/gen-tests-makefile.sh
A libs/EXTERNAL/libyosys/tests/memlib/.gitignore
A libs/EXTERNAL/libyosys/tests/memlib/generate.py
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sdp.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sdp.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sdp_1clk.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sdp_1clk.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sp.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_sp.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_tdp.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_block_tdp.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_lut.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_lut.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_read.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_read.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_sdp.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_sdp.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_sp.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_sp.v
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_write.txt
A libs/EXTERNAL/libyosys/tests/memlib/memlib_wide_write.v
A libs/EXTERNAL/libyosys/tests/memlib/run-test.sh
A libs/EXTERNAL/libyosys/tests/memories/read_arst.v
M libs/EXTERNAL/libyosys/tests/memories/read_two_mux.v
M libs/EXTERNAL/libyosys/tests/memories/run-test.sh
A libs/EXTERNAL/libyosys/tests/memories/trans_addr_enable.v
A libs/EXTERNAL/libyosys/tests/memories/trans_sdp.v
A libs/EXTERNAL/libyosys/tests/memories/trans_sp.v
A libs/EXTERNAL/libyosys/tests/memories/wide_all.v
A libs/EXTERNAL/libyosys/tests/memories/wide_read_async.v
A libs/EXTERNAL/libyosys/tests/memories/wide_read_mixed.v
A libs/EXTERNAL/libyosys/tests/memories/wide_read_sync.v
A libs/EXTERNAL/libyosys/tests/memories/wide_read_trans.v
A libs/EXTERNAL/libyosys/tests/memories/wide_thru_priority.v
A libs/EXTERNAL/libyosys/tests/memories/wide_write.v
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M libs/EXTERNAL/libyosys/tests/opt/opt_clean_mem.ys
M libs/EXTERNAL/libyosys/tests/opt/opt_dff_en.ys
M libs/EXTERNAL/libyosys/tests/opt/opt_dff_mux.ys
M libs/EXTERNAL/libyosys/tests/opt/opt_dff_qd.ys
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A libs/EXTERNAL/libyosys/tests/proc/bug2962.ys
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A libs/EXTERNAL/libyosys/tests/sat/grom_cpu.v
A libs/EXTERNAL/libyosys/tests/sat/ram_memory.v
A libs/EXTERNAL/libyosys/tests/sat/sim_counter.ys
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A libs/EXTERNAL/libyosys/tests/sim/adff.v
A libs/EXTERNAL/libyosys/tests/sim/adffe.v
A libs/EXTERNAL/libyosys/tests/sim/adlatch.v
A libs/EXTERNAL/libyosys/tests/sim/aldff.v
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A libs/EXTERNAL/libyosys/tests/sim/dlatch.v
A libs/EXTERNAL/libyosys/tests/sim/dlatchsr.v
A libs/EXTERNAL/libyosys/tests/sim/run-test.sh
A libs/EXTERNAL/libyosys/tests/sim/sdff.v
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A libs/EXTERNAL/libyosys/tests/sim/sdffe.v
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A libs/EXTERNAL/libyosys/tests/sim/tb/tb_adlatch.v
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A libs/EXTERNAL/libyosys/tests/sim/tb/tb_dffsr.v
A libs/EXTERNAL/libyosys/tests/sim/tb/tb_dlatch.v
A libs/EXTERNAL/libyosys/tests/sim/tb/tb_dlatchsr.v
A libs/EXTERNAL/libyosys/tests/sim/tb/tb_sdff.v
A libs/EXTERNAL/libyosys/tests/sim/tb/tb_sdffce.v
A libs/EXTERNAL/libyosys/tests/sim/tb/tb_sdffe.v
M libs/EXTERNAL/libyosys/tests/simple/attrib01_module.v
M libs/EXTERNAL/libyosys/tests/simple/attrib02_port_decl.v
M libs/EXTERNAL/libyosys/tests/simple/attrib03_parameter.v
M libs/EXTERNAL/libyosys/tests/simple/attrib04_net_var.v
M libs/EXTERNAL/libyosys/tests/simple/attrib05_port_conn.v.DISABLED
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M libs/EXTERNAL/libyosys/tests/simple/attrib07_func_call.v.DISABLED
M libs/EXTERNAL/libyosys/tests/simple/attrib08_mod_inst.v
M libs/EXTERNAL/libyosys/tests/simple/attrib09_case.v
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M libs/EXTERNAL/libyosys/tests/simple/const_branch_finish.v
M libs/EXTERNAL/libyosys/tests/simple/const_fold_func.v
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M libs/EXTERNAL/libyosys/tests/simple/defvalue.sv
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M libs/EXTERNAL/libyosys/tests/simple/genblk_dive.v
M libs/EXTERNAL/libyosys/tests/simple/genblk_order.v
M libs/EXTERNAL/libyosys/tests/simple/genblk_port_shadow.v
M libs/EXTERNAL/libyosys/tests/simple/hierarchy.v
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A libs/EXTERNAL/libyosys/tests/simple/signed_full_slice.v
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A libs/EXTERNAL/libyosys/tests/verilog/dynamic_range_lhs.sh
A libs/EXTERNAL/libyosys/tests/verilog/dynamic_range_lhs.v
A libs/EXTERNAL/libyosys/tests/verilog/for_decl_no_init.ys
A libs/EXTERNAL/libyosys/tests/verilog/for_decl_no_sv.ys
A libs/EXTERNAL/libyosys/tests/verilog/for_decl_shadow.sv
A libs/EXTERNAL/libyosys/tests/verilog/for_decl_shadow.ys
A libs/EXTERNAL/libyosys/tests/verilog/func_tern_hint.sv
A libs/EXTERNAL/libyosys/tests/verilog/func_tern_hint.ys
A libs/EXTERNAL/libyosys/tests/verilog/func_upto.sv
A libs/EXTERNAL/libyosys/tests/verilog/func_upto.ys
A libs/EXTERNAL/libyosys/tests/verilog/genfor_decl_no_init.ys
A libs/EXTERNAL/libyosys/tests/verilog/genfor_decl_no_sv.ys
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_1.sv
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_1.ys
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_2.sv
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_2.ys
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_3.sv
A libs/EXTERNAL/libyosys/tests/verilog/genvar_loop_decl_3.ys
A libs/EXTERNAL/libyosys/tests/verilog/net_types.sv
A libs/EXTERNAL/libyosys/tests/verilog/net_types.ys
A libs/EXTERNAL/libyosys/tests/verilog/past_signedness.ys
A libs/EXTERNAL/libyosys/tests/verilog/prefix.sv
A libs/EXTERNAL/libyosys/tests/verilog/prefix.ys
A libs/EXTERNAL/libyosys/tests/verilog/sign_array_query.ys
A libs/EXTERNAL/libyosys/tests/verilog/size_cast.sv
A libs/EXTERNAL/libyosys/tests/verilog/size_cast.ys
M libs/EXTERNAL/libyosys/tests/verilog/struct_access.sv
A libs/EXTERNAL/libyosys/tests/verilog/unbased_unsized_tern.sv
A libs/EXTERNAL/libyosys/tests/verilog/unbased_unsized_tern.ys
A libs/EXTERNAL/libyosys/tests/verilog/unreachable_case_sign.ys
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_util.cpp

M libs/libarchfpga/src/cad_types.h
A libs/libarchfpga/src/device_grid.cpp
A libs/libarchfpga/src/device_grid.h

A libs/libarchfpga/src/histogram.cpp
A libs/libarchfpga/src/histogram.h
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/parse_switchblocks.cpp
M libs/libarchfpga/src/physical_types.h
M libs/libarchfpga/src/physical_types_util.cpp
M libs/libarchfpga/src/physical_types_util.h
M libs/libarchfpga/src/read_fpga_interchange_arch.cpp

M libs/libarchfpga/src/read_xml_arch_file.cpp
A libs/libarchfpga/src/write_arch_bb.cpp
A libs/libarchfpga/src/write_models_bb.cpp
A libs/libarchfpga/src/write_models_bb.h
A libs/libarchfpga/test/main.cpp
A libs/libarchfpga/test/test_read_xml_arch_file.cpp

M libs/librrgraph/CMakeLists.txt
A libs/librrgraph/src/base/SCHEMA_GENERATOR.md
A libs/librrgraph/src/base/check_rr_graph.cpp
A libs/librrgraph/src/base/check_rr_graph.h
A libs/librrgraph/src/base/get_parallel_segs.cpp
A libs/librrgraph/src/base/get_parallel_segs.h

M libs/librrgraph/src/base/rr_graph_builder.h
A libs/librrgraph/src/base/rr_graph_cost.h

M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h
A libs/librrgraph/src/base/rr_graph_storage_utils.h
A libs/librrgraph/src/base/rr_graph_type.h
R libs/librrgraph/src/base/rr_graph_util.cpp
R libs/librrgraph/src/base/rr_graph_util.h
A libs/librrgraph/src/base/rr_graph_utils.cpp
M libs/librrgraph/src/base/rr_graph_utils.h
M libs/librrgraph/src/base/rr_graph_view.h
A libs/librrgraph/src/base/rr_metadata.cpp
A libs/librrgraph/src/base/rr_metadata.h

A libs/librrgraph/src/base/rr_rc_data.cpp
A libs/librrgraph/src/base/rr_rc_data.h

M libs/librrgraph/src/base/rr_spatial_lookup.h
A libs/librrgraph/src/io/gen/README.gen.md
A libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
A libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
A libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
A libs/librrgraph/src/io/rr_graph.xsd
A libs/librrgraph/src/io/rr_graph_reader.cpp
A libs/librrgraph/src/io/rr_graph_reader.h
A libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
A libs/librrgraph/src/io/rr_graph_writer.cpp
A libs/librrgraph/src/io/rr_graph_writer.h
A libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp
A libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h
A libs/librrgraph/src/utils/describe_rr_node.cpp
A libs/librrgraph/src/utils/describe_rr_node.h

M libs/libvqm/vqm_common.c
M libs/libvqm/vqm_dll.h
M libs/libvqm/vqm_parser.y
A libs/libvtrutil/src/vpr_error.cpp
A libs/libvtrutil/src/vpr_error.h
M libs/libvtrutil/src/vtr_bimap.h
M libs/libvtrutil/src/vtr_flat_map.h
M libs/libvtrutil/src/vtr_list.cpp
M libs/libvtrutil/src/vtr_memory.cpp
M requirements.txt
M utils/fasm/src/fasm.cpp
M utils/fasm/src/fasm.h
M utils/fasm/src/main.cpp
M utils/fasm/test/test_fasm.cpp
M utils/route_diag/src/main.cpp
M utils/vqm2blif/src/base/preprocess.h
M vpr/CMakeLists.txt
M vpr/main.ui

M vpr/src/base/SetupVPR.cpp
M vpr/src/base/SetupVPR.h
M vpr/src/base/ShowSetup.cpp

M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h
M vpr/src/base/clustered_netlist_fwd.h
R vpr/src/base/device_grid.cpp
R vpr/src/base/device_grid.h
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/netlist.h
M vpr/src/base/netlist.tpp
M vpr/src/base/netlist_writer.cpp
M vpr/src/base/netlist_writer.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h

M vpr/src/base/read_blif.cpp
M vpr/src/base/read_blif.h
M vpr/src/base/read_circuit.cpp

M vpr/src/base/read_interchange_netlist.cpp

M vpr/src/base/read_netlist.cpp
M vpr/src/base/read_netlist.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h

A vpr/src/base/setup_noc.cpp
A vpr/src/base/setup_noc.h
M vpr/src/base/stats.cpp

M vpr/src/base/stats.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h

M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.cpp
M vpr/src/base/vpr_types.h

M vpr/src/draw/breakpoint.h

M vpr/src/draw/buttons.cpp
M vpr/src/draw/buttons.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/draw.h
A vpr/src/draw/draw_basic.cpp
A vpr/src/draw/draw_basic.h

M vpr/src/draw/draw_color.h
M vpr/src/draw/draw_debug.cpp
M vpr/src/draw/draw_debug.h
A vpr/src/draw/draw_floorplanning.cpp
A vpr/src/draw/draw_floorplanning.h
M vpr/src/draw/draw_global.h

A vpr/src/draw/draw_mux.cpp
A vpr/src/draw/draw_mux.h
A vpr/src/draw/draw_noc.cpp
A vpr/src/draw/draw_noc.h
A vpr/src/draw/draw_rr.cpp
A vpr/src/draw/draw_rr.h
A vpr/src/draw/draw_rr_edges.cpp
A vpr/src/draw/draw_rr_edges.h
A vpr/src/draw/draw_searchbar.cpp
A vpr/src/draw/draw_searchbar.h
A vpr/src/draw/draw_toggle_functions.cpp
A vpr/src/draw/draw_toggle_functions.h
A vpr/src/draw/draw_triangle.cpp
A vpr/src/draw/draw_triangle.h
M vpr/src/draw/draw_types.cpp
M vpr/src/draw/draw_types.h

M vpr/src/draw/hsl.h

M vpr/src/draw/intra_logic_block.cpp
M vpr/src/draw/intra_logic_block.h
M vpr/src/draw/manual_moves.cpp

M vpr/src/draw/manual_moves.h
M vpr/src/draw/save_graphics.h
M vpr/src/draw/search_bar.cpp
M vpr/src/draw/search_bar.h
A vpr/src/draw/ui_setup.cpp
A vpr/src/draw/ui_setup.h
A vpr/src/noc/bfs_routing.cpp
A vpr/src/noc/bfs_routing.h
A vpr/src/noc/noc_data_types.h
A vpr/src/noc/noc_link.cpp
A vpr/src/noc/noc_link.h
A vpr/src/noc/noc_router.cpp
A vpr/src/noc/noc_router.h
A vpr/src/noc/noc_routing.h
A vpr/src/noc/noc_routing_algorithm_creator.cpp
A vpr/src/noc/noc_routing_algorithm_creator.h
A vpr/src/noc/noc_storage.cpp
A vpr/src/noc/noc_storage.h
A vpr/src/noc/noc_traffic_flows.cpp
A vpr/src/noc/noc_traffic_flows.h
A vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
A vpr/src/noc/read_xml_noc_traffic_flows_file.h
A vpr/src/noc/xy_routing.cpp
A vpr/src/noc/xy_routing.h
M vpr/src/pack/cluster.cpp
M vpr/src/pack/cluster.h
M vpr/src/pack/cluster_feasibility_filter.cpp
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/lb_type_rr_graph.cpp
M vpr/src/pack/output_clustering.cpp
M vpr/src/pack/pack.cpp
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/pb_type_graph.h
M vpr/src/pack/pb_type_graph_annotations.cpp
M vpr/src/pack/post_routing_pb_pin_fixup.cpp
M vpr/src/pack/post_routing_pb_pin_fixup.h

M vpr/src/pack/prepack.cpp
M vpr/src/pack/prepack.h
A vpr/src/pack/re_cluster.cpp
A vpr/src/pack/re_cluster.h
A vpr/src/pack/re_cluster_util.cpp
A vpr/src/pack/re_cluster_util.h
M vpr/src/place/analytic_placer.cpp

M vpr/src/place/cut_spreader.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/initial_placement.h
M vpr/src/place/place.cpp
M vpr/src/place/place.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/place/place_delay_model.cpp
M vpr/src/place/place_delay_model.h

M vpr/src/place/place_macro.cpp
M vpr/src/place/place_macro.h
M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h

M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/timing_place_lookup.h
M vpr/src/power/power.cpp
M vpr/src/power/power.h
M vpr/src/power/power_callibrate.cpp
M vpr/src/power/power_cmos_tech.cpp
M vpr/src/power/power_components.cpp
M vpr/src/power/power_sizing.cpp
M vpr/src/power/power_util.cpp
R vpr/src/route/SCHEMA_GENERATOR.md
M vpr/src/route/annotate_routing.cpp
M vpr/src/route/annotate_routing.h
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/bucket.cpp
M vpr/src/route/build_switchblocks.cpp
M vpr/src/route/cb_metrics.cpp
M vpr/src/route/check_route.cpp
M vpr/src/route/check_route.h
R vpr/src/route/check_rr_graph.cpp
R vpr/src/route/check_rr_graph.h

M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/clock_network_builders.h
M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h

R vpr/src/route/gen/README.gen.md
R vpr/src/route/gen/rr_graph_uxsdcxx.h
R vpr/src/route/gen/rr_graph_uxsdcxx_capnp.h
R vpr/src/route/gen/rr_graph_uxsdcxx_interface.h
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h
M vpr/src/route/route_export.h
M vpr/src/route/route_profiling.cpp
M vpr/src/route/route_timing.cpp
M vpr/src/route/route_timing.h
M vpr/src/route/route_tree_timing.cpp
M vpr/src/route/route_tree_timing.h
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead.h
M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_extended_map.h
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map.h
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph.h
R vpr/src/route/rr_graph.xsd

M vpr/src/route/rr_graph2.cpp
M vpr/src/route/rr_graph2.h
M vpr/src/route/rr_graph_area.cpp

M vpr/src/route/rr_graph_area.h

M vpr/src/route/rr_graph_clock.cpp
M vpr/src/route/rr_graph_clock.h
M vpr/src/route/rr_graph_indexed_data.cpp
M vpr/src/route/rr_graph_indexed_data.h

R vpr/src/route/rr_graph_reader.cpp
R vpr/src/route/rr_graph_reader.h
M vpr/src/route/rr_graph_sbox.cpp
M vpr/src/route/rr_graph_sbox.h
M vpr/src/route/rr_graph_timing_params.cpp
R vpr/src/route/rr_graph_util.cpp
R vpr/src/route/rr_graph_util.h
R vpr/src/route/rr_graph_uxsdcxx_serializer.h
R vpr/src/route/rr_graph_writer.cpp
R vpr/src/route/rr_graph_writer.h
R vpr/src/route/rr_metadata.cpp
R vpr/src/route/rr_metadata.h
R vpr/src/route/rr_rc_data.cpp
R vpr/src/route/rr_rc_data.h
M vpr/src/route/rr_types.h
M vpr/src/route/segment_stats.cpp
A vpr/src/timing/timing_fail_error.cpp
A vpr/src/timing/timing_fail_error.h
M vpr/src/timing/timing_util.cpp
M vpr/src/util/hash.cpp
M vpr/src/util/hash.h

R vpr/src/util/histogram.cpp
R vpr/src/util/histogram.h
R vpr/src/util/vpr_error.cpp
R vpr/src/util/vpr_error.h

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_bfs_routing.cpp
A vpr/test/test_clustered_netlist.cpp
M vpr/test/test_connection_router.cpp
M vpr/test/test_interchange_device.cpp
A vpr/test/test_noc_storage.cpp
A vpr/test/test_noc_traffic_flows.cpp
M vpr/test/test_place_delay_model_serdes.cpp

A vpr/test/test_post_verilog.cpp
A vpr/test/test_post_verilog_arch.xml
A vpr/test/test_post_verilog_i_gnd_o_unconnected.golden.v
A vpr/test/test_post_verilog_i_nets_o_unconnected.golden.v
A vpr/test/test_post_verilog_i_unconnected_o_nets.golden.v
A vpr/test/test_post_verilog_i_unconnected_o_unconnected.golden.v
A vpr/test/test_post_verilog_i_vcc_o_unconnected.golden.v

A vpr/test/test_read_xml_noc_traffic_flows_file.cpp

A vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp

A vpr/test/test_xy_routing.cpp
M vpr/test/testarch.device
A vpr/test/unconnected.eblif
M vpr/valgrind.supp
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.denser.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.densest.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.denser.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.densest.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.coupled.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.denser.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.densest.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.dsp_heavy.xml
M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.mem_heavy.xml

M vtr_flow/arch/COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
M vtr_flow/arch/Readme.txt
A vtr_flow/arch/noc/mesh_noc_topology/stratixiv_arch.timing_with_a_embedded_3X3_mesh_noc_topology.xml
A vtr_flow/arch/noc/non_mesh_noc_topology/k6_frac_N10_frac_chain_mem32K_40nm_with_a_embedded_star_noc_topology.xml
M vtr_flow/arch/timing/k4_N4_90nm.xml

A vtr_flow/arch/titan/stratixiv_arch_neuron.timing.xml
A vtr_flow/arch/xilinx/simple-7series.xml
A vtr_flow/arch/xilinx/simple-7series_diagonal.xml
M vtr_flow/benchmarks/hdl_include/include/memory_controller.v
A vtr_flow/benchmarks/noc/Readme.txt
A vtr_flow/benchmarks/noc/Test_Designs/test_design_for_noc_traffic_flows_feature/multiple_noc_routers.blif
A vtr_flow/benchmarks/noc/Test_Designs/test_design_for_noc_traffic_flows_feature/multiple_noc_routers.flows
A vtr_flow/benchmarks/system_verilog/f4pga/README.md
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/button_controller.sv
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/debounce.sv
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/display_control.sv
A vtr_flow/benchmarks/system_verilog/f4pga/button_controller/timer.sv
A vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/PWM.v
A vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/pulse_led.v
A vtr_flow/benchmarks/system_verilog/f4pga/timer/clock.sv
A vtr_flow/benchmarks/system_verilog/f4pga/timer/display_control.sv
A vtr_flow/benchmarks/system_verilog/f4pga/timer/modify_count.sv
A vtr_flow/benchmarks/system_verilog/f4pga/timer/time_counter.sv
A vtr_flow/benchmarks/system_verilog/f4pga/timer/timer.sv
A vtr_flow/benchmarks/system_verilog/fx68k/LICENSE
A vtr_flow/benchmarks/system_verilog/fx68k/README.md
A vtr_flow/benchmarks/system_verilog/fx68k/fx68k.sv
A vtr_flow/benchmarks/system_verilog/fx68k/fx68kAlu.sv
A vtr_flow/benchmarks/system_verilog/fx68k/microrom.mem
A vtr_flow/benchmarks/system_verilog/fx68k/nanorom.mem
A vtr_flow/benchmarks/system_verilog/fx68k/uaddrPla.sv
A vtr_flow/benchmarks/system_verilog/hdmi/.github/FUNDING.yml
A vtr_flow/benchmarks/system_verilog/hdmi/.github/workflows/testbench.yml
A vtr_flow/benchmarks/system_verilog/hdmi/.gitignore
A vtr_flow/benchmarks/system_verilog/hdmi/LICENSE-APACHE
A vtr_flow/benchmarks/system_verilog/hdmi/LICENSE-MIT
A vtr_flow/benchmarks/system_verilog/hdmi/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/README.md
A vtr_flow/benchmarks/system_verilog/hdmi/README_fr.md
A vtr_flow/benchmarks/system_verilog/hdmi/demo.gif
A vtr_flow/benchmarks/system_verilog/hdmi/requirements.txt
A vtr_flow/benchmarks/system_verilog/hdmi/sim/audio_clock_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/sim/audio_param_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/sim/spd_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/sim/top_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/sim/vsim.do
A vtr_flow/benchmarks/system_verilog/hdmi/src/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/src/audio_clock_regeneration_packet.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/audio_info_frame.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/audio_sample_packet.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/auxiliary_video_information_info_frame.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/hdmi.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/packet_assembler.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/packet_picker.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/serializer.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/source_product_description_info_frame.sv
A vtr_flow/benchmarks/system_verilog/hdmi/src/tmds_channel.sv
A vtr_flow/benchmarks/system_verilog/hdmi/test/audio_clock_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/test/audio_clock_tb/audio_clock_tb.sv
A vtr_flow/benchmarks/system_verilog/hdmi/test/audio_param_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/test/audio_param_tb/audio_param_tb.sv
A vtr_flow/benchmarks/system_verilog/hdmi/test/spd_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/test/spd_tb/spd_tb.sv
A vtr_flow/benchmarks/system_verilog/hdmi/test/top_tb/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/test/top_tb/pll.sv
A vtr_flow/benchmarks/system_verilog/hdmi/test/top_tb/top_tb.sv
A vtr_flow/benchmarks/system_verilog/hdmi/top/Manifest.py
A vtr_flow/benchmarks/system_verilog/hdmi/top/top.sv
M vtr_flow/benchmarks/tests/test_eblif.eblif
A vtr_flow/benchmarks/titan_other_blif/neuron_stratixiv_arch_timing.blif
M vtr_flow/benchmarks/verilog/koios/README.md
M vtr_flow/benchmarks/verilog/koios/attention_layer.v
M vtr_flow/benchmarks/verilog/koios/bnn.v
A vtr_flow/benchmarks/verilog/koios/bwave_like.fixed.large.v
A vtr_flow/benchmarks/verilog/koios/bwave_like.fixed.small.v
A vtr_flow/benchmarks/verilog/koios/bwave_like.float.large.v
A vtr_flow/benchmarks/verilog/koios/bwave_like.float.small.v
M vtr_flow/benchmarks/verilog/koios/clstm_like.large.v
M vtr_flow/benchmarks/verilog/koios/clstm_like.medium.v
M vtr_flow/benchmarks/verilog/koios/clstm_like.small.v
M vtr_flow/benchmarks/verilog/koios/complex_dsp_include.v
M vtr_flow/benchmarks/verilog/koios/conv_layer.v
M vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v
A vtr_flow/benchmarks/verilog/koios/deepfreeze.style1.sv
A vtr_flow/benchmarks/verilog/koios/deepfreeze.style2.sv
A vtr_flow/benchmarks/verilog/koios/deepfreeze.style3.sv
A vtr_flow/benchmarks/verilog/koios/dla_like.large.v
M vtr_flow/benchmarks/verilog/koios/dla_like.medium.v
M vtr_flow/benchmarks/verilog/koios/dla_like.small.v
A vtr_flow/benchmarks/verilog/koios/dnnweaver.v
M vtr_flow/benchmarks/verilog/koios/eltwise_layer.v
M vtr_flow/benchmarks/verilog/koios/gemm_layer.v
A vtr_flow/benchmarks/verilog/koios/hard_block_include.v
A vtr_flow/benchmarks/verilog/koios/hard_mem_include.v
A vtr_flow/benchmarks/verilog/koios/lenet.v
M vtr_flow/benchmarks/verilog/koios/lstm.v
A vtr_flow/benchmarks/verilog/koios/proxy.1.v
A vtr_flow/benchmarks/verilog/koios/proxy.2.v
A vtr_flow/benchmarks/verilog/koios/proxy.3.v
A vtr_flow/benchmarks/verilog/koios/proxy.4.v
A vtr_flow/benchmarks/verilog/koios/proxy.5.v
A vtr_flow/benchmarks/verilog/koios/proxy.6.v
A vtr_flow/benchmarks/verilog/koios/proxy.7.v
A vtr_flow/benchmarks/verilog/koios/proxy.8.v
M vtr_flow/benchmarks/verilog/koios/reduction_layer.v
M vtr_flow/benchmarks/verilog/koios/robot_rl.v
M vtr_flow/benchmarks/verilog/koios/softmax.v
M vtr_flow/benchmarks/verilog/koios/spmv.v
A vtr_flow/benchmarks/verilog/koios/tdarknet_like.large.v
A vtr_flow/benchmarks/verilog/koios/tdarknet_like.small.v
M vtr_flow/benchmarks/verilog/koios/test.v
R vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.medium.v
R vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.large.os.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.large.ws.v
R vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.small.os.v
R vtr_flow/benchmarks/verilog/koios/tpu_like.small.v
A vtr_flow/benchmarks/verilog/koios/tpu_like.small.ws.v
A vtr_flow/misc/yosyslib/synthesis.tcl
R vtr_flow/misc/yosyslib/synthesis.ys
A vtr_flow/misc/yosyslib/synthesis_parmys.tcl
M vtr_flow/misc/yosyslib/yosys_models.v
M vtr_flow/parse/parse_config/common/vpr.pack.txt
M vtr_flow/parse/parse_config/common/vpr.place.txt
M vtr_flow/parse/parse_config/timing/vpr.route_fixed_chan_width.txt
M vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width.txt
A vtr_flow/parse/pass_requirements/pass_requirements.timing_fail.txt
A vtr_flow/parse/pass_requirements/pass_requirements_vpr_custom_sb.txt
A vtr_flow/parse/qor_config/qor_vpr_custom_sb.txt
M vtr_flow/scripts/python_libs/vtr/__init__.py
M vtr_flow/scripts/python_libs/vtr/odin/odin.py
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py
M vtr_flow/scripts/python_libs/vtr/paths.py
M vtr_flow/scripts/python_libs/vtr/task.py
M vtr_flow/scripts/python_libs/vtr/util.py
M vtr_flow/scripts/python_libs/vtr/yosys/__init__.py
M vtr_flow/scripts/python_libs/vtr/yosys/yosys.py
M vtr_flow/scripts/qor_compare.py
M vtr_flow/scripts/run_vtr_flow.py
M vtr_flow/scripts/run_vtr_task.py
A vtr_flow/sdc/samples/H.sdc
A vtr_flow/sdc/samples/easy_pass_timing.sdc
A vtr_flow/sdc/samples/impossible_pass_timing.sdc
A vtr_flow/sdc/samples/neuron_stratixiv_arch_timing.sdc
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/symbiflow/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_ispd/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_custom_sb_diff_chan_width/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_custom_sb_diff_chan_width/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_custom_sb_diff_chan_width/stratixiv_arch.timing.100to75_xy_chan_ratio.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_complex_dsp/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_complex_dsp/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_ispd/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/half_blocks_half.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/one_big_partition.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan/sixteenth.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin_multi_arch/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin_multi_arch/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin_no_hard_block/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_yosys_odin_no_hard_block/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_support/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/golden_results.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_complex_dsp/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_complex_dsp/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_yosys_odin/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_yosys_odin/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_yosys_odin_no_hard_block/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_yosys_odin_no_hard_block/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys/FX68K/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys/f4pga_button_controller/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys/f4pga_pulse_width_led/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys/f4pga_timer/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys/hdmi/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_yosys/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/FX68K/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/f4pga_button_controller/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/f4pga_pulse_width_led/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/f4pga_timer/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/hdmi/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_yosys_odin/vtr_benchmarks/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/koios/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/koios/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/vtr_benchmarks/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/vtr_benchmarks/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into patch-1


Commit: 8f524fbe399236a082a75090ba79a89e8b104d55
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8f524fbe399236a082a75090ba79a89e8b104d55
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-02-12 (Mon, 12 Feb 2024)

Changed paths:
M vpr/src/base/vpr_api.cpp
M vpr/src/place/place_util.cpp

Log Message:
-----------
const ref and c_str


Commit: 5d01eb36925984ac1773487ebb7abba0f39e72ab
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d01eb36925984ac1773487ebb7abba0f39e72ab
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-02-12 (Mon, 12 Feb 2024)

Changed paths:
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
store movable blocks in placement context


Commit: 5a11f2bf52708815b74578ba5134b422a6ccdc5d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5a11f2bf52708815b74578ba5134b422a6ccdc5d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-02-12 (Mon, 12 Feb 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/place/move_utils.cpp

Log Message:
-----------
select random blocks from movable blocks


Commit: 433b495e2d29ea9dc1e962abb54f67cbcdb677ac
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/433b495e2d29ea9dc1e962abb54f67cbcdb677ac
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-02-12 (Mon, 12 Feb 2024)

Changed paths:
M vpr/src/base/read_place.cpp

Log Message:
-----------
make reading placement file more robust


Commit: 3d9ebdc26a4c0a0de15af0e2e384b95de25e02ba
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3d9ebdc26a4c0a0de15af0e2e384b95de25e02ba
Author: soheil <sohe...@gmail.com>
Date: 2024-02-24 (Sat, 24 Feb 2024)

Changed paths:
M doc/src/vpr/command_line_usage.rst
M libs/EXTERNAL/libargparse/argparse_test.cpp
M libs/libarchfpga/src/physical_types_util.h
M libs/librrgraph/src/base/rr_graph_storage.h
M libs/libvtrutil/src/vtr_dynamic_bitset.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist_utils.cpp
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/noc/noc_link.cpp
M vpr/src/noc/noc_link.h
M vpr/src/noc/noc_routing_algorithm_creator.cpp
M vpr/src/noc/noc_routing_algorithm_creator.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_checkpoint.h
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h
A vpr/src/route/DecompNetlistRouter.h
A vpr/src/route/DecompNetlistRouter.tpp
M vpr/src/route/ParallelNetlistRouter.h
M vpr/src/route/ParallelNetlistRouter.tpp
M vpr/src/route/SerialNetlistRouter.tpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h
M vpr/src/route/connection_router_interface.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/partition_tree.cpp
M vpr/src/route/partition_tree.h
M vpr/src/route/route.cpp
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h
M vpr/src/route/route_net.cpp
M vpr/src/route/route_net.h
M vpr/src/route/route_net.tpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_tree.h
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
A vpr/src/route/sink_sampling.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_xy_routing.cpp
M vtr_flow/parse/parse_config/vpr_noc.txt
M vtr_flow/scripts/python_libs/vtr/util.py

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: 03fce648c1ac2e76d0a2ec210a9ebf3e5b811f18
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/03fce648c1ac2e76d0a2ec210a9ebf3e5b811f18
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M .github/workflows/test.yml
M CMakeLists.txt
M libs/EXTERNAL/libargparse/README.md
M libs/EXTERNAL/libargparse/src/argparse.cpp
M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/librrgraph/CMakeLists.txt
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h
M libs/librrgraph/src/base/rr_graph_view.h
M libs/libvtrutil/CMakeLists.txt
M libs/libvtrutil/cmake/modules/configure_version.cmake
M libs/libvtrutil/src/vtr_util.cpp
M libs/libvtrutil/src/vtr_util.h
M libs/libvtrutil/test/test_array_view.cpp
M utils/fasm/CMakeLists.txt
M utils/vqm2blif/CMakeLists.txt
M utils/vqm2blif/src/base/cleanup.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/ShowSetup.h
M vpr/src/base/read_interchange_netlist.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw.cpp
M vpr/src/noc/bfs_routing.cpp
M vpr/src/noc/bfs_routing.h
A vpr/src/noc/channel_dependency_graph.cpp
A vpr/src/noc/channel_dependency_graph.h
A vpr/src/noc/negative_first_routing.cpp
A vpr/src/noc/negative_first_routing.h
M vpr/src/noc/noc_routing.h
M vpr/src/noc/noc_routing_algorithm_creator.cpp
M vpr/src/noc/noc_routing_algorithm_creator.h
M vpr/src/noc/noc_traffic_flows.cpp
M vpr/src/noc/noc_traffic_flows.h
A vpr/src/noc/north_last_routing.cpp
A vpr/src/noc/north_last_routing.h
A vpr/src/noc/odd_even_routing.cpp
A vpr/src/noc/odd_even_routing.h
A vpr/src/noc/turn_model_routing.cpp
A vpr/src/noc/turn_model_routing.h
A vpr/src/noc/west_first_routing.cpp
A vpr/src/noc/west_first_routing.h
M vpr/src/noc/xy_routing.cpp
M vpr/src/noc/xy_routing.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_transactions.cpp
M vpr/src/place/move_transactions.h
M vpr/src/place/move_utils.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h
M vpr/src/route/route_net.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_path_manager.cpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_utilization.cpp
M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/rr_graph.cpp
M vpr/test/test_bfs_routing.cpp
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_noc_traffic_flows.cpp
M vpr/test/test_xy_routing.cpp
M vtr_flow/arch/COFFE_22nm/stratix10_arch.xml
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_16_noc_2way_ring.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_noc_clique.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_noc_star.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_noc_star_no_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_12_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_24_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_2_bandwdiths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_31_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_3_bandwdiths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_4_bandwdiths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_32_star_4_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_4_noc_2way_ring.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_bucket_sort.fixed
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_bucket_sort.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_clique.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_gaussian_elimination.fixed
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_gaussian_elimination.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_genome_seq.fixed
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_genome_seq.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_page_rank.fixed
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_page_rank.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_12_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_24_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_2_bandwidths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_3_bandwidths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_40_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_4_bandwidths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_4_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_58_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_5_bandwidths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_63_latency_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_6_bandwidths.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_64_noc_star_no_constraints.flows
A vtr_flow/benchmarks/noc/Synthetic_Designs/congestion_traffic_flow_files/complex_8_noc_2way_ring.flows
M yosys/Makefile

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: 15cf98ed8a5259633d38787dee494292192cba2b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/15cf98ed8a5259633d38787dee494292192cba2b
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
address PR comments


Commit: 8bd04e46447b54800b92ad1fa63cb7cc858242c9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8bd04e46447b54800b92ad1fa63cb7cc858242c9
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/simpleRL_move_generator.cpp

Log Message:
-----------
add movable_blocks_per_type()


Commit: 14fd2dad34c9c0e4cbe2653b10773f04ac59f08b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/14fd2dad34c9c0e4cbe2653b10773f04ac59f08b
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-11 (Thu, 11 Apr 2024)

Changed paths:
M vpr/src/place/place.cpp

Log Message:
-----------
call create_move_generators() after initial_placement()


Commit: edfc3cc6e005cb0ea90c78d9f55b78f528369d73
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/edfc3cc6e005cb0ea90c78d9f55b78f528369d73
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-11 (Thu, 11 Apr 2024)

Changed paths:
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/place.cpp
M vpr/src/place/simpleRL_move_generator.cpp

Log Message:
-----------
remove blocks_per_type() from clustered_netlist


Commit: 0e0c633e902fe07371b1ae75505db4acc05774c9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0e0c633e902fe07371b1ae75505db4acc05774c9
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-16 (Tue, 16 Apr 2024)

Changed paths:
M vpr/src/place/simpleRL_move_generator.cpp

Log Message:
-----------
RL agents selects empty block type when all blocks are locked


Commit: a26f328eb39e1fd0f9bbe47980d9d6655613f4c3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a26f328eb39e1fd0f9bbe47980d9d6655613f4c3
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)

Changed paths:
M vpr/src/base/read_place.cpp

Log Message:
-----------
warning message to say why mismatches are ignored


Commit: 544d175271e727f1f47fa95810b5200b18bcc75a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/544d175271e727f1f47fa95810b5200b18bcc75a
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)

Changed paths:
M libs/libarchfpga/src/read_xml_arch_file.cpp
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/read_blif.cpp
M vpr/src/base/read_circuit.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/place/move_utils.cpp

Log Message:
-----------
remove unused #includes


Commit: ebabb0d6fb34668022cce3602879a52a31c16e15
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ebabb0d6fb34668022cce3602879a52a31c16e15
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)

Changed paths:
M .github/scripts/install_dependencies.sh
M CMakeLists.txt
M blifexplorer/CMakeLists.txt
M doc/src/vtr/benchmarks.rst
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libvtrutil/src/vtr_util.cpp
M libs/libvtrutil/src/vtr_util.h
M utils/fasm/src/fasm.cpp
M utils/fasm/src/fasm.h
M utils/fasm/src/fasm_utils.cpp
M utils/fasm/src/fasm_utils.h
M utils/vqm2blif/src/base/hard_block_recog.cpp
M utils/vqm2blif/src/base/preprocess.cpp
M utils/vqm2blif/src/base/vqm2blif_util.cpp
M vpr/src/base/read_blif.cpp
M vpr/src/base/vpr_api.cpp
M yosys/CMakeLists.txt

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: 419324ee87e7051ac890613424d0f80567859528
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/419324ee87e7051ac890613424d0f80567859528
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-05-01 (Wed, 01 May 2024)

Changed paths:
M doc/src/vpr/basic_flow.rst
M doc/src/vpr/command_line_usage.rst
M odin_ii/src/verilog/verilog_bison.y
M vpr/src/base/read_options.cpp

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: 2d34797c17aeee448989a2ec324ab70bba83ace0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d34797c17aeee448989a2ec324ab70bba83ace0
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-05-01 (Wed, 01 May 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

Log Message:
-----------
replace unordered_map with vector for storing movable blocks for each type


Commit: cfd9afa581142d14849e6809d00d7300e13a55b2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cfd9afa581142d14849e6809d00d7300e13a55b2
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-05-23 (Thu, 23 May 2024)

Changed paths:
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

Log Message:
-----------
Added option to select D-arity, turn on/off use of a new heap_elem which contains node cost to prevent unnecessary dereferecing, and turn on/off alignment for that struct


Commit: 0db85d9a612262aaad4737142292215da46033ce
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0db85d9a612262aaad4737142292215da46033ce
Author: Nathan Shreve <14270370...@users.noreply.github.com>
Date: 2024-05-23 (Thu, 23 May 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/CMakeLists.txt
M libs/libvtrutil/CMakeLists.txt

M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h

M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/SetupGrid.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/atom_netlist.cpp
M vpr/src/base/atom_netlist.h
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.cpp
M vpr/src/base/vpr_types.h

M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/manual_moves.cpp
M vpr/src/noc/noc_data_types.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h

M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp

M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/constraints_report.cpp
A vpr/src/pack/noc_aware_cluster_util.cpp
A vpr/src/pack/noc_aware_cluster_util.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/centroid_move_generator.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/directed_moves_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_noc_placment.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_generator.h

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/place_constraints.cpp
M vpr/src/place/simpleRL_move_generator.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
Merge branch 'verilog-to-routing:master' into improve_binary_heap


Commit: 6038ff6ca388b9a6a0765dc8951fe7df664218b6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6038ff6ca388b9a6a0765dc8951fe7df664218b6
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-05-28 (Tue, 28 May 2024)

Changed paths:
A binary_heap_profiler.py
A binary_heap_profiling_helper.cpp
A run_heap_tests.py
M vpr/src/route/binary_heap.h

Log Message:
-----------
Wrote scripts to help running tests and profile results


Commit: 3fde94915efc733665404d0da1bb29110e0525bd
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3fde94915efc733665404d0da1bb29110e0525bd
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-05-28 (Tue, 28 May 2024)

Changed paths:
A binary_heap_profiler.py
A binary_heap_profiling_helper.cpp
A run_heap_tests.py
M vpr/src/route/binary_heap.h

Log Message:
-----------
Wrote scripts to help running tests and profile results


Commit: 51f78a86885851be894f84483e92a8b3eb836533
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/51f78a86885851be894f84483e92a8b3eb836533
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-05-28 (Tue, 28 May 2024)

Changed paths:

Log Message:
-----------
Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: 5625dcb9712cb71cada84f46100790b304e9459d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5625dcb9712cb71cada84f46100790b304e9459d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-05-31 (Fri, 31 May 2024)

Changed paths:
M .github/workflows/containers.yml
M .github/workflows/labeler.yml
M .github/workflows/test.yml
M .gitmodules
M CMakeLists.txt
M Dockerfile
M README.developers.md
M blifexplorer/src/container.cpp
M blifexplorer/src/mainwindow.cpp
M dev/DOCKER_DEPLOY.md
M doc/src/quickstart/index.rst
M doc/src/tutorials/flow/basic_flow.rst
M doc/src/vpr/command_line_usage.rst
M libs/EXTERNAL/CMakeLists.txt
M libs/EXTERNAL/libtatum/.gitignore
M libs/EXTERNAL/libtatum/.travis.yml
M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.cpp
M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.hpp
M libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp
M libs/EXTERNAL/libtatum/scripts/reg_test.py

A libs/EXTERNAL/sockpp
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp

M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/echo_arch.cpp
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/physical_types.h

M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h

M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/libpugiutil/src/pugixml_util.cpp
M libs/libpugiutil/src/pugixml_util.hpp
M libs/librrgraph/src/base/rr_graph_obj.cpp
M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h
M libs/libvqm/vqm_dll.cpp
M libs/libvqm/vqm_parser.y
M libs/libvtrutil/CMakeLists.txt
M libs/libvtrutil/src/vtr_array_view.h

M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h

M libs/libvtrutil/src/vtr_ndmatrix.h
M libs/libvtrutil/src/vtr_ragged_matrix.h
M libs/libvtrutil/src/vtr_string_interning.h
M libs/libvtrutil/src/vtr_vector.h
M odin_ii/src/ast/ast_loop_unroll.cpp
M requirements.txt
M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/SetupGrid.cpp
M vpr/src/base/SetupGrid.h

M vpr/src/base/SetupVPR.cpp
M vpr/src/base/SetupVPR.h
M vpr/src/base/ShowSetup.cpp

M vpr/src/base/atom_netlist.cpp
M vpr/src/base/atom_netlist.h
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_interchange_netlist.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints.cpp

M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.cpp
M vpr/src/base/vpr_types.h

M vpr/src/draw/draw.cpp
M vpr/src/draw/draw_basic.cpp
M vpr/src/draw/draw_basic.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_rr.cpp
A vpr/src/draw/gtkcomboboxhelper.cpp
A vpr/src/draw/gtkcomboboxhelper.h
M vpr/src/draw/manual_moves.cpp
M vpr/src/noc/bfs_routing.h
M vpr/src/noc/noc_data_types.h
M vpr/src/noc/noc_link.cpp
M vpr/src/noc/noc_link.h
M vpr/src/noc/noc_router.cpp
M vpr/src/noc/noc_router.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h

M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp

M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/constraints_report.cpp
A vpr/src/pack/noc_aware_cluster_util.cpp
A vpr/src/pack/noc_aware_cluster_util.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/centroid_move_generator.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/cut_spreader.cpp
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/directed_moves_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_noc_placment.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_generator.h
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h
M vpr/src/place/placer_context.h
M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/place/simpleRL_move_generator.h
M vpr/src/place/static_move_generator.cpp
M vpr/src/place/static_move_generator.h
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp
M vpr/src/route/DecompNetlistRouter.tpp
M vpr/src/route/ParallelNetlistRouter.tpp
M vpr/src/route/SerialNetlistRouter.tpp
M vpr/src/route/cb_metrics.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/overuse_report.cpp
M vpr/src/route/route.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_utils.cpp
M vpr/src/route/route_utils.h
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead.h
M vpr/src/route/router_lookahead_compressed_map.cpp

M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_map_utils.h
M vpr/src/route/router_lookahead_sampling.cpp

M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph.h
A vpr/src/server/bytearray.h
A vpr/src/server/commconstants.h
A vpr/src/server/convertutils.cpp
A vpr/src/server/convertutils.h
A vpr/src/server/gateio.cpp
A vpr/src/server/gateio.h
A vpr/src/server/pathhelper.cpp
A vpr/src/server/pathhelper.h
A vpr/src/server/serverupdate.cpp
A vpr/src/server/serverupdate.h
A vpr/src/server/task.cpp
A vpr/src/server/task.h
A vpr/src/server/taskresolver.cpp
A vpr/src/server/taskresolver.h
A vpr/src/server/telegrambuffer.cpp
A vpr/src/server/telegrambuffer.h
A vpr/src/server/telegramframe.h
A vpr/src/server/telegramheader.cpp
A vpr/src/server/telegramheader.h
A vpr/src/server/telegramoptions.cpp
A vpr/src/server/telegramoptions.h
A vpr/src/server/telegramparser.cpp
A vpr/src/server/telegramparser.h
A vpr/src/server/zlibutils.cpp
A vpr/src/server/zlibutils.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_bfs_routing.cpp
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
A vpr/test/test_server_convertutils.cpp
A vpr/test/test_server_taskresolver.cpp
A vpr/test/test_server_telegrambuffer.cpp
A vpr/test/test_server_telegramoptions.cpp
A vpr/test/test_server_telegramparser.cpp
A vpr/test/test_server_zlibutils.cpp
M vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr_constraints.cpp
M vpr/test/test_xy_routing.cpp
M vtr_flow/arch/multi_die/README.md
M vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/arch/titan/stratix10_arch.timing.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: 8db689a6358a002f30b22deebe21c3b802d178ad
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8db689a6358a002f30b22deebe21c3b802d178ad
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/place/compressed_grid.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
add compressed_cluster_constraints


Commit: 6d94b754b9db164a8a198a075566c443862057ff
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6d94b754b9db164a8a198a075566c443862057ff
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/place/move_utils.cpp

Log Message:
-----------
update search_range in intersect_range_limit_with_floorplan_constraints()


Commit: 8a32b610c8c7cec6b100f4bf519aadb5809510be
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8a32b610c8c7cec6b100f4bf519aadb5809510be
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp

Log Message:
-----------
cluster_to_atoms() returns a reference


Commit: 3bb2e9d2ffa40342a1324b2936d215f7d120ffef
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3bb2e9d2ffa40342a1324b2936d215f7d120ffef
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

Log Message:
-----------
removed unused argument of intersect_range_limit_with_floorplan_constraints()


Commit: 976813b0d38fbf7780ae04ab0a0d0a776dc57630
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/976813b0d38fbf7780ae04ab0a0d0a776dc57630
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/base/vpr_context.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
add comments


Commit: 4c516ab952c476318f65c9c0c7bee2a5fdc310e5
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4c516ab952c476318f65c9c0c7bee2a5fdc310e5
Author: Hang Yan <ue...@outlook.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M README.developers.md

Log Message:
-----------
[Docs] Updated Profiling VTR Section in Developer Guide

Rewrote the existing Profiling VTR section, specifically the one using
GNU `gprof` tool.

Added another subsection to explain how to use the Linux `perf` tool to
profile VPR and visualize its output.


Commit: 72b4146c098ea702cc71914504e47da8e680bc9e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/72b4146c098ea702cc71914504e47da8e680bc9e
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------
pass block ids by value instead of reference


Commit: 788c9fd707e8ea9fbf44b08a944dbf0ade2029b9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/788c9fd707e8ea9fbf44b08a944dbf0ade2029b9
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/place/compressed_grid.h

Log Message:
-----------
fix grid_loc_to_compressed_loc_approx_round_up()


Commit: 5b20e718cf55b1bf2173db3313ddc5ff87bd4b7a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5b20e718cf55b1bf2173db3313ddc5ff87bd4b7a
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/place/compressed_grid.h

Log Message:
-----------
avoid duplicate code in grid_loc_to_compressed_loc_approx_round_down() and grid_loc_to_compressed_loc_approx_round_up()


Commit: 657325077a6e09bde37f51e7e2bd20463d3bbede
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/657325077a6e09bde37f51e7e2bd20463d3bbede
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------
removed unnecessary referneces


Commit: e9f5821cff2454524d22d5cc888598da8facd018
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e9f5821cff2454524d22d5cc888598da8facd018
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h

Log Message:
-----------
doxygen comments for GridTileLookup


Commit: 9438f73722a7e5b8baf943ffb85afc46e845f76d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9438f73722a7e5b8baf943ffb85afc46e845f76d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
doxygen comments for place_constraints.h


Commit: 8944b986a32f026cf19717205dc1827c4296be48
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8944b986a32f026cf19717205dc1827c4296be48
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-12 (Wed, 12 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------
[vpr][place] use simple place delay model by default


Commit: 817c833c0cb9ff3cd4b09052c71bcce601018439
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/817c833c0cb9ff3cd4b09052c71bcce601018439
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-14 (Fri, 14 Jun 2024)

Changed paths:
A yosys/backends/cxxrtl/cxxrtl_backend-5034ba6e.o.tmp
A yosys/backends/edif/edif-cb2bdc21.o.tmp
A yosys/frontends/ast/simplify-a445dbf2.o.tmp
A yosys/kernel/qcsat-69f320f8.o.tmp
A yosys/kernel/satgen-a89c01a2.o.tmp
A yosys/passes/cmds/clean_zerowidth-68bb5837.o.tmp
A yosys/passes/cmds/rename-b345864e.o.tmp
A yosys/passes/cmds/select-acea7d17.o.tmp
A yosys/passes/cmds/show-059b0d6f.o.tmp
A yosys/passes/cmds/splice-34e0a6f8.o.tmp
A yosys/passes/cmds/splitcells-8a77afb0.o.tmp
A yosys/passes/cmds/tee-6bb69f62.o.tmp
A yosys/passes/cmds/torder-db40973f.o.tmp
A yosys/passes/cmds/xprop-422c3060.o.tmp
A yosys/passes/equiv/equiv_make-e3c4ab17.o.tmp
A yosys/passes/equiv/equiv_simple-39bd66be.o.tmp
A yosys/passes/equiv/equiv_struct-d636981e.o.tmp
A yosys/passes/fsm/fsm_detect-946501bf.o.tmp
A yosys/passes/fsm/fsm_extract-c6d45022.o.tmp
A yosys/passes/hierarchy/hierarchy-974634c2.o.tmp
A yosys/passes/memory/memlib-eac6f82f.o.tmp
A yosys/passes/memory/memory_bram-b6a72459.o.tmp
A yosys/passes/memory/memory_libmap-a57ac7a9.o.tmp
A yosys/passes/memory/memory_libmap-ae9a099f.o.tmp
A yosys/passes/memory/memory_share-9ce1b6e9.o.tmp
A yosys/passes/opt/opt_clean-da291790.o.tmp
A yosys/passes/opt/opt_clean-e5c626c1.o.tmp
A yosys/passes/opt/opt_dff-03a14b85.o.tmp
A yosys/passes/opt/opt_dff-681bbd7a.o.tmp
A yosys/passes/opt/opt_expr-5ec5b0aa.o.tmp
A yosys/passes/opt/opt_expr-fd3dfbb8.o.tmp
A yosys/passes/opt/opt_lut-6bfecab7.o.tmp
A yosys/passes/opt/opt_lut_ins-3f8b762c.o.tmp
A yosys/passes/opt/opt_mem_priority-1418bf86.o.tmp
A yosys/passes/opt/opt_merge-dafbe477.o.tmp
A yosys/passes/opt/opt_reduce-3c49b5bf.o.tmp
A yosys/passes/opt/opt_share-d62784de.o.tmp
A yosys/passes/opt/share-1cabecc1.o.tmp
A yosys/passes/opt/share-77e976a4.o.tmp
A yosys/passes/opt/wreduce-0f9f1d7b.o.tmp
A yosys/passes/opt/wreduce-8ca76f66.o.tmp
A yosys/passes/pmgen/xilinx_dsp-0ca5b332.o.tmp
A yosys/passes/proc/proc_arst-746b474d.o.tmp
A yosys/passes/proc/proc_dff-12b3b166.o.tmp
A yosys/passes/proc/proc_dlatch-a3071b6f.o.tmp
A yosys/passes/sat/freduce-a5004ca2.o.tmp
A yosys/passes/sat/qbfsat-a6bbccbc.o.tmp
A yosys/passes/sat/recover_names-c945361a.o.tmp
A yosys/passes/techmap/extract-961f1944.o.tmp
A yosys/passes/techmap/extract_counter-94ac71d0.o.tmp
A yosys/passes/techmap/flatten-d6e444a1.o.tmp
A yosys/passes/techmap/iopadmap-848fe72e.o.tmp
A yosys/passes/techmap/nlutmap-f297d59f.o.tmp
A yosys/passes/techmap/techmap-bfb45225.o.tmp
A yosys/passes/tests/test_abcloop-c9208d47.o.tmp
A yosys/passes/tests/test_cell-d453b186.o.tmp
A yosys/techlibs/ice40/synth_ice40-31f89c69.o.tmp

Log Message:
-----------
Updated black version to 21.4b0 from 20.8b1 so that make env works


Commit: 05beae391924b132694dcf24e84dd86e80ba4e57
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/05beae391924b132694dcf24e84dd86e80ba4e57
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-15 (Sat, 15 Jun 2024)

Changed paths:
A .github/scripts/install_noble_dependencies.sh
M .github/workflows/containers.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml
M .gitmodules
M CMakeLists.txt
M README.developers.md
M dev/pylint_check.py
M dev/subtree_config.xml
A doc/_exts/constraintsdomain/__init__.py
M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/server.rst
M doc/src/arch/reference.rst
M doc/src/conf.py
M doc/src/vpr/command_line_usage.rst
A doc/src/vpr/global_routing_constraints.rst

M doc/src/vpr/index.rst
M doc/src/vpr/placement_constraints.rst
A doc/src/vpr/vpr_constraints.rst

M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/libarchfpga/src/physical_types.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/librrgraph/src/base/check_rr_graph.cpp
M libs/librrgraph/src/base/check_rr_graph.h
M libs/librrgraph/src/base/rr_graph_builder.h
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h
M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
M libs/librrgraph/src/io/rr_graph.xsd
M libs/librrgraph/src/io/rr_graph_reader.cpp
M libs/librrgraph/src/io/rr_graph_reader.h
M libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
M libs/librrgraph/src/io/rr_graph_writer.cpp
M libs/librrgraph/src/io/rr_graph_writer.h
M libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h
M utils/fasm/test/test_fasm.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
A vpr/src/base/user_place_constraints.cpp
A vpr/src/base/user_place_constraints.h
A vpr/src/base/user_route_constraints.cpp
A vpr/src/base/user_route_constraints.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_reader.h
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/draw_basic.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/noc/bfs_routing.cpp
M vpr/src/noc/channel_dependency_graph.cpp
M vpr/src/noc/channel_dependency_graph.h
M vpr/src/noc/negative_first_routing.cpp
M vpr/src/noc/negative_first_routing.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/noc/noc_traffic_flows.cpp
M vpr/src/noc/noc_traffic_flows.h
M vpr/src/noc/north_last_routing.cpp
M vpr/src/noc/north_last_routing.h
M vpr/src/noc/odd_even_routing.cpp
M vpr/src/noc/odd_even_routing.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h
A vpr/src/noc/sat_routing.cpp
A vpr/src/noc/sat_routing.h
M vpr/src/noc/turn_model_routing.cpp
M vpr/src/noc/turn_model_routing.h
M vpr/src/noc/west_first_routing.cpp
M vpr/src/noc/west_first_routing.h
M vpr/src/noc/xy_routing.cpp
M vpr/src/noc/xy_routing.h
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/output_clustering.cpp
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/rr_graph.cpp
M vpr/src/server/bytearray.h
A vpr/src/server/commcmd.h
M vpr/src/server/commconstants.h
M vpr/src/server/gateio.cpp
M vpr/src/server/gateio.h
M vpr/src/server/pathhelper.cpp
M vpr/src/server/pathhelper.h
M vpr/src/server/serverupdate.cpp
M vpr/src/server/task.cpp
M vpr/src/server/task.h
M vpr/src/server/taskresolver.cpp
M vpr/src/server/taskresolver.h
M vpr/src/server/telegrambuffer.cpp
M vpr/src/server/telegrambuffer.h
M vpr/src/server/telegramframe.h
M vpr/src/server/telegramheader.cpp
M vpr/src/server/telegramheader.h
M vpr/src/server/telegramoptions.h
M vpr/src/server/telegramparser.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_server_taskresolver.cpp
M vpr/test/test_server_telegrambuffer.cpp
M vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp
M vtr_flow/parse/parse_config/vpr_noc.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

Log Message:
-----------
resolve conflicts with master


Commit: fb3beca5813ce5c6d3b31aa0872551d58061e1d7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fb3beca5813ce5c6d3b31aa0872551d58061e1d7
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)

Changed paths:
M libs/libvtrutil/src/vtr_geometry.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h

Log Message:
-----------
updated Region and RegionRectCoord to support layer range


Commit: d06e43644f8ab0370c74653809d43c710a1982de
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d06e43644f8ab0370c74653809d43c710a1982de
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M libs/libarchfpga/src/physical_types.h
M libs/libvtrutil/src/vtr_assert.cpp
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: fb891151b594a2fcc2b81f03be79786129d773b2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fb891151b594a2fcc2b81f03be79786129d773b2
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width_small.txt

Log Message:
-----------
[test] add pass_requirements.vpr_route_fixed_chan_width_small.txt


Commit: 136dd11ccb567dc58a097ee4d65c6f8a1dd0cb59
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/136dd11ccb567dc58a097ee4d65c6f8a1dd0cb59
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt

Log Message:
-----------
[test] ass pass_requirements.vpr_route_min_chan_width_small.txt


Commit: a9b24580d6f230b39b00e2f661d78139fd4a9121
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a9b24580d6f230b39b00e2f661d78139fd4a9121
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_relaxed_chan_width_small.txt

Log Message:
-----------
[test] add pass_requirements.vpr_route_relaxed_chan_width_small.txt


Commit: 8ce0a8d347b6d3d8b629c8a9d2c26d886ac13e46
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8ce0a8d347b6d3d8b629c8a9d2c26d886ac13e46
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/pass_requirements_chain_small.txt

Log Message:
-----------
[test] add pass_requirements_chain_small.txt


Commit: dd159ba156eb852fe66a16c81d17b160943ca521
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dd159ba156eb852fe66a16c81d17b160943ca521
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/config.txt

Log Message:
-----------
[test] change pass requirement for nightly test 1 to small pass requirements


Commit: 2d8b826002d167ea30f5ce71079b23f5d7450782
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d8b826002d167ea30f5ce71079b23f5d7450782
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt

Log Message:
-----------
[test] fix a few failures


Commit: a52b88e8e26d487dc55931a2bd8befe821a90771
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a52b88e8e26d487dc55931a2bd8befe821a90771
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/pass_requirements_small.txt

Log Message:
-----------
[test] add pass_requirement_small


Commit: 576ee76568f29642237397614c90a562dca84ca9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/576ee76568f29642237397614c90a562dca84ca9
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt

Log Message:
-----------
[test] update strong test


Commit: 0907fcfb21a3842246b8e931bc37bf2cd2a3036c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0907fcfb21a3842246b8e931bc37bf2cd2a3036c
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M libs/libarchfpga/src/echo_arch.cpp
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/region.cpp
M vpr/src/base/user_place_constraints.h
M vpr/src/base/user_route_constraints.cpp
M vpr/src/base/user_route_constraints.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/pack/pack.cpp
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/route/route_net.tpp
M vpr/src/server/pathhelper.cpp

Log Message:
-----------
add layer_low and layer_high to vpr_contstraints.xsd


Commit: 875a238c699f9974e9e097b4333a09fa1ec6e0d4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/875a238c699f9974e9e097b4333a09fa1ec6e0d4
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h

Log Message:
-----------
add layer_low and layer_high to vpr_constraints_writer


Commit: 448aa85a6ff6a020b9fbd8939c7e3f6e9bbc9855
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/448aa85a6ff6a020b9fbd8939c7e3f6e9bbc9855
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
update grid_tile_lookup to support layer range


Commit: 4abdcdcc8bdc63123f6495ae756012fe3ad98302
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4abdcdcc8bdc63123f6495ae756012fe3ad98302
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt

Log Message:
-----------
[test] add small circuit timing


Commit: 0957197ac6b81f14fc3fa458b4eb3c9429b1d06b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0957197ac6b81f14fc3fa458b4eb3c9429b1d06b
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 golden results


Commit: 967d3c7a9cb73262d104e49f839d22573da9fa21
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/967d3c7a9cb73262d104e49f839d22573da9fa21
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 odin golden results


Commit: 17d983b6c569eeb55541ed37289dfb163b247a4f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/17d983b6c569eeb55541ed37289dfb163b247a4f
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[test] update nightly test3/odin


Commit: dc6cef2c8aff49eafad97fa9c0fe055f7f1c5c36
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dc6cef2c8aff49eafad97fa9c0fe055f7f1c5c36
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 7


Commit: a6afa55c9c22657db438ff0a21cbf85f1dec4d1d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a6afa55c9c22657db438ff0a21cbf85f1dec4d1d
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

Log Message:
-----------
[cli] set place delay model to delta if router lookahead is not of the type map


Commit: 65a188fb895e94ed0165c117d28d8b2fed7fc82c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/65a188fb895e94ed0165c117d28d8b2fed7fc82c
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt

Log Message:
-----------
[test] update basic golden results


Commit: 89e2e29865ab029dc2dbd624bcfbb08a66b088e4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/89e2e29865ab029dc2dbd624bcfbb08a66b088e4
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M vpr/src/draw/draw_types.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: a67c8c29f9aed6ccd8ca91086c1c3a11508171f3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a67c8c29f9aed6ccd8ca91086c1c3a11508171f3
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
updated initial placement to support layer range


Commit: 58f45450e6a41e8bd547412b007da890d1aacf4d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/58f45450e6a41e8bd547412b007da890d1aacf4d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
A .github/scripts/install_noble_dependencies.sh
M .github/workflows/containers.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml
M CMakeLists.txt
M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/server.rst
M doc/src/vpr/command_line_usage.rst
M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/physical_types.h
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h
M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/draw_basic.h
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_types.cpp
M vpr/src/noc/bfs_routing.cpp
M vpr/src/noc/channel_dependency_graph.cpp
M vpr/src/noc/channel_dependency_graph.h
M vpr/src/noc/negative_first_routing.cpp
M vpr/src/noc/negative_first_routing.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/noc/noc_traffic_flows.cpp
M vpr/src/noc/noc_traffic_flows.h
M vpr/src/noc/north_last_routing.cpp
M vpr/src/noc/north_last_routing.h
M vpr/src/noc/odd_even_routing.cpp
M vpr/src/noc/odd_even_routing.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h
A vpr/src/noc/sat_routing.cpp
A vpr/src/noc/sat_routing.h
M vpr/src/noc/turn_model_routing.cpp
M vpr/src/noc/turn_model_routing.h
M vpr/src/noc/west_first_routing.cpp
M vpr/src/noc/west_first_routing.h
M vpr/src/noc/xy_routing.cpp
M vpr/src/noc/xy_routing.h
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/server/bytearray.h
A vpr/src/server/commcmd.h
M vpr/src/server/commconstants.h
M vpr/src/server/gateio.cpp
M vpr/src/server/gateio.h
M vpr/src/server/pathhelper.cpp
M vpr/src/server/pathhelper.h
M vpr/src/server/serverupdate.cpp
M vpr/src/server/task.cpp
M vpr/src/server/task.h
M vpr/src/server/taskresolver.cpp
M vpr/src/server/taskresolver.h
M vpr/src/server/telegrambuffer.cpp
M vpr/src/server/telegrambuffer.h
M vpr/src/server/telegramframe.h
M vpr/src/server/telegramheader.cpp
M vpr/src/server/telegramheader.h
M vpr/src/server/telegramoptions.h
M vpr/src/server/telegramparser.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_server_taskresolver.cpp
M vpr/test/test_server_telegrambuffer.cpp
M vpr/test/test_setup_noc.cpp
M vtr_flow/parse/parse_config/vpr_noc.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into update_search_range_with_floorplan_constraint


Commit: 9ddf089a71c312de2e29c61128ae8da2870b2cd7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ddf089a71c312de2e29c61128ae8da2870b2cd7
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------
test grid_loc_to_compressed_loc_approx_round_up() and grid_loc_to_compressed_loc_approx_round_down()


Commit: cd9e1c393aa0b9d6c8211b117cc26613db1b6b61
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cd9e1c393aa0b9d6c8211b117cc26613db1b6b61
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M vpr/src/base/vpr_context.h

Log Message:
-----------
apply the remaining pr suggestions


Commit: 25e5145d1a4b80c6d05414e5851f3465eec1b8a4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/25e5145d1a4b80c6d05414e5851f3465eec1b8a4
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_clustered_netlist.cpp
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'update_search_range_with_floorplan_constraint' into 3d_constraints


Commit: abfba5d5613805d4789b91a5dd33d447ded7a233
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/abfba5d5613805d4789b91a5dd33d447ded7a233
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 golden


Commit: bce6cc0613da4b9389e4096431766eea418931ef
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/bce6cc0613da4b9389e4096431766eea418931ef
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 odin golden


Commit: fb35cde36277f8f0850c6d136453d1da53a84246
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fb35cde36277f8f0850c6d136453d1da53a84246
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 3 odin golden


Commit: 685bcaa49830bc2848169dced265af341cc01967
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/685bcaa49830bc2848169dced265af341cc01967
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt

Log Message:
-----------
[test] update strong


Commit: fe5f121c042d6781dab729d8389db6e874050907
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fe5f121c042d6781dab729d8389db6e874050907
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt

Log Message:
-----------
[test] change seed number for strong_post_routing to 5


Commit: e07cc08fc350b2dba7814416a9812e3fcc670e50
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e07cc08fc350b2dba7814416a9812e3fcc670e50
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[test] update strong_odin


Commit: e97bfffee65982cfd824c181b15f0feaa6e02a2e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e97bfffee65982cfd824c181b15f0feaa6e02a2e
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M vpr/src/base/region.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
update place_constraints.cpp to support layer range


Commit: cd75e2171dbe0a69d044d74d067f045deac2ff98
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cd75e2171dbe0a69d044d74d067f045deac2ff98
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/place/move_utils.cpp

Log Message:
-----------
early check to see if a block can be placed in a layer


Commit: dfedc23b56840aefa43341f677a77dfefd34abe6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dfedc23b56840aefa43341f677a77dfefd34abe6
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][src][route] use chan_nodes_added instead of nodes_add when high fanout rt is used


Commit: dad7ac6ca85d40789116752a8e0eb9058f71ab3a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dad7ac6ca85d40789116752a8e0eb9058f71ab3a
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][route] remove has path to sink


Commit: a21d763375dfe0dcae7ca9aee1d0b0b562565fbe
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a21d763375dfe0dcae7ca9aee1d0b0b562565fbe
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M .gitignore
M utils/route_diag/src/main.cpp
M vpr/src/base/read_route.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/test/test_connection_router.cpp

Log Message:
-----------
Created final FourAryHeap implementation, but kept BinaryHeap as a inherited class of KAryHeap


Commit: ebd8148218ac1e29ddb5078e6e65b394ef0d924b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ebd8148218ac1e29ddb5078e6e65b394ef0d924b
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M .gitignore
R run_heap_tests.py
M utils/route_diag/src/main.cpp
M vpr/src/base/read_route.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/test/test_connection_router.cpp

Log Message:
-----------
Created final FourAryHeap implementation, but kept BinaryHeap as a inherited class of KAryHeap


Commit: a7f33f69fe56c1d533a9a0febb4ebd271f048e4d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a7f33f69fe56c1d533a9a0febb4ebd271f048e4d
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
R binary_heap_profiler.py
R binary_heap_profiling_helper.cpp

Log Message:
-----------
Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: b68ce5f89cba35d3ffc607301448c18bc9b73c2c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b68ce5f89cba35d3ffc607301448c18bc9b73c2c
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/physical_types.h
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing


Commit: 89a5c882037817fd6f057d65d8e88f418db5eb94
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/89a5c882037817fd6f057d65d8e88f418db5eb94
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
A .github/scripts/install_noble_dependencies.sh

M .github/workflows/containers.yml
M .github/workflows/labeler.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml

M .gitmodules
M CMakeLists.txt
M README.developers.md
M dev/pylint_check.py
M dev/subtree_config.xml
A doc/_exts/constraintsdomain/__init__.py
M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/server.rst
M doc/src/arch/reference.rst
M doc/src/conf.py
M doc/src/vpr/command_line_usage.rst
A doc/src/vpr/global_routing_constraints.rst

M doc/src/vpr/index.rst
M doc/src/vpr/placement_constraints.rst
A doc/src/vpr/vpr_constraints.rst

M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/EXTERNAL/libtatum/.gitignore
M libs/EXTERNAL/libtatum/.travis.yml
M libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp
M libs/EXTERNAL/libtatum/scripts/reg_test.py

M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp

M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/physical_types.h

M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h

M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/libpugiutil/src/pugixml_util.cpp
M libs/libpugiutil/src/pugixml_util.hpp
M libs/librrgraph/src/base/check_rr_graph.cpp
M libs/librrgraph/src/base/check_rr_graph.h
M libs/librrgraph/src/base/rr_graph_builder.h
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h
M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
M libs/librrgraph/src/io/rr_graph.xsd
M libs/librrgraph/src/io/rr_graph_reader.cpp
M libs/librrgraph/src/io/rr_graph_reader.h
M libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
M libs/librrgraph/src/io/rr_graph_writer.cpp
M libs/librrgraph/src/io/rr_graph_writer.h
M libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
M libs/libvtrutil/src/vtr_array_view.h
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_ragged_matrix.h
M libs/libvtrutil/src/vtr_string_interning.h
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h
M libs/libvtrutil/src/vtr_vector.h
M utils/fasm/test/test_fasm.cpp
M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h
A vpr/src/base/user_place_constraints.cpp
A vpr/src/base/user_place_constraints.h
A vpr/src/base/user_route_constraints.cpp
A vpr/src/base/user_route_constraints.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints.cpp

M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_reader.h
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw.cpp
M vpr/src/draw/draw_basic.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_types.cpp
M vpr/src/noc/bfs_routing.cpp
M vpr/src/noc/bfs_routing.h
M vpr/src/noc/channel_dependency_graph.cpp
M vpr/src/noc/channel_dependency_graph.h
M vpr/src/noc/negative_first_routing.cpp
M vpr/src/noc/negative_first_routing.h
M vpr/src/noc/noc_link.cpp
M vpr/src/noc/noc_link.h
M vpr/src/noc/noc_router.cpp
M vpr/src/noc/noc_router.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/noc/noc_traffic_flows.cpp
M vpr/src/noc/noc_traffic_flows.h
M vpr/src/noc/north_last_routing.cpp
M vpr/src/noc/north_last_routing.h
M vpr/src/noc/odd_even_routing.cpp
M vpr/src/noc/odd_even_routing.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h
A vpr/src/noc/sat_routing.cpp
A vpr/src/noc/sat_routing.h
M vpr/src/noc/turn_model_routing.cpp
M vpr/src/noc/turn_model_routing.h
M vpr/src/noc/west_first_routing.cpp
M vpr/src/noc/west_first_routing.h
M vpr/src/noc/xy_routing.cpp
M vpr/src/noc/xy_routing.h
M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/output_clustering.cpp
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp

M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/place/placer_context.h
M vpr/src/place/timing_place_lookup.cpp
M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp
M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/route.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_utils.cpp
M vpr/src/route/route_utils.h
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead.h
M vpr/src/route/router_lookahead_compressed_map.cpp

M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_map_utils.h

M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph.h
M vpr/src/server/bytearray.h
A vpr/src/server/commcmd.h
M vpr/src/server/commconstants.h
M vpr/src/server/gateio.cpp
M vpr/src/server/gateio.h
M vpr/src/server/pathhelper.cpp
M vpr/src/server/pathhelper.h
M vpr/src/server/serverupdate.cpp
M vpr/src/server/task.cpp
M vpr/src/server/task.h
M vpr/src/server/taskresolver.cpp
M vpr/src/server/taskresolver.h
M vpr/src/server/telegrambuffer.cpp
M vpr/src/server/telegrambuffer.h
M vpr/src/server/telegramframe.h
M vpr/src/server/telegramheader.cpp
M vpr/src/server/telegramheader.h
M vpr/src/server/telegramoptions.h
M vpr/src/server/telegramparser.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_bfs_routing.cpp
A vpr/test/test_compressed_grid.cpp
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_server_taskresolver.cpp
M vpr/test/test_server_telegrambuffer.cpp
M vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp
M vpr/test/test_xy_routing.cpp
M vtr_flow/arch/multi_die/README.md
M vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/arch/titan/stratix10_arch.timing.xml
M vtr_flow/parse/parse_config/vpr_noc.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
A yosys/backends/cxxrtl/cxxrtl_backend-5034ba6e.o.tmp
A yosys/backends/edif/edif-cb2bdc21.o.tmp
A yosys/frontends/ast/simplify-a445dbf2.o.tmp
A yosys/kernel/qcsat-69f320f8.o.tmp
A yosys/kernel/satgen-a89c01a2.o.tmp
A yosys/passes/cmds/clean_zerowidth-68bb5837.o.tmp
A yosys/passes/cmds/rename-b345864e.o.tmp
A yosys/passes/cmds/select-acea7d17.o.tmp
A yosys/passes/cmds/show-059b0d6f.o.tmp
A yosys/passes/cmds/splice-34e0a6f8.o.tmp
A yosys/passes/cmds/splitcells-8a77afb0.o.tmp
A yosys/passes/cmds/tee-6bb69f62.o.tmp
A yosys/passes/cmds/torder-db40973f.o.tmp
A yosys/passes/cmds/xprop-422c3060.o.tmp
A yosys/passes/equiv/equiv_make-e3c4ab17.o.tmp
A yosys/passes/equiv/equiv_simple-39bd66be.o.tmp
A yosys/passes/equiv/equiv_struct-d636981e.o.tmp
A yosys/passes/fsm/fsm_detect-946501bf.o.tmp
A yosys/passes/fsm/fsm_extract-c6d45022.o.tmp
A yosys/passes/hierarchy/hierarchy-974634c2.o.tmp
A yosys/passes/memory/memlib-eac6f82f.o.tmp
A yosys/passes/memory/memory_bram-b6a72459.o.tmp
A yosys/passes/memory/memory_libmap-a57ac7a9.o.tmp
A yosys/passes/memory/memory_libmap-ae9a099f.o.tmp
A yosys/passes/memory/memory_share-9ce1b6e9.o.tmp
A yosys/passes/opt/opt_clean-da291790.o.tmp
A yosys/passes/opt/opt_clean-e5c626c1.o.tmp
A yosys/passes/opt/opt_dff-03a14b85.o.tmp
A yosys/passes/opt/opt_dff-681bbd7a.o.tmp
A yosys/passes/opt/opt_expr-5ec5b0aa.o.tmp
A yosys/passes/opt/opt_expr-fd3dfbb8.o.tmp
A yosys/passes/opt/opt_lut-6bfecab7.o.tmp
A yosys/passes/opt/opt_lut_ins-3f8b762c.o.tmp
A yosys/passes/opt/opt_mem_priority-1418bf86.o.tmp
A yosys/passes/opt/opt_merge-dafbe477.o.tmp
A yosys/passes/opt/opt_reduce-3c49b5bf.o.tmp
A yosys/passes/opt/opt_share-d62784de.o.tmp
A yosys/passes/opt/share-1cabecc1.o.tmp
A yosys/passes/opt/share-77e976a4.o.tmp
A yosys/passes/opt/wreduce-0f9f1d7b.o.tmp
A yosys/passes/opt/wreduce-8ca76f66.o.tmp
A yosys/passes/pmgen/xilinx_dsp-0ca5b332.o.tmp
A yosys/passes/proc/proc_arst-746b474d.o.tmp
A yosys/passes/proc/proc_dff-12b3b166.o.tmp
A yosys/passes/proc/proc_dlatch-a3071b6f.o.tmp
A yosys/passes/sat/freduce-a5004ca2.o.tmp
A yosys/passes/sat/qbfsat-a6bbccbc.o.tmp
A yosys/passes/sat/recover_names-c945361a.o.tmp
A yosys/passes/techmap/extract-961f1944.o.tmp
A yosys/passes/techmap/extract_counter-94ac71d0.o.tmp
A yosys/passes/techmap/flatten-d6e444a1.o.tmp
A yosys/passes/techmap/iopadmap-848fe72e.o.tmp
A yosys/passes/techmap/nlutmap-f297d59f.o.tmp
A yosys/passes/techmap/techmap-bfb45225.o.tmp
A yosys/passes/tests/test_abcloop-c9208d47.o.tmp
A yosys/passes/tests/test_cell-d453b186.o.tmp
A yosys/techlibs/ice40/synth_ice40-31f89c69.o.tmp

Log Message:
-----------
Merge branch 'master' into improve_binary_heap


Commit: 51762617f6f752fffb3804bfea438374dbc4a947
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/51762617f6f752fffb3804bfea438374dbc4a947
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M .gitignore
A del_files.py
R yosys/backends/cxxrtl/cxxrtl_backend-5034ba6e.o.tmp
R yosys/backends/edif/edif-cb2bdc21.o.tmp
R yosys/frontends/ast/simplify-a445dbf2.o.tmp
R yosys/kernel/qcsat-69f320f8.o.tmp
R yosys/kernel/satgen-a89c01a2.o.tmp
R yosys/passes/cmds/clean_zerowidth-68bb5837.o.tmp
R yosys/passes/cmds/rename-b345864e.o.tmp
R yosys/passes/cmds/select-acea7d17.o.tmp
R yosys/passes/cmds/show-059b0d6f.o.tmp
R yosys/passes/cmds/splice-34e0a6f8.o.tmp
R yosys/passes/cmds/splitcells-8a77afb0.o.tmp
R yosys/passes/cmds/tee-6bb69f62.o.tmp
R yosys/passes/cmds/torder-db40973f.o.tmp
R yosys/passes/cmds/xprop-422c3060.o.tmp
R yosys/passes/equiv/equiv_make-e3c4ab17.o.tmp
R yosys/passes/equiv/equiv_simple-39bd66be.o.tmp
R yosys/passes/equiv/equiv_struct-d636981e.o.tmp
R yosys/passes/fsm/fsm_detect-946501bf.o.tmp
R yosys/passes/fsm/fsm_extract-c6d45022.o.tmp
R yosys/passes/hierarchy/hierarchy-974634c2.o.tmp
R yosys/passes/memory/memlib-eac6f82f.o.tmp
R yosys/passes/memory/memory_bram-b6a72459.o.tmp
R yosys/passes/memory/memory_libmap-a57ac7a9.o.tmp
R yosys/passes/memory/memory_libmap-ae9a099f.o.tmp
R yosys/passes/memory/memory_share-9ce1b6e9.o.tmp
R yosys/passes/opt/opt_clean-da291790.o.tmp
R yosys/passes/opt/opt_clean-e5c626c1.o.tmp
R yosys/passes/opt/opt_dff-03a14b85.o.tmp
R yosys/passes/opt/opt_dff-681bbd7a.o.tmp
R yosys/passes/opt/opt_expr-5ec5b0aa.o.tmp
R yosys/passes/opt/opt_expr-fd3dfbb8.o.tmp
R yosys/passes/opt/opt_lut-6bfecab7.o.tmp
R yosys/passes/opt/opt_lut_ins-3f8b762c.o.tmp
R yosys/passes/opt/opt_mem_priority-1418bf86.o.tmp
R yosys/passes/opt/opt_merge-dafbe477.o.tmp
R yosys/passes/opt/opt_reduce-3c49b5bf.o.tmp
R yosys/passes/opt/opt_share-d62784de.o.tmp
R yosys/passes/opt/share-1cabecc1.o.tmp
R yosys/passes/opt/share-77e976a4.o.tmp
R yosys/passes/opt/wreduce-0f9f1d7b.o.tmp
R yosys/passes/opt/wreduce-8ca76f66.o.tmp
R yosys/passes/pmgen/xilinx_dsp-0ca5b332.o.tmp
R yosys/passes/proc/proc_arst-746b474d.o.tmp
R yosys/passes/proc/proc_dff-12b3b166.o.tmp
R yosys/passes/proc/proc_dlatch-a3071b6f.o.tmp
R yosys/passes/sat/freduce-a5004ca2.o.tmp
R yosys/passes/sat/qbfsat-a6bbccbc.o.tmp
R yosys/passes/sat/recover_names-c945361a.o.tmp
R yosys/passes/techmap/extract-961f1944.o.tmp
R yosys/passes/techmap/extract_counter-94ac71d0.o.tmp
R yosys/passes/techmap/flatten-d6e444a1.o.tmp
R yosys/passes/techmap/iopadmap-848fe72e.o.tmp
R yosys/passes/techmap/nlutmap-f297d59f.o.tmp
R yosys/passes/techmap/techmap-bfb45225.o.tmp
R yosys/passes/tests/test_abcloop-c9208d47.o.tmp
R yosys/passes/tests/test_cell-d453b186.o.tmp
R yosys/techlibs/ice40/synth_ice40-31f89c69.o.tmp

Log Message:
-----------
Removed .gitignore changes


Commit: da0018a86330389c35f397915ecf8ba9c57ef490
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/da0018a86330389c35f397915ecf8ba9c57ef490
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M .gitignore
R yosys/backends/cxxrtl/cxxrtl_backend-5034ba6e.o.tmp
R yosys/backends/edif/edif-cb2bdc21.o.tmp
R yosys/frontends/ast/simplify-a445dbf2.o.tmp
R yosys/kernel/qcsat-69f320f8.o.tmp
R yosys/kernel/satgen-a89c01a2.o.tmp
R yosys/passes/cmds/clean_zerowidth-68bb5837.o.tmp
R yosys/passes/cmds/rename-b345864e.o.tmp
R yosys/passes/cmds/select-acea7d17.o.tmp
R yosys/passes/cmds/show-059b0d6f.o.tmp
R yosys/passes/cmds/splice-34e0a6f8.o.tmp
R yosys/passes/cmds/splitcells-8a77afb0.o.tmp
R yosys/passes/cmds/tee-6bb69f62.o.tmp
R yosys/passes/cmds/torder-db40973f.o.tmp
R yosys/passes/cmds/xprop-422c3060.o.tmp
R yosys/passes/equiv/equiv_make-e3c4ab17.o.tmp
R yosys/passes/equiv/equiv_simple-39bd66be.o.tmp
R yosys/passes/equiv/equiv_struct-d636981e.o.tmp
R yosys/passes/fsm/fsm_detect-946501bf.o.tmp
R yosys/passes/fsm/fsm_extract-c6d45022.o.tmp
R yosys/passes/hierarchy/hierarchy-974634c2.o.tmp
R yosys/passes/memory/memlib-eac6f82f.o.tmp
R yosys/passes/memory/memory_bram-b6a72459.o.tmp
R yosys/passes/memory/memory_libmap-a57ac7a9.o.tmp
R yosys/passes/memory/memory_libmap-ae9a099f.o.tmp
R yosys/passes/memory/memory_share-9ce1b6e9.o.tmp
R yosys/passes/opt/opt_clean-da291790.o.tmp
R yosys/passes/opt/opt_clean-e5c626c1.o.tmp
R yosys/passes/opt/opt_dff-03a14b85.o.tmp
R yosys/passes/opt/opt_dff-681bbd7a.o.tmp
R yosys/passes/opt/opt_expr-5ec5b0aa.o.tmp
R yosys/passes/opt/opt_expr-fd3dfbb8.o.tmp
R yosys/passes/opt/opt_lut-6bfecab7.o.tmp
R yosys/passes/opt/opt_lut_ins-3f8b762c.o.tmp
R yosys/passes/opt/opt_mem_priority-1418bf86.o.tmp
R yosys/passes/opt/opt_merge-dafbe477.o.tmp
R yosys/passes/opt/opt_reduce-3c49b5bf.o.tmp
R yosys/passes/opt/opt_share-d62784de.o.tmp
R yosys/passes/opt/share-1cabecc1.o.tmp
R yosys/passes/opt/share-77e976a4.o.tmp
R yosys/passes/opt/wreduce-0f9f1d7b.o.tmp
R yosys/passes/opt/wreduce-8ca76f66.o.tmp
R yosys/passes/pmgen/xilinx_dsp-0ca5b332.o.tmp
R yosys/passes/proc/proc_arst-746b474d.o.tmp
R yosys/passes/proc/proc_dff-12b3b166.o.tmp
R yosys/passes/proc/proc_dlatch-a3071b6f.o.tmp
R yosys/passes/sat/freduce-a5004ca2.o.tmp
R yosys/passes/sat/qbfsat-a6bbccbc.o.tmp
R yosys/passes/sat/recover_names-c945361a.o.tmp
R yosys/passes/techmap/extract-961f1944.o.tmp
R yosys/passes/techmap/extract_counter-94ac71d0.o.tmp
R yosys/passes/techmap/flatten-d6e444a1.o.tmp
R yosys/passes/techmap/iopadmap-848fe72e.o.tmp
R yosys/passes/techmap/nlutmap-f297d59f.o.tmp
R yosys/passes/techmap/techmap-bfb45225.o.tmp
R yosys/passes/tests/test_abcloop-c9208d47.o.tmp
R yosys/passes/tests/test_cell-d453b186.o.tmp
R yosys/techlibs/ice40/synth_ice40-31f89c69.o.tmp

Log Message:
-----------
Removed .gitignore changes


Commit: 7d869d265c871bc7b19f37699c6f5b25fa193102
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/7d869d265c871bc7b19f37699c6f5b25fa193102
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

Log Message:
-----------
Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: a5e7c7a0db28d887b3899805adb03e1577687daf
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a5e7c7a0db28d887b3899805adb03e1577687daf
Author: KA7E <kthu...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------
added default filename generation for input flat placement file


Commit: 02b338a4daae301e32f62fb81d5225733fd4acff
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/02b338a4daae301e32f62fb81d5225733fd4acff
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------
Merge pull request #2625 from verilog-to-routing/add_default_flat_placement_filename

added default filename generation for input flat placement file


Commit: 9a5d3b1e2f5ddfb50ed7f32b392e858530fc852d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9a5d3b1e2f5ddfb50ed7f32b392e858530fc852d
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/read_options.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/netlist_routers.h
M vpr/src/route/router_delay_profiling.h

Log Message:
-----------
Fixed bug in FourAryHeap::get_heap_head and make FourAryHeap default heap implementation


Commit: fddfd80d9f4b010014618f2f7e12a139ab23c577
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fddfd80d9f4b010014618f2f7e12a139ab23c577
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt

Log Message:
-----------
[test] update golden multiclock odin


Commit: a3256f4463093e734601da6d5dde3fa9c17831d8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a3256f4463093e734601da6d5dde3fa9c17831d8
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

Log Message:
-----------
[test] update golden results for strong test


Commit: c58ca707d90c213fc865671cdd1f72e51c4f25a7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c58ca707d90c213fc865671cdd1f72e51c4f25a7
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
parent() is now static function


Commit: acbb0beee5f2d5c31b3c2e32c905fd7b25c5edc2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/acbb0beee5f2d5c31b3c2e32c905fd7b25c5edc2
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
update strong odin


Commit: 339fe8d3c18da6509cd37a362186471800f5add3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/339fe8d3c18da6509cd37a362186471800f5add3
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Revert "parent() is now static function"

This reverts commit c58ca707d90c213fc865671cdd1f72e51c4f25a7.


Commit: 423f975d9c4c08389c02f254cf929331f5d8bbc9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/423f975d9c4c08389c02f254cf929331f5d8bbc9
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/region.cpp
M vpr/src/base/region.h

Log Message:
-----------
replace initial rect coordinates with numeric_limits functions


Commit: 686011bde16905f32f0c096071b2fdc836432d97
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/686011bde16905f32f0c096071b2fdc836432d97
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
fix compilation errors in test_vpr_constraints.cpp


Commit: d73139d283d8e36979983ecb00ad986f56078f8d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d73139d283d8e36979983ecb00ad986f56078f8d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
add unit tests for 3d floorplan regions


Commit: e998e82e457d1484b06cc09ceb8feca1487e2a8c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e998e82e457d1484b06cc09ceb8feca1487e2a8c
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
add StringMaker<vtr::Rect<T>>


Commit: 54bf5184a9bbe539cb30582100056bc190127a13
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/54bf5184a9bbe539cb30582100056bc190127a13
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/region.cpp

Log Message:
-----------
fix false empty region intersection bug


Commit: 0fcae3aa2ecde3de01b23b24dbe21f9219734120
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0fcae3aa2ecde3de01b23b24dbe21f9219734120
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/region.cpp

Log Message:
-----------
fix empty region check bug


Commit: 32e6900a18b7d4f456c5003f7798ca36d80aa45f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/32e6900a18b7d4f456c5003f7798ca36d80aa45f
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
update test_vpr_constraints with cases that have regions spanning multiple layers


Commit: bde3caed47244d5e4948f8f7bf69f040bc455b40
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/bde3caed47244d5e4948f8f7bf69f040bc455b40
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------

Eliminated duplicate code in ShowRouterOpts()


Commit: 679618a2ef93a77f154bde3d67123facc1a358a2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/679618a2ef93a77f154bde3d67123facc1a358a2
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:
M vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.h
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Added Doxygen comments to HeapImplementation and its children (excluding bucket heap)


Commit: d580ab1961d972da9d2f7e2bd686eabe962d7582
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d580ab1961d972da9d2f7e2bd686eabe962d7582
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt

Log Message:
-----------
Updated golden values


Commit: d56143b05e91aaac5e6b2623b1eca955d233c32e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d56143b05e91aaac5e6b2623b1eca955d233c32e
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/base/ShowSetup.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Modified Doxygen comments on heaps


Commit: 15fb10844c8e581c2e990b006555ef06672a7696
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/15fb10844c8e581c2e990b006555ef06672a7696
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------
Merge branch 'master' into improve_binary_heap


Commit: aeb4612671bd556a3d2c5578beeef5d66cf414d1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aeb4612671bd556a3d2c5578beeef5d66cf414d1
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
bugfix: consider the last layer in exhaustive initial placement of a block


Commit: 6fa53e1d467462bc18a8c31d9853aedfdece974a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6fa53e1d467462bc18a8c31d9853aedfdece974a
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/place/place.cpp

Log Message:
-----------
create move generators after movable blocks are determined


Commit: 8641b861a4d166e09f7e7eeb220d0026ee928885
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8641b861a4d166e09f7e7eeb220d0026ee928885
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into fix_fixed_clusters_issue


Commit: e32f037b0748d5cb3823060a306a378c0f95fc06
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e32f037b0748d5cb3823060a306a378c0f95fc06
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
bugfix: consider the last layer when constructing GridTileLookup


Commit: 56691b5114f9fec1992788c72b3f2ffa82e9bb20
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56691b5114f9fec1992788c72b3f2ffa82e9bb20
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/base/region.cpp
M vpr/src/pack/constraints_report.cpp

Log Message:
-----------
default layer range when the layer is not specified


Commit: 0abbaa271aa87515a885fae6eb58d967be9ec22d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0abbaa271aa87515a885fae6eb58d967be9ec22d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------
update min_chan_width_routing_area_total and min_chan_width_routing_area_per_tile for regression_tests/vtr_reg_strong_odin/strong_fix_pins_random


Commit: 62d1243021ed427408b7df871ccbece09c08470a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/62d1243021ed427408b7df871ccbece09c08470a
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------
Merge pull request #2603 from verilog-to-routing/update_search_range_with_floorplan_constraint

Fix high rejection rate for constrained blocks during annealing


Commit: d51f91af930eb9a5aeb75b062d5f7a8e6c6bcc66
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d51f91af930eb9a5aeb75b062d5f7a8e6c6bcc66
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
Updated more golden results


Commit: f96d37b725423c5a4a43e576904149c30c9f1a56
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f96d37b725423c5a4a43e576904149c30c9f1a56
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[CI] update strong golden results


Commit: 63aa39cb76df77761beb09bcedf25ac1b83780e8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/63aa39cb76df77761beb09bcedf25ac1b83780e8
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt

Log Message:
-----------
[ci] update systemverilog test


Commit: a3789ff3ad7db9df3c14c825b5003d7acec18807
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a3789ff3ad7db9df3c14c825b5003d7acec18807
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt

Log Message:
-----------
[test] increase route chan width


Commit: 6484a38383e5c546144336fa1421c98b23b635d9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6484a38383e5c546144336fa1421c98b23b635d9
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M README.developers.md
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: a2e2970aab2d11babcd08d60a175498dd5ab0462
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a2e2970aab2d11babcd08d60a175498dd5ab0462
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/route/four_ary_heap.cpp

Log Message:
-----------
Fixed bug in FourAryHeap::smallest_child()


Commit: a054a1457607bf99d4c4b70f65e72bf76d9446e8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a054a1457607bf99d4c4b70f65e72bf76d9446e8
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt

Log Message:
-----------
Added regression test for BinaryHeap


Commit: 51cd8d49e5401b860f6ca1ab89189b09e3340122
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/51cd8d49e5401b860f6ca1ab89189b09e3340122
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M vpr/src/route/heap_type.h

Log Message:
-----------
Added router heap to VPRINTERNALS API


Commit: d906ea860a40742b95a5d5f17b1d642c535c66d6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d906ea860a40742b95a5d5f17b1d642c535c66d6
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M doc/src/api/vprinternals/router_heap.rst
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/route/heap_type.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------
Merge branch 'master' into improve_binary_heap


Commit: 4e296fc32a1f59a5d1c471936bd56092118301ab
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4e296fc32a1f59a5d1c471936bd56092118301ab
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[ci] update strong odin


Commit: 4d8a519f4a5bd6649bc3550d0417c8b427d83c1e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4d8a519f4a5bd6649bc3550d0417c8b427d83c1e
Author: saaramahmoudi <sin2...@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph2.cpp

Log Message:
-----------
bug resolved: both incr and dec track switches were using same index


Commit: fc49189099dc471b22916071bc336d39b60f7a2b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fc49189099dc471b22916071bc336d39b60f7a2b
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
Added more golden results


Commit: 24449d365a8e31e7f38a6d5eec05bb1c60b3eb5d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/24449d365a8e31e7f38a6d5eec05bb1c60b3eb5d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M libs/libvtrutil/src/vtr_geometry.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp

Log Message:
-----------
remove RegionRectCoord class


Commit: fa40fc31646997f47d8d80c3b3ecd61e7ab96016
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fa40fc31646997f47d8d80c3b3ecd61e7ab96016
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
remove calls to get_region_bounds() and set_region_bounds()


Commit: 3d6941fcf8baafddb39d0af8eb64012d013a3761
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3d6941fcf8baafddb39d0af8eb64012d013a3761
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/three_partitionregion_multiregion.xml

Log Message:
-----------
add CI test for 3d placement constraints


Commit: 0c2261abac76a44e191aeeeb33c3087a0a0237a4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0c2261abac76a44e191aeeeb33c3087a0a0237a4
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vtr_flow/scripts/python_libs/vtr/log_parse.py

Log Message:
-----------
[debug] print check value


Commit: f77e0e41bc6757fff4fbdc72c0724a2317db9a2f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f77e0e41bc6757fff4fbdc72c0724a2317db9a2f
Author: Amin Mohaghegh <amin1377....@gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
Merge pull request #2624 from verilog-to-routing/high_fanout_rt

CHAN Node Count - High Fanout RT


Commit: 2d1de0c793a770a6b8ce7aa804cacd7b2a149167
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d1de0c793a770a6b8ce7aa804cacd7b2a149167
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vpr/src/base/partition_region.cpp
M vpr/src/base/vpr_context.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_noc.h

Log Message:
-----------
draw floorplan regions for 3d architectures


Commit: 33ee602bf7b876670691b6982b3462780ddb5a63
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/33ee602bf7b876670691b6982b3462780ddb5a63
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: 6e5a814f65cd643a3fee6afd0aac05f346224a89
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6e5a814f65cd643a3fee6afd0aac05f346224a89
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vtr_flow/scripts/python_libs/vtr/log_parse.py

Log Message:
-----------
[debug] use orginal check val


Commit: 558a2c123eeb7c2f75562c4526b1e6029c756d95
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/558a2c123eeb7c2f75562c4526b1e6029c756d95
Author: saaramahmoudi <sin2...@gmail.com>
Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph.cpp

Log Message:
-----------
block_type_pin_index_to_name requires a third argument


Commit: 31b8261bc4848d95a89adead79c551c89565cd6a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31b8261bc4848d95a89adead79c551c89565cd6a
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py

Log Message:
-----------
[debug] print pass for failed tests


Commit: 42934616e96ed97465f4b3b3fff67d9100f9f308
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/42934616e96ed97465f4b3b3fff67d9100f9f308
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][route] remove target_node is valid


Commit: 1ce545f813e906d6ba4d7c305b2809c9a023b1fc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1ce545f813e906d6ba4d7c305b2809c9a023b1fc
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph.cpp

Log Message:
-----------
Merge pull request #2631 from verilog-to-routing/fc_log

VTR_LOG to print Fc values for pins bug


Commit: dce37b9da8da475d6b56898b871a2d8398f0a525
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dce37b9da8da475d6b56898b871a2d8398f0a525
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M .gitignore
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_route.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/test/test_connection_router.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt

Log Message:
-----------
Merge pull request #2627 from nedsels/improve_binary_heap

Update BinaryHeap to FourAryHeap


Commit: 5c40446ceea01f61ccf31483f6d5ba6da97733b5
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5c40446ceea01f61ccf31483f6d5ba6da97733b5
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h
M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------
Merge pull request #2495 from verilog-to-routing/fix_fixed_clusters_issue

Fix fixed clusters issue


Commit: 3e9bc7d8f0f4476f32dab3dd310c63d9cb645f12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3e9bc7d8f0f4476f32dab3dd310c63d9cb645f12
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M doc/src/api/vprinternals/router_heap.rst
M vpr/src/route/heap_type.h

Log Message:
-----------
In documentation, FourAryHeap and KAryHeap no longer show inherited member info; also, t_heap fn.s described better


Commit: f1041229baccf9b1cfe1c6b33245fe65b0db2c7d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f1041229baccf9b1cfe1c6b33245fe65b0db2c7d
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M doc/src/api/vprinternals/router_heap.rst
M vpr/src/route/heap_type.h

Log Message:
-----------
Merge pull request #2634 from nedsels/update_heap_documentation

Router Heap documentation update


Commit: 08d886c1159be49d7f1c2934008343e565763ba9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/08d886c1159be49d7f1c2934008343e565763ba9
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph2.cpp

Log Message:
-----------
Merge pull request #2630 from verilog-to-routing/rr_graph_edge_bug

RR graph edge creation uses a incorrect switch type for decremental tracks


Commit: 8d41358e01c287cf7a33e6f3b337c007ae9d2aa4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d41358e01c287cf7a33e6f3b337c007ae9d2aa4
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:
M vpr/src/base/partition_region.h
M vpr/src/base/region.cpp

Log Message:
-----------
add hash function for PartitionRegion


Commit: 9fd7389af033307fd2a54fc281b9242d3bc01931
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9fd7389af033307fd2a54fc281b9242d3bc01931
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:
M vpr/src/base/partition_region.h

Log Message:
-----------
add == operator for PartitionRegion


Commit: 571cedec79db531f9d96bef28539d9f139915fae
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/571cedec79db531f9d96bef28539d9f139915fae
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp

Log Message:
-----------
changed floorplan_constraints_regions_overfull() to check whether whole PartitionRegions are full instead of individual Regions


Commit: c74ca63dba3d7b17e9b1cce75902a1646575047c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c74ca63dba3d7b17e9b1cce75902a1646575047c
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:
M vpr/src/base/vpr_constraints_serializer.h

Log Message:
-----------
check the legality of region when parsing it


Commit: e7ec2194cb9cf05873317b8cb48a949b594b3b3f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e7ec2194cb9cf05873317b8cb48a949b594b3b3f
Author: Amin Mohaghegh <amin1377....@gmail.com>
Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------
Merge pull request #2626 from verilog-to-routing/remove_has_path_to_sink

Remove `has_path_to_sink`


Commit: ea6464eef785f1f343d305921b3f13c53d0470c0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ea6464eef785f1f343d305921b3f13c53d0470c0
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:
M vpr/src/base/region.cpp
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/pack/constraints_report.cpp
M vpr/src/pack/constraints_report.h
M vpr/src/place/grid_tile_lookup.h

Log Message:
-----------
add comments


Commit: e4f6f4f3c6aa5cb4003ca11fdd877a6c71078062
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e4f6f4f3c6aa5cb4003ca11fdd877a6c71078062
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:
M .gitignore
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h
M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/read_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/test/test_connection_router.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: fc85d7163bc297cda972d07a373a121fd302d8b0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fc85d7163bc297cda972d07a373a121fd302d8b0
Author: AlexandreSinger <alex....@mail.utoronto.ca>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------
[Tests] Updated Golden Solutions

CI was failing due to three nightly test failures. Updated the golden
results for these tests to resolve the errors.


Commit: 74805b84d33964a0ec93b7af132350b117ebb501
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/74805b84d33964a0ec93b7af132350b117ebb501
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[ci] add status result to nightly test 1


Commit: cb681d7e3f0cc511bd64ba3eac0b1330a9461e02
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cb681d7e3f0cc511bd64ba3eac0b1330a9461e02
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[ci] add status field to nightly_test1_odin


Commit: aa6623f0572d03ce921679a8be883ae39c19c04d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aa6623f0572d03ce921679a8be883ae39c19c04d
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt

Log Message:
-----------
[ci] increase channel width for vpr_verify_rr_Graph


Commit: 56a3b3d08fc8d8305d4ab7e9b9808d896aa6f451
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56a3b3d08fc8d8305d4ab7e9b9808d896aa6f451
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt

Log Message:
-----------
[ci] update nightly test2 odin golden


Commit: 2bb270e64dae3a3e8aa39d1d89dbf563a94ec1f1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2bb270e64dae3a3e8aa39d1d89dbf563a94ec1f1
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[ci] update stron odin golden results


Commit: 2596b4de9230f568625f499bc925e0b9076ca793
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2596b4de9230f568625f499bc925e0b9076ca793
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/scripts/python_libs/vtr/log_parse.py
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py

Log Message:
-----------
[ci] remove debugging messages from script


Commit: a26bbbbe75ad0264d98be26378877a13a7095929
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a26bbbbe75ad0264d98be26378877a13a7095929
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt

Log Message:
-----------
[ci] update basic golden result


Commit: 00e5b65328a54bc4d81986ad560e9226c68db9c8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/00e5b65328a54bc4d81986ad560e9226c68db9c8
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
fix the failing unit test


Commit: 9ddb7d51c8787264fc93a90252f09fcd148af32b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ddb7d51c8787264fc93a90252f09fcd148af32b
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------
Merge pull request #2640 from AlexandreSinger/feature-ci-update-golden

[Tests] Updated Golden Solutions


Commit: 9849395817dd9a13296dc100ec54d2eaa1365b8a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9849395817dd9a13296dc100ec54d2eaa1365b8a
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M doc/src/vpr/placement_constraints.rst

Log Message:
-----------
updated docs with layer_low and layer_high


Commit: 2d959d882511ac3be83efd9cf8cba8c0ae7026ca
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d959d882511ac3be83efd9cf8cba8c0ae7026ca
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vpr/src/base/read_options.cpp
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/locked_down.xml
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/three_partitionregion_multiregion.xml

Log Message:
-----------
add a 3D constraint file where are atoms are locked down


Commit: ba786496888e578e69ed85a04030c857f979b10a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ba786496888e578e69ed85a04030c857f979b10a
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M .gitignore
M README.developers.md
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h
M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/read_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/test/test_connection_router.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt

Log Message:
-----------
Merge remote-tracking branch 'origin/master' into 3d_constraints


Commit: c276183fd617e4eb76ebe9e4b0fd1b1b6693c2f9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c276183fd617e4eb76ebe9e4b0fd1b1b6693c2f9
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: 1618ee34fbbd7a69e09e2d6c5c91121ba33fa862
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1618ee34fbbd7a69e09e2d6c5c91121ba33fa862
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[ci] add vpr status to nightly test 1 golden res


Commit: 1a6bb5ee506689c0459269a561bd79899f49426c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1a6bb5ee506689c0459269a561bd79899f49426c
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt

Log Message:
-----------
[ci] add vpr status to power extend


Commit: b00967cd43974a6066b86e5a80bd7055e50a85b9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b00967cd43974a6066b86e5a80bd7055e50a85b9
Author: Amin Mohaghegh <amin1377....@gmail.com>
Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:
M vpr/src/base/read_options.cpp
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width_small.txt
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_relaxed_chan_width_small.txt
A vtr_flow/parse/pass_requirements/pass_requirements_chain_small.txt
A vtr_flow/parse/pass_requirements/pass_requirements_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt

Log Message:
-----------
Merge pull request #2608 from verilog-to-routing/enable_simple_place_delay_matrix

Use Simple Place Delay Model By Default


Commit: a446074667279efb8987bc0eb362a385466627bc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a446074667279efb8987bc0eb362a385466627bc
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:
M vpr/src/base/vpr_constraints_writer.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt

Log Message:
-----------
add vpr_tight_floorplan_3d to task list


Commit: a24e8abc3f7c93ae84f67dae16f350b0f15cd0d2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a24e8abc3f7c93ae84f67dae16f350b0f15cd0d2
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:
M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
bugfix: consider the last layer in region_with_subtile_count()


Commit: 224c8acb1d8cdd2665ca6d60fb6b6b4bfcee8325
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/224c8acb1d8cdd2665ca6d60fb6b6b4bfcee8325
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp
A vtr_flow/arch/titan/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/locked_down.xml

Log Message:
-----------
fixbug: print block type name and the number of tiles for overfull prs


Commit: cb55d6641e4f9779df339b43ed01a479511aef49
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cb55d6641e4f9779df339b43ed01a479511aef49
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-08 (Mon, 08 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------
Merge pull request #2596 from verilog-to-routing/yosys_update

Yosys Update -> v0.42


Commit: f37ec16665d60a431b593fcdbcb29fb133b8f3dc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f37ec16665d60a431b593fcdbcb29fb133b8f3dc
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-08 (Mon, 08 Jul 2024)

Changed paths:
M doc/src/vpr/placement_constraints.rst
M libs/libarchfpga/src/echo_arch.cpp
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_options.cpp
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/user_place_constraints.h
M vpr/src/base/user_route_constraints.cpp
M vpr/src/base/user_route_constraints.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h

M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_noc.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/pack/constraints_report.h
M vpr/src/pack/pack.cpp
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/route/route_net.tpp
M vpr/src/server/pathhelper.cpp
M vpr/test/test_clustered_netlist.cpp
M vpr/test/test_vpr_constraints.cpp
A vtr_flow/arch/titan/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml

Log Message:
-----------
Merge pull request #2623 from verilog-to-routing/3d_constraints

3D Placement Constraints


Commit: 3af3beaf751394053b905ebd25421d16af2eea81
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3af3beaf751394053b905ebd25421d16af2eea81
Author: AlexandreSinger <49374526+Ale...@users.noreply.github.com>
Date: 2024-07-09 (Tue, 09 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------
Revert "Yosys Update -> v0.42"


Commit: 16adbfa4f0f5d7269ace3ce9dec1ab2a19fa1fea
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/16adbfa4f0f5d7269ace3ce9dec1ab2a19fa1fea
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-09 (Tue, 09 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------
Merge pull request #2643 from verilog-to-routing/revert-2596-yosys_update

Revert "Yosys Update -> v0.42"


Commit: 0b85c507c932774162cd978b42b71bc2b6ff3a86
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0b85c507c932774162cd978b42b71bc2b6ff3a86
Author: KA7E <kthu...@gmail.com>

Date: 2024-07-15 (Mon, 15 Jul 2024)

Changed paths:

M vtr_flow/arch/ispd/ultrascale_ispd.xml

Log Message:
-----------
fix typo


Commit: f2d38a92442e57afed05a8124f1c4db63fb2a4be
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f2d38a92442e57afed05a8124f1c4db63fb2a4be
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-15 (Mon, 15 Jul 2024)

Changed paths:

M vtr_flow/arch/ispd/ultrascale_ispd.xml

Log Message:
-----------
Merge pull request #2645 from verilog-to-routing/ultrascale_xml_typo

fix typo


Commit: 5d0486fc222d374c86dcc9c28ef30ed57561384f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5d0486fc222d374c86dcc9c28ef30ed57561384f
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-15 (Mon, 15 Jul 2024)

Changed paths:

M README.developers.md

Log Message:
-----------
Merge pull request #2605 from ueqri/feature-doc-update-profiling-vpr

[Docs] Updated Profiling VTR Section in Developer Guide

Commit: b6a98cfc68517b227664a48e907d68c1b2362365
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b6a98cfc68517b227664a48e907d68c1b2362365

Author: AlexandreSinger <49374526+Ale...@users.noreply.github.com>
Date: 2024-07-15 (Mon, 15 Jul 2024)

Changed paths:
M .gitattributes
A .github/dependabot.yml

M .github/labeler.yml
M .github/scripts/hostsetup.sh
M .github/scripts/install_dependencies.sh
A .github/scripts/install_noble_dependencies.sh
M .github/scripts/run-vtr.sh
M .github/workflows/containers.yml
M .github/workflows/labeler.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml
M .gitignore
A .gitmodules
M .readthedocs.yaml
M BUILDING.md
M CHANGELOG.md
M CMakeLists.txt
M CONTRIBUTING.md
M Dockerfile

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R ODIN_II/SRC/BlockMemories.cpp
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R ODIN_II/SRC/Verilog.cpp
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R ODIN_II/regression_test/benchmark/verilog/keywords/or/replicate_or_ultra_wide.vh
R ODIN_II/regression_test/benchmark/verilog/keywords/or/replicate_or_ultra_wide_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/or/replicate_or_ultra_wide_odin_output
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R ODIN_II/regression_test/benchmark/verilog/keywords/or/replicate_or_wide_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations.v
R ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/output/multiple_declarations_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/output/output_port_failure.v
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/multiple_parameter.v
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/multiple_parameter_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/multiple_parameter_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/multiple_parameter_yosys_input
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R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_define.v
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_define_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_define_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_define_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_define_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_override.v
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_override_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_override_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_override_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/parameter/parameter_override_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/posedge/posedge.v
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R ODIN_II/regression_test/benchmark/verilog/keywords/posedge/posedge_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg.v
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_failure.v
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_port.v
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_port_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_port_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_port_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_port_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/reg/reg_yosys_output
R ODIN_II/regression_test/benchmark/verilog/keywords/signed_unsigned/signed_to_signed.v
R ODIN_II/regression_test/benchmark/verilog/keywords/signed_unsigned/signed_to_signed_odin_input
R ODIN_II/regression_test/benchmark/verilog/keywords/signed_unsigned/signed_to_signed_odin_output
R ODIN_II/regression_test/benchmark/verilog/keywords/signed_unsigned/signed_to_signed_yosys_input
R ODIN_II/regression_test/benchmark/verilog/keywords/signed_unsigned/signed_to_signed_yosys_output
R ODIN_II/regression_test/benchmark/verilog/syntax/README
R ODIN_II/regression_test/benchmark/verilog/syntax/config.txt

R comparison_output.xlsx

M dev/DOCKER_DEPLOY.md
M dev/odin2_helper/Makefile
M dev/pylint_check.py
M dev/subtree_config.xml
M dev/test_git_bisect.sh
A doc/.DS_Store
M doc/README
M doc/_doxygen/ODIN_II.dox
A doc/_exts/constraintsdomain/__init__.py
M doc/requirements.txt
A doc/src/.DS_Store
A doc/src/Images/.DS_Store
A doc/src/Images/Block_Settings.png
A doc/src/Images/Net_Settings.png
A doc/src/Images/Overall_view.png
A doc/src/Images/Routing_Options.png
A doc/src/Images/crit_path.png
A doc/src/Images/manual_move.png
A doc/src/Images/view_menu.png
M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/route_tree.rst
A doc/src/api/vpr/server.rst

M doc/src/api/vprinternals/index.rst

A doc/src/api/vprinternals/noc_data_types.rst
A doc/src/api/vprinternals/noc_link.rst
A doc/src/api/vprinternals/noc_router.rst
A doc/src/api/vprinternals/noc_routing.rst
A doc/src/api/vprinternals/noc_storage.rst
A doc/src/api/vprinternals/noc_traffic_flows.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_noc.rst
A doc/src/api/vprinternals/vpr_router.rst

M doc/src/arch/reference.rst
M doc/src/conf.py
M doc/src/dev/c_api_doc.rst

M doc/src/vtr/python_libs/vtr.rst
M doc/src/vtr/run_vtr_flow.rst

M doc/src/vtr/running_vtr.rst
A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.cpp
M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.hpp
M libs/EXTERNAL/libtatum/libtatum/tatum/graph_walkers/SerialIncrWalker.hpp
M libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp
M libs/EXTERNAL/libtatum/libtatum/tatum/util/tatum_strong_id.hpp
M libs/EXTERNAL/libtatum/scripts/reg_test.py

R libs/EXTERNAL/libyosys/.github/workflows/deprecated.yml
R libs/EXTERNAL/libyosys/.github/workflows/emcc.yml

R libs/EXTERNAL/libyosys/CMakeLists.txt
R libs/EXTERNAL/libyosys/Makefile
R libs/EXTERNAL/libyosys/README.md
R libs/EXTERNAL/libyosys/backends/json/json.cc

R libs/EXTERNAL/libyosys/backends/smt2/witness.py
R libs/EXTERNAL/libyosys/docs/.gitignore
R libs/EXTERNAL/libyosys/docs/images/Makefile
R libs/EXTERNAL/libyosys/docs/source/CHAPTER_Prog.rst
R libs/EXTERNAL/libyosys/docs/source/index.rst

R libs/EXTERNAL/libyosys/manual/appnotes.sh
R libs/EXTERNAL/libyosys/manual/command-reference-manual.tex
R libs/EXTERNAL/libyosys/manual/literature.bib
R libs/EXTERNAL/libyosys/manual/manual.sh
R libs/EXTERNAL/libyosys/manual/manual.tex
R libs/EXTERNAL/libyosys/manual/weblinks.bib

R libs/EXTERNAL/libyosys/passes/cmds/Makefile.inc
R libs/EXTERNAL/libyosys/passes/cmds/plugin.cc
R libs/EXTERNAL/libyosys/passes/sat/Makefile.inc
R libs/EXTERNAL/libyosys/passes/sat/formalff.cc
R libs/EXTERNAL/libyosys/passes/techmap/Makefile.inc
R libs/EXTERNAL/libyosys/passes/techmap/bmuxmap.cc
R libs/EXTERNAL/libyosys/passes/techmap/insbuf.cc
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R libs/EXTERNAL/libyosys/techlibs/gatemate/cells_sim.v
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R libs/EXTERNAL/libyosys/techlibs/intel_alm/common/bram_m10k_map.v
R libs/EXTERNAL/libyosys/techlibs/machxo2/Makefile.inc
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R libs/EXTERNAL/libyosys/techlibs/machxo2/cells_sim.v
R libs/EXTERNAL/libyosys/techlibs/nexus/brams_map.v

R libs/EXTERNAL/libyosys/techlibs/xilinx/cells_sim.v
R libs/EXTERNAL/libyosys/techlibs/xilinx/cells_xtra.py
R libs/EXTERNAL/libyosys/techlibs/xilinx/cells_xtra.v

R libs/EXTERNAL/libyosys/tests/arch/anlogic/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/common/blockram.v
R libs/EXTERNAL/libyosys/tests/arch/ecp5/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/gatemate/fsm.ys
R libs/EXTERNAL/libyosys/tests/arch/intel_alm/counter.ys
R libs/EXTERNAL/libyosys/tests/arch/intel_alm/mux.ys

R libs/EXTERNAL/libyosys/tests/arch/machxo2/fsm.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/logic.ys
R libs/EXTERNAL/libyosys/tests/arch/machxo2/mux.ys

R libs/EXTERNAL/libyosys/tests/arch/machxo2/tribuf.ys
R libs/EXTERNAL/libyosys/tests/arch/nexus/mux.ys
R libs/EXTERNAL/libyosys/tests/arch/xilinx/dsp_abc9.ys
R libs/EXTERNAL/libyosys/tests/memlib/generate.py
R libs/EXTERNAL/libyosys/tests/memlib/memlib_lut.txt
R libs/EXTERNAL/libyosys/tests/memlib/memlib_lut.v
R libs/EXTERNAL/libyosys/tests/simple/arrays01.v
R libs/EXTERNAL/libyosys/tests/simple/forgen02.v
R libs/EXTERNAL/libyosys/tests/svinterfaces/run-test.sh
R libs/EXTERNAL/libyosys/tests/svtypes/struct_array.sv
R libs/EXTERNAL/libyosys/tests/svtypes/typedef_scopes.sv
R libs/EXTERNAL/libyosys/tests/techmap/aigmap.ys
R libs/EXTERNAL/libyosys/tests/various/help.ys

A libs/EXTERNAL/sockpp
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/cad_types.h

M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/echo_arch.cpp

M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/parse_switchblocks.cpp
M libs/libarchfpga/src/physical_types.h
M libs/libarchfpga/src/physical_types_util.cpp
M libs/libarchfpga/src/physical_types_util.h
M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h

R libs/libarchfpga/src/write_arch_bb.cpp

M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/liblog/CMakeLists.txt
M libs/libpugiutil/CMakeLists.txt
M libs/libpugiutil/src/pugixml_util.cpp
M libs/libpugiutil/src/pugixml_util.hpp
M libs/librrgraph/CMakeLists.txt

M libs/librrgraph/src/base/check_rr_graph.cpp
M libs/librrgraph/src/base/check_rr_graph.h

M libs/librrgraph/src/base/rr_edge.h
M libs/librrgraph/src/base/rr_graph_builder.cpp
M libs/librrgraph/src/base/rr_graph_builder.h

M libs/librrgraph/src/base/rr_graph_fwd.h
M libs/librrgraph/src/base/rr_graph_obj.cpp
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h

M libs/librrgraph/src/base/rr_graph_utils.cpp
M libs/librrgraph/src/base/rr_graph_utils.h
M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h
M libs/librrgraph/src/base/rr_spatial_lookup.cpp
M libs/librrgraph/src/base/rr_spatial_lookup.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
M libs/librrgraph/src/io/rr_graph.xsd
M libs/librrgraph/src/io/rr_graph_reader.cpp
M libs/librrgraph/src/io/rr_graph_reader.h
M libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
M libs/librrgraph/src/io/rr_graph_writer.cpp
M libs/librrgraph/src/io/rr_graph_writer.h
M libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp
M libs/librrgraph/src/utils/describe_rr_node.cpp
M libs/librrgraph/src/utils/describe_rr_node.h

M libs/librtlnumber/CMakeLists.txt
M libs/librtlnumber/src/include/internal_bits.hpp
M libs/librtlnumber/src/include/rtl_utils.hpp
M libs/librtlnumber/src/rtl_int.cpp
M libs/libvqm/CMakeLists.txt

M libs/libvqm/vqm_dll.cpp

M libs/libvqm/vqm_parser.y
M libs/libvtrcapnproto/extended_map_lookahead.capnp
M libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
A libs/libvtrcapnproto/intra_cluster_serdes.h
M libs/libvtrcapnproto/map_lookahead.capnp
M libs/libvtrcapnproto/matrix.capnp
M libs/libvtrcapnproto/place_delay_model.capnp
M libs/libvtrutil/CMakeLists.txt
M libs/libvtrutil/cmake/modules/configure_version.cmake
A libs/libvtrutil/src/specrand.cpp
A libs/libvtrutil/src/specrand.h
A libs/libvtrutil/src/tl_optional.hpp

M libs/libvtrutil/src/vtr_array_view.h
M libs/libvtrutil/src/vtr_assert.cpp

M libs/libvtrutil/src/vtr_cache.h
M libs/libvtrutil/src/vtr_dynamic_bitset.h
M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp

A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_int_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_int_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_int_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_ultra_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_ultra_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_ultra_wide_odin_output
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_ultra_wide_yosys_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_ultra_wide_yosys_output
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_wide_odin_input
A odin_ii/regression_test/benchmark/verilog/keywords/nand/range_nand_wide_odin_output
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A odin_ii/regression_test/benchmark/verilog/keywords/nand/replicate_nand_int_wide.vh
A odin_ii/regression_test/benchmark/verilog/keywords/nand/replicate_nand_int_wide_odin_input
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Log Message:
-----------
Merge branch 'master' into patch-1


Commit: 121a16c5718322e10fa5efa2d9badd946e7764d4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/121a16c5718322e10fa5efa2d9badd946e7764d4
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-16 (Tue, 16 Jul 2024)

Changed paths:
M BUILDING.md

Log Message:
-----------
Merge pull request #1997 from trick2011/patch-1

Fixed wrong path for current directory

Commit: 31f60a5fc9e3ce14e5a8a50ba9846b5500943902
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31f60a5fc9e3ce14e5a8a50ba9846b5500943902
Author: vaughnbetz <vaugh...@gmail.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)

Changed paths:
M vpr/src/base/ShowSetup.cpp

Log Message:
-----------
Merge pull request #1919 from nbstrong/absorb_buffer_typo

Corrected typo of abosrb to absorb

Commit: 5ebe2dfece9637e4c43cd153a293a092b412a2f3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5ebe2dfece9637e4c43cd153a293a092b412a2f3
Author: Amir Arjomand <53239438+am...@users.noreply.github.com>
Date: 2024-07-19 (Fri, 19 Jul 2024)

Changed paths:
M .github/workflows/test.yml
M vpr/src/base/ShowSetup.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into Yosys42


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/06a9608805c4...5ebe2dfece96

[sara_mahmoudi]

Branch: refs/heads/specify_loc_for_custom_SB

Commit: 4c516ab952c476318f65c9c0c7bee2a5fdc310e5
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4c516ab952c476318f65c9c0c7bee2a5fdc310e5
Author: Hang Yan <ue...@outlook.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M README.developers.md

Log Message:
-----------
[Docs] Updated Profiling VTR Section in Developer Guide

Rewrote the existing Profiling VTR section, specifically the one using
GNU `gprof` tool.

Added another subsection to explain how to use the Linux `perf` tool to
profile VPR and visualize its output.

Commit: e40128d3db73b44f23891d84ef040ce132b6dd94
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e40128d3db73b44f23891d84ef040ce132b6dd94
Author: saaramahmoudi <sin2...@gmail.com>

Date: 2024-07-19 (Fri, 19 Jul 2024)

Changed paths:

M BUILDING.md
M README.developers.md
M vpr/src/base/ShowSetup.cpp

M vtr_flow/arch/ispd/ultrascale_ispd.xml

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into specify_loc_for_custom_SB


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/5b5d8b46677e...e40128d3db73

[Amir Arjomand]

Branch: refs/heads/Yosys42

M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_context.h

M vpr/src/base/vpr_types.h
M vpr/src/noc/noc_link.cpp
M vpr/src/noc/noc_link.h
M vpr/src/noc/noc_routing_algorithm_creator.cpp
M vpr/src/noc/noc_routing_algorithm_creator.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_checkpoint.h
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h
A vpr/src/route/DecompNetlistRouter.h
A vpr/src/route/DecompNetlistRouter.tpp
M vpr/src/route/ParallelNetlistRouter.h
M vpr/src/route/ParallelNetlistRouter.tpp
M vpr/src/route/SerialNetlistRouter.tpp

M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h

M vpr/src/route/connection_router_interface.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/partition_tree.cpp
M vpr/src/route/partition_tree.h
M vpr/src/route/route.cpp

M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h

M vpr/src/route/route_net.cpp
M vpr/src/route/route_net.h
M vpr/src/route/route_net.tpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_tree.h
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
A vpr/src/route/sink_sampling.h
M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_xy_routing.cpp
M vtr_flow/parse/parse_config/vpr_noc.txt
M vtr_flow/scripts/python_libs/vtr/util.py

Log Message:
-----------

Merge branch 'master' into fix_fixed_clusters_issue


Commit: 03fce648c1ac2e76d0a2ec210a9ebf3e5b811f18
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/03fce648c1ac2e76d0a2ec210a9ebf3e5b811f18
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M .github/workflows/test.yml
M CMakeLists.txt
M libs/EXTERNAL/libargparse/README.md

M libs/EXTERNAL/libargparse/src/argparse.cpp
M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/librrgraph/CMakeLists.txt
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h

M libs/librrgraph/src/base/rr_graph_view.h
M libs/libvtrutil/CMakeLists.txt
M libs/libvtrutil/cmake/modules/configure_version.cmake

M libs/libvtrutil/src/vtr_util.cpp
M libs/libvtrutil/src/vtr_util.h

M libs/libvtrutil/test/test_array_view.cpp
M utils/fasm/CMakeLists.txt
M utils/vqm2blif/CMakeLists.txt
M utils/vqm2blif/src/base/cleanup.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp

M vpr/src/base/ShowSetup.cpp
M vpr/src/base/ShowSetup.h
M vpr/src/base/read_interchange_netlist.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h

M vpr/src/route/connection_router.cpp
M vpr/src/route/connection_router.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
M vpr/src/route/route_common.cpp
M vpr/src/route/route_common.h

M vpr/src/route/route_net.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_path_manager.cpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_utilization.cpp

M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp

Log Message:
-----------

Merge branch 'master' into fix_fixed_clusters_issue


Commit: 15cf98ed8a5259633d38787dee494292192cba2b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/15cf98ed8a5259633d38787dee494292192cba2b
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
address PR comments


Commit: 8bd04e46447b54800b92ad1fa63cb7cc858242c9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8bd04e46447b54800b92ad1fa63cb7cc858242c9
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-10 (Wed, 10 Apr 2024)

Changed paths:
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

M vpr/src/place/simpleRL_move_generator.cpp

Log Message:
-----------
add movable_blocks_per_type()


Commit: 14fd2dad34c9c0e4cbe2653b10773f04ac59f08b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/14fd2dad34c9c0e4cbe2653b10773f04ac59f08b
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-11 (Thu, 11 Apr 2024)

Changed paths:
M vpr/src/place/place.cpp

Log Message:
-----------
call create_move_generators() after initial_placement()


Commit: edfc3cc6e005cb0ea90c78d9f55b78f528369d73
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/edfc3cc6e005cb0ea90c78d9f55b78f528369d73
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-04-11 (Thu, 11 Apr 2024)

Changed paths:

M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h

M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libvtrutil/src/vtr_util.cpp
M libs/libvtrutil/src/vtr_util.h
M utils/fasm/src/fasm.cpp
M utils/fasm/src/fasm.h

M utils/fasm/src/fasm_utils.cpp
M utils/fasm/src/fasm_utils.h
M utils/vqm2blif/src/base/hard_block_recog.cpp
M utils/vqm2blif/src/base/preprocess.cpp
M utils/vqm2blif/src/base/vqm2blif_util.cpp
M vpr/src/base/read_blif.cpp
M vpr/src/base/vpr_api.cpp
M yosys/CMakeLists.txt

Log Message:
-----------

Merge branch 'master' into fix_fixed_clusters_issue


Commit: 419324ee87e7051ac890613424d0f80567859528
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/419324ee87e7051ac890613424d0f80567859528
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-05-01 (Wed, 01 May 2024)

Changed paths:

M doc/src/vpr/basic_flow.rst
M doc/src/vpr/command_line_usage.rst
M odin_ii/src/verilog/verilog_bison.y
M vpr/src/base/read_options.cpp

Log Message:
-----------

Date: 2024-05-23 (Thu, 23 May 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/CMakeLists.txt
M libs/libvtrutil/CMakeLists.txt

M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h

M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/SetupGrid.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/atom_netlist.cpp
M vpr/src/base/atom_netlist.h
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition.h

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.cpp
M vpr/src/base/vpr_types.h

M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/manual_moves.cpp
M vpr/src/noc/noc_data_types.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h

M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp

M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/constraints_report.cpp
A vpr/src/pack/noc_aware_cluster_util.cpp
A vpr/src/pack/noc_aware_cluster_util.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/centroid_move_generator.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/directed_moves_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_noc_placment.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_generator.h

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/place_constraints.cpp
M vpr/src/place/simpleRL_move_generator.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------

Log Message:
-----------

Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: 5625dcb9712cb71cada84f46100790b304e9459d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5625dcb9712cb71cada84f46100790b304e9459d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-05-31 (Fri, 31 May 2024)

Changed paths:
M .github/workflows/containers.yml
M .github/workflows/labeler.yml
M .github/workflows/test.yml
M .gitmodules

M CMakeLists.txt
M Dockerfile
M README.developers.md
M blifexplorer/src/container.cpp
M blifexplorer/src/mainwindow.cpp
M dev/DOCKER_DEPLOY.md
M doc/src/quickstart/index.rst
M doc/src/tutorials/flow/basic_flow.rst
M doc/src/vpr/command_line_usage.rst
M libs/EXTERNAL/CMakeLists.txt
M libs/EXTERNAL/libtatum/.gitignore
M libs/EXTERNAL/libtatum/.travis.yml

M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.cpp
M libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.hpp
M libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp
M libs/EXTERNAL/libtatum/scripts/reg_test.py

A libs/EXTERNAL/sockpp
M libs/libarchfpga/CMakeLists.txt
M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp

M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/echo_arch.cpp
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/physical_types.h

M libs/libarchfpga/src/read_fpga_interchange_arch.cpp
M libs/libarchfpga/src/read_fpga_interchange_arch.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h

M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/libpugiutil/src/pugixml_util.cpp
M libs/libpugiutil/src/pugixml_util.hpp
M libs/librrgraph/src/base/rr_graph_obj.cpp

M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h

M libs/libvqm/vqm_dll.cpp
M libs/libvqm/vqm_parser.y
M libs/libvtrutil/CMakeLists.txt
M libs/libvtrutil/src/vtr_array_view.h

M libs/libvtrutil/src/vtr_error.h
M libs/libvtrutil/src/vtr_expr_eval.cpp
M libs/libvtrutil/src/vtr_expr_eval.h

M libs/libvtrutil/src/vtr_ndmatrix.h
M libs/libvtrutil/src/vtr_ragged_matrix.h
M libs/libvtrutil/src/vtr_string_interning.h
M libs/libvtrutil/src/vtr_vector.h
M odin_ii/src/ast/ast_loop_unroll.cpp
M requirements.txt
M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/CheckSetup.h
M vpr/src/base/SetupGrid.cpp
M vpr/src/base/SetupGrid.h

M vpr/src/base/SetupVPR.cpp
M vpr/src/base/SetupVPR.h
M vpr/src/base/ShowSetup.cpp

M vpr/src/base/atom_netlist.cpp
M vpr/src/base/atom_netlist.h
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h
M vpr/src/base/partition.cpp
M vpr/src/base/partition.h

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/base/read_interchange_netlist.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h

M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints.cpp

M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.cpp
M vpr/src/base/vpr_types.h

M vpr/src/draw/draw.cpp
M vpr/src/draw/draw_basic.cpp
M vpr/src/draw/draw_basic.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_rr.cpp
A vpr/src/draw/gtkcomboboxhelper.cpp
A vpr/src/draw/gtkcomboboxhelper.h
M vpr/src/draw/manual_moves.cpp
M vpr/src/noc/bfs_routing.h
M vpr/src/noc/noc_data_types.h
M vpr/src/noc/noc_link.cpp
M vpr/src/noc/noc_link.h
M vpr/src/noc/noc_router.cpp
M vpr/src/noc/noc_router.h
M vpr/src/noc/noc_storage.cpp
M vpr/src/noc/noc_storage.h
M vpr/src/noc/read_xml_noc_traffic_flows_file.cpp
M vpr/src/noc/read_xml_noc_traffic_flows_file.h

M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/attraction_groups.h
M vpr/src/pack/cluster.cpp

M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h
M vpr/src/pack/constraints_report.cpp
A vpr/src/pack/noc_aware_cluster_util.cpp
A vpr/src/pack/noc_aware_cluster_util.h
M vpr/src/pack/pack.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/centroid_move_generator.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/cut_spreader.cpp
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/directed_moves_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_noc_placment.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_generator.h

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_constraints.cpp

M vpr/src/place/place_util.cpp
M vpr/src/place/place_util.h

M vpr/src/place/placer_context.h
M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/place/simpleRL_move_generator.h
M vpr/src/place/static_move_generator.cpp
M vpr/src/place/static_move_generator.h
M vpr/src/place/timing_place_lookup.cpp

M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp

M vpr/src/route/DecompNetlistRouter.tpp
M vpr/src/route/ParallelNetlistRouter.tpp
M vpr/src/route/SerialNetlistRouter.tpp
M vpr/src/route/cb_metrics.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/overuse_report.cpp
M vpr/src/route/route.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_utils.cpp
M vpr/src/route/route_utils.h

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead.h

M vpr/src/route/router_lookahead_compressed_map.cpp

M vpr/src/route/router_lookahead_extended_map.cpp
M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_map_utils.h
M vpr/src/route/router_lookahead_sampling.cpp

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' into fix_fixed_clusters_issue


Commit: 8db689a6358a002f30b22deebe21c3b802d178ad
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8db689a6358a002f30b22deebe21c3b802d178ad
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:

M vpr/src/base/vpr_context.h
M vpr/src/place/compressed_grid.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
add compressed_cluster_constraints


Commit: 6d94b754b9db164a8a198a075566c443862057ff
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6d94b754b9db164a8a198a075566c443862057ff
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:

M vpr/src/place/move_utils.cpp

Log Message:
-----------
update search_range in intersect_range_limit_with_floorplan_constraints()


Commit: 8a32b610c8c7cec6b100f4bf519aadb5809510be
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8a32b610c8c7cec6b100f4bf519aadb5809510be
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

M vpr/src/util/vpr_utils.cpp

Log Message:
-----------
cluster_to_atoms() returns a reference


Commit: 3bb2e9d2ffa40342a1324b2936d215f7d120ffef
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3bb2e9d2ffa40342a1324b2936d215f7d120ffef
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

Log Message:
-----------
removed unused argument of intersect_range_limit_with_floorplan_constraints()


Commit: 976813b0d38fbf7780ae04ab0a0d0a776dc57630
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/976813b0d38fbf7780ae04ab0a0d0a776dc57630
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-10 (Mon, 10 Jun 2024)

Changed paths:
M vpr/src/base/vpr_context.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
add comments

Commit: 4c516ab952c476318f65c9c0c7bee2a5fdc310e5
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4c516ab952c476318f65c9c0c7bee2a5fdc310e5
Author: Hang Yan <ue...@outlook.com>
Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:
M README.developers.md

Log Message:
-----------
[Docs] Updated Profiling VTR Section in Developer Guide

Rewrote the existing Profiling VTR section, specifically the one using
GNU `gprof` tool.

Added another subsection to explain how to use the Linux `perf` tool to
profile VPR and visualize its output.

Commit: 72b4146c098ea702cc71914504e47da8e680bc9e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/72b4146c098ea702cc71914504e47da8e680bc9e
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------
pass block ids by value instead of reference


Commit: 788c9fd707e8ea9fbf44b08a944dbf0ade2029b9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/788c9fd707e8ea9fbf44b08a944dbf0ade2029b9
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/place/compressed_grid.h

Log Message:
-----------
fix grid_loc_to_compressed_loc_approx_round_up()


Commit: 5b20e718cf55b1bf2173db3313ddc5ff87bd4b7a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5b20e718cf55b1bf2173db3313ddc5ff87bd4b7a
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/place/compressed_grid.h

Log Message:
-----------
avoid duplicate code in grid_loc_to_compressed_loc_approx_round_down() and grid_loc_to_compressed_loc_approx_round_up()


Commit: 657325077a6e09bde37f51e7e2bd20463d3bbede
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/657325077a6e09bde37f51e7e2bd20463d3bbede
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------
removed unnecessary referneces


Commit: e9f5821cff2454524d22d5cc888598da8facd018
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e9f5821cff2454524d22d5cc888598da8facd018
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h

Log Message:
-----------
doxygen comments for GridTileLookup


Commit: 9438f73722a7e5b8baf943ffb85afc46e845f76d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9438f73722a7e5b8baf943ffb85afc46e845f76d
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-11 (Tue, 11 Jun 2024)

Changed paths:

M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
doxygen comments for place_constraints.h


Commit: 8944b986a32f026cf19717205dc1827c4296be48
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8944b986a32f026cf19717205dc1827c4296be48
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-12 (Wed, 12 Jun 2024)

Changed paths:

A .github/workflows/noble.yml
M .github/workflows/test.yml

M .gitmodules
M CMakeLists.txt
M README.developers.md
M dev/pylint_check.py
M dev/subtree_config.xml
A doc/_exts/constraintsdomain/__init__.py

M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/server.rst
M doc/src/arch/reference.rst
M doc/src/conf.py
M doc/src/vpr/command_line_usage.rst
A doc/src/vpr/global_routing_constraints.rst

M doc/src/vpr/index.rst
M doc/src/vpr/placement_constraints.rst
A doc/src/vpr/vpr_constraints.rst

M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/libarchfpga/src/physical_types.h
M libs/libarchfpga/src/read_xml_arch_file.cpp

M libs/librrgraph/src/base/check_rr_graph.cpp
M libs/librrgraph/src/base/check_rr_graph.h
M libs/librrgraph/src/base/rr_graph_builder.h
M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h
M libs/librrgraph/src/base/rr_graph_view.h

M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
M libs/librrgraph/src/io/rr_graph.xsd
M libs/librrgraph/src/io/rr_graph_reader.cpp
M libs/librrgraph/src/io/rr_graph_reader.h
M libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
M libs/librrgraph/src/io/rr_graph_writer.cpp
M libs/librrgraph/src/io/rr_graph_writer.h

M libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h

M utils/fasm/test/test_fasm.cpp
M vpr/CMakeLists.txt
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h

M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h

M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h

M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h

M vpr/src/pack/output_clustering.cpp
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp

M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp

M vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp

M vtr_flow/parse/parse_config/vpr_noc.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml
M vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

Log Message:
-----------
resolve conflicts with master


Commit: fb3beca5813ce5c6d3b31aa0872551d58061e1d7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fb3beca5813ce5c6d3b31aa0872551d58061e1d7
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-17 (Mon, 17 Jun 2024)

Changed paths:

M libs/libvtrutil/src/vtr_geometry.h
M vpr/src/base/region.cpp
M vpr/src/base/region.h

Log Message:
-----------
updated Region and RegionRectCoord to support layer range


Commit: d06e43644f8ab0370c74653809d43c710a1982de
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d06e43644f8ab0370c74653809d43c710a1982de
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
M libs/libarchfpga/src/physical_types.h
M libs/libvtrutil/src/vtr_assert.cpp

M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h

M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h

Log Message:
-----------

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/config.txt

Log Message:
-----------
[test] change pass requirement for nightly test 1 to small pass requirements


Commit: 2d8b826002d167ea30f5ce71079b23f5d7450782
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d8b826002d167ea30f5ce71079b23f5d7450782
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt

Log Message:
-----------
[test] fix a few failures


Commit: a52b88e8e26d487dc55931a2bd8befe821a90771
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a52b88e8e26d487dc55931a2bd8befe821a90771
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/pass_requirements_small.txt

Log Message:
-----------
[test] add pass_requirement_small


Commit: 576ee76568f29642237397614c90a562dca84ca9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/576ee76568f29642237397614c90a562dca84ca9
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt

Log Message:
-----------
[test] update strong test


Commit: 0907fcfb21a3842246b8e931bc37bf2cd2a3036c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0907fcfb21a3842246b8e931bc37bf2cd2a3036c
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M libs/libarchfpga/src/echo_arch.cpp
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/partition.cpp

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h

M vpr/src/base/region.cpp
M vpr/src/base/user_place_constraints.h
M vpr/src/base/user_route_constraints.cpp
M vpr/src/base/user_route_constraints.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/pack/pack.cpp
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h
M vpr/src/route/route_net.tpp
M vpr/src/server/pathhelper.cpp

Log Message:
-----------
add layer_low and layer_high to vpr_contstraints.xsd


Commit: 875a238c699f9974e9e097b4333a09fa1ec6e0d4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/875a238c699f9974e9e097b4333a09fa1ec6e0d4
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h

Log Message:
-----------
add layer_low and layer_high to vpr_constraints_writer


Commit: 448aa85a6ff6a020b9fbd8939c7e3f6e9bbc9855
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/448aa85a6ff6a020b9fbd8939c7e3f6e9bbc9855
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:

M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
update grid_tile_lookup to support layer range


Commit: 4abdcdcc8bdc63123f6495ae756012fe3ad98302
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4abdcdcc8bdc63123f6495ae756012fe3ad98302
Author: amin1377 <amin1377....@gmail.com>
Date: 2024-06-18 (Tue, 18 Jun 2024)

Changed paths:
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt

Log Message:
-----------
[test] add small circuit timing


Commit: 0957197ac6b81f14fc3fa458b4eb3c9429b1d06b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0957197ac6b81f14fc3fa458b4eb3c9429b1d06b
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 golden results


Commit: 967d3c7a9cb73262d104e49f839d22573da9fa21
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/967d3c7a9cb73262d104e49f839d22573da9fa21
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 odin golden results


Commit: 17d983b6c569eeb55541ed37289dfb163b247a4f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/17d983b6c569eeb55541ed37289dfb163b247a4f
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[test] update nightly test3/odin


Commit: dc6cef2c8aff49eafad97fa9c0fe055f7f1c5c36
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dc6cef2c8aff49eafad97fa9c0fe055f7f1c5c36
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 7


Commit: a6afa55c9c22657db438ff0a21cbf85f1dec4d1d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a6afa55c9c22657db438ff0a21cbf85f1dec4d1d
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vpr/src/base/read_options.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

Log Message:
-----------
[cli] set place delay model to delta if router lookahead is not of the type map


Commit: 65a188fb895e94ed0165c117d28d8b2fed7fc82c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/65a188fb895e94ed0165c117d28d8b2fed7fc82c
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt

Log Message:
-----------
[test] update basic golden results


Commit: 89e2e29865ab029dc2dbd624bcfbb08a66b088e4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/89e2e29865ab029dc2dbd624bcfbb08a66b088e4
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h

M vpr/src/draw/draw_types.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h

A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: a67c8c29f9aed6ccd8ca91086c1c3a11508171f3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a67c8c29f9aed6ccd8ca91086c1c3a11508171f3
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h
M vpr/src/place/initial_placement.cpp

Log Message:
-----------
updated initial placement to support layer range


Commit: 58f45450e6a41e8bd547412b007da890d1aacf4d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/58f45450e6a41e8bd547412b007da890d1aacf4d
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
A .github/scripts/install_noble_dependencies.sh
M .github/workflows/containers.yml

A .github/workflows/noble.yml
M .github/workflows/test.yml
M CMakeLists.txt
M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst

A doc/src/api/vpr/server.rst
M doc/src/vpr/command_line_usage.rst
M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/physical_types.h
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h

M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_context.h

M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h

A vpr/test/test_compressed_grid.cpp
M vpr/test/test_noc_place_utils.cpp
M vpr/test/test_noc_storage.cpp
M vpr/test/test_server_taskresolver.cpp
M vpr/test/test_server_telegrambuffer.cpp
M vpr/test/test_setup_noc.cpp
M vtr_flow/parse/parse_config/vpr_noc.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' into update_search_range_with_floorplan_constraint


Commit: 9ddf089a71c312de2e29c61128ae8da2870b2cd7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ddf089a71c312de2e29c61128ae8da2870b2cd7
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vpr/test/test_compressed_grid.cpp

Log Message:
-----------
test grid_loc_to_compressed_loc_approx_round_up() and grid_loc_to_compressed_loc_approx_round_down()


Commit: cd9e1c393aa0b9d6c8211b117cc26613db1b6b61
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cd9e1c393aa0b9d6c8211b117cc26613db1b6b61
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:

M vpr/src/base/vpr_context.h

Log Message:
-----------
apply the remaining pr suggestions


Commit: 25e5145d1a4b80c6d05414e5851f3465eec1b8a4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/25e5145d1a4b80c6d05414e5851f3465eec1b8a4
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-19 (Wed, 19 Jun 2024)

Changed paths:
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h

M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
M vpr/test/test_clustered_netlist.cpp
A vpr/test/test_compressed_grid.cpp

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------

Merge branch 'update_search_range_with_floorplan_constraint' into 3d_constraints


Commit: abfba5d5613805d4789b91a5dd33d447ded7a233
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/abfba5d5613805d4789b91a5dd33d447ded7a233
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 golden


Commit: bce6cc0613da4b9389e4096431766eea418931ef
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/bce6cc0613da4b9389e4096431766eea418931ef
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 1 odin golden


Commit: fb35cde36277f8f0850c6d136453d1da53a84246
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fb35cde36277f8f0850c6d136453d1da53a84246
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[test] update nightly test 3 odin golden


Commit: 685bcaa49830bc2848169dced265af341cc01967
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/685bcaa49830bc2848169dced265af341cc01967
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt

Log Message:
-----------
[test] update strong


Commit: fe5f121c042d6781dab729d8389db6e874050907
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fe5f121c042d6781dab729d8389db6e874050907
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt

Log Message:
-----------
[test] change seed number for strong_post_routing to 5


Commit: e07cc08fc350b2dba7814416a9812e3fcc670e50
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e07cc08fc350b2dba7814416a9812e3fcc670e50
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[test] update strong_odin


Commit: e97bfffee65982cfd824c181b15f0feaa6e02a2e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e97bfffee65982cfd824c181b15f0feaa6e02a2e
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M vpr/src/base/region.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

Log Message:
-----------
update place_constraints.cpp to support layer range


Commit: cd75e2171dbe0a69d044d74d067f045deac2ff98
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cd75e2171dbe0a69d044d74d067f045deac2ff98
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/place/move_utils.cpp

Log Message:
-----------
early check to see if a block can be placed in a layer


Commit: dfedc23b56840aefa43341f677a77dfefd34abe6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dfedc23b56840aefa43341f677a77dfefd34abe6
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][src][route] use chan_nodes_added instead of nodes_add when high fanout rt is used


Commit: dad7ac6ca85d40789116752a8e0eb9058f71ab3a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dad7ac6ca85d40789116752a8e0eb9058f71ab3a
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][route] remove has path to sink


Commit: a21d763375dfe0dcae7ca9aee1d0b0b562565fbe
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a21d763375dfe0dcae7ca9aee1d0b0b562565fbe
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M .gitignore
M utils/route_diag/src/main.cpp
M vpr/src/base/read_route.cpp

M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h

M vpr/test/test_connection_router.cpp

Log Message:
-----------
Created final FourAryHeap implementation, but kept BinaryHeap as a inherited class of KAryHeap


Commit: ebd8148218ac1e29ddb5078e6e65b394ef0d924b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ebd8148218ac1e29ddb5078e6e65b394ef0d924b
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:

M .gitignore
R run_heap_tests.py
M utils/route_diag/src/main.cpp
M vpr/src/base/read_route.cpp

M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h

M vpr/test/test_connection_router.cpp

Log Message:
-----------
Created final FourAryHeap implementation, but kept BinaryHeap as a inherited class of KAryHeap


Commit: a7f33f69fe56c1d533a9a0febb4ebd271f048e4d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a7f33f69fe56c1d533a9a0febb4ebd271f048e4d
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
R binary_heap_profiler.py
R binary_heap_profiling_helper.cpp

Log Message:
-----------

Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: b68ce5f89cba35d3ffc607301448c18bc9b73c2c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b68ce5f89cba35d3ffc607301448c18bc9b73c2c
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-20 (Thu, 20 Jun 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h

M libs/libarchfpga/src/physical_types.h
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp

M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h

M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_placement.cpp

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing

Commit: 89a5c882037817fd6f057d65d8e88f418db5eb94
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/89a5c882037817fd6f057d65d8e88f418db5eb94
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
A .github/scripts/install_noble_dependencies.sh

M .github/workflows/containers.yml
M .github/workflows/labeler.yml
A .github/workflows/noble.yml
M .github/workflows/test.yml

M .gitmodules
M CMakeLists.txt
M README.developers.md
M dev/pylint_check.py
M dev/subtree_config.xml
A doc/_exts/constraintsdomain/__init__.py

M doc/src/api/vpr/contexts.rst
M doc/src/api/vpr/index.rst
A doc/src/api/vpr/server.rst
M doc/src/arch/reference.rst
M doc/src/conf.py
M doc/src/vpr/command_line_usage.rst
A doc/src/vpr/global_routing_constraints.rst

M doc/src/vpr/index.rst
M doc/src/vpr/placement_constraints.rst
A doc/src/vpr/vpr_constraints.rst

M doc/src/vtr/index.rst

A doc/src/vtr/server_mode/comm_telegram_body_structure.odg
A doc/src/vtr/server_mode/comm_telegram_body_structure.svg
A doc/src/vtr/server_mode/comm_telegram_structure.odg
A doc/src/vtr/server_mode/comm_telegram_structure.svg
A doc/src/vtr/server_mode/index.rst

M libs/EXTERNAL/libargparse/src/argparse.hpp
M libs/EXTERNAL/libcatch2
M libs/EXTERNAL/libtatum/.gitignore
M libs/EXTERNAL/libtatum/.travis.yml
M libs/EXTERNAL/libtatum/libtatum/tatum/tags/TimingTags.hpp
M libs/EXTERNAL/libtatum/scripts/reg_test.py

M libs/libarchfpga/src/arch_check.cpp
M libs/libarchfpga/src/arch_types.h
M libs/libarchfpga/src/arch_util.cpp

M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h
M libs/libarchfpga/src/main.cpp
M libs/libarchfpga/src/physical_types.h

M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libarchfpga/src/read_xml_arch_file.h
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
A libs/libarchfpga/src/read_xml_arch_file_noc_tag.h
M libs/libarchfpga/src/read_xml_util.cpp
M libs/libarchfpga/src/read_xml_util.h

M libs/libarchfpga/test/test_read_xml_arch_file.cpp
M libs/libpugiutil/src/pugixml_util.cpp
M libs/libpugiutil/src/pugixml_util.hpp

M libs/librrgraph/src/base/check_rr_graph.cpp
M libs/librrgraph/src/base/check_rr_graph.h
M libs/librrgraph/src/base/rr_graph_builder.h

M libs/librrgraph/src/base/rr_graph_storage.cpp
M libs/librrgraph/src/base/rr_graph_storage.h

M libs/librrgraph/src/base/rr_graph_view.h
M libs/librrgraph/src/base/rr_node_impl.h
M libs/librrgraph/src/base/rr_node_types.h

M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
M libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
M libs/librrgraph/src/io/rr_graph.xsd
M libs/librrgraph/src/io/rr_graph_reader.cpp
M libs/librrgraph/src/io/rr_graph_reader.h
M libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
M libs/librrgraph/src/io/rr_graph_writer.cpp
M libs/librrgraph/src/io/rr_graph_writer.h

M libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
M libs/libvtrutil/src/vtr_array_view.h
M libs/libvtrutil/src/vtr_assert.cpp
M libs/libvtrutil/src/vtr_ragged_matrix.h
M libs/libvtrutil/src/vtr_string_interning.h
M libs/libvtrutil/src/vtr_time.cpp
M libs/libvtrutil/src/vtr_time.h

M libs/libvtrutil/src/vtr_vector.h
M utils/fasm/test/test_fasm.cpp
M vpr/CMakeLists.txt
M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/constraints_load.cpp
M vpr/src/base/constraints_load.h

M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx.h

M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/place_and_route.cpp
M vpr/src/base/place_and_route.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/setup_noc.cpp
M vpr/src/base/setup_noc.h
A vpr/src/base/user_place_constraints.cpp
A vpr/src/base/user_place_constraints.h
A vpr/src/base/user_route_constraints.cpp
A vpr/src/base/user_route_constraints.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h
M vpr/src/base/vpr_constraints.cpp

M vpr/src/pack/cluster_placement.cpp
M vpr/src/pack/cluster_placement.h
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/cluster_util.h

M vpr/src/pack/output_clustering.cpp
M vpr/src/pack/pack.cpp
M vpr/src/pack/pack.h
M vpr/src/pack/pb_type_graph.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/centroid_move_generator.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_noc_placement.cpp
M vpr/src/place/initial_placement.cpp

M vpr/src/place/median_move_generator.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h

M vpr/src/place/noc_place_checkpoint.cpp
M vpr/src/place/noc_place_utils.cpp
M vpr/src/place/noc_place_utils.h
M vpr/src/place/place.cpp
M vpr/src/place/place_checkpoint.cpp
M vpr/src/place/placer_context.h
M vpr/src/place/timing_place_lookup.cpp

M vpr/src/place/weighted_centroid_move_generator.cpp
M vpr/src/place/weighted_median_move_generator.cpp

M vpr/src/route/clock_connection_builders.cpp
M vpr/src/route/clock_network_builders.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/route.cpp
M vpr/src/route/route_net.tpp
M vpr/src/route/route_tree.cpp
M vpr/src/route/route_utils.cpp
M vpr/src/route/route_utils.h

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/router_lookahead.cpp
M vpr/src/route/router_lookahead.h

M vpr/src/route/router_lookahead_compressed_map.cpp

M vpr/src/route/router_lookahead_map.cpp
M vpr/src/route/router_lookahead_map_utils.cpp
M vpr/src/route/router_lookahead_map_utils.h

M vpr/test/test_setup_noc.cpp
M vpr/test/test_vpr.cpp
M vpr/test/test_vpr_constraints.cpp

M vpr/test/test_xy_routing.cpp
M vtr_flow/arch/multi_die/README.md
M vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/arch/titan/stratix10_arch.timing.xml
M vtr_flow/parse/parse_config/vpr_noc.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' into improve_binary_heap


Commit: 51762617f6f752fffb3804bfea438374dbc4a947
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/51762617f6f752fffb3804bfea438374dbc4a947
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

Log Message:
-----------

Merge branch 'improve_binary_heap' of github.com:nedsels/vtr-verilog-to-routing into improve_binary_heap


Commit: a5e7c7a0db28d887b3899805adb03e1577687daf
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a5e7c7a0db28d887b3899805adb03e1577687daf
Author: KA7E <kthu...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/base/read_options.cpp

Log Message:
-----------
added default filename generation for input flat placement file


Commit: 02b338a4daae301e32f62fb81d5225733fd4acff
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/02b338a4daae301e32f62fb81d5225733fd4acff
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------

Merge pull request #2625 from verilog-to-routing/add_default_flat_placement_filename

added default filename generation for input flat placement file


Commit: 9a5d3b1e2f5ddfb50ed7f32b392e858530fc852d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9a5d3b1e2f5ddfb50ed7f32b392e858530fc852d
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/read_options.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/connection_router.cpp
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/netlist_routers.h
M vpr/src/route/router_delay_profiling.h

Log Message:
-----------
Fixed bug in FourAryHeap::get_heap_head and make FourAryHeap default heap implementation


Commit: fddfd80d9f4b010014618f2f7e12a139ab23c577
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fddfd80d9f4b010014618f2f7e12a139ab23c577
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt

Log Message:
-----------
[test] update golden multiclock odin


Commit: a3256f4463093e734601da6d5dde3fa9c17831d8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a3256f4463093e734601da6d5dde3fa9c17831d8
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

Log Message:
-----------
[test] update golden results for strong test


Commit: c58ca707d90c213fc865671cdd1f72e51c4f25a7
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c58ca707d90c213fc865671cdd1f72e51c4f25a7
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
parent() is now static function


Commit: acbb0beee5f2d5c31b3c2e32c905fd7b25c5edc2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/acbb0beee5f2d5c31b3c2e32c905fd7b25c5edc2
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
update strong odin


Commit: 339fe8d3c18da6509cd37a362186471800f5add3
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/339fe8d3c18da6509cd37a362186471800f5add3
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h
M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Revert "parent() is now static function"

This reverts commit c58ca707d90c213fc865671cdd1f72e51c4f25a7.


Commit: 423f975d9c4c08389c02f254cf929331f5d8bbc9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/423f975d9c4c08389c02f254cf929331f5d8bbc9
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/base/region.cpp
M vpr/src/base/region.h

Log Message:
-----------
replace initial rect coordinates with numeric_limits functions


Commit: 686011bde16905f32f0c096071b2fdc836432d97
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/686011bde16905f32f0c096071b2fdc836432d97
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
fix compilation errors in test_vpr_constraints.cpp


Commit: d73139d283d8e36979983ecb00ad986f56078f8d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d73139d283d8e36979983ecb00ad986f56078f8d
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
add unit tests for 3d floorplan regions


Commit: e998e82e457d1484b06cc09ceb8feca1487e2a8c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e998e82e457d1484b06cc09ceb8feca1487e2a8c
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
add StringMaker<vtr::Rect<T>>


Commit: 54bf5184a9bbe539cb30582100056bc190127a13
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/54bf5184a9bbe539cb30582100056bc190127a13
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/base/region.cpp

Log Message:
-----------
fix false empty region intersection bug


Commit: 0fcae3aa2ecde3de01b23b24dbe21f9219734120
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0fcae3aa2ecde3de01b23b24dbe21f9219734120
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/src/base/region.cpp

Log Message:
-----------
fix empty region check bug


Commit: 32e6900a18b7d4f456c5003f7798ca36d80aa45f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/32e6900a18b7d4f456c5003f7798ca36d80aa45f
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-21 (Fri, 21 Jun 2024)

Changed paths:

M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
update test_vpr_constraints with cases that have regions spanning multiple layers


Commit: bde3caed47244d5e4948f8f7bf69f040bc455b40
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/bde3caed47244d5e4948f8f7bf69f040bc455b40
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:

M vpr/src/base/ShowSetup.cpp

Log Message:
-----------
Eliminated duplicate code in ShowRouterOpts()


Commit: 679618a2ef93a77f154bde3d67123facc1a358a2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/679618a2ef93a77f154bde3d67123facc1a358a2
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:

M vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.h
M vpr/src/route/k_ary_heap.cpp
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Added Doxygen comments to HeapImplementation and its children (excluding bucket heap)


Commit: d580ab1961d972da9d2f7e2bd686eabe962d7582
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d580ab1961d972da9d2f7e2bd686eabe962d7582
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-23 (Sun, 23 Jun 2024)

Changed paths:

M vpr/src/route/four_ary_heap.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/k_ary_heap.h
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt

Log Message:
-----------
Updated golden values


Commit: d56143b05e91aaac5e6b2623b1eca955d233c32e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d56143b05e91aaac5e6b2623b1eca955d233c32e
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/base/ShowSetup.cpp
M vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.h
M vpr/src/route/k_ary_heap.h

Log Message:
-----------
Modified Doxygen comments on heaps


Commit: 15fb10844c8e581c2e990b006555ef06672a7696
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/15fb10844c8e581c2e990b006555ef06672a7696
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M vpr/src/base/read_options.cpp

Log Message:
-----------

Merge branch 'master' into improve_binary_heap


Commit: aeb4612671bd556a3d2c5578beeef5d66cf414d1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aeb4612671bd556a3d2c5578beeef5d66cf414d1
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/place/initial_placement.cpp

Log Message:
-----------
bugfix: consider the last layer in exhaustive initial placement of a block


Commit: 6fa53e1d467462bc18a8c31d9853aedfdece974a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6fa53e1d467462bc18a8c31d9853aedfdece974a
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/place/place.cpp

Log Message:
-----------
create move generators after movable blocks are determined


Commit: 8641b861a4d166e09f7e7eeb220d0026ee928885
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8641b861a4d166e09f7e7eeb220d0026ee928885
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M README.developers.md
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/device_grid.cpp
M libs/libarchfpga/src/device_grid.h

M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h

M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_types.cpp
M vpr/src/pack/cluster_util.cpp
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/place/compressed_grid.cpp
M vpr/src/place/compressed_grid.h
M vpr/src/place/directed_moves_util.cpp
M vpr/src/place/initial_placement.cpp

M vpr/src/util/vpr_utils.cpp
M vpr/src/util/vpr_utils.h
A vpr/test/test_compressed_grid.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_timing_update_diff/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_timing_update_diff/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' into fix_fixed_clusters_issue


Commit: e32f037b0748d5cb3823060a306a378c0f95fc06
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e32f037b0748d5cb3823060a306a378c0f95fc06
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
bugfix: consider the last layer when constructing GridTileLookup


Commit: 56691b5114f9fec1992788c72b3f2ffa82e9bb20
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56691b5114f9fec1992788c72b3f2ffa82e9bb20
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/base/region.cpp
M vpr/src/pack/constraints_report.cpp

Log Message:
-----------
default layer range when the layer is not specified


Commit: 0abbaa271aa87515a885fae6eb58d967be9ec22d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0abbaa271aa87515a885fae6eb58d967be9ec22d
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------
update min_chan_width_routing_area_total and min_chan_width_routing_area_per_tile for regression_tests/vtr_reg_strong_odin/strong_fix_pins_random


Commit: 62d1243021ed427408b7df871ccbece09c08470a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/62d1243021ed427408b7df871ccbece09c08470a
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------

Merge pull request #2603 from verilog-to-routing/update_search_range_with_floorplan_constraint

Fix high rejection rate for constrained blocks during annealing


Commit: d51f91af930eb9a5aeb75b062d5f7a8e6c6bcc66
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d51f91af930eb9a5aeb75b062d5f7a8e6c6bcc66
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
Updated more golden results


Commit: f96d37b725423c5a4a43e576904149c30c9f1a56
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f96d37b725423c5a4a43e576904149c30c9f1a56
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[CI] update strong golden results


Commit: 63aa39cb76df77761beb09bcedf25ac1b83780e8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/63aa39cb76df77761beb09bcedf25ac1b83780e8
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt

Log Message:
-----------
[ci] update systemverilog test


Commit: a3789ff3ad7db9df3c14c825b5003d7acec18807
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a3789ff3ad7db9df3c14c825b5003d7acec18807
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt

Log Message:
-----------
[test] increase route chan width


Commit: 6484a38383e5c546144336fa1421c98b23b635d9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6484a38383e5c546144336fa1421c98b23b635d9
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
M README.developers.md

M vpr/src/base/CheckSetup.cpp
M vpr/src/base/SetupGrid.h
M vpr/src/base/SetupVPR.cpp
M vpr/src/base/echo_files.cpp
M vpr/src/base/echo_files.h
A vpr/src/base/load_flat_place.cpp
A vpr/src/base/load_flat_place.h

M vpr/src/base/read_options.cpp
M vpr/src/base/read_options.h
M vpr/src/base/read_place.cpp
M vpr/src/base/read_place.h
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_api.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/base/vpr_types.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: a2e2970aab2d11babcd08d60a175498dd5ab0462
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a2e2970aab2d11babcd08d60a175498dd5ab0462
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:

M vpr/src/route/four_ary_heap.cpp

Log Message:
-----------
Fixed bug in FourAryHeap::smallest_child()


Commit: a054a1457607bf99d4c4b70f65e72bf76d9446e8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a054a1457607bf99d4c4b70f65e72bf76d9446e8
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>
Date: 2024-06-24 (Mon, 24 Jun 2024)

Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt

Log Message:
-----------
Added regression test for BinaryHeap


Commit: 51cd8d49e5401b860f6ca1ab89189b09e3340122
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/51cd8d49e5401b860f6ca1ab89189b09e3340122
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M vpr/src/route/heap_type.h

Log Message:
-----------
Added router heap to VPRINTERNALS API


Commit: d906ea860a40742b95a5d5f17b1d642c535c66d6
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/d906ea860a40742b95a5d5f17b1d642c535c66d6
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M doc/src/api/vprinternals/router_heap.rst
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_context.h
M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

M vpr/src/route/heap_type.h
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_compressed_grid.cpp

Log Message:
-----------

Merge branch 'master' into improve_binary_heap


Commit: 4e296fc32a1f59a5d1c471936bd56092118301ab
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4e296fc32a1f59a5d1c471936bd56092118301ab
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[ci] update strong odin


Commit: 4d8a519f4a5bd6649bc3550d0417c8b427d83c1e
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/4d8a519f4a5bd6649bc3550d0417c8b427d83c1e
Author: saaramahmoudi <sin2...@gmail.com>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M vpr/src/route/rr_graph2.cpp

Log Message:
-----------
bug resolved: both incr and dec track switches were using same index


Commit: fc49189099dc471b22916071bc336d39b60f7a2b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fc49189099dc471b22916071bc336d39b60f7a2b
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
Added more golden results


Commit: 24449d365a8e31e7f38a6d5eec05bb1c60b3eb5d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/24449d365a8e31e7f38a6d5eec05bb1c60b3eb5d
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
M libs/libvtrutil/src/vtr_geometry.h
M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h

M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h

M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/initial_placement.cpp
M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp

Log Message:
-----------
remove RegionRectCoord class


Commit: fa40fc31646997f47d8d80c3b3ecd61e7ab96016
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fa40fc31646997f47d8d80c3b3ecd61e7ab96016
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:

M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
remove calls to get_region_bounds() and set_region_bounds()


Commit: 3d6941fcf8baafddb39d0af8eb64012d013a3761
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3d6941fcf8baafddb39d0af8eb64012d013a3761
Author: soheilshahrouz <sohe...@gmail.com>
Date: 2024-06-25 (Tue, 25 Jun 2024)

Changed paths:
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/three_partitionregion_multiregion.xml

Log Message:
-----------
add CI test for 3d placement constraints


Commit: 0c2261abac76a44e191aeeeb33c3087a0a0237a4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/0c2261abac76a44e191aeeeb33c3087a0a0237a4
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:

M vtr_flow/scripts/python_libs/vtr/log_parse.py

Log Message:
-----------
[debug] print check value


Commit: f77e0e41bc6757fff4fbdc72c0724a2317db9a2f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f77e0e41bc6757fff4fbdc72c0724a2317db9a2f
Author: Amin Mohaghegh <amin1377....@gmail.com>

Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------

Merge pull request #2624 from verilog-to-routing/high_fanout_rt

CHAN Node Count - High Fanout RT


Commit: 2d1de0c793a770a6b8ce7aa804cacd7b2a149167
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d1de0c793a770a6b8ce7aa804cacd7b2a149167
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:

M vpr/src/base/partition_region.cpp
M vpr/src/base/vpr_context.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_noc.h

Log Message:
-----------
draw floorplan regions for 3d architectures


Commit: 33ee602bf7b876670691b6982b3462780ddb5a63
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/33ee602bf7b876670691b6982b3462780ddb5a63
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: 6e5a814f65cd643a3fee6afd0aac05f346224a89
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/6e5a814f65cd643a3fee6afd0aac05f346224a89
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-26 (Wed, 26 Jun 2024)

Changed paths:

M vtr_flow/scripts/python_libs/vtr/log_parse.py

Log Message:
-----------
[debug] use orginal check val


Commit: 558a2c123eeb7c2f75562c4526b1e6029c756d95
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/558a2c123eeb7c2f75562c4526b1e6029c756d95
Author: saaramahmoudi <sin2...@gmail.com>

Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:

M vpr/src/route/rr_graph.cpp

Log Message:
-----------
block_type_pin_index_to_name requires a third argument


Commit: 31b8261bc4848d95a89adead79c551c89565cd6a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/31b8261bc4848d95a89adead79c551c89565cd6a
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:

M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py

Log Message:
-----------
[debug] print pass for failed tests


Commit: 42934616e96ed97465f4b3b3fff67d9100f9f308
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/42934616e96ed97465f4b3b3fff67d9100f9f308
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:

M vpr/src/route/connection_router.cpp

Log Message:
-----------
[vpr][route] remove target_node is valid


Commit: 1ce545f813e906d6ba4d7c305b2809c9a023b1fc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1ce545f813e906d6ba4d7c305b2809c9a023b1fc
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph.cpp

Log Message:
-----------

Merge pull request #2631 from verilog-to-routing/fc_log

VTR_LOG to print Fc values for pins bug


Commit: dce37b9da8da475d6b56898b871a2d8398f0a525
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/dce37b9da8da475d6b56898b871a2d8398f0a525
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-27 (Thu, 27 Jun 2024)

Changed paths:

M .gitignore
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst
M utils/route_diag/src/main.cpp
M vpr/src/base/ShowSetup.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_route.cpp

M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h

M vpr/test/test_connection_router.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt

Log Message:
-----------

Merge pull request #2627 from nedsels/improve_binary_heap

Update BinaryHeap to FourAryHeap


Commit: 5c40446ceea01f61ccf31483f6d5ba6da97733b5
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/5c40446ceea01f61ccf31483f6d5ba6da97733b5
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:

M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp

M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h

M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------

Merge pull request #2495 from verilog-to-routing/fix_fixed_clusters_issue

Fix fixed clusters issue


Commit: 3e9bc7d8f0f4476f32dab3dd310c63d9cb645f12
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3e9bc7d8f0f4476f32dab3dd310c63d9cb645f12
Author: Nathan Shreve <shre...@betzgrp-wintermute.eecg.utoronto.ca>

Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:

M doc/src/api/vprinternals/router_heap.rst
M vpr/src/route/heap_type.h

Log Message:
-----------
In documentation, FourAryHeap and KAryHeap no longer show inherited member info; also, t_heap fn.s described better


Commit: f1041229baccf9b1cfe1c6b33245fe65b0db2c7d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f1041229baccf9b1cfe1c6b33245fe65b0db2c7d
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M doc/src/api/vprinternals/router_heap.rst
M vpr/src/route/heap_type.h

Log Message:
-----------

Merge pull request #2634 from nedsels/update_heap_documentation

Router Heap documentation update


Commit: 08d886c1159be49d7f1c2934008343e565763ba9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/08d886c1159be49d7f1c2934008343e565763ba9
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-06-28 (Fri, 28 Jun 2024)

Changed paths:
M vpr/src/route/rr_graph2.cpp

Log Message:
-----------

Merge pull request #2630 from verilog-to-routing/rr_graph_edge_bug

RR graph edge creation uses a incorrect switch type for decremental tracks


Commit: 8d41358e01c287cf7a33e6f3b337c007ae9d2aa4
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/8d41358e01c287cf7a33e6f3b337c007ae9d2aa4
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:

M vpr/src/base/partition_region.h
M vpr/src/base/region.cpp

Log Message:
-----------
add hash function for PartitionRegion


Commit: 9fd7389af033307fd2a54fc281b9242d3bc01931
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9fd7389af033307fd2a54fc281b9242d3bc01931
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:

M vpr/src/base/partition_region.h

Log Message:
-----------
add == operator for PartitionRegion


Commit: 571cedec79db531f9d96bef28539d9f139915fae
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/571cedec79db531f9d96bef28539d9f139915fae
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:

M vpr/src/base/vpr_context.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp

Log Message:
-----------
changed floorplan_constraints_regions_overfull() to check whether whole PartitionRegions are full instead of individual Regions


Commit: c74ca63dba3d7b17e9b1cce75902a1646575047c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/c74ca63dba3d7b17e9b1cce75902a1646575047c
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-06-30 (Sun, 30 Jun 2024)

Changed paths:

M vpr/src/base/vpr_constraints_serializer.h

Log Message:
-----------
check the legality of region when parsing it


Commit: e7ec2194cb9cf05873317b8cb48a949b594b3b3f
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e7ec2194cb9cf05873317b8cb48a949b594b3b3f
Author: Amin Mohaghegh <amin1377....@gmail.com>

Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:
M vpr/src/route/connection_router.cpp

Log Message:
-----------

Merge pull request #2626 from verilog-to-routing/remove_has_path_to_sink

Remove `has_path_to_sink`


Commit: ea6464eef785f1f343d305921b3f13c53d0470c0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ea6464eef785f1f343d305921b3f13c53d0470c0
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:

M vpr/src/base/region.cpp
M vpr/src/base/vpr_constraints_serializer.h
M vpr/src/pack/constraints_report.cpp
M vpr/src/pack/constraints_report.h
M vpr/src/place/grid_tile_lookup.h

Log Message:
-----------
add comments


Commit: e4f6f4f3c6aa5cb4003ca11fdd877a6c71078062
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/e4f6f4f3c6aa5cb4003ca11fdd877a6c71078062
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-01 (Mon, 01 Jul 2024)

Changed paths:

M .gitignore
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst

M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M utils/route_diag/src/main.cpp

M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h

M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/read_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h

M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/test/test_connection_router.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: fc85d7163bc297cda972d07a373a121fd302d8b0
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/fc85d7163bc297cda972d07a373a121fd302d8b0
Author: AlexandreSinger <alex....@mail.utoronto.ca>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------
[Tests] Updated Golden Solutions

CI was failing due to three nightly test failures. Updated the golden
results for these tests to resolve the errors.


Commit: 74805b84d33964a0ec93b7af132350b117ebb501
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/74805b84d33964a0ec93b7af132350b117ebb501
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[ci] add status result to nightly test 1


Commit: cb681d7e3f0cc511bd64ba3eac0b1330a9461e02
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cb681d7e3f0cc511bd64ba3eac0b1330a9461e02
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt

Log Message:
-----------
[ci] add status field to nightly_test1_odin


Commit: aa6623f0572d03ce921679a8be883ae39c19c04d
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/aa6623f0572d03ce921679a8be883ae39c19c04d
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt

Log Message:
-----------
[ci] increase channel width for vpr_verify_rr_Graph


Commit: 56a3b3d08fc8d8305d4ab7e9b9808d896aa6f451
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/56a3b3d08fc8d8305d4ab7e9b9808d896aa6f451
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt

Log Message:
-----------
[ci] update nightly test2 odin golden


Commit: 2bb270e64dae3a3e8aa39d1d89dbf563a94ec1f1
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2bb270e64dae3a3e8aa39d1d89dbf563a94ec1f1
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt

Log Message:
-----------
[ci] update stron odin golden results


Commit: 2596b4de9230f568625f499bc925e0b9076ca793
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2596b4de9230f568625f499bc925e0b9076ca793
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/scripts/python_libs/vtr/log_parse.py
M vtr_flow/scripts/python_libs/vtr/parse_vtr_task.py

Log Message:
-----------
[ci] remove debugging messages from script


Commit: a26bbbbe75ad0264d98be26378877a13a7095929
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a26bbbbe75ad0264d98be26378877a13a7095929
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt

Log Message:
-----------
[ci] update basic golden result


Commit: 00e5b65328a54bc4d81986ad560e9226c68db9c8
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/00e5b65328a54bc4d81986ad560e9226c68db9c8
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vpr/test/test_vpr_constraints.cpp

Log Message:
-----------
fix the failing unit test


Commit: 9ddb7d51c8787264fc93a90252f09fcd148af32b
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9ddb7d51c8787264fc93a90252f09fcd148af32b
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------

Merge pull request #2640 from AlexandreSinger/feature-ci-update-golden

[Tests] Updated Golden Solutions


Commit: 9849395817dd9a13296dc100ec54d2eaa1365b8a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/9849395817dd9a13296dc100ec54d2eaa1365b8a
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M doc/src/vpr/placement_constraints.rst

Log Message:
-----------
updated docs with layer_low and layer_high


Commit: 2d959d882511ac3be83efd9cf8cba8c0ae7026ca
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2d959d882511ac3be83efd9cf8cba8c0ae7026ca
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:
M vpr/src/base/read_options.cpp
M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/locked_down.xml
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/three_partitionregion_multiregion.xml

Log Message:
-----------
add a 3D constraint file where are atoms are locked down


Commit: ba786496888e578e69ed85a04030c857f979b10a
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/ba786496888e578e69ed85a04030c857f979b10a
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-03 (Wed, 03 Jul 2024)

Changed paths:

M .gitignore
M README.developers.md
M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst

M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/read_xml_arch_file.cpp
M utils/route_diag/src/main.cpp

M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h

M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/read_route.cpp
M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_context.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h

Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt

Log Message:
-----------

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enable_simple_place_delay_matrix


Commit: 1618ee34fbbd7a69e09e2d6c5c91121ba33fa862
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1618ee34fbbd7a69e09e2d6c5c91121ba33fa862
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt

Log Message:
-----------
[ci] add vpr status to nightly test 1 golden res


Commit: 1a6bb5ee506689c0459269a561bd79899f49426c
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/1a6bb5ee506689c0459269a561bd79899f49426c
Author: amin1377 <amin1377....@gmail.com>

Date: 2024-07-04 (Thu, 04 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt

Log Message:
-----------
[ci] add vpr status to power extend


Commit: b00967cd43974a6066b86e5a80bd7055e50a85b9
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/b00967cd43974a6066b86e5a80bd7055e50a85b9
Author: Amin Mohaghegh <amin1377....@gmail.com>

Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt

Log Message:
-----------

Merge pull request #2608 from verilog-to-routing/enable_simple_place_delay_matrix

Use Simple Place Delay Model By Default


Commit: a446074667279efb8987bc0eb362a385466627bc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a446074667279efb8987bc0eb362a385466627bc
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:

M vpr/src/base/vpr_constraints_writer.cpp
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt

Log Message:
-----------
add vpr_tight_floorplan_3d to task list


Commit: a24e8abc3f7c93ae84f67dae16f350b0f15cd0d2
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/a24e8abc3f7c93ae84f67dae16f350b0f15cd0d2
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:

M vpr/src/place/grid_tile_lookup.cpp

Log Message:
-----------
bugfix: consider the last layer in region_with_subtile_count()


Commit: 224c8acb1d8cdd2665ca6d60fb6b6b4bfcee8325
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/224c8acb1d8cdd2665ca6d60fb6b6b4bfcee8325
Author: soheilshahrouz <sohe...@gmail.com>

Date: 2024-07-05 (Fri, 05 Jul 2024)

Changed paths:

M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp
A vtr_flow/arch/titan/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
R vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/locked_down.xml

Log Message:
-----------
fixbug: print block type name and the number of tiles for overfull prs

Commit: baa5607345b7713acf7eff54b1b67af5bb9f8161
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/baa5607345b7713acf7eff54b1b67af5bb9f8161
Author: Amir Arjomand <amirarj...@gmail.com>
Date: 2024-07-08 (Mon, 08 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------
Turned off vtr_reg_system_verilog and parmys_reg_strong [-DYOSYS_F4PGA_PLUGINS=ON] test in test.yml

Commit: cb55d6641e4f9779df339b43ed01a479511aef49
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/cb55d6641e4f9779df339b43ed01a479511aef49
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-08 (Mon, 08 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------

Merge pull request #2596 from verilog-to-routing/yosys_update

Yosys Update -> v0.42


Commit: f37ec16665d60a431b593fcdbcb29fb133b8f3dc
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/f37ec16665d60a431b593fcdbcb29fb133b8f3dc
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-08 (Mon, 08 Jul 2024)

Changed paths:
M doc/src/vpr/placement_constraints.rst
M libs/libarchfpga/src/echo_arch.cpp
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp

M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/partition.cpp

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h

M vpr/src/base/read_options.cpp
M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/user_place_constraints.h
M vpr/src/base/user_route_constraints.cpp
M vpr/src/base/user_route_constraints.h
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp
M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h

M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_noc.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/pack/constraints_report.h
M vpr/src/pack/pack.cpp
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h

M vpr/src/route/route_net.tpp
M vpr/src/server/pathhelper.cpp
M vpr/test/test_clustered_netlist.cpp
M vpr/test/test_vpr_constraints.cpp
A vtr_flow/arch/titan/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml

Log Message:
-----------

Merge pull request #2623 from verilog-to-routing/3d_constraints

3D Placement Constraints


Commit: 3af3beaf751394053b905ebd25421d16af2eea81
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/3af3beaf751394053b905ebd25421d16af2eea81
Author: AlexandreSinger <49374526+Ale...@users.noreply.github.com>

Date: 2024-07-09 (Tue, 09 Jul 2024)

Changed paths:

M .github/workflows/test.yml

Log Message:
-----------
Revert "Yosys Update -> v0.42"


Commit: 16adbfa4f0f5d7269ace3ce9dec1ab2a19fa1fea
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/16adbfa4f0f5d7269ace3ce9dec1ab2a19fa1fea
Author: vaughnbetz <vaugh...@gmail.com>

Date: 2024-07-09 (Tue, 09 Jul 2024)

Changed paths:
M .github/workflows/test.yml

Log Message:
-----------

Merge pull request #2643 from verilog-to-routing/revert-2596-yosys_update

Revert "Yosys Update -> v0.42"

Commit: 021d635388e5408ac282e7d3aa7b44e5549d4f42
https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/021d635388e5408ac282e7d3aa7b44e5549d4f42
Author: Amir Arjomand <53239438+am...@users.noreply.github.com>

Date: 2024-07-19 (Fri, 19 Jul 2024)

Changed paths:

M .gitignore
M BUILDING.md
M README.developers.md

M doc/src/api/vprinternals/index.rst
A doc/src/api/vprinternals/router_heap.rst
A doc/src/api/vprinternals/vpr_router.rst

M doc/src/vpr/placement_constraints.rst
M libs/libarchfpga/src/arch_util.cpp
M libs/libarchfpga/src/arch_util.h
M libs/libarchfpga/src/echo_arch.cpp
M libs/libarchfpga/src/read_xml_arch_file.cpp
M libs/libvtrutil/src/vtr_geometry.h
M libs/libvtrutil/src/vtr_geometry.tpp
M utils/route_diag/src/main.cpp

M vpr/src/base/ShowSetup.cpp
M vpr/src/base/clustered_netlist.cpp
M vpr/src/base/clustered_netlist.h

M vpr/src/base/gen/vpr_constraints_uxsdcxx.h
M vpr/src/base/gen/vpr_constraints_uxsdcxx_interface.h
M vpr/src/base/partition.cpp

M vpr/src/base/partition_region.cpp
M vpr/src/base/partition_region.h

M vpr/src/base/read_circuit.cpp
M vpr/src/base/read_options.cpp
M vpr/src/base/read_place.cpp
M vpr/src/base/read_route.cpp

M vpr/src/base/region.cpp
M vpr/src/base/region.h
M vpr/src/base/user_place_constraints.h
M vpr/src/base/user_route_constraints.cpp
M vpr/src/base/user_route_constraints.h

M vpr/src/base/vpr_api.cpp
M vpr/src/base/vpr_constraints.cpp
M vpr/src/base/vpr_constraints.h
M vpr/src/base/vpr_constraints.xsd
M vpr/src/base/vpr_constraints_reader.cpp

M vpr/src/base/vpr_constraints_serializer.h

M vpr/src/base/vpr_constraints_writer.cpp
M vpr/src/base/vpr_constraints_writer.h
M vpr/src/base/vpr_context.h

M vpr/src/base/vpr_types.h
M vpr/src/draw/draw_floorplanning.cpp
M vpr/src/draw/draw_noc.cpp
M vpr/src/draw/draw_noc.h
M vpr/src/pack/attraction_groups.cpp
M vpr/src/pack/constraints_report.cpp
M vpr/src/pack/constraints_report.h
M vpr/src/pack/pack.cpp

M vpr/src/pack/re_cluster.cpp
M vpr/src/pack/re_cluster_util.cpp
M vpr/src/pack/re_cluster_util.h
M vpr/src/place/RL_agent_util.cpp
M vpr/src/place/RL_agent_util.h

M vpr/src/place/compressed_grid.h

M vpr/src/place/grid_tile_lookup.cpp
M vpr/src/place/grid_tile_lookup.h
M vpr/src/place/initial_placement.cpp

M vpr/src/place/move_utils.cpp
M vpr/src/place/move_utils.h
M vpr/src/place/place.cpp

M vpr/src/place/place_constraints.cpp
M vpr/src/place/place_constraints.h
M vpr/src/place/simpleRL_move_generator.cpp
M vpr/src/route/binary_heap.cpp
M vpr/src/route/binary_heap.h

M vpr/src/route/connection_router.cpp
A vpr/src/route/four_ary_heap.cpp
A vpr/src/route/four_ary_heap.h
M vpr/src/route/heap_type.cpp
M vpr/src/route/heap_type.h
A vpr/src/route/k_ary_heap.cpp
A vpr/src/route/k_ary_heap.h
M vpr/src/route/netlist_routers.h
M vpr/src/route/route.cpp

M vpr/src/route/route_net.tpp
M vpr/src/route/router_delay_profiling.cpp
M vpr/src/route/router_delay_profiling.h
M vpr/src/route/rr_graph.cpp
M vpr/src/route/rr_graph2.cpp
M vpr/src/server/pathhelper.cpp
M vpr/src/util/vpr_utils.cpp
M vpr/test/test_clustered_netlist.cpp
M vpr/test/test_compressed_grid.cpp
M vpr/test/test_connection_router.cpp
M vpr/test/test_vpr_constraints.cpp
M vtr_flow/arch/ispd/ultrascale_ispd.xml
A vtr_flow/arch/titan/3d_full_OPIN_inter_die_stratixiv_arch.timing.xml

A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_fixed_chan_width_small.txt
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_relaxed_chan_width_small.txt
A vtr_flow/parse/pass_requirements/pass_requirements_chain_small.txt
A vtr_flow/parse/pass_requirements/pass_requirements_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_min_chan_width_small.txt
A vtr_flow/parse/pass_requirements/timing/pass_requirements.vpr_route_relaxed_chan_width_small.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/config.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/FIR_filters_frac/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/adder_trees/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/figure_8/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/open_cores_frac/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_arch_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/power_extended_circuit_list/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/vpr_reg_mcnc_equiv/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_bidir/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_bidir/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor_chain_predictor_off/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/titan_s10_qor/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/task_list.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml
A vtr_flow/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml

M vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/config.txt
A vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/config.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt

M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt
M vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt

Log Message:
-----------
Merge branch 'master' into Yosys42


Compare: https://github.com/verilog-to-routing/vtr-verilog-to-routing/compare/a23006e1e6f0...021d635388e5

[Amir Arjomand]

[sara_mahmoudi]

[tangxifan]