We are able to send the command and address and even data to to be
written into the memory into the flash memory.But the problem is sir
for flash memory to give some output in return we will have to design
it in such a way.
And during read cycle if we some how are directly taking the data read
from the memory as the input from the test bench then the moment we
are bringing it into AMBA-slave from ONFI side due to clock
differences of onfi and flash we are facing timing problems.Something
we are presently working on.
Sir we have attached the top level block diagram of the design we are
working on.
But sir we really think you need to enlighten for what is actually
done in such processor and memory interactions and not just any memory
flash memory.
Thank you
regards
VSDV 2011