codes-control ip generator,h_trans decoder,data sending block,test becnch for write

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Chandrakant Jayanti

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Jan 9, 2012, 10:46:06 PM1/9/12

to ashwath.c.h, vsdv2011

control input
contro input -- onfi bus state
3'b000 -- stand_by
3'b001 -- idle
3'b010 -- command
3'b011 -- address
3'b100 -- data_input
3'b101 -- data_output

the data is getting divided in data_div block and is begin sent.Please
look at trhe snap shot for better understanding.

comm_mux_block.v

control_ip.v

cycles_decd.v

data_div.v

h_tran_decoder.v

syncb_top_d.v

tb.v

Screenshot-3.png

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