Pci Express M.2 Specification Revision 1.0 14.pdfl

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Supersedes General Order 24-B (effective July 1, 1964). General Order 24-C became effective on August 27, 2012. Revisions to General Order 24 include: 1) the filing of a General Order 24 report on a quarterly instead of a monthly basis for the first year of the Financing Rule. Commencing in the second year, reports will be filed semi-annually (June and December); 2) revisions to the type of information provided in such reports; 3) elimination of requirement that a utility maintain a separate bank account to record money derived from the sale of securities, except where the Commission specifically designates what the proceeds can be used for, or in instances where the loan will be repaid by surcharge; and 4) an updated list of information required in the report, given the manner in which securities transactions are now recorded by utilities as required by other regulatory entities.

Construction and filing of tariffs issued by highway common carriers, petroleum irregular route carriers, freight forwarders and express corporations (except air express companies and air freight forwarders). This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Pci Express M.2 Specification Revision 1.0 14.pdfl

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Handling, and accounting for C.O.D. shipments by express corporations, freight forwarders, highway carriers, passenger stage corporations and household goods carriers. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Issuance of free or reduced rate transportation and recording of passes. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Bonding requirements in connection with subhauling or leasing of equipment from an employee. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Petitions for suspension and investigation of tariffs and schedules of common carriers, air transportation companies, warehousemen and wharfingers. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Construction and filing of tariffs issued by vessel carriers, pipeline corporations, toll bridge corporations, wharfingers and common carriers other than railroads and other than those governed by General Order No. 79 or No. 80-A

Public inspection of tariff schedules of common carriers. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Filing of rate quotation statements for transportation by common carriers for state, county or municipal governments. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Rules Governing the Organization and operation of Rate Bureaus and their Common Carrier Member Engaged in Collective Ratemaking. This GO has been preempted in part, or no longer applies to some carriers. Please refer to PUC Resolution TEA-2 and TEA-4 when interpreting it.

Rules Governing the Development of Programs to Increase Participation of Women, Minority, Disabled Veteran and Lesbian, Gay, Bisexual and Transgender (LGBT) Business Enterprises in Procurement of Contracts from Utilities as Required by Public Utilities Code Sections 8281-8286

Rules and regulation pertaining to private carriers of passengers, as defined by Public Utilities Code Section 4001, and organizations that provide transportation services incidental to operation of a youth camp which are required to register as private carriers pursuant to Public Utilities Code Section 5353(n)(2)(A).

Rulemaking for electric distribution facility standard setting D.98-07-097 (adopted G.O. 166). Revised: 5/20/21 (D.21-05-019). Utilities should refer to the most recent version of Guidelines for Notification of the CPUC Energy Division of Electric Emergencies for instructions regarding reporting of 6 levels of electric service outage emergencies.

NVM Express (NVMe) or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS) is an open, logical-device interface specification for accessing a computer's non-volatile storage media usually attached via the PCI Express bus. The initial NVM stands for non-volatile memory, which is often NAND flash memory that comes in several physical form factors, including solid-state drives (SSDs), PCIe add-in cards, and M.2 cards, the successor to mSATA cards. NVM Express, as a logical-device interface, has been designed to capitalize on the low latency and internal parallelism of solid-state storage devices.[2]

Architecturally, the logic for NVMe is physically stored within and executed by the NVMe controller chip that is physically co-located with the storage media, usually an SSD. Version changes for NVMe, e.g., 1.3 to 1.4, are incorporated within the storage media, and do not affect PCIe-compatible components such as motherboards and CPUs.[3]

By its design, NVM Express allows host hardware and software to fully exploit the levels of parallelism possible in modern SSDs. As a result, NVM Express reduces I/O overhead and brings various performance improvements relative to previous logical-device interfaces, including multiple long command queues, and reduced latency. The previous interface protocols like AHCI were developed for use with far slower hard disk drives (HDD) where a very lengthy delay (relative to CPU operations) exists between a request and data transfer, where data speeds are much slower than RAM speeds, and where disk rotation and seek time give rise to further optimization requirements.

NVM Express devices are chiefly available in the form of standard-sized PCI Express expansion cards[4] and as 2.5-inch form-factor devices that provide a four-lane PCI Express interface through the U.2 connector (formerly known as SFF-8639).[5][6] Storage devices using SATA Express and the M.2 specification which support NVM Express as the logical-device interface are a popular use-case for NVMe and have become the dominant form of solid-state storage for servers, desktops, and laptops alike.[7][8]

High-end SSDs had been made using the PCI Express bus before NVMe, but using non-standard specification interfaces. By standardizing the interface of SSDs, operating systems only need one common device driver to work with all SSDs adhering to the specification. It also means that each SSD manufacturer does not have to design specific interface drivers. This is similar to how USB mass storage devices are built to follow the USB mass-storage device class specification and work with all computers, with no per-device drivers needed.[12]

NVM Express devices are also used as the building block of the burst buffer storage in many leading supercomputers, such as Fugaku Supercomputer, Summit Supercomputer and Sierra Supercomputer, etc.[13][14]

The first details of a new standard for accessing non-volatile memory emerged at the Intel Developer Forum 2007, when NVMHCI was shown as the host-side protocol of a proposed architectural design that had Open NAND Flash Interface Working Group (ONFI) on the memory (flash) chips side.[15] A NVMHCI working group led by Intel was formed that year. The NVMHCI 1.0 specification was completed in April 2008 and released on Intel's web site.[16][17][18]

Technical work on NVMe began in the second half of 2009.[19] The NVMe specifications were developed by the NVM Express Workgroup, which consists of more than 90 companies; Amber Huffman of Intel was the working group's chair. Version 1.0 of the specification was released on 1 March 2011,[20] while version 1.1 of the specification was released on 11 October 2012.[21] Major features added in version 1.1 are multi-path I/O (with namespace sharing) and arbitrary-length scatter-gather I/O. It is expected that future revisions will significantly enhance namespace management.[19] Because of its feature focus, NVMe 1.1 was initially called "Enterprise NVMHCI".[22] An update for the base NVMe specification, called version 1.0e, was released in January 2013.[23] In June 2011, a Promoter Group led by seven companies was formed.

The first commercially available NVMe chipsets were released by Integrated Device Technology (89HF16P04AG3 and 89HF32P08AG3) in August 2012.[24][25] The first NVMe drive, Samsung's XS1715 enterprise drive, was announced in July 2013; according to Samsung, this drive supported 3 GB/s read speeds, six times faster than their previous enterprise offerings.[26] The LSI SandForce SF3700 controller family, released in November 2013, also supports NVMe.[27][28] A Kingston HyperX "prosumer" product using this controller was showcased at the Consumer Electronics Show 2014 and promised similar performance.[29][30] In June 2014, Intel announced their first NVM Express products, the Intel SSD data center family that interfaces with the host through PCI Express bus, which includes the DC P3700 series, the DC P3600 series, and the DC P3500 series.[31] As of November 2014[update], NVMe drives are commercially available.

In March 2014, the group incorporated to become NVM Express, Inc., which as of November 2014[update] consists of more than 65 companies from across the industry. NVM Express specifications are owned and maintained by NVM Express, Inc., which also promotes industry awareness of NVM Express as an industry-wide standard. NVM Express, Inc. is directed by a thirteen-member board of directors selected from the Promoter Group, which includes Cisco, Dell, EMC, HGST, Intel, Micron, Microsoft, NetApp, Oracle, PMC, Samsung, SanDisk and Seagate.[32]

NVMe Host Memory Buffer (HMB) added in version 1.2 of the NVMe specification.[33] HMB allows SSDs to utilize the host's DRAM, which can improve the I/O performance for DRAM-less SSDs.[34] For example, HMB can be used for cache the FTL table by the SSD controller, which can improve I/O performance.[35] NVMe 2.0 added Zoned Namespaces (ZNS) and support for rotating media such as hard drives. ZNS allows data to be mapped directly to its physical location in flash memory to directly access data on an SSD without a flash translation layer.[36]