Fwd: FW: Synapse Bangalore - Open Positions
Sandeep Bishnoi
From: Manivel Duraisamy <mdura...@synapse-da.com>
Date: Thu, Aug 2, 2012 at 10:53 AM
Subject: FW: Synapse Bangalore - Open Positions
To: "sandeepb...@gmail.com" <sandeepb...@gmail.com>
Hi All
Synapse Bangalore Open Positions
Job Code : DV_1010
Position : Design Verification Engineers
Experience: 3 to 8yrs
Location: Bangalore
No of Positions: 50
Job Description
· Create verification plans for SoC / IP level verification.
· Create test benches in System Verilog / Specman.
· Write test cases in C / C++, Assembly, e / SV etc.
· Utilize advanced verification methodologies like VMM / OVM / UVM / eRM for writing verification environments.
· Expertise in standard IP blocks and protocols such as PCIe, USB 3.0, SATA, Ethernet, TCP/IP, IPSec, iSCSI, DDR3.
· Extensively worked on debugging tests in RTL / GLS both at SOC and IP level.
· Worked on generating code / functional coverage and analyzing the results.
· Low power verification techniques using industry standard tools.
· Worked on writing assertions using standard languages.
· Write tools and scripts in Perl and other scripting languages to enhance the verification process.
· Excellent problem solving and debugging skills.
Desired Skills:
· Working knowledge of e / SV is must and exposure to C / C++ is a plus.
· Experience in writing BFMs, protocol checkers etc is plus.
· Working knowledge of ARM-based processors and AMBA bus protocols is a plus.
Job Code : PD_1011
Position : Physical Design Engineer
Experience: 3 to 8yrs
Location: Bangalore
No of Positions: 50
Job Description:
· Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)
· Work on Place and Route in 65nm, 45nm and 28nm technologies
· Define the floor plan, including pin placement, power busing, placement of blocks and macros
· Physical Synthesis and Timing Closure for Multi Mode Multi Corner
· Design complex clocking structures for MMMC mode
· Noise Analysis, X-talk Optimization and DFM Routing
· Physical Verification including DRC, ERC and LVS.
· Static and Dynamic IR Analysis
· Perl/tcl scripting proficiency
· Timing Analysis using STA.
· Formal Verification
Mandatory Skills:
· Experience using Synopsys ICC, Magma Talus, Cadence Encounter, Mentor Olympus or Atoptech tools
· Successful tape out experience of multiple complex chips (10M+ gates) at 65 or 45 nm
· Expertise in floor planning, Physical Synthesis, CTS, Routing
· Knowledge of low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc.)
· Hands on experience with STA (Primetime), Power analysis (Apache), DRC / LVS (Calibre), Noise analysis (Celtic / PT-SI)
· Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
· Circuit level comprehension of time critical paths in the design
· Programming experience in tcl, Perl or C
Job Code : DFT_1012
Position : Design For Test Engineer (DFT)
Experience: 3 to 8yrs
Location: Bangalore
No of Positions: 25
Experience on Design, Implementation and verification of LBIST, MBIST, PBIST, SCAN, ATPG, Boundary Scan, P1500 on complex chip at leading edge technologies.
Experience on Coverage analysis , debugging skills on faults, and enhancement as required.
Write scripts in Perl and other scripting languages to enhance the DFT process
Work on complex low power designs, ASICS, SOCs.
Silicon debugging on failure patterns will be an added advantage
Mandatory Skills:
· Expertise with SCAN, ATPG, from reputed DFT vendors
· Experience with simulators from one or more EDA vendor
· Experience working with multiple complex chips at different technologies like 90nm, 65nm, .... etc
· Proficiency with Linux, Perl and TCL is required
· Good problem solving and debugging skills
Job Code: STA/SYN_1013
Position : Static Timing Analysis/ Synthesis (STA/SYN)
Location: Bangalore
No of Positions: 10
Experience: 3 to 8 yrs
Job Description
· Responsible for timing closure at the chip and block level
· Execute static timing analysis, synthesis, formal verification and power analysis
· Analyze results and work with the RTL designers and place / route team to resolve issues
· Work on complex low power designs
Mandatory Skills:
· Expertise with STA tools such as Synopsys Primetime-SI or Cadence ETS
· Expertise with formal verification such as Cadence’s Conformal equivalence checker
· Expertise with synthesis, floor planning, IR drop, dynamic power analysis and noise analysis
· Successful tape out experience of multiple complex chips at 65 or 45 nm
· Proficiency with Linux, Perl and TCL
· Constraints development
· STA at different modes and corners
· Knowledge of DCTCL and PTTCL
· Expertise in LEC and debug
· Nice to have Some domain knowledge
Job Code : BSP_ 1014
Domain / Function : Board Support Packages
Role : Software Engineer/ Senior Software Engineers/Lead Engineers/Architect
Location: Bangalore
Experience: 3 to 12 yrs
Roles and Responsibilities:
· Individual contributions (9 engineers)
o Implementation/bug-fixes/porting of the drivers to different platforms or different hardware
o Software design, Unit and Integration, System Integration
· Lead (3 engineers team)
o Define their software architecture, Reviewing the team work and guide, Reports
o Implementation/bug-fixes/porting of the drivers to different platforms or different hardware
· Architect (1 engineer)
o Spearheads all of the software development activities
o He is responsible for dictating design choices to software leads/developers.
o Gain a complete understanding of the client needs and effectively communicate them to the team.
o Architecting the system
o Defining the High-level architecture and set-ups
Mandatory Skills:
1. Good hands-on experience C programming
2. ARM or Intel hardware platform experiences
3. Good working experience in Mobile and Media platforms. Hence working experience in ANY OF THE following drivers Splits
i. Multimedia (Graphics, ISP, Camera, Display, Touch, DTV, STB)
ii. Audio/Video (Audio, Video encode/decode, V4L, I2S, McBSP)
iii. Connectivity (WLAN, BT, USB, Bluetooth, NFC, RFID, PCIe, SDIO), RIL
iv. Storage (flash rivers, MMC/SD drivers, file system driver)
v. Core (I2C, SPI, UART, PCIe, IPC, DMA, RTC, KEYPAD), Gyro, accelerometer sensor, Battery, SIM
4. Bootloaders, Linux build system, Makefiles, Good working experience in Linux, Windows CE, Android, Windows 7/8.
5. Good working experience in Kernel code debugging methods (printk, kgdb)
6. Software debugging on hardware platform (JTAG, Lauterbach, ITP, JLink, segger)
Desired Skills (Optional):
7. Good working experience in system integration (Application processor and Baseband processor integration, connectivity solutions integration with AP, ISP integration with AP … etc)
8. Code Compose Studio, Segger, IAR workbench, CodeWarrior
Education Qualification : BE/ B.Tech / ME / M Tech/ MS in Electronics and Communications or Computer Science