Fwd: Job | Lead Design Engineer :: Cadence-Pune
Sandeep Bishnoi
From: Pradeep <prad...@techpointsolutions.com>
Date: Fri, Jul 11, 2014 at 12:27 PM
Subject: Job | Lead Design Engineer :: Cadence-Pune
To: prad...@techpointsolutions.com
Hi! Friend
I got your reference from our Professional Database .Regarding Job Opening with Cadence-Pune
Greetings from Techpoint solutions!
Sincere Apologies if it is considered SPAM (or) Not Interested.
Introducing My Self Pradeep Kumar working as a IT Recruiter and Software Consulting Company with (Techpoint Solutions(I) Pvt Ltd ).
Please let me know your interest and get back to me with your updated resume in word format send to ASAP : prad...@techpointsolutions.com
Mandatory Details & Updated Resume
1.Relavant Experience in OVM/UVM :
Relevant Exp in Simulation or Emulation Testbenches:
2.Current Salary Package P/A ? :
3.Expected Salary Package P/A ? :
4.Required Notice Period ? :
5.willing to Relocate Pune ? Y/N
Job Type : Permanent Position
Required Experience : 3 – 11 Years
Client : Tensilica Technologies India Pvt Ltd – A Cadence Group Company
Position Title: Lead Design Engineer
Job Location: Pune
Tensilica's processors are based on the proven Xtensa architecture, which is used across a wide range of electronic products, from low-cost portable consumer applications to carrier-class networking routers. All Xtensa configurable processors have two essential unique features:
Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need
Extensibility - designers can add multi-cycle execution units, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology, where the designer only has to specify and verify the functional behavior of the new data path and the RTL is automatically generated.
Position Description:
As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals.
You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
You will also assist with developing testplans, debugging failures and analyzing coverage information.
You will work closely with the RTL and EDA teams.
Required Skills and Experience:
5-7 years of design verification experience
BS (or higher) in EE/Computer Engineering
Experience in mentoring junior engineer
Excellent knowledge of computer architecture and design verification fundamentals
Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
Experience in developing complex test bench in SystemVerilog using OVM/UVM methodology
Exposure to scripting languages like Perl, Unix shell or similar languages
Some experience with assembly language programming required
Excellent written and oral communication skills necessary
Please give any references of your friends/colleagues who are interested, Waiting for Your Earliest Reply
Best Regards...?
Pradeep kumar | IT Recruiter
Mailto : prad...@techpointsolutions.com
Techpoint Solutions(I) Pvt Ltd | Contact : 040-44326616
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