- Group: Experts in SystemVerilog/Specman/VERA/System C
- Subject: Wafer Space is Hiring !!!! Need 50 Verification Engineers/Leads/Technical Manager with 4-12 Years of exp.
Apply now - am...@waferspace.com
Dear All,
Good News !! We are expanding, we are looking for serious folks joining us on verification side with 4- 12 Years of experience with domains like networking/multimedia/Wireless etc.
Go through the below requirements and email resumes to am...@waferspace.com
REQ - 1
Verification Eng/Lead/Manager
3-12 experience in Design Verification(PCIE/USB)
•Experience in Specman / System Verilog and UVM/OVM
•Experience reading specs to create/update test plans and write/run test cases (*must*)
•Experience developing test benches, taking over existing test benches and enhancing them as well as using them to complete verification (*must*)
•Block level as well as top level verification experience
•Domain wise, Ethernet and OTN (*good to have*)
•Experience working with PCIe and SPI interfaces (*nice to have*)
REQ - 2
SoC Verification Engineer
Desired Candidate Profile:
•BE/BTech or ME/MTech with 3+ yrs and above experience in SoC Verification / ARM SOC
•Prior experience in Leading/ Mentoring is a plus but not required
•Thorough understanding of state-of-the-art verification methodologies, tools and languages
•Expert in Design Verification at SoC level
•Expert in C and Verilog based verification
•Good knowledge of protocols and debugging skills
•C/PERL/TCL and UNIX scripting experience is a plus
•Excellent communication skills and ability to communicate information and ideas succinctly
•Ability and desire to learn new methodologies, languages, protocols etc is required
REQ 3
Processor Verification
Sr. Engineer/Lead
Experience: 4- 12 Years
. The candidate will be part of the Application Processor Subsystem Verification team, delivering complex sub systems to multiple SoC targeted towards cellular markets.
. The Candidate needs to be comfortable with the Multi CPU/Caches microarchitecture, associated design components like power management schemes, interrupt controllers, watchdog schemes, standard bus protocols like AHB/AXI/ACE etc & the debugging of these components.
. The candidate should be proficient with the development of C/Assembly test cases & the development of test-benches using System Verilog.
. Knowledge of scripting languages like Perl/C-Shell are plus.
REQ 4
Sr. Verification Engineer/Leads
•Develop verification environment and testbench components such as BFMs and checkers.
•Develop comprehensive test plan and implement test cases.
•Verify design in unit level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
•Write SVA and verify design components using Formal Verification (Jasper)
•Write functional covergroups and coverpoints for coverage closure.
•Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations.
Job Requirements:
•ME/BE from Reputed Institute, plus 6-12 years of equivalent experience in ASIC design and verification.
•Highly motivated and be able to work both independently and as a member of team.
•Experience in verifying designs at system level and block level using constrained random verification.
•Expert in System Verilog and OVM/UVM based verification.
•Strong experience in ASIC design verification flows and DV methodologies.
•Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers
•Strong and independent design debugging capability.
•Understanding of AHB, AXI and other bus protocols and system architecture
Kind Regards
Aman
Posted By Aman Ghani
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