Looking for Change- Here is the opportunity to work with top rated Semicon clients
Semiconductor Recruiter
Job Category: Digital Circuit Design
Qualification: Masters in Electrical/Electronics Engineering
Experience required: 5-10 years
Work Location :hyderabad
Desired skills:
- Hands-on experience with high-speed custom digital designs
- Strong understanding of circuit design fundamentals and realization of logic using transistors.
- Strong understanding of sequential elements like flip-flops, latches and clock-gaters.
- Hands-on experience with static timing analysis (setup/hold) in digital circuits.
- Hands-on experience in transistor level simulations, preferably spice/spectre simulations
- Familiarity with any HDL language, preferably Verilog
- Experience in PLL design is a plus
2)
| Qualification : Masters or BTech in Electrical/Electronics Engineering Experience5 – 10+ years in Physical Deisgn. Work Location :Bangalore and hyderabad |
Wish list : Top 5 Skills | - Hands-on experience with RTL2GDSII. - Strong understanding of Physical design fundamentals and realization of IP Design using Digital gates and Hard macros. - Familiarity with any Industry tools for Physical Design Implementation. - Hands-on experience with static timing analysis (setup/hold) in digital implementation. - Tapeout experience with good knowledge of PhyV, Custom Implementation, Scripts, Tcl a must. - Experience in SERDES and PLL design Implementation is a plus. - Interaction with Global Teams a must. |
3)Verification 6-15yrs
Work Location :Bangalore and Hyderabad
Job Description:
Key Responsibilities:
• Create test plans for verification of the various features and test plan execution
• Develop cover points and perform coverage analysis
• In-depth understanding of verification flows and methodologies
• Working knowledge of Verilog, System Verilog, C/C++, OVM/VMM, exposure to
Assertion based verification.
• Graphics/Multimedia verification experience; Good understanding of PCIe protocol;
Chipset knowledge (Northbridge, Southbridge, DDR Interface, Memory controllers)
• Comfortable with Verilog/PLI and industry-standard EDA tools such as VCS or NcSim
• Experience in silicon debug and characterization is a plus.
• Being a mentor and technical leader for more junior verification engineers.
• Leading or participating in Video IP/SOC level verification as a senior member of the
Performance modelling.
work Location :Bangalore
Below is the JD;- with 6+yrs. Exp.
Microarchitecture, C++ programming, modeling and simulation, Operating systems, compilers
CAD Engineers
Work Location :Hyderabad
- Define/develop analog/mixed signal custom design flow
- Tool expertise, automation, & customization in Schematic capture, custom layouts, custom placement, & custom routes in cadence analog design environment
- Design and develop full custom reference flows with standard EDA tools
- Design and develop automation flows as required for design engineers & layout engineers
- Design and develop flows for reliability checks including EM/IR, device reliability checks
- Interface with design team at multiple locations, understand & resolve problems
- PDK installation, support, & maintenance
- Design & develop QA flows
- Automation of Library development, Characterization, view generation, & QA checks for standard cells, I/O cell libraries,
- Automation of IP level datasheet generation, & customer releases
- Interface with EDA vendors, internal IT teams, internal development teams in enhancing company’s productivity & optimizing EDA licensing utilization
Requirements:
- Minimum requirement: Bachelor’s degree in EE or CS with 5+ years of relevant experience
- Expertise in SKILL, & Ocean scripts, Cadence ADE environment, Virtuoso, Spectre & AMS simulators
- Proficiency in setting up flows for LVS/DRC/ERC/XRC flows using Mentor Calibre and StarRC
- Knowledge of CVS & SOS revision control systems
- Expertise in one more of the scripting languages: SKILL, Tcl, Perl, Shell, Python, C/C++
- Understanding of Devise physics & CMOS circuits
- Understanding of device physics & deep-sub micron issues
- Knowledge of Unix/Linux env, and scripting (Tcl, SKILL, or Perl)
- Good understanding of entire IC design/development flow
- Ability to work & communicate with cross functional teams, overseas teams, and strong oral & written communication skills
- Understanding of Memory compiler software is a plus
Candidate must have transistor level circuit design experience of memories. He/She should have worked on 65nm / 45nm / 28nm process technologies and must have Understanding of design issues related to process. Candidate is expected to work as individual contributor on memory characterization projects. Understanding of memory critical paths and characterization tools. Candidate must have done logic verification of memories using verilog or ESPCV. Candidate must have significant exposure to validation of the characterized data and undertaken at least few memory compilers or instances.
Memory Layout
Work Location :Hyderabad
Candidate must have experience in layout design of memory leaf cells and at top level of memories should have worked on 65nm / 45nm / 28nm process technologies and Good understanding of issues like WPE, LOD effects. He/She must have good understanding of physical verification checks. DRC, LVS, ERC and reliability checks . IR and EM
STA
Work Location :Hyderabad
Exp :6-12yrs
STA /Synthesis Engineer
Experience on SOC and/or IP Timing closure and signoff of high speed complex design with multiple clocks and power domains
Experience in setting up timing constraints, analyzing STA timing reports, driving timing closure at the block and chip level – both pre-layout and post-layout
Expertise on Cadence EDI and ETS, particularly ETS
Knowledge of scripting languages like PERL/TCL/Skill
Analog Layout
Work Location :Hyderabad
Exp:4-15yrs
Hands on experience in Analog Layout design of various designs SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc. and understand deep sub-micron and DFM issues and layout techniques
Experience in CMOS process technologies 22nm, 28nm, 45nm, 65nm etc.
Thorough working knowledge of layout design and physical verification tools - Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
Responsible for timely and quality execution of layout design.
Hoping to Hear from you
Best Regards
Vasu