Design verification position @ Chelsio

[Sandeep Bishnoi]

 

 

Requirements:

 

 

Good communications skills, both verbal and writing.

 

BE/BTech or ME/MTech with a minimum of 2-5 years experience in relevant area 

• Specification development
  • Capture and analysis of design requirements
  • Creation of functional verification plan based on requirements
  • Identification of suitable IP blocks and create specifications for BFM/Stub development.
  • IC architecture development (block architecture, interfaces, etc.)
• Developing a robust verification plan and environment with different methodologies
  • Specification to model testbench
  • Architecting layered, Class based automated testbenches
  • Hands-on development experience with Constrained Random test-bench using High Level Verification Languages(SystemVerilog/VERA preferred)
  • Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)

§  Developing and integrating verification IP

• Experience in verification environment development using OVM/VMM/UVM
• Emulation / silicon validation experience is plus
• Strong knowledge on Perl, UNIX shell, or equivalent scripting languages
• Generating and Analyzing Code Coverage reports.

·         Domain knowledge

• PCIE or MAC or  DDR or Networking protocols work experience
• Security experience is plus
• PowerPC or MIPS or Tensilica processor knowledge

§  TCP, RDMA, FCOE, iSCSI

Keywords:

 

-          SV or Vera must

-          Working experience on PCIE or Security protocols or Networking protocols one of them is required.

-          MAC and DDR is additional plus.