Re: [vlsi careers: 49] Digest for vlsicareers@googlegroups.com - 1 Message in 1 Topic
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Kannan Mahalingam
May 3, 2011, 7:49:58 AM5/3/11
to vlsic...@googlegroups.com
Dear,
Currently we have some excellent ,Multiple requirements at Bangalore and I would like to share the requirements here
Please feel free to reach: kmmailf...@gmail.com
1.Physical Design Engineer/Lead/Manager who is hands on on following :
Tools : ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR
Drop, PT/PTSI , Calibre Activities : Physical design of Hard
Macros/Partitions of sizes upto 1000K placeable instances from
gate-level-Netlist to GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Hard Macro floorplan/IR
Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
Drop, PT/PTSI , Calibre Activities : Physical design of Hard
Macros/Partitions of sizes upto 1000K placeable instances from
gate-level-Netlist to GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Hard Macro floorplan/IR
Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
2. Physical Design Engineer/Lead/Manager who is hands on on following
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan ,
Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable
instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Synthesis of RTL to gate netlist, Netlist level
optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints
management , floorplan/IR-Drop/placement/CTS/Routing/Timing
Optimization/Timing Closure/DRC/LVS .
Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable
instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Synthesis of RTL to gate netlist, Netlist level
optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints
management , floorplan/IR-Drop/placement/CTS/Routing/Timing
Optimization/Timing Closure/DRC/LVS .
3. Physical Design - Analog
Skilled Candidates with hands on experience in physical-verification
preferable with analog layout domain.
preferable with analog layout domain.
Experience with calibre rule-writing ,interfacing with foundry is added
advantages
advantages
The candidate should have working knowledge of one of the scripting
languages PERLTCL,SHELL,Cadence skill The candidate should have good
aptitude and ready to adapt and learn different domains.
languages PERLTCL,SHELL,Cadence skill The candidate should have good
aptitude and ready to adapt and learn different domains.
Experience: 2 to 4 Years suitable work experience
4. STA/Synthesis
Strong Skill in STA/Synthesis with Design Compiler/Prime Time Experience.
Required Experience: 3 to 8 Years' experience
Required Experience: 3 to 8 Years' experience
5. ARM Based SOC Verification:
SOC verification exposure (ARM based preferably) using C
. Good command over C language Protocols - AXI/AHB/APB Hands on experience
on the following.System Verilog based oreboard/coverage/regression
development & debug . OVM methodology using System Verilog. . Exposure to
Verilog testbenches and Testcase/regression/coverage development & debug. .
Preferably - Cortex-A9 exposure
. Good command over C language Protocols - AXI/AHB/APB Hands on experience
on the following.System Verilog based oreboard/coverage/regression
development & debug . OVM methodology using System Verilog. . Exposure to
Verilog testbenches and Testcase/regression/coverage development & debug. .
Preferably - Cortex-A9 exposure
Key Words: ARM,Cortex-A9 exposure, command on C language, Protocols -
AXI/AHB/APB
AXI/AHB/APB
Experience: 3 - 8 Years
6. RTL Integration.
1. Verilog/VHDL RTL
2. Synthesis ( DC )
3. Spyglass ( lint, DFT, PM, CLK/RST )
4. SoC integration flows ( integrating multiple IPs and associated QC
)
)
5. Understanding of Power Management ( voltage domain, power domains,
clock domains )
clock domains )
6. OCP and AXI protocols
7. ARM understanding
8. Misc : Debussy, simulators (mti/ncsim ), perl
.
Job Description for DFT
Job Description for DFT
Required Skills: Scan insertion, ATPG, Pattern Simulation with and without
timing annotation, Experience on Scan compression techniques, Memory BIST,
Boundary Scan, JTAG concepts, basic understanding of Tester requirements,
basics of synthesis and timing. Knowledge of formal verification. Exposure
to SoC level DFT. Proficiency with Mentor Graphics/Synopsys EDA tools like
Fastscan, Test Kompress, TetraMax, DFTMax, DFTCompiler, DFTAdvisor.
Expertise with memory BIST insertion tools preferably Logic Vision
MBIST/Mentor's MBIST Architect.
timing annotation, Experience on Scan compression techniques, Memory BIST,
Boundary Scan, JTAG concepts, basic understanding of Tester requirements,
basics of synthesis and timing. Knowledge of formal verification. Exposure
to SoC level DFT. Proficiency with Mentor Graphics/Synopsys EDA tools like
Fastscan, Test Kompress, TetraMax, DFTMax, DFTCompiler, DFTAdvisor.
Expertise with memory BIST insertion tools preferably Logic Vision
MBIST/Mentor's MBIST Architect.
Must have good experience with one of the simulation tools -
VCS/Modelsim/NCSim. Good to have knowledge on Debussy/Verdi
VCS/Modelsim/NCSim. Good to have knowledge on Debussy/Verdi
Request you to Please share this email with your friends
On Thu, Mar 10, 2011 at 9:31 PM, <vlsicaree...@googlegroups.com> wrote:
Group: http://groups.google.com/group/vlsicareers/topics
- VLSI: Broadcom Jobs [1 Update]
Topic: VLSI: Broadcom JobsAnent Prakash <ane...@gmail.com> Mar 09 06:45PM +0530 ^
--
--
Best Regards,
Anent Prakash
http://blog.anent.in/
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