ASIC DESIGN AND VERIFICATION POSITIONS WITH PRODUCT COMPAPANIES(4-12yrs)
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Vasu
May 2, 2011, 1:16:31 AM5/2/11
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Dear Candidate
Please share your resume if you are looking out for change
positions in Pune and bangalore
Position: Senior Verification Engineer (Transport)
Location: Pune
This individual will be a key member of the ASIC system level
verification team. ASIC/FGPA verification using advanced verification
concepts and environments ie Specman, OVM, URM, System Verilog, Vera
on both module level and chip level with the use of constrained random
verification techniques
The successful candidate will be involved in hands-on implementation
work for every aspect of ASIC verification, working closely with the
system group, architects, design and verification teams.
The successful candidate should have experience in going through
several complete and successful ASIC Design/Verification cycles from
architecting and creating of ASIC test environment (communications/
networking related preferred)to full completion of the verification
work.
Knowledge of communications protocols an asset: OTN, Ethernet, Sonet,
PON, GFP, Error Correction Codes
Defining, developing test plans , running regressions, generating
coverage metrics and providing automated status.
Writing test benches and test cases given a set of requirements
Knowledge of C/C++, Matlab, perl, Python an asset
BSEE, MS (preferred)
Strong debugging skills a must. Must have good communication skills
and the ability and desire to work as a team
Background in communications/networking a plus.
Position: Senior Design Engineer (Transport)
Location: Pune/Bangalore
* Candidate is expected to participate n all facets of front digital
ASIC design: developing detailed design requirements, architecture
design, VHDL or Verilog RTL detailed design, unit level simulation,
follow DFT guidelines, generate test plans, STA, equivalence checking,
conduct design reviews, etc.
* Should be well versed with use industry standard tools such as
Cadence RC, Synopsys PrimeTime, DC-Compiler, etc. used to generate
netlists for backend.
* Knowledge of communications protocols an asset: OTN, Ethernet,
Sonet, GFP, PON, Error Correction Codes, Flow control, Queuing
architectures
* Knowledge of relevant standards (IEEE, ITU,etc) a plus.
Responsibilities:
* Responsibilities will include block level ownership of design, unit
level verification, design reviews.
* Working in a team environment on multi overseas sites projects
particularly with offices in the US/Canada
Requirements:
* BSEE, MS (preferred)
* Experience with multimillion gate design, COT, multi-clock, high
frequency design with an emphasis on low power.
* Must have good communication skills and the ability and desire to
work as a team. Background in communications/networking a plus
Optional Experience:
* Patents are a plus
* Knowledge of place and route a plus
* Knowledge/Experience of FPGA Design an asset
* Experience with sub 65ns technologies an asset
Experience Requirement
Minimum 7 years of relevant experience
Essential skills:
. Real processor core (PowerPC, x86, ARM, SPARC ) verification
experience is needed.
. Should have gone through the processor verification cycle on at
least 1 processor core.
. Ability to understand and develop Assembly tests
. CPU architecture knowledge a must (including multi processors,
coprocessors, cache design, coherency and coherent interconnects)
. hands on experience with verification environment design, modeling
and implementation using HVL languages
like System Verilog/SystemC/vera
. programming experience to include C/C++ and at least one scripting
language (perl, Tcl)
. Must have both Block level and full chip level verification
experience
. Knowledge and proven experience in coverage driven and assertion
based verification methodology.
. JTAG knowledge will be an additional plus.
Senior/Staff Validation Engineer (FPGA)
Location: Pune
• ASIC Prototyping in FPGA.
• Knowledge of FPGA based Product design
• Familiar with Xilinx ISE, Syplify pro/premier flow
• Pre silicon and post silicon Validation experience
• Knowledge of Ethernet, DDR2, DDR3,AXI
• Xilinx, Synpify tool flow experience ( synthesis, STA, PAR, bit
generation)
• Simulation tools Modelsim, Questasim
* Scripting Knowledge of Perl, TCL
* Knowledge of debugging in FPGA based designs, using LA, embedded
ICE, Chip-scope etc is desired.
Position: Senior Processor Verification Engineer
Location: Pune
Primary Job Responsibilities:
- Responsible for verification of the multi-core PowerPC processor
cores .
- writing test plan and coverage plan
- developing and debugging tests
Education Requirement or Equivalent
BSEE, MSEE
Experience Requirement
Minimum 7 years of relevant experience
Essential skills:
. Real processor core (PowerPC, x86, ARM, SPARC ) verification
experience is needed.
. Should have gone through the processor verification cycle on at
least 1 processor core.
. Ability to understand and develop Assembly tests
. CPU architecture knowledge a must (including multi processors,
coprocessors, cache design, coherency and coherent interconnects)
. hands on experience with verification environment design, modeling
and implementation using HVL languages
like System Verilog/SystemC/vera
. programming experience to include C/C++ and at least one scripting
language (perl, Tcl)
. Must have both Block level and full chip level verification
experience
. Knowledge and proven experience in coverage driven and assertion
based verification methodology.
. JTAG knowledge will be an additional plus.
Position: Senior SoC Design Engineer (USB/PCIE/Security Engine/SATA/
Serdes)
Location: Pune
Responsibilities:
* Will be responsible for micro-architecture definition and RTL design
of blocks and all other associated tasks as a designer eg: working
with the verification team, defining synthesis constraints etc.
Requirements:
* Should have good knowledge of the protocol
* Should have experience working with verification teams and guiding
them with the verification plan
* Should have been involved in atleast a couple of tapeouts
* Should have good understanding about the entire ASIC flow
* Team Player
Optional Experience:
• IPsec background is a plus
* AMBA protocol knowledge is a plus
Position: Diagnostic Test Developer
Location: Pune
Diagnostic test development
• Will be responsible to design/develop board diagnostic test suite on
our evk/validation board
• Experience on SoC diagnostic test development
• Strong at C programming & debugging skills with JTAG debugger
• Experience/knowledge on IP bring-up such as PCIE/SATA/USB/SDIO/ETH/
I2C/SPI
• U-boot or firmware development experience will be plus
• Low-level IP driver development experience will be plus
• FPGA platform bring-up experience will be plus
Position: Linux kernel based IP Validation Engineer
Location: Pune
Linux kernel based data flow test development for IP validation and
Stress/Characterization
• Will be responsible to develop system level validation test suite
• Experience on embedded Linux programming
• Strong at C programming & debugging skills with JTAG debugger
• Kernel/Driver development experience will be plus
• Experience on bring-up IP driver in Linux such as PCIE/SATA/USB/SDIO/
ETH/I2C/SPI interfaces will be plus
• Experience on script language programming such as Tcl, Shell, or
Perl
Please Note: All are for Individula contributor role
Regards
vas
Please share your resume if you are looking out for change
positions in Pune and bangalore
Position: Senior Verification Engineer (Transport)
Location: Pune
This individual will be a key member of the ASIC system level
verification team. ASIC/FGPA verification using advanced verification
concepts and environments ie Specman, OVM, URM, System Verilog, Vera
on both module level and chip level with the use of constrained random
verification techniques
The successful candidate will be involved in hands-on implementation
work for every aspect of ASIC verification, working closely with the
system group, architects, design and verification teams.
The successful candidate should have experience in going through
several complete and successful ASIC Design/Verification cycles from
architecting and creating of ASIC test environment (communications/
networking related preferred)to full completion of the verification
work.
Knowledge of communications protocols an asset: OTN, Ethernet, Sonet,
PON, GFP, Error Correction Codes
Defining, developing test plans , running regressions, generating
coverage metrics and providing automated status.
Writing test benches and test cases given a set of requirements
Knowledge of C/C++, Matlab, perl, Python an asset
BSEE, MS (preferred)
Strong debugging skills a must. Must have good communication skills
and the ability and desire to work as a team
Background in communications/networking a plus.
Position: Senior Design Engineer (Transport)
Location: Pune/Bangalore
* Candidate is expected to participate n all facets of front digital
ASIC design: developing detailed design requirements, architecture
design, VHDL or Verilog RTL detailed design, unit level simulation,
follow DFT guidelines, generate test plans, STA, equivalence checking,
conduct design reviews, etc.
* Should be well versed with use industry standard tools such as
Cadence RC, Synopsys PrimeTime, DC-Compiler, etc. used to generate
netlists for backend.
* Knowledge of communications protocols an asset: OTN, Ethernet,
Sonet, GFP, PON, Error Correction Codes, Flow control, Queuing
architectures
* Knowledge of relevant standards (IEEE, ITU,etc) a plus.
Responsibilities:
* Responsibilities will include block level ownership of design, unit
level verification, design reviews.
* Working in a team environment on multi overseas sites projects
particularly with offices in the US/Canada
Requirements:
* BSEE, MS (preferred)
* Experience with multimillion gate design, COT, multi-clock, high
frequency design with an emphasis on low power.
* Must have good communication skills and the ability and desire to
work as a team. Background in communications/networking a plus
Optional Experience:
* Patents are a plus
* Knowledge of place and route a plus
* Knowledge/Experience of FPGA Design an asset
* Experience with sub 65ns technologies an asset
Experience Requirement
Minimum 7 years of relevant experience
Essential skills:
. Real processor core (PowerPC, x86, ARM, SPARC ) verification
experience is needed.
. Should have gone through the processor verification cycle on at
least 1 processor core.
. Ability to understand and develop Assembly tests
. CPU architecture knowledge a must (including multi processors,
coprocessors, cache design, coherency and coherent interconnects)
. hands on experience with verification environment design, modeling
and implementation using HVL languages
like System Verilog/SystemC/vera
. programming experience to include C/C++ and at least one scripting
language (perl, Tcl)
. Must have both Block level and full chip level verification
experience
. Knowledge and proven experience in coverage driven and assertion
based verification methodology.
. JTAG knowledge will be an additional plus.
Senior/Staff Validation Engineer (FPGA)
Location: Pune
• ASIC Prototyping in FPGA.
• Knowledge of FPGA based Product design
• Familiar with Xilinx ISE, Syplify pro/premier flow
• Pre silicon and post silicon Validation experience
• Knowledge of Ethernet, DDR2, DDR3,AXI
• Xilinx, Synpify tool flow experience ( synthesis, STA, PAR, bit
generation)
• Simulation tools Modelsim, Questasim
* Scripting Knowledge of Perl, TCL
* Knowledge of debugging in FPGA based designs, using LA, embedded
ICE, Chip-scope etc is desired.
Position: Senior Processor Verification Engineer
Location: Pune
Primary Job Responsibilities:
- Responsible for verification of the multi-core PowerPC processor
cores .
- writing test plan and coverage plan
- developing and debugging tests
Education Requirement or Equivalent
BSEE, MSEE
Experience Requirement
Minimum 7 years of relevant experience
Essential skills:
. Real processor core (PowerPC, x86, ARM, SPARC ) verification
experience is needed.
. Should have gone through the processor verification cycle on at
least 1 processor core.
. Ability to understand and develop Assembly tests
. CPU architecture knowledge a must (including multi processors,
coprocessors, cache design, coherency and coherent interconnects)
. hands on experience with verification environment design, modeling
and implementation using HVL languages
like System Verilog/SystemC/vera
. programming experience to include C/C++ and at least one scripting
language (perl, Tcl)
. Must have both Block level and full chip level verification
experience
. Knowledge and proven experience in coverage driven and assertion
based verification methodology.
. JTAG knowledge will be an additional plus.
Position: Senior SoC Design Engineer (USB/PCIE/Security Engine/SATA/
Serdes)
Location: Pune
Responsibilities:
* Will be responsible for micro-architecture definition and RTL design
of blocks and all other associated tasks as a designer eg: working
with the verification team, defining synthesis constraints etc.
Requirements:
* Should have good knowledge of the protocol
* Should have experience working with verification teams and guiding
them with the verification plan
* Should have been involved in atleast a couple of tapeouts
* Should have good understanding about the entire ASIC flow
* Team Player
Optional Experience:
• IPsec background is a plus
* AMBA protocol knowledge is a plus
Position: Diagnostic Test Developer
Location: Pune
Diagnostic test development
• Will be responsible to design/develop board diagnostic test suite on
our evk/validation board
• Experience on SoC diagnostic test development
• Strong at C programming & debugging skills with JTAG debugger
• Experience/knowledge on IP bring-up such as PCIE/SATA/USB/SDIO/ETH/
I2C/SPI
• U-boot or firmware development experience will be plus
• Low-level IP driver development experience will be plus
• FPGA platform bring-up experience will be plus
Position: Linux kernel based IP Validation Engineer
Location: Pune
Linux kernel based data flow test development for IP validation and
Stress/Characterization
• Will be responsible to develop system level validation test suite
• Experience on embedded Linux programming
• Strong at C programming & debugging skills with JTAG debugger
• Kernel/Driver development experience will be plus
• Experience on bring-up IP driver in Linux such as PCIE/SATA/USB/SDIO/
ETH/I2C/SPI interfaces will be plus
• Experience on script language programming such as Tcl, Shell, or
Perl
Please Note: All are for Individula contributor role
Regards
vas
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